coreboot-gerrit August 2019

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Change in ...coreboot[master]: MAINTAINERS: Add myself as a maintainer for Lenovo G505S and ASUS AM1I-A
by Mike Banon (Code Review) 31 Dec '19

31 Dec '19

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33872 Change subject: MAINTAINERS: Add myself as a maintainer for Lenovo G505S and ASUS AM1I-A ...................................................................... MAINTAINERS: Add myself as a maintainer for Lenovo G505S and ASUS AM1I-A These are the boards I have and currently working on. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I874770813a96ecd27138b02a16f6bc737572351a --- M MAINTAINERS 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/33872/1 diff --git a/MAINTAINERS b/MAINTAINERS index 73ca6df..14d075a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -164,6 +164,11 @@ S: Maintained F: src/mainboard/lenovo/ +LENOVO G505S MAINBOARD +M: Mike Banon <mikebdp2(a)gmail.com> +S: Maintained +F: src/mainboard/lenovo/g505s + APPLE MAINBOARDS M: Evgeny Zinoviev <me(a)ch1p.io> S: Maintained @@ -333,6 +338,11 @@ S: Maintained F: src/mainboard/asrock/h81m-hds/ +ASUS AM1I-A MAINBOARD +M: Mike Banon <mikebdp2(a)gmail.com> +S: Maintained +F: src/mainboard/asus/am1i-a + ASUS KFSN4-DRE & KFSN4-DRE_K8 MAINBOARDS M: Timothy Pearson <tpearson(a)raptorengineeringinc.com> S: Supported -- To view, visit https://review.coreboot.org/c/coreboot/+/33872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I874770813a96ecd27138b02a16f6bc737572351a Gerrit-Change-Number: 33872 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: chromeec: Depend on events_copy_b to identify the wake source.
by Ravi Chandra Sadineni (Code Review) 29 Dec '19

29 Dec '19

Ravi Chandra Sadineni has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34801 ) Change subject: chromeec: Depend on events_copy_b to identify the wake source. ...................................................................... chromeec: Depend on events_copy_b to identify the wake source. Using google_chromeec_get_event() clears the event too. Thus if the kernel has to identify the wake source, it has no way to do that. Thus instead depend on events_copy_b to log the wake source. Please look at go/hostevent-refactor for more info. BUG=b:133262012 BRANCH=None TEST=Hack hatch bios and make sure hostevent log is correct. Change-Id: I39caae2689e0c2a7bec16416978877885a9afc6c Signed-off-by: Ravi Chandra Sadineni <ravisadineni(a)chromium.org> --- M src/ec/google/chromeec/ec.c 1 file changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/34801/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 5a2630e..9ba9b1b 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -428,7 +428,8 @@ void google_chromeec_log_events(uint64_t mask) { - u8 event; + u64 events; + int i; uint64_t wake_mask; bool restore_wake_mask = false; @@ -445,11 +446,14 @@ restore_wake_mask = true; } - while ((event = google_chromeec_get_event()) != 0) { - if (EC_HOST_EVENT_MASK(event) & mask) - elog_add_event_byte(ELOG_TYPE_EC_EVENT, event); + events = google_chromeec_get_events_b() & mask; + for (i = 0; i < sizeof(events) * 8; i++) { + if (EC_HOST_EVENT_MASK(i) & events) + elog_add_event_byte(ELOG_TYPE_EC_EVENT, i); } + google_chromeec_clear_events_b(events); + if (restore_wake_mask) google_chromeec_set_wake_mask(wake_mask); } @@ -467,10 +471,6 @@ /* Disable SMI and wake events. */ google_chromeec_set_smi_mask(0); - /* Clear pending events. */ - while (google_chromeec_get_event() != 0) - ; - /* Restore SCI event mask. */ google_chromeec_set_sci_mask(info->sci_events); -- To view, visit https://review.coreboot.org/c/coreboot/+/34801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39caae2689e0c2a7bec16416978877885a9afc6c Gerrit-Change-Number: 34801 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi Chandra Sadineni <ravisadineni(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: arch/x86: Drop Kconfig SIPI_VECTOR_IN_ROM
by Kyösti Mälkki (Code Review) 21 Dec '19

21 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30856 Change subject: arch/x86: Drop Kconfig SIPI_VECTOR_IN_ROM ...................................................................... arch/x86: Drop Kconfig SIPI_VECTOR_IN_ROM This was used to enforce 4kiB alignment of _start16bit in romcc bootblock. Platforms requiring this moved away to C_ENVIRONMENT_BOOTBLOCK that globally forces the alignment. Change-Id: I8ca453bbc56ab2aeb127f3e081c69e1b38bb8396 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/Kconfig M src/arch/x86/failover.ld M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/model_106cx/Kconfig M src/cpu/intel/socket_LGA775/Kconfig M src/cpu/intel/socket_mPGA604/Kconfig M src/cpu/x86/16bit/entry16.inc 7 files changed, 5 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/30856/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 242a7cf..c2fc914 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -81,13 +81,6 @@ default n depends on ARCH_X86 && SMP -# Aligns 16bit entry code in bootblock so that hyper-threading CPUs -# can boot AP CPUs to enable their shared caches. -config SIPI_VECTOR_IN_ROM - bool - default n - depends on ARCH_X86 - # Set the rambase for systems that still need it, only 5 chipsets as of # Sep 2018. This value was 0x100000, chosen to match the entry point # of Linux 2.2 in 1999. The new value, 14 MiB, makes a lot more sense diff --git a/src/arch/x86/failover.ld b/src/arch/x86/failover.ld index b32aa29..eabc9f7 100644 --- a/src/arch/x86/failover.ld +++ b/src/arch/x86/failover.ld @@ -23,12 +23,11 @@ TARGET(binary) SECTIONS { - /* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs - * with Startup IPI message without RAM. Align .rom to next 4 byte - * boundary anyway, so no pad byte appears between _rom and _start. + /* Align .rom to 4 byte boundary so no pad byte appears + * between _rom and _start. */ .bogus ROMLOC_MIN : { - . = CONFIG_SIPI_VECTOR_IN_ROM ? ALIGN(4096) : ALIGN(4); + . = ALIGN(4); ROMLOC = .; } >rom = 0xff @@ -49,12 +48,7 @@ * may cause the total size of a section to change when the start * address gets applied. */ - ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - - (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0); - - /* Post-check proper SIPI vector. */ - _bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || (ap_sipi_vector_in_rom == 0xff), - "Address mismatch on AP_SIPI_VECTOR"); + ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16); /DISCARD/ : { *(.comment) diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index fda572d..5c579a1 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -23,10 +23,6 @@ /* Macro to access Local APIC registers at default base. */ #define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) -#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) -/* Fixed location, ASSERTED in failover.ld if it changes. */ -.set ap_sipi_vector_in_rom, 0xff -#endif #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index f365cf1..2a324fb 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -7,7 +7,6 @@ select SMP select SSE2 select UDELAY_LAPIC - select SIPI_VECTOR_IN_ROM select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 8b227bd..6c3d837 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -13,7 +13,6 @@ select CPU_INTEL_MODEL_1067X select MMX select SSE - select SIPI_VECTOR_IN_ROM config DCACHE_RAM_SIZE hex diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index ca2f7b3..e860ded 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -9,7 +9,6 @@ select MMX select SSE select UDELAY_TSC - select SIPI_VECTOR_IN_ROM select C_ENVIRONMENT_BOOTBLOCK # mPGA604 are usually Intel Netburst CPUs which should have SSE2 diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 2a9f8c5..f110980 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -29,8 +29,7 @@ #include <arch/rom_segs.h> -#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) || \ - IS_ENABLED(CONFIG_SIPI_VECTOR_IN_ROM) +#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) /* Symbol _start16bit must be aligned to 4kB to start AP CPUs with * Startup IPI message without RAM. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ca453bbc56ab2aeb127f3e081c69e1b38bb8396 Gerrit-Change-Number: 30856 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation/binaries: Add AMD FSP documentation
by Richard Spiegel (Code Review) 21 Dec '19

21 Dec '19

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34662 ) Change subject: Documentation/binaries: Add AMD FSP documentation ...................................................................... Documentation/binaries: Add AMD FSP documentation Create a document explaining, at a high level, the differences between Intel's FSP and the one developed by AMD. BUG=none. TEST=none. Change-Id: I59a5d34df93cd0ff647e2ccfdbf8700b4df00a59 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- A Documentation/binaries/AMD_FSP_family_17h.md A Documentation/binaries/index.md 2 files changed, 49 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/34662/1 diff --git a/Documentation/binaries/AMD_FSP_family_17h.md b/Documentation/binaries/AMD_FSP_family_17h.md new file mode 100644 index 0000000..b46beb3 --- /dev/null +++ b/Documentation/binaries/AMD_FSP_family_17h.md @@ -0,0 +1,41 @@ +# FSP implementation differences between Intel and AMD + +## Introduction +Starting with family 17h, AMD is developing an "_As Close As Possible_" FSP +binary. However, some premisses are different for family 17h and beyond, +making it necessary to have some FSP implementation differences. Some other +implementation differences were more of an engineering decision. + +The family 17h deviation from older AMD and Intel CPU/SOC are: +* The memory is initialized by the PSP (similar to Intel's ME) ARM. +* There's _**no support**_ for cache as RAM. +* Reset vector is not the old 0xFFFFFFF0. + +This document is a "work in progress", documenting the differences at a +high level. This document will be updated as more information becomes +available. + +## Differences caused by differences in premisses +1. **No FSP-T** +Because family 17h does not support CAR, there's no FSP-T. +2. **FSP-M only reports memory** +Because memory is inittialized by the PSP, FSP-M only reports the final +memory configuration. +3. **FSP-M is loaded to DRAM** +PSP can be made to load a section of the flash into RAM before releasing +the reset, thus FSP-M can be made to run directly from memory. +4. **FSP-M can be made position independent** +Because it's loaded to memory and does not uses CAR, FSP-M can be made PIC +(Position Independent Code). + +## Differences by engineering decision +1. **Memory fragmentation** +Though FSP still fragments memory, it has added control for flexibility +of where the chunks will reside. +2. **UPD interface** +UPD interface uses native intergers and don't need to be packed by compiler. +3. **UPD with no UEFI dependencies** +UPD interface can be made C99 or C11 compatible with no hard dependencies +to UEFI. +4. **Platform specific code** +Similar to AGESA, FSP will make call back to platform specific code. diff --git a/Documentation/binaries/index.md b/Documentation/binaries/index.md new file mode 100644 index 0000000..9093bf7 --- /dev/null +++ b/Documentation/binaries/index.md @@ -0,0 +1,8 @@ +# binaries-specific documentation + +This section contains documentation about any binary used by coreboot + +## Video + +## Platform initialization +- [AMD FSP](AMD_FSP_family_17h.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/34662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59a5d34df93cd0ff647e2ccfdbf8700b4df00a59 Gerrit-Change-Number: 34662 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/cpu/x86 STM Support
by Name of user not set (Code Review) 20 Dec '19

20 Dec '19

Name of user not set #1002358 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33236 Change subject: src/cpu/x86 STM Support ...................................................................... src/cpu/x86 STM Support STM initialization Change-Id: I3a0adcefc0f6e22a9da5fe53952481a77737e5eb --- M src/cpu/x86/mp_init.c 1 file changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/33236/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 3889c7d..881d8a2 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -37,8 +37,12 @@ #include <symbols.h> #include <thread.h> +#include <security/intel/stm/StmApi.h> + #define MAX_APIC_IDS 256 +extern int LoadStmImage(uint32_t mseg); + struct mp_callback { void (*func)(void *); void *arg; @@ -823,6 +827,10 @@ { size_t smm_save_state_size = mp_state.smm_save_state_size; +#ifdef CONFIG_STM + uint32_t mseg; +#endif + /* Do nothing if SMM is disabled.*/ if (!is_smm_enabled()) return; @@ -839,6 +847,14 @@ printk(BIOS_ERR, "Unable to install SMM permanent handler.\n"); smm_disable(); } +#ifdef CONFIG_STM + + /* Calculate mseg location*/ + mseg = mp_state.perm_smbase + (mp_state.perm_smsize - CONFIG_MSEG_SIZE); + + /* Load the STM into the MSEG */ + LoadStmImage(mseg); +#endif /* Ensure the SMM handlers hit DRAM before performing first SMI. */ wbinvd(); @@ -1023,6 +1039,15 @@ if (ops->get_smm_info != NULL) ops->get_smm_info(&state->perm_smbase, &state->perm_smsize, &state->smm_save_state_size); +#ifdef CONFIG_STM + + /* Currently, the CPU SMM save state size is based on a simplistic + * algorithm. (set it to 1K) + * note: In the future, this will need to handle newer x86 processors + * that require 32k alignment of the save state on 32K boundries.*/ + state->smm_save_state_size += (sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR) + 0x1000) & 0xfffff000; + +#endif /* CONFIG_STM */ /* * Default to smm_initiate_relocation() if trigger callback isn't -- To view, visit https://review.coreboot.org/c/coreboot/+/33236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a0adcefc0f6e22a9da5fe53952481a77737e5eb Gerrit-Change-Number: 33236 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002358 Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/x86/smm/ STM Support
by Name of user not set (Code Review) 20 Dec '19

20 Dec '19

Name of user not set #1002358 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33235 Change subject: cpu/x86/smm/ STM Support ...................................................................... cpu/x86/smm/ STM Support SMI Handler modifications needed to setup the STM data structures Change-Id: I935cd5a8bc0bf293240324c2e3a04a655d44c69f --- M src/cpu/x86/smm/smm_module_handler.c M src/cpu/x86/smm/smm_module_loader.c M src/cpu/x86/smm/smm_stub.S M src/include/cpu/x86/smm.h 4 files changed, 92 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/33235/1 diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index f9af965..26ddd66 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -18,6 +18,15 @@ #include <cpu/x86/smm.h> #include <rmodule.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/cache.h> + +#include <security/intel/stm/StmApi.h> +#include <security/intel/stm/StmPlatformResource.h> +#include <arch/acpi.h> +#include <lib.h> +#include <security/intel/stm/SmmStm.h> + #if IS_ENABLED(CONFIG_SPI_FLASH_SMM) #include <spi-generic.h> #endif @@ -116,6 +125,10 @@ return base; } +#ifdef CONFIG_STM + static uint32_t MsegInit = 0; // used for STM/mseg initialization +#endif + asmlinkage void smm_handler_start(void *arg) { const struct smm_module_params *p; @@ -123,7 +136,16 @@ int cpu; uintptr_t actual_canary; uintptr_t expected_canary; +#ifdef CONFIG_STM + int MsegInit2 = 1; // assume that the STM has been set + /* this initialzation strategy works on the assumption that all + * processors will enter SMM at generally the same time. + * If a single processor lags then a locking/counting scheme will + * need to be implemented. */ + if (MsegInit == 0) + MsegInit2 = 0; +#endif p = arg; runtime = p->runtime; cpu = p->cpu; @@ -140,9 +162,33 @@ "Invalid CPU number assigned in SMM stub: %d\n", cpu); return; } +#ifdef CONFIG_STM + if (MsegInit == 0) { + + /* Initialize the MSEG base address for each logical processor + * and indicate that there is an STM present */ + msr_t InitMseg; + msr_t MsegChk; + + InitMseg.lo = smm_runtime->mseg | IA32_SMM_MONITOR_VALID; + InitMseg.hi = 0; + + wrmsr(IA32_SMM_MONITOR_CTL_MSR_INDEX, InitMseg); + + MsegChk = rdmsr(IA32_SMM_MONITOR_CTL_MSR_INDEX); + console_init(); + + printk(BIOS_DEBUG, "MSEG Initialized (%d) 0x%08x 0x%08x\n", + cpu, MsegChk.hi, MsegChk.lo); + } + +#endif /* Are we ok to execute the handler? */ if (!smi_obtain_lock()) { +#ifdef CONFIG_STM + void *smbase = (void *) smm_runtime->smbase; +#endif /* For security reasons we don't release the other CPUs * until the CPU with the lock is actually done */ while (smi_handler_status == SMI_LOCKED) { @@ -150,13 +196,35 @@ ".byte 0xf3, 0x90\n" /* PAUSE */ ); } +#ifdef CONFIG_STM + if (MsegInit2 == 0) { + + /* Setup an SMM Descriptor for this logical processor */ + SetupSmmDescriptor(smbase, smm_runtime->save_state_size, cpu, smm_runtime->start32_offset); + MsegInit2 = 1; + } +#endif + wbinvd(); return; } +#ifdef CONFIG_STM + + if (MsegInit == 0) { + void *smbase = (void *) smm_runtime->smbase; + + AddResourcesCmd(); + + /* Setup an SMM Descriptor for this logical processor */ + + SetupSmmDescriptor(smbase, smm_runtime->save_state_size, cpu, + smm_runtime->start32_offset); + MsegInit = 1; // flag that we are done + wbinvd(); // force the tables to memory + } +#endif smi_backup_pci_address(); - console_init(); - printk(BIOS_SPEW, "\nSMI# #%d\n", cpu); /* Allow drivers to initialize variables in SMM context. */ diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 6c16645..4f15fdd 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -18,6 +18,7 @@ #include <cpu/x86/smm.h> #include <cpu/x86/cache.h> #include <console/console.h> +#include <security/intel/stm/SmmStm.h> #define FXSAVE_SIZE 512 @@ -268,6 +269,9 @@ stub_params->fxsave_area_size = FXSAVE_SIZE; stub_params->runtime.smbase = (uintptr_t)smbase; stub_params->runtime.save_state_size = params->per_cpu_save_state_size; + + /* mseg is after the smi handler */ + stub_params->runtime.mseg = (uint32_t) params->stack_top; /* Initialize the APIC id to CPU number table to be 1:1 */ for (i = 0; i < params->num_concurrent_stacks; i++) @@ -354,7 +358,13 @@ /* Stacks start at the top of the region. */ base = smram; + +#ifdef CONFIG_STM + base += size - CONFIG_MSEG_SIZE; // take out the mseg +#else base += size; +#endif + params->stack_top = base; /* SMM module starts at offset SMM_DEFAULT_SIZE with the load alignment diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index 59eb27c..3817424 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -46,6 +46,11 @@ .long 0 save_state_size: .long 0 +mseg: +.long 0 +/* allows the STM to bring up SMM in 32-bit mode*/ +start32_offset: +.long smm_trampoline32 - _start /* apic_to_cpu_num is a table mapping the default APIC id to CPU num. If the * APIC id is found at the given index, the contiguous CPU number is index * into the table. */ @@ -92,6 +97,10 @@ /* gdt selector 0x10, flat data segment */ .word 0xffff, 0x0000 .byte 0x00, 0x93, 0xcf, 0x00 + + /* gdt selector 0x18 tr segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x8b, 0x80, 0x00 smm_relocate_gdt_end: .align 4 diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 576449d..b2d7445 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -512,6 +512,9 @@ struct smm_runtime { u32 smbase; u32 save_state_size; + u32 mseg; + /* used so that the STM can start the SMI handler in 32bit mode */ + u32 start32_offset; /* The apic_id_to_cpu provides a mapping from APIC id to CPU number. * The CPU number is indicated by the index into the array by matching * the default APIC id and value at the index. The stub loader -- To view, visit https://review.coreboot.org/c/coreboot/+/33235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I935cd5a8bc0bf293240324c2e3a04a655d44c69f Gerrit-Change-Number: 33235 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002358 Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP] Move AGESA and apufw higher in CBFS
by Kyösti Mälkki (Code Review) 19 Dec '19

19 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31076 Change subject: [WIP] Move AGESA and apufw higher in CBFS ...................................................................... [WIP] Move AGESA and apufw higher in CBFS Increases continuous free space in CBFS from 5.8 MiB to 7.1 MiB. Will not work with released binaryPI build from 3rdparty/blobs. Change-Id: I3c166102b8774499a0b21f212b5e8a66fe6c52eb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/amd/pi/hudson/Makefile.inc M src/vendorcode/amd/pi/Kconfig 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/31076/1 diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 81fe7ff..57bad38 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -75,7 +75,7 @@ ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) HUDSON_FWM_POSITION=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 0x20000 1) else -HUDSON_FWM_POSITION=0xfff20000 +HUDSON_FWM_POSITION=0xfffa0000 endif ifeq ($(CONFIG_HUDSON_PSP), y) diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig index f463b7d..3dc7052 100644 --- a/src/vendorcode/amd/pi/Kconfig +++ b/src/vendorcode/amd/pi/Kconfig @@ -96,7 +96,7 @@ config AGESA_BINARY_PI_LOCATION hex "AGESA PI binary address in ROM" - default 0xFFE00000 + default 0xFFF00000 depends on !AGESA_BINARY_PI_AS_STAGE help Specify the ROM address at which to store the binary Platform -- To view, visit https://review.coreboot.org/c/coreboot/+/31076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c166102b8774499a0b21f212b5e8a66fe6c52eb Gerrit-Change-Number: 31076 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: include/cpu/x86: Add STM Support
by Name of user not set (Code Review) 19 Dec '19

19 Dec '19

Name of user not set #1002358 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33985 Change subject: include/cpu/x86: Add STM Support ...................................................................... include/cpu/x86: Add STM Support Addtions to cpu/x86 include for STM support. Change-Id: I2b8e68b2928aefc7996b6a9560c52f71c7c0e1d0 --- M src/include/cpu/x86/msr.h M src/include/cpu/x86/smm.h 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/33985/1 diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index d1e9169..c9d92a7 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -30,6 +30,7 @@ #define IA32_BIOS_SIGN_ID 0x8b #define IA32_MPERF 0xe7 #define IA32_APERF 0xe8 +/* STM */ #define IA32_SMM_MONITOR_CTL_MSR 0x9B #define IA32_SMM_MONITOR_VALID (1<<0) #define IA32_MCG_CAP 0x179 diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index b2d7445..3bd6e41 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -512,6 +512,7 @@ struct smm_runtime { u32 smbase; u32 save_state_size; + /* useg to get the mseg address into smm for setup */ u32 mseg; /* used so that the STM can start the SMI handler in 32bit mode */ u32 start32_offset; -- To view, visit https://review.coreboot.org/c/coreboot/+/33985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b8e68b2928aefc7996b6a9560c52f71c7c0e1d0 Gerrit-Change-Number: 33985 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002358 Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mainboard/lenovo: remove stdlib.h when unused
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33901 Change subject: mainboard/lenovo: remove stdlib.h when unused ...................................................................... mainboard/lenovo: remove stdlib.h when unused Change-Id: I6af1d44f9a05c153b6a355318a39adc9a3d6c0c9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/lenovo/g505s/BiosCallOuts.c M src/mainboard/lenovo/g505s/buildOpts.c 2 files changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/33901/1 diff --git a/src/mainboard/lenovo/g505s/BiosCallOuts.c b/src/mainboard/lenovo/g505s/BiosCallOuts.c index 2b1ac04..afa2fce 100644 --- a/src/mainboard/lenovo/g505s/BiosCallOuts.c +++ b/src/mainboard/lenovo/g505s/BiosCallOuts.c @@ -16,10 +16,8 @@ #include <AGESA.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/state_machine.h> - #include <southbridge/amd/agesa/hudson/imc.h> #include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> -#include <stdlib.h> const BIOS_CALLOUT_STRUCT BiosCallouts[] = { diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index c3e40ce..559e1a6 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -27,8 +27,6 @@ #include "mainboard.h" -#include <stdlib.h> - #include <vendorcode/amd/agesa/f15tn/AGESA.h> /* Include the files that instantiate the configuration definitions. */ @@ -43,7 +41,6 @@ #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h> #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h> - /* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE -- To view, visit https://review.coreboot.org/c/coreboot/+/33901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6af1d44f9a05c153b6a355318a39adc9a3d6c0c9 Gerrit-Change-Number: 33901 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/arch: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32820 Change subject: src/arch: Use 'include <stdlib.h>' when appropriate ...................................................................... src/arch: Use 'include <stdlib.h>' when appropriate Change-Id: I79f065703b5249ca9630b06de7142bc52675076e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm/armv7/mmu.c M src/arch/arm/cpu.c M src/arch/mips/mmu.c M src/arch/x86/acpigen_dsm.c M src/arch/x86/cbmem.c M src/arch/x86/mmap_boot.c 6 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/32820/1 diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c index ce9d3fd..f0a5fa6 100644 --- a/src/arch/arm/armv7/mmu.c +++ b/src/arch/arm/armv7/mmu.c @@ -29,12 +29,9 @@ */ #include <assert.h> -#include <stdlib.h> #include <stdint.h> #include <symbols.h> - #include <console/console.h> - #include <arch/cache.h> #if CONFIG(ARM_LPAE) diff --git a/src/arch/arm/cpu.c b/src/arch/arm/cpu.c index fae1a37..0637bf6 100644 --- a/src/arch/arm/cpu.c +++ b/src/arch/arm/cpu.c @@ -27,7 +27,6 @@ * SUCH DAMAGE. * */ -#include <stdlib.h> #include <arch/cpu.h> /* Return the CPU struct which is at the high memory address of the stack. diff --git a/src/arch/mips/mmu.c b/src/arch/mips/mmu.c index b144fd3..2ceb2a7 100644 --- a/src/arch/mips/mmu.c +++ b/src/arch/mips/mmu.c @@ -18,7 +18,6 @@ #include <console/console.h> #include <stddef.h> #include <stdint.h> -#include <stdlib.h> #define MIN_PAGE_SIZE (4 * KiB) diff --git a/src/arch/x86/acpigen_dsm.c b/src/arch/x86/acpigen_dsm.c index 1aab90b..8c9cd350 100644 --- a/src/arch/x86/acpigen_dsm.c +++ b/src/arch/x86/acpigen_dsm.c @@ -15,7 +15,6 @@ #include <arch/acpigen.h> #include <arch/acpigen_dsm.h> -#include <stdlib.h> /* ------------------- I2C HID DSM ---------------------------- */ diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c index 648633f..abd163d 100644 --- a/src/arch/x86/cbmem.c +++ b/src/arch/x86/cbmem.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <cbmem.h> #include <arch/acpi.h> diff --git a/src/arch/x86/mmap_boot.c b/src/arch/x86/mmap_boot.c index abfa024..98b5643 100644 --- a/src/arch/x86/mmap_boot.c +++ b/src/arch/x86/mmap_boot.c @@ -15,7 +15,6 @@ #include <boot_device.h> #include <endian.h> -#include <stdlib.h> /* The ROM is memory mapped just below 4GiB. Form a pointer for the base. */ #define rom_base ((void *)(uintptr_t)(0x100000000ULL-CONFIG_ROM_SIZE)) -- To view, visit https://review.coreboot.org/c/coreboot/+/32820 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79f065703b5249ca9630b06de7142bc52675076e Gerrit-Change-Number: 32820 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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