coreboot-gerrit August 2019

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Change in ...coreboot[master]: inteltool: add support for CannonPoint-LP
by Matt DeVillier (Code Review) 15 Mar '20

15 Mar '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33411 Change subject: inteltool: add support for CannonPoint-LP ...................................................................... inteltool: add support for CannonPoint-LP Add support for CannonPoint-LP U Premium (CoffeeLake-U and WhiskeyLake-U) GPIO info taken from Intel 300 Series Chipset Family On-Package Platform Controller Hub, Datasheet volume 1 of 2, document #337867-002 Test: Read GPIOs from out-of-tree WhiskeyLake-U board Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> Change-Id: Ic3593ffe7d997261e9b7189ec4083cf75aaf3cf9 --- M util/inteltool/Makefile M util/inteltool/gpio.c M util/inteltool/gpio_groups.c M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/pcr.c M util/inteltool/platform.h A util/inteltool/platform_cannonlake_lp.c 8 files changed, 373 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/33411/1 diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index c71c711..0ee1991 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -28,7 +28,8 @@ CPPFLAGS += -I$(top)/src/commonlib/include PLATFORMS = platform_sunrise.o platform_apollolake.o platform_cannonlake.o \ - platform_denverton.o platform_lynxpoint.o platform_i631x.o + platform_cannonlake_lp.o platform_denverton.o \ + platform_lynxpoint.o platform_i631x.o OBJS = inteltool.o pcr.o cpu.o gpio.o gpio_groups.o rootcmplx.o powermgt.o \ memory.o pcie.o amb.o ivy_memory.o spi.o gfx.o ahci.o \ diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 670ecf3..e9a919f 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -345,6 +345,7 @@ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: + case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM: case PCI_DEVICE_ID_INTEL_H310: case PCI_DEVICE_ID_INTEL_H370: case PCI_DEVICE_ID_INTEL_Z390: diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 27df34b..f3743bf 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -129,6 +129,12 @@ communities = apl_communities; pcr_init(sb); break; + case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM: + community_count = cannonlake_pch_lp_communities_count; + communities = cannonlake_pch_lp_communities; + pad_stepping = 16; + pcr_init(sb); + break; case PCI_DEVICE_ID_INTEL_H310: case PCI_DEVICE_ID_INTEL_H370: case PCI_DEVICE_ID_INTEL_Z390: diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 7e02510..f1a4c76 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -137,6 +137,10 @@ "7th generation (Kaby Lake family) Core Processor (Mobile)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3, "7th generation (Kaby Lake family) Core Processor Xeon E3-1200" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_1, + "8th generation (Coffee Lake family) Core Processor (Mobile)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_2, + "8th generation (Whiskey Lake family) Core Processor (Mobile)" }, /* Southbridges (LPC controllers) */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10, "ICH10" }, @@ -246,6 +250,8 @@ "Sunrise Point-LP U iHDCP 2.2 Premium/Kabylake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM, "Sunrise Point-LP Y iHDCP 2.2 Premium/Kabylake" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM, + "Cannon Point-LP U Premium/CoffeeLake/Whiskeylake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H110, "H110" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H170, "H170" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z170, "Z170" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 483c930..e26c229 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -155,6 +155,7 @@ #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE 0x9d50 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM 0x9d4e #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM 0x9d4b +#define PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM 0x9d84 #define PCI_DEVICE_ID_INTEL_H110 0xa143 #define PCI_DEVICE_ID_INTEL_H170 0xa144 #define PCI_DEVICE_ID_INTEL_Z170 0xa145 @@ -276,6 +277,8 @@ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y 0x590C /* Kabylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q 0x5914 /* Kabylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3 0x5918 /* Kabylake Xeon E3 */ +#define PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_1 0x3ed0 /* Coffeelake (Mobile) */ +#define PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_2 0x3e34 /* Whiskeylake (Mobile) */ /* Intel GPUs */ diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c index c969620..9323362 100644 --- a/util/inteltool/pcr.c +++ b/util/inteltool/pcr.c @@ -119,6 +119,7 @@ case PCI_DEVICE_ID_INTEL_QM370: case PCI_DEVICE_ID_INTEL_HM370: case PCI_DEVICE_ID_INTEL_CM246: + case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM: sbbar_phys = 0xfd000000; use_p2sb = false; break; diff --git a/util/inteltool/platform.h b/util/inteltool/platform.h index d5fa8e6..8fd674b 100644 --- a/util/inteltool/platform.h +++ b/util/inteltool/platform.h @@ -25,6 +25,9 @@ extern const struct gpio_community *const cannonlake_pch_h_communities[]; size_t cannonlake_pch_h_communities_count; +extern const struct gpio_community *const cannonlake_pch_lp_communities[]; +size_t cannonlake_pch_lp_communities_count; + extern const struct gpio_community *const denverton_communities[]; size_t denverton_communities_count; diff --git a/util/inteltool/platform_cannonlake_lp.c b/util/inteltool/platform_cannonlake_lp.c new file mode 100644 index 0000000..b3a2eaf --- /dev/null +++ b/util/inteltool/platform_cannonlake_lp.c @@ -0,0 +1,351 @@ +/* + * inteltool - dump all registers on an Intel CPU + chipset based system. + * + * Copyright (C) 2019 Purism SPC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "inteltool.h" +#include "gpio.h" +#include "platform.h" + +const char *const cannonlake_pch_lp_group_a_names[] = { + "GPP_A0", "RCIN#", "TIME_SYNC1", "n/a", + "GPP_A1", "LAD0", "ESPI_IO0", "n/a", + "GPP_A2", "LAD1", "ESPI_IO1", "n/a", + "GPP_A3", "LAD2", "ESPI_IO2", "n/a", + "GPP_A4", "LAD3", "ESPI_IO3", "n/a", + "GPP_A5", "LFRAME#", "ESPI_CS0#", "n/a", + "GPP_A6", "SERIRQ", "n/a", "n/a", + "GPP_A7", "PIRQA#", "GSPI0_CS1#", "n/a", + "GPP_A8", "CLKRUN#", "n/a", "n/a", + "GPP_A9", "CLKOUT_LPC0", "ESPI_CLK", "n/a", + "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", + "GPP_A11", "PME#", "GSPI1_CS1#", "SD_VDD2_PWR_EN#", + "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", + "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", + "GPP_A14", "SUS_STAT#", "ESPI_RESET#", "n/a", + "GPP_A15", "SUSACK#", "n/a", "n/a", + "GPP_A16", "SD_1P8_SEL", "n/a", "n/a", + "GPP_A17", "SD_VDD1_PWR_EN#", "ISH_GP7", "n/a", + "GPP_A18", "ISH_GP0", "n/a", "n/a", + "GPP_A19", "ISH_GP1", "n/a", "n/a", + "GPP_A20", "ISH_GP2", "n/a", "n/a", + "GPP_A21", "ISH_GP3", "n/a", "n/a", + "GPP_A22", "ISH_GP4", "n/a", "n/a", + "GPP_A23", "ISH_GP5", "n/a", "n/a", +}; + +const struct gpio_group cannonlake_pch_lp_group_a = { + .display = "------- GPIO Group GPP_A -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_a_names) / 4, + .func_count = 4, + .pad_names = cannonlake_pch_lp_group_a_names, +}; + +const char *const cannonlake_pch_lp_group_b_names[] = { + "GPP_B0", "Reserved", "n/a", + "GPP_B1", "Reserved", "n/a", + "GPP_B2", "VRALERT#", "n/a", + "GPP_B3", "CPU_GP2", "n/a", + "GPP_B4", "CPU_GP3", "n/a", + "GPP_B5", "SRCCLKREQ0#", "n/a", + "GPP_B6", "SRCCLKREQ1#", "n/a", + "GPP_B7", "SRCCLKREQ2#", "n/a", + "GPP_B8", "SRCCLKREQ3#", "n/a", + "GPP_B9", "SRCCLKREQ4#", "n/a", + "GPP_B10", "SRCCLKREQ5#", "n/a", + "GPP_B11", "EXT_PWR_GATE#", "n/a", + "GPP_B12", "SLP_S0#", "n/a", + "GPP_B13", "PLTRST#", "n/a", + "GPP_B14", "SPKR", "n/a", + "GPP_B15", "GSPI0_CS0#", "n/a", + "GPP_B16", "GSPI0_CLK", "n/a", + "GPP_B17", "GSPI0_MISO", "n/a", + "GPP_B18", "GSPI0_MOSI", "n/a", + "GPP_B19", "GSPI1_CS0#", "n/a", + "GPP_B20", "GSPI1_CLK", "n/a", + "GPP_B21", "GSPI1_MISO", "n/a", + "GPP_B22", "GSPI1_MOSI", "n/a", + "GPP_B23", "SML1ALERT#", "PCHHOT#", +}; + +const struct gpio_group cannonlake_pch_lp_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_b_names) / 3, + .func_count = 3, + .pad_names = cannonlake_pch_lp_group_b_names, +}; + +const char *const cannonlake_pch_lp_group_c_names[] = { + "GPP_C0", "SMBCLK", "n/a", + "GPP_C1", "SMBDATA", "n/a", + "GPP_C2", "SMBALERT#", "n/a", + "GPP_C3", "SML0CLK", "n/a", + "GPP_C4", "SML0DATA", "n/a", + "GPP_C5", "SML0ALERT#", "n/a", + "GPP_C6", "SML1CLK", "n/a", + "GPP_C7", "SML1DATA", "n/a", + "GPP_C8", "UART0_RXD", "n/a", + "GPP_C9", "UART0_TXD", "n/a", + "GPP_C10", "UART0_RTS#", "n/a", + "GPP_C11", "UART0_CTS#", "n/a", + "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", + "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", + "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", + "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", + "GPP_C16", "I2C0_SDA", "n/a", + "GPP_C17", "I2C0_SCL", "n/a", + "GPP_C18", "I2C1_SDA", "n/a", + "GPP_C19", "I2C1_SCL", "n/a", + "GPP_C20", "UART2_RXD", "n/a", + "GPP_C21", "UART2_TXD", "n/a", + "GPP_C22", "UART2_RTS#", "n/a", + "GPP_C23", "UART2_CTS#", "n/a", +}; + +const struct gpio_group cannonlake_pch_lp_group_c = { + .display = "------- GPIO Group GPP_C -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_c_names) / 3, + .func_count = 3, + .pad_names = cannonlake_pch_lp_group_c_names, +}; + +const char *const cannonlake_pch_lp_group_d_names[] = { + "GPP_D0", "SPI1_CS#", "BK0", "SBK0", + "GPP_D1", "SPI1_CLK", "BK1", "SBK1", + "GPP_D2", "SPI1_MISO", "BK2", "SBK2", + "GPP_D3", "SPI1_MOSI", "BK3", "SBK3", + "GPP_D4", "IMGCLKOUT0", "BK4", "SBK4", + "GPP_D5", "ISH_I2C0_SDA", "n/a", "n/a", + "GPP_D6", "ISH_I2C0_SCL", "n/a", "n/a", + "GPP_D7", "ISH_I2C1_SDA", "n/a", "n/a", + "GPP_D8", "ISH_I2C1_SCL", "n/a", "n/a", + "GPP_D9", "ISH_SPI_CS#", "n/a", "GSPI2_CS0#", + "GPP_D10", "ISH_SPI_CLK", "n/a", "GSPI2_CLK", + "GPP_D11", "ISH_SPI_MISO", "n/a", "GSPI2_MISO", + "GPP_D12", "ISH_SPI_MOSI", "n/a", "GSPI2_MOSI", + "GPP_D13", "ISH_UART0_RXD", "SML0BDATA", "I2C4B_SDA", + "GPP_D14", "ISH_UART0_TXD", "SML0BCLK", "I2C4B_SCL", + "GPP_D15", "ISH_UART0_RTS#", "GSPI2_CS1#", "n/a", + "GPP_D16", "ISH_UART0_CTS#", "SML0BALERT", "n/a", + "GPP_D17", "DMIC_CLK1", "SNDW3_CLK", "n/a", + "GPP_D18", "DMIC_DATA1", "SNDW3_DATA", "n/a", + "GPP_D19", "DMIC_CLK0", "SNDW4_CLK", "n/a", + "GPP_D20", "DMIC_DATA0", "SNDW4_DATA", "n/a", + "GPP_D21", "SPI1_IO2", "n/a", "n/a", + "GPP_D22", "SPI1_IO3", "n/a", "n/a", + "GPP_D23", "I2S_MCLK", "n/a", "n/a", +}; + +const struct gpio_group cannonlake_pch_lp_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_d_names) / 4, + .func_count = 4, + .pad_names = cannonlake_pch_lp_group_d_names, +}; + +const char *const cannonlake_pch_lp_group_e_names[] = { + "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", + "GPP_E1", "SATAXPCIE1", "n/a", "n/a", + "GPP_E2", "SATAXPCIE2", "n/a", "n/a", + "GPP_E3", "CPU_GP0", "n/a", "n/a", + "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a", + "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a", + "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a", + "GPP_E7", "CPU_GP1", "n/a", "n/a", + "GPP_E8", "SATALED#", "n/a", "n/a", + "GPP_E9", "USB2_OC0#", "n/a", "n/a", + "GPP_E10", "USB2_OC1#", "n/a", "n/a", + "GPP_E11", "USB2_OC2#", "n/a", "n/a", + "GPP_E12", "USB2_OC3#", "n/a", "n/a", + "GPP_E13", "DDPB_HPD0", "DISP_MISC0", "n/a", + "GPP_E14", "DDPC_HPD1", "DISP_MISC1", "n/a", + "GPP_E15", "DDPD_HPD2", "DISP_MISC2", "n/a", + "GPP_E16", "n/a", "DISP_MISC3", "n/a", + "GPP_E17", "EDP_HPD", "DISP_MISC4", "n/a", + "GPP_E18", "DPPB_CTRLCLK", "n/a", "CNV_BT_HOST_WAKE#", + "GPP_E19", "DPPB_CTRLDATA", "n/a", "CNV_BT_IF_SELECT", + "GPP_E20", "DPPC_CTRLCLK", "n/a", "n/a", + "GPP_E21", "DPPC_CTRLDATA", "n/a", "n/a", + "GPP_E22", "DPPD_CTRLCLK", "n/a", "n/a", + "GPP_E23", "DPPD_CTRLDATA", "n/a", "n/a", +}; + +const struct gpio_group cannonlake_pch_lp_group_e = { + .display = "------- GPIO Group GPP_E -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_e_names) / 4, + .func_count = 4, + .pad_names = cannonlake_pch_lp_group_e_names, +}; + +const char *const cannonlake_pch_lp_group_f_names[] = { + "GPP_F0", "SATAXPCIE3", "SATAGP3", + "GPP_F1", "SATAXPCIE4", "SATAGP4", + "GPP_F2", "SATAXPCIE5", "SATAGP5", + "GPP_F3", "SATAXPCIE6", "SATAGP6", + "GPP_F4", "SATAXPCIE7", "SATAGP7", + "GPP_F5", "SATA_DEVSLP3", "n/a", + "GPP_F6", "SATA_DEVSLP4", "n/a", + "GPP_F7", "SATA_DEVSLP5", "n/a", + "GPP_F8", "SATA_DEVSLP6", "n/a", + "GPP_F9", "SATA_DEVSLP7", "n/a", + "GPP_F10", "SATA_SCLOCK", "n/a", + "GPP_F11", "SATA_SLOAD", "n/a", + "GPP_F12", "SATA_SDATAOUT1", "n/a", + "GPP_F13", "SATA_SDATAOUT0", "n/a", + "GPP_F14", "n/a", "PS_ON#", + "GPP_F15", "USB2_OC4#", "n/a", + "GPP_F16", "USB2_OC5#", "n/a", + "GPP_F17", "USB2_OC6#", "n/a", + "GPP_F18", "USB2_OC7#", "n/a", + "GPP_F19", "eDP_VDDEN", "n/a", + "GPP_F20", "eDP_BKLTEN", "n/a", + "GPP_F21", "eDP_BKLTCTL", "n/a", + "GPP_F22", "DDPF_CTRLCLK", "n/a", + "GPP_F23", "DDPF_CTRLDATA", "n/a", +}; + +const struct gpio_group cannonlake_pch_lp_group_f = { + .display = "------- GPIO Group GPP_F -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_f_names) / 3, + .func_count = 3, + .pad_names = cannonlake_pch_lp_group_f_names, +}; + +const char *const cannonlake_pch_lp_group_g_names[] = { + "GPP_G0", "SD_CMD", + "GPP_G1", "SD_DATA0", + "GPP_G2", "SD_DATA1", + "GPP_G3", "SD_DATA2", + "GPP_G4", "SD_DATA3", + "GPP_G5", "SD3_CD#", + "GPP_G6", "SD3_CLK", + "GPP_G7", "SD3_WP", +}; + +const struct gpio_group cannonlake_pch_lp_group_g = { + .display = "------- GPIO Group GPP_G -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_g_names) / 2, + .func_count = 2, + .pad_names = cannonlake_pch_lp_group_g_names, +}; + +const char *const cannonlake_pch_lp_group_h_names[] = { + "GPP_H0", "I2S2_SCLK", "CNV_BT_I2S_SCLK", "n/a", + "GPP_H1", "I2S2_SFRM", "CNV_BT_I2S_BCLK", "CNV_RF_RESET#", + "GPP_H2", "I2S2_TXD", "CNV_BT_I2S_SDI", "MODEM_CLKREQ", + "GPP_H3", "I2S2_RXD", "CNV_BT_I2S_SDO", "n/a", + "GPP_H4", "I2C2_SDA", "n/a", "n/a", + "GPP_H5", "I2C2_SCL", "n/a", "n/a", + "GPP_H6", "I2C3_SDA", "n/a", "n/a", + "GPP_H7", "I2C3_SCL", "n/a", "n/a", + "GPP_H8", "I2C4_SDA", "n/a", "n/a", + "GPP_H9", "I2C4_SCL", "n/a", "n/a", + "GPP_H10", "I2C5_SDA", "ISH_I2C2_SDA", "n/a", + "GPP_H11", "I2C5_SCL", "ISH_I2C2_SCL", "n/a", + "GPP_H12", "M2_SKT2_CFG0", "n/a", "n/a", + "GPP_H13", "M2_SKT2_CFG1", "n/a", "n/a", + "GPP_H14", "M2_SKT2_CFG2", "n/a", "n/a", + "GPP_H15", "M2_SKT2_CFG3", "n/a", "n/a", + "GPP_H16", "n/a", "n/a", "n/a", + "GPP_H17", "n/a", "n/a", "n/a", + "GPP_H18", "CPU_C10_GATE#", "n/a", "n/a", + "GPP_H19", "TIME_SYNC0", "n/a", "n/a", + "GPP_H20", "IMGCLKOUT1", "n/a", "n/a", + "GPP_H21", "n/a", "n/a", "n/a", + "GPP_H22", "n/a", "n/a", "n/a", + "GPP_H23", "n/a", "n/a", "n/a", +}; + +const struct gpio_group cannonlake_pch_lp_group_h = { + .display = "------- GPIO Group GPP_H -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_h_names) / 4, + .func_count = 4, + .pad_names = cannonlake_pch_lp_group_h_names, +}; + +const char *const cannonlake_pch_lp_group_gpd_names[] = { + "GPD0", "BATLOW#", + "GPD1", "ACPRESENT", + "GPD2", "LAN_WAKE#", + "GPD3", "PRWBTN#", + "GPD4", "SLP_S3#", + "GPD5", "SLP_S4#", + "GPD6", "SLP_A#", + "GPD7", "n/a", + "GPD8", "SUSCLK", + "GPD9", "SLP_WLAN#", + "GPD10", "SLP_S5#", + "GPD11", "LANPHYPC", +}; +const struct gpio_group cannonlake_pch_lp_group_gpd = { + .display = "------- GPIO Group GPD -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_gpd_names) / 2, + .func_count = 2, + .pad_names = cannonlake_pch_lp_group_gpd_names, +}; + +const struct gpio_group *const cannonlake_pch_lp_community_0_groups[] = { + &cannonlake_pch_lp_group_a, + &cannonlake_pch_lp_group_b, + &cannonlake_pch_lp_group_g, +}; +const struct gpio_community cannonlake_pch_lp_community_0 = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0x6e, + .group_count = ARRAY_SIZE(cannonlake_pch_lp_community_0_groups), + .groups = cannonlake_pch_lp_community_0_groups, +}; + +const struct gpio_group *const cannonlake_pch_lp_community_1_groups[] = { + &cannonlake_pch_lp_group_d, + &cannonlake_pch_lp_group_f, + &cannonlake_pch_lp_group_h, +}; +const struct gpio_community cannonlake_pch_lp_community_1 = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0x6d, + .group_count = ARRAY_SIZE(cannonlake_pch_lp_community_1_groups), + .groups = cannonlake_pch_lp_community_1_groups, +}; + +const struct gpio_group *const cannonlake_pch_lp_community_2_groups[] = { + &cannonlake_pch_lp_group_gpd, +}; + +const struct gpio_community cannonlake_pch_lp_community_2 = { + .name = "------- GPIO Community 2 -------", + .pcr_port_id = 0x6c, + .group_count = ARRAY_SIZE(cannonlake_pch_lp_community_2_groups), + .groups = cannonlake_pch_lp_community_2_groups, +}; + +const struct gpio_group *const cannonlake_pch_lp_community_4_groups[] = { + &cannonlake_pch_lp_group_c, + &cannonlake_pch_lp_group_e, +}; + +const struct gpio_community cannonlake_pch_lp_community_4 = { + .name = "------- GPIO Community 4 -------", + .pcr_port_id = 0x6a, + .group_count = ARRAY_SIZE(cannonlake_pch_lp_community_4_groups), + .groups = cannonlake_pch_lp_community_4_groups, +}; + +const struct gpio_community *const cannonlake_pch_lp_communities[] = { + &cannonlake_pch_lp_community_0, + &cannonlake_pch_lp_community_1, + &cannonlake_pch_lp_community_2, + &cannonlake_pch_lp_community_4, +}; + +size_t cannonlake_pch_lp_communities_count = ARRAY_SIZE(cannonlake_pch_lp_communities); -- To view, visit https://review.coreboot.org/c/coreboot/+/33411 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3593ffe7d997261e9b7189ec4083cf75aaf3cf9 Gerrit-Change-Number: 33411 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

2 8

Change in coreboot[master]: google/kukui: Load and run dram init blob
by Tristan Hsieh (Code Review) 12 Mar '20

12 Mar '20

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34872 ) Change subject: google/kukui: Load and run dram init blob ...................................................................... google/kukui: Load and run dram init blob Load dram.bin and run it for full dram calibration. If any error occurred, try default dram init flow. BUG=b:134351649 BRANCH=none TEST=emerge-kukui coreboot Change-Id: Iad05a77e6353f37cd5ea897203d528762f44176e Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- M src/mainboard/google/kukui/Makefile.inc M src/mainboard/google/kukui/romstage.c M src/soc/mediatek/mt8183/include/soc/memlayout.ld 3 files changed, 45 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/34872/1 diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index a0556c1..d7621f1 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -25,3 +25,8 @@ ramstage-y += mainboard.c ramstage-y += memlayout.ld ramstage-y += reset.c + +cbfs-files-y += dram.bin +dram.bin-file := 3rdparty/blobs/soc/mediatek/mt8183/dram.bin +dram.bin-type := raw +dram.bin-compression := $(CBFS_COMPRESS_FLAG) diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index 1465243..8521cf8 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -19,9 +19,45 @@ #include <soc/mt6358.h> #include <soc/pll.h> #include <soc/rtc.h> +#include <string.h> #include "early_init.h" +#include <cbfs.h> +#include <console/console.h> + +DECLARE_REGION(dram_init_code) + +static int dram_blob_load_and_run(void) +{ + int (*dram_init)(void *); + size_t blob_size, region_size; + + region_size = _edram_init_code - _dram_init_code; + blob_size = cbfs_boot_load_file("dram.bin", _dram_init_code, + region_size, CBFS_TYPE_RAW); + if (blob_size == 0) { + printk(BIOS_ERR, "dram.bin not found\n"); + return -1; + } + + memset(_dram_init_code + blob_size, 0, region_size - blob_size); + + dram_init = (int (*)(void *))_dram_init_code; + + return dram_init(NULL); +} + +static void dram_config(void) +{ + int err = dram_blob_load_and_run(); + if (err == 0) + return; + + printk(BIOS_ERR, "dram_blob error:%d\n", err); + mt_mem_init(get_sdram_config()); +} + void platform_romstage_main(void) { /* This will be done in verstage if CONFIG_VBOOT is enabled. */ @@ -33,6 +69,6 @@ pmic_set_vsim2_cali(2700); mt_pll_raise_ca53_freq(1989 * MHz); rtc_boot(); - mt_mem_init(get_sdram_config()); + dram_config(); mtk_mmu_after_dram(); } diff --git a/src/soc/mediatek/mt8183/include/soc/memlayout.ld b/src/soc/mediatek/mt8183/include/soc/memlayout.ld index 7da282e..9a71645 100644 --- a/src/soc/mediatek/mt8183/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8183/include/soc/memlayout.ld @@ -24,6 +24,8 @@ */ #define SRAM_L2C_START(addr) SYMBOL(sram_l2c, addr) #define SRAM_L2C_END(addr) SYMBOL(esram_l2c, addr) +#define DRAM_INIT_CODE(addr, size) \ + REGION(dram_init_code, addr, size, 4) SECTIONS { @@ -43,6 +45,7 @@ DECOMPRESSOR(0x00201000, 28K) BOOTBLOCK(0x00208000, 64K) OVERLAP_VERSTAGE_ROMSTAGE(0x00218000, 160K) + DRAM_INIT_CODE(0x00240000, 256K) SRAM_L2C_END(0x00280000) DRAM_START(0x40000000) -- To view, visit https://review.coreboot.org/c/coreboot/+/34872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad05a77e6353f37cd5ea897203d528762f44176e Gerrit-Change-Number: 34872 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-MessageType: newchange

9 31

Change in ...coreboot[master]: google/kukui: DRAM freq switch to 2400Mbps
by Tristan Hsieh (Code Review) 12 Mar '20

12 Mar '20

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30613 Change subject: google/kukui: DRAM freq switch to 2400Mbps ...................................................................... google/kukui: DRAM freq switch to 2400Mbps Forcing DRAM frequency 2400Mbps. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Ie3ac04080b32a84b8451910d309b43f2f1921d9a Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/emi.c 3 files changed, 53 insertions(+), 69 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/30613/1 diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c index da6c7d2..555bb02 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c @@ -17,8 +17,8 @@ struct sdram_params params = { .impedance = { - [ODT_OFF] = {0x7, 0x6, 0x0, 0xF}, - [ODT_ON] = {0x9, 0x9, 0x0, 0xF} + [ODT_OFF] = {0x5, 0x6, 0x0, 0xF}, + [ODT_ON] = {0x6, 0x9, 0x0, 0xE} }, .wr_level = { [CHANNEL_A] = { {0x22, 0x1b}, {0x22, 0x19} }, diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c index 9197ceb..551205f 100644 --- a/src/soc/mediatek/mt8183/dramc_init_setting.c +++ b/src/soc/mediatek/mt8183/dramc_init_setting.c @@ -126,17 +126,17 @@ {&ch[0].phy.pll2, 0x00000000}, {&ch[0].phy.misc_cg_ctrl0, 0x0000000f}, {&mt8183_infracfg->dramc_wbr, 0x00000000}, - {&ch[0].phy.shu[0].ca_cmd[6], 0x000604c0}, - {&ch[1].phy.shu[0].ca_cmd[6], 0x00060440}, + {&ch[0].phy.shu[0].ca_cmd[6], 0x000607c0}, + {&ch[1].phy.shu[0].ca_cmd[6], 0x00060740}, {&ch[0].phy.shu[0].ca_dll[1], 0x0004e104}, - {&ch[0].phy.shu[0].b[0].dq[6], 0x00060440}, + {&ch[0].phy.shu[0].b[0].dq[6], 0x00060740}, {&ch[0].phy.shu[0].b[0].dll[1], 0x00022401}, - {&ch[0].phy.shu[0].b[1].dq[6], 0x00060440}, + {&ch[0].phy.shu[0].b[1].dq[6], 0x00060740}, {&ch[0].phy.shu[0].b[1].dll[1], 0x00022401}, {&ch[1].phy.shu[0].ca_dll[1], 0x0004e101}, - {&ch[1].phy.shu[0].b[0].dq[6], 0x00060440}, + {&ch[1].phy.shu[0].b[0].dq[6], 0x00060740}, {&ch[1].phy.shu[0].b[0].dll[1], 0x00022401}, - {&ch[1].phy.shu[0].b[1].dq[6], 0x00060440}, + {&ch[1].phy.shu[0].b[1].dq[6], 0x00060740}, {&ch[1].phy.shu[0].b[1].dll[1], 0x00022401}, {&ch[0].phy.shu[0].pll[4], 0xe5780000}, {&ch[0].phy.shu[0].pll[6], 0xe5780000}, @@ -146,15 +146,15 @@ {&ch[0].ao.dvfsdll, 0x00000000}, {&ch[0].phy.shu[0].ca_dll[0], 0x00698619}, {&ch[0].phy.shu[0].ca_dll[1], 0x0004e104}, - {&ch[0].phy.shu[0].ca_cmd[6], 0x000604c0}, + {&ch[0].phy.shu[0].ca_cmd[6], 0x000607C0}, {&ch[0].phy.b[0].dq[7], 0x00000055}, {&ch[0].phy.b[1].dq[7], 0x00000055}, {&ch[0].phy.ca_cmd[7], 0x00000055}, {&ch[0].phy.ca_cmd[2], 0x00200000}, {&ch[0].phy.misc_cg_ctrl0, 0x0000000f}, - {&ch[0].phy.shu[0].b[0].dq[6], 0x00060440}, - {&ch[0].phy.shu[0].b[1].dq[6], 0x00060440}, - {&ch[0].phy.shu[0].ca_cmd[6], 0x000604c0}, + {&ch[0].phy.shu[0].b[0].dq[6], 0x00060740}, + {&ch[0].phy.shu[0].b[1].dq[6], 0x00060740}, + {&ch[0].phy.shu[0].ca_cmd[6], 0x000607C0}, {&ch[0].phy.pll4, 0x000c0000}, {&ch[0].phy.pll1, 0x00000000}, {&ch[0].phy.pll2, 0x00000000}, @@ -169,26 +169,26 @@ {&ch[0].phy.b[1].dll_fine_tune[0], 0x00000000}, {&ch[0].phy.shu[0].pll[8], 0x00040000}, {&ch[0].phy.shu[0].pll[10], 0x00040000}, - {&ch[0].phy.shu[0].pll[5], 0x7b000002}, - {&ch[0].phy.shu[0].pll[7], 0x7b000002}, + {&ch[0].phy.shu[0].pll[5], 0x5c000002}, + {&ch[0].phy.shu[0].pll[7], 0x5c000002}, {&ch[0].phy.ca_dll_fine_tune[0], 0x00000002}, {&ch[0].phy.b[0].dll_fine_tune[0], 0x00000002}, {&ch[0].phy.b[1].dll_fine_tune[0], 0x00000002}, {&ch[0].phy.ca_dll_fine_tune[1], 0x00200000}, {&ch[0].phy.b[0].dll_fine_tune[1], 0x00000000}, {&ch[0].phy.b[1].dll_fine_tune[1], 0x00000000}, - {&ch[0].phy.shu[0].b[0].dq[6], 0x02860440}, - {&ch[0].phy.shu[0].b[1].dq[6], 0x02860440}, - {&ch[0].phy.shu[0].ca_cmd[6], 0x028604c0}, + {&ch[0].phy.shu[0].b[0].dq[6], 0x02C60740}, + {&ch[0].phy.shu[0].b[1].dq[6], 0x02C60740}, + {&ch[0].phy.shu[0].ca_cmd[6], 0x02C607C0}, {&ch[0].phy.ca_dll_fine_tune[0], 0x0000000a}, {&ch[0].phy.b[0].dll_fine_tune[0], 0x0000000a}, {&ch[0].phy.b[1].dll_fine_tune[0], 0x0000000a}, {&ch[0].phy.pll1, 0x80000000}, {&ch[0].phy.pll2, 0x80000000}, {&ch[0].phy.pll4, 0x004d0000}, - {&ch[0].phy.shu[0].b[0].dq[6], 0x06860440}, - {&ch[0].phy.shu[0].b[1].dq[6], 0x06860440}, - {&ch[0].phy.shu[0].ca_cmd[6], 0x068604c0}, + {&ch[0].phy.shu[0].b[0].dq[6], 0x06C60740}, + {&ch[0].phy.shu[0].b[1].dq[6], 0x06C60740}, + {&ch[0].phy.shu[0].ca_cmd[6], 0x06C607C0}, {&ch[0].phy.ca_dll_fine_tune[3], 0x000ba000}, {&ch[0].phy.b[0].dll_fine_tune[3], 0x0002e800}, {&ch[0].phy.b[1].dll_fine_tune[3], 0x0002e800}, @@ -208,14 +208,6 @@ {&ch[0].phy.ca_cmd[7], 0x00000040}, {&ch[0].ao.ckectrl, 0x00100400}, {&ch[1].ao.ckectrl, 0x00100400}, - {&ch[0].phy.shu[0].pll[5], 0x7b000003}, - {&ch[0].phy.shu[0].pll[7], 0x7b000003}, - {&ch[0].phy.shu[0].pll[14], 0x00000002}, - {&ch[0].phy.shu[0].pll20, 0x00000002}, - {&ch[0].phy.shu[0].pll[14], 0x02080002}, - {&ch[0].phy.shu[0].pll20, 0x02080002}, - {&ch[0].phy.shu[0].pll[15], 0x0c030000}, - {&ch[0].phy.shu[0].pll21, 0x0c030000}, {&ch[1].phy.shu[0].pll[4], 0x00000000}, {&ch[1].phy.shu[0].pll[6], 0x00000000}, {&ch[1].phy.misc_shu_opt, 0x00090909}, @@ -224,15 +216,15 @@ {&ch[1].ao.dvfsdll, 0x00000000}, {&ch[1].phy.shu[0].ca_dll[0], 0xc0778609}, {&ch[1].phy.shu[0].ca_dll[1], 0x0004e101}, - {&ch[1].phy.shu[0].ca_cmd[6], 0x00060440}, + {&ch[1].phy.shu[0].ca_cmd[6], 0x00060740}, {&ch[1].phy.b[0].dq[7], 0x00000055}, {&ch[1].phy.b[1].dq[7], 0x00000055}, {&ch[1].phy.ca_cmd[7], 0x00000055}, {&ch[1].phy.ca_cmd[2], 0x00200000}, {&ch[1].phy.misc_cg_ctrl0, 0x0000000f}, - {&ch[1].phy.shu[0].b[0].dq[6], 0x00060440}, - {&ch[1].phy.shu[0].b[1].dq[6], 0x00060440}, - {&ch[1].phy.shu[0].ca_cmd[6], 0x00060440}, + {&ch[1].phy.shu[0].b[0].dq[6], 0x00060740}, + {&ch[1].phy.shu[0].b[1].dq[6], 0x00060740}, + {&ch[1].phy.shu[0].ca_cmd[6], 0x00060740}, {&ch[1].phy.pll4, 0x00000000}, {&ch[1].phy.pll1, 0x00000000}, {&ch[1].phy.pll2, 0x00000000}, @@ -247,26 +239,26 @@ {&ch[1].phy.b[1].dll_fine_tune[0], 0x00000000}, {&ch[1].phy.shu[0].pll[8], 0x00040000}, {&ch[1].phy.shu[0].pll[10], 0x00040000}, - {&ch[1].phy.shu[0].pll[5], 0x7b000000}, - {&ch[1].phy.shu[0].pll[7], 0x7b000000}, + {&ch[1].phy.shu[0].pll[5], 0x5c000000}, + {&ch[1].phy.shu[0].pll[7], 0x5c000000}, {&ch[1].phy.ca_dll_fine_tune[0], 0x00000002}, {&ch[1].phy.b[0].dll_fine_tune[0], 0x00000002}, {&ch[1].phy.b[1].dll_fine_tune[0], 0x00000002}, {&ch[1].phy.ca_dll_fine_tune[1], 0x00200000}, {&ch[1].phy.b[0].dll_fine_tune[1], 0x00000000}, {&ch[1].phy.b[1].dll_fine_tune[1], 0x00000000}, - {&ch[1].phy.shu[0].b[0].dq[6], 0x02860440}, - {&ch[1].phy.shu[0].b[1].dq[6], 0x02860440}, - {&ch[1].phy.shu[0].ca_cmd[6], 0x02860440}, + {&ch[1].phy.shu[0].b[0].dq[6], 0x02C60740}, + {&ch[1].phy.shu[0].b[1].dq[6], 0x02C60740}, + {&ch[1].phy.shu[0].ca_cmd[6], 0x02C60740}, {&ch[1].phy.ca_dll_fine_tune[0], 0x0000000a}, {&ch[1].phy.b[0].dll_fine_tune[0], 0x0000000a}, {&ch[1].phy.b[1].dll_fine_tune[0], 0x0000000a}, {&ch[1].phy.pll1, 0x80000000}, {&ch[1].phy.pll2, 0x80000000}, {&ch[1].phy.pll4, 0x00410000}, - {&ch[1].phy.shu[0].b[0].dq[6], 0x06860440}, - {&ch[1].phy.shu[0].b[1].dq[6], 0x06860440}, - {&ch[1].phy.shu[0].ca_cmd[6], 0x06860440}, + {&ch[1].phy.shu[0].b[0].dq[6], 0x06C60740}, + {&ch[1].phy.shu[0].b[1].dq[6], 0x06C60740}, + {&ch[1].phy.shu[0].ca_cmd[6], 0x06C60740}, {&ch[1].phy.ca_dll_fine_tune[3], 0x0003a000}, {&ch[1].phy.b[0].dll_fine_tune[3], 0x0002e800}, {&ch[1].phy.b[1].dll_fine_tune[3], 0x0002e800}, @@ -286,14 +278,6 @@ {&ch[1].phy.ca_cmd[7], 0x00000040}, {&ch[0].ao.ckectrl, 0x00100400}, {&ch[1].ao.ckectrl, 0x00100400}, - {&ch[1].phy.shu[0].pll[5], 0x00000001}, - {&ch[1].phy.shu[0].pll[7], 0x00000001}, - {&ch[1].phy.shu[0].pll[14], 0x00000002}, - {&ch[1].phy.shu[0].pll20, 0x00000002}, - {&ch[1].phy.shu[0].pll[14], 0x02080000}, - {&ch[1].phy.shu[0].pll20, 0x02080000}, - {&ch[1].phy.shu[0].pll[15], 0x0c030000}, - {&ch[1].phy.shu[0].pll21, 0x0c030000}, {&mt8183_infracfg->dramc_wbr, 0x0000001f}, {&ch[0].ao.drsctrl, 0x20080000}, {&ch[0].ao.ckectrl, 0x08100400}, @@ -431,12 +415,12 @@ {&ch[0].ao.shu[0].rk[1].selph_dq[2], 0x33333333}, {&ch[0].ao.shu[0].rk[1].selph_dq[3], 0x33333333}, {&ch[0].ao.shu[0].dqsg_retry, 0x8120050c}, - {&ch[0].phy.shu[0].b[0].dq[7], 0x00008090}, - {&ch[0].phy.shu[0].b[1].dq[7], 0x00008080}, + {&ch[0].phy.shu[0].b[0].dq[7], 0x0000B090}, + {&ch[0].phy.shu[0].b[1].dq[7], 0x0000B080}, {&ch[0].ao.shu[0].dqs2dq_tx, 0x00000000}, {&ch[0].ao.shu[0].odtctrl, 0xc0010003}, - {&ch[0].phy.shu[0].b[0].dq[7], 0x00008090}, - {&ch[0].phy.shu[0].b[1].dq[7], 0x00008080}, + {&ch[0].phy.shu[0].b[0].dq[7], 0x0000B090}, + {&ch[0].phy.shu[0].b[1].dq[7], 0x0000B080}, {&ch[0].phy.r[0].b[0].rxdvs[2], 0x20000000}, {&ch[0].phy.r[1].b[0].rxdvs[2], 0x20000000}, {&ch[0].phy.r[0].b[1].rxdvs[2], 0x20000000}, @@ -468,10 +452,10 @@ {&ch[0].phy.b[0].dq[6], 0x010352e9}, {&ch[0].phy.b[1].dq[6], 0x010352e9}, {&ch[0].phy.ca_cmd[6], 0x00034269}, - {&ch[0].phy.shu[0].b[0].dq[5], 0x0030000e}, - {&ch[0].phy.b[0].dq[5], 0x82110e00}, - {&ch[0].phy.shu[0].b[1].dq[5], 0x0030000e}, - {&ch[0].phy.b[1].dq[5], 0x82110e00}, + {&ch[0].phy.shu[0].b[0].dq[5], 0x0030000E}, + {&ch[0].phy.b[0].dq[5], 0x82110E00}, + {&ch[0].phy.shu[0].b[1].dq[5], 0x0030000E}, + {&ch[0].phy.b[1].dq[5], 0x82110E00}, {&ch[0].phy.b[0].dq[8], 0x00000007}, {&ch[0].phy.b[1].dq[8], 0x00000007}, {&ch[0].phy.ca_cmd[9], 0x00010007}, @@ -502,16 +486,16 @@ {&ch[0].phy.ca_cmd[8], 0x00080a0a}, {&ch[0].ao.shu[0].misc, 0x0000f132}, {&ch[0].ao.shu[0].dqsg, 0x02a19800}, - {&ch[0].phy.shu[0].b[0].dq[5], 0x0030000e}, - {&ch[0].phy.shu[0].b[1].dq[5], 0x0030000e}, + {&ch[0].phy.shu[0].b[0].dq[5], 0x0030000E}, + {&ch[0].phy.shu[0].b[1].dq[5], 0x0030000E}, {&ch[0].phy.shu[0].ca_cmd[5], 0x00000000}, {&mt8183_infracfg->dramc_wbr, 0x00000000}, - {&ch[0].phy.shu[0].b[0].dq[6], 0x06860440}, - {&ch[0].phy.shu[0].b[1].dq[6], 0x06860440}, - {&ch[0].phy.shu[0].ca_cmd[6], 0x068604c0}, - {&ch[1].phy.shu[0].b[0].dq[6], 0x06860440}, - {&ch[1].phy.shu[0].b[1].dq[6], 0x06860440}, - {&ch[1].phy.shu[0].ca_cmd[6], 0x06860440}, + {&ch[0].phy.shu[0].b[0].dq[6], 0x06C60740}, + {&ch[0].phy.shu[0].b[1].dq[6], 0x06C60740}, + {&ch[0].phy.shu[0].ca_cmd[6], 0x06C607C0}, + {&ch[1].phy.shu[0].b[0].dq[6], 0x06C60740}, + {&ch[1].phy.shu[0].b[1].dq[6], 0x06C60740}, + {&ch[1].phy.shu[0].ca_cmd[6], 0x06C60740}, {&mt8183_infracfg->dramc_wbr, 0x0000001f}, {&ch[0].ao.shu[0].impcal1, 0x81080004}, {&ch[0].ao.srefctrl, 0x4840f000}, @@ -600,10 +584,10 @@ /* dramc duty calibration */ {&ch[0].phy.shu[0].rk[0].ca_cmd[1], 0x00000000}, - {&ch[0].phy.shu[0].rk[0].ca_cmd[0], 0x00000000}, + {&ch[0].phy.shu[0].rk[0].ca_cmd[0], 0x11000000}, {&ch[0].phy.shu[0].rk[1].ca_cmd[1], 0x00000000}, - {&ch[0].phy.shu[0].rk[1].ca_cmd[0], 0x00000000}, - {&ch[0].phy.shu[0].ca_cmd[3], 0x00000400}, + {&ch[0].phy.shu[0].rk[1].ca_cmd[0], 0x11000000}, + {&ch[0].phy.shu[0].ca_cmd[3], 0x00000600}, {&ch[0].phy.shu[0].rk[0].b[0].dq[1], 0x00110000}, {&ch[0].phy.shu[0].rk[0].b[1].dq[1], 0x00110000}, {&ch[0].phy.shu[0].rk[1].b[0].dq[1], 0x00110000}, diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index bb617f9..4d05dd0 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -272,10 +272,10 @@ { for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { clrsetbits_le32(&ch[chn].ao.shu[0].actim[3], - 0xff << 16, 0x64 << 16); + 0xff << 16, 0x48 << 16); clrbits_le32(&ch[chn].ao.shu[0].ac_time_05t, 0x1 << 2); clrsetbits_le32(&ch[chn].ao.shu[0].actim[4], - 0x3ff << 0, 0x77 << 0); + 0x3ff << 0, 0x5B << 0); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/30613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3ac04080b32a84b8451910d309b43f2f1921d9a Gerrit-Change-Number: 30613 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: drivers/spi/acpi: Support power resource as parent in device tree
by Tim Wawrzynczak (Code Review) 11 Mar '20

11 Mar '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35076 ) Change subject: drivers/spi/acpi: Support power resource as parent in device tree ...................................................................... drivers/spi/acpi: Support power resource as parent in device tree This allows supporting an independent power resource for SPI ACPI devices, so that the power resource configuration can be refactored out of individual drivers and coalesced into a separate one. Change-Id: Ib1e52a0f31d430637c9d819e231f9c4af6c68672 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/drivers/spi/acpi/acpi.c 1 file changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/35076/1 diff --git a/src/drivers/spi/acpi/acpi.c b/src/drivers/spi/acpi/acpi.c index 5ae010f..07f1a4b 100644 --- a/src/drivers/spi/acpi/acpi.c +++ b/src/drivers/spi/acpi/acpi.c @@ -23,6 +23,7 @@ #include <stdint.h> #include <string.h> #include "chip.h" +#include "drivers/generic/power_resource/chip.h" static int spi_acpi_get_bus(const struct device *dev) { @@ -73,8 +74,19 @@ static void spi_acpi_fill_ssdt_generator(struct device *dev) { + const int parent_is_power_resource = + CONFIG(DRIVERS_GENERIC_POWER_RESOURCE) && + (dev->bus && dev->bus->children == dev && + dev->bus->dev->chip_ops == &drivers_generic_power_resource_ops); + /* + * Because the power resource is a "pseudo-device", we don't want it + * to be included in the ACPI path + */ + const char *pr_scope = parent_is_power_resource ? + acpi_device_scope(dev->bus->dev) : + NULL; struct drivers_spi_acpi_config *config = dev->chip_info; - const char *scope = acpi_device_scope(dev); + const char *scope = (pr_scope == NULL) ? acpi_device_scope(dev) : pr_scope; const char *path = acpi_device_path(dev); struct acpi_spi spi = { .device_select = dev->path.spi.cs, @@ -184,6 +196,9 @@ acpi_device_path(dev)); acpi_add_device_power_resource("PRIC"); + } else if (parent_is_power_resource) { + /* Parent device is a power resource, so set up _PR0/_PR3 */ + acpi_add_device_power_resource(acpi_device_path(dev->bus->dev)); } acpigen_pop_len(); /* Device */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1e52a0f31d430637c9d819e231f9c4af6c68672 Gerrit-Change-Number: 35076 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

1 3

Change in coreboot[master]: drivers/i2c/generic: Support power resource as parent in device tree
by Tim Wawrzynczak (Code Review) 11 Mar '20

11 Mar '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35075 ) Change subject: drivers/i2c/generic: Support power resource as parent in device tree ...................................................................... drivers/i2c/generic: Support power resource as parent in device tree This allows supporting an independent power resource for I2C generic devices, so that the power resource configuration can be refactored out of individual drivers and coalesced into a separate one. Change-Id: I7554ab4fef88ffea0d3423ea27bb18a56b7f4de5 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/drivers/i2c/generic/generic.c 1 file changed, 16 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/35075/1 diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 27ff9ff..a3411b0 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -23,6 +23,7 @@ #include <stdint.h> #include <string.h> #include "chip.h" +#include "drivers/generic/power_resource/chip.h" #if CONFIG(HAVE_ACPI_TABLES) @@ -59,7 +60,18 @@ void (*callback)(struct device *dev), struct drivers_i2c_generic_config *config) { - const char *scope = acpi_device_scope(dev); + const int parent_is_power_resource = + CONFIG(DRIVERS_GENERIC_POWER_RESOURCE) && + (dev->bus && dev->bus->children == dev && + dev->bus->dev->chip_ops == &drivers_generic_power_resource_ops); + /* + * Because the power resource is a "pseudo-device", we don't want it + * to be included in the ACPI path + */ + const char *pr_scope = parent_is_power_resource ? + acpi_device_scope(dev->bus->dev) : + NULL; + const char *scope = (pr_scope == NULL) ? acpi_device_scope(dev) : pr_scope; struct acpi_i2c i2c = { .address = dev->path.i2c.device, .mode_10bit = dev->path.i2c.mode_10bit, @@ -163,7 +175,9 @@ acpi_device_path(dev)); acpi_add_device_power_resource("PRIC"); - + } else if (parent_is_power_resource) { + /* Parent device is a power resource, so set up _PR0/_PR3 */ + acpi_add_device_power_resource(acpi_device_path(dev->bus->dev)); } /* Callback if any. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7554ab4fef88ffea0d3423ea27bb18a56b7f4de5 Gerrit-Change-Number: 35075 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: device: Allow scan_generic_bus to recurse on pseudo-devices
by Tim Wawrzynczak (Code Review) 11 Mar '20

11 Mar '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35074 ) Change subject: device: Allow scan_generic_bus to recurse on pseudo-devices ...................................................................... device: Allow scan_generic_bus to recurse on pseudo-devices To handle cases of pseudo-devices containing a child device, e.g., power resources, recurse onto them, treating them like a bus. Change-Id: Ia8442939ef1e840c112ad4dd23e324afd99ff7d3 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/device/root_device.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/35074/1 diff --git a/src/device/root_device.c b/src/device/root_device.c index f8e2907..ec24ff5 100644 --- a/src/device/root_device.c +++ b/src/device/root_device.c @@ -112,6 +112,13 @@ printk(BIOS_DEBUG, "%s %s\n", dev_path(child), child->enabled ? "enabled" : "disabled"); + + /* + * To handle cases of pseudo-devices containing a child + * device when it's not explicitly a bus, e.g., power + * resources, we recurse into them. + */ + scan_generic_bus(child); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/35074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8442939ef1e840c112ad4dd23e324afd99ff7d3 Gerrit-Change-Number: 35074 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: drivers/generic: Add new driver for power resource pseudo-device
by Tim Wawrzynczak (Code Review) 11 Mar '20

11 Mar '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35073 ) Change subject: drivers/generic: Add new driver for power resource pseudo-device ...................................................................... drivers/generic: Add new driver for power resource pseudo-device There is some duplication of fields dealing with ACPI power resources (see drivers/i2c/generic.c, also used by drivers/i2c/hid, as well as drivers/spi/acpi). This CL creates a new driver for this pseudo-device. This patch allows a new style of dealing with power resources in the device tree: device pci 00.0 chip drivers/generic/power_resource register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A1)" device generic 0 on chip drivers/i2c/generic register ... end end end end and then the power resource driver does most of the work. This should make it easier to support other drivers requiring ACPI power resources in the future (see the diff in the two changed here). Change-Id: Id9d66fedd342eb5359d90d9778c515e7aa2de1d7 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- A src/drivers/generic/power_resource/Kconfig A src/drivers/generic/power_resource/Makefile.inc A src/drivers/generic/power_resource/chip.h A src/drivers/generic/power_resource/power_resource.c 4 files changed, 128 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/35073/1 diff --git a/src/drivers/generic/power_resource/Kconfig b/src/drivers/generic/power_resource/Kconfig new file mode 100644 index 0000000..447edb9 --- /dev/null +++ b/src/drivers/generic/power_resource/Kconfig @@ -0,0 +1,5 @@ +# TODO: once everything is moved to the new power resource structure, +# those drivers that use it should auto-select this config option +config DRIVERS_GENERIC_POWER_RESOURCE + bool + depends on HAVE_ACPI_TABLES diff --git a/src/drivers/generic/power_resource/Makefile.inc b/src/drivers/generic/power_resource/Makefile.inc new file mode 100644 index 0000000..2120ef1 --- /dev/null +++ b/src/drivers/generic/power_resource/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_GENERIC_POWER_RESOURCE) += power_resource.c diff --git a/src/drivers/generic/power_resource/chip.h b/src/drivers/generic/power_resource/chip.h new file mode 100644 index 0000000..e698296 --- /dev/null +++ b/src/drivers/generic/power_resource/chip.h @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GENERIC_POWER_RESOURCE_CHIP_H__ +#define __GENERIC_POWER_RESOURCE_CHIP_H__ + +#include <device/device.h> +#include <arch/acpi_device.h> + +extern struct chip_operations drivers_generic_power_resource_ops; + +struct drivers_generic_power_resource_config { + /* GPIO used to take device out of reset or to put it into reset. */ + struct acpi_gpio reset_gpio; + /* Delay to be inserted after device is taken out of reset. */ + unsigned int reset_delay_ms; + /* Delay to be inserted after device is put into reset. */ + unsigned int reset_off_delay_ms; + /* GPIO used to enable device. */ + struct acpi_gpio enable_gpio; + /* Delay to be inserted after device is enabled. */ + unsigned int enable_delay_ms; + /* Delay to be inserted after device is disabled. */ + unsigned int enable_off_delay_ms; + /* GPIO used to stop operation of device. */ + struct acpi_gpio stop_gpio; + /* Delay to be inserted after disabling stop. */ + unsigned int stop_delay_ms; + /* Delay to be inserted after enabling stop. */ + unsigned int stop_off_delay_ms; + /* ACPI device name */ + char acpi_name[5]; +}; + +#endif /* __GENERIC_POWER_RESOURCE_CHIP_H__ */ diff --git a/src/drivers/generic/power_resource/power_resource.c b/src/drivers/generic/power_resource/power_resource.c new file mode 100644 index 0000000..d08c1a2 --- /dev/null +++ b/src/drivers/generic/power_resource/power_resource.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/path.h> +#include <console/console.h> +#include <string.h> +#include "chip.h" + +static void power_resource_fill_ssdt(struct device *dev) +{ + bool ret; + struct drivers_generic_power_resource_config *config = dev->chip_info; + const struct acpi_power_res_params power_res_params = { + &config->reset_gpio, + config->reset_delay_ms, + config->reset_off_delay_ms, + &config->enable_gpio, + config->enable_delay_ms, + config->enable_off_delay_ms, + &config->stop_gpio, + config->stop_delay_ms, + config->stop_off_delay_ms + }; + + ret = acpi_declare_scoped_power_resource(acpi_device_scope(dev), + acpi_device_name(dev), + &power_res_params); + if (!ret) + printk(BIOS_ERR, "Failed to add power resource %s\n", + acpi_device_name(dev)); + +} + +static const char *power_resource_acpi_name(const struct device *dev) +{ + static unsigned int count; + struct drivers_generic_power_resource_config *config = dev->chip_info; + + if (config->acpi_name[0] == '\0') + snprintf(config->acpi_name, sizeof(config->acpi_name), "PR%02X", count++); + + return config->acpi_name; +} + +static struct device_operations power_resource_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .scan_bus = scan_generic_bus, + .acpi_name = power_resource_acpi_name, + .acpi_fill_ssdt_generator = power_resource_fill_ssdt +}; + +static void power_resource_enable(struct device *dev) +{ + dev->ops = &power_resource_ops; +} + +struct chip_operations drivers_generic_power_resource_ops = { + CHIP_NAME("Power Resource") + .enable_dev = power_resource_enable +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/35073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9d66fedd342eb5359d90d9778c515e7aa2de1d7 Gerrit-Change-Number: 35073 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

3 10

Change in coreboot[master]: drivers/generic: Add new driver for power resource pseudo device
by Tim Wawrzynczak (Code Review) 11 Mar '20

11 Mar '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35036 ) Change subject: drivers/generic: Add new driver for power resource pseudo device ...................................................................... drivers/generic: Add new driver for power resource pseudo device There is some duplication of fields dealing with ACPI power resources (see drivers/i2c/generic.c, also used by drivers/i2c/hid, as well as drivers/spi/acpi). This CL creates a new driver for this pseudo-device. This patch allows a new style of dealing with power resources in the device tree: device pci 00.0 chip drivers/generic/power_resource register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A1)" device generic 0 on chip drivers/i2c/generic register ... end end end end and then the power resource driver does most of the work. This should make it easier to support other drivers requiring ACPI power resources in the future (see the diff in the two changed here). I tested this patch on a device using ACPI power resources, and it was successfully able to invoke the _ON and _OFF routines for the device, both with the new-style and old-style way of creating power resources. My hope would be to update device trees in later patches to accomodate this new style, and then deprecate the old style. Change-Id: I358c48f4d4e4c4ef591ecf09ea9e9488c2652c96 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/arch/x86/acpi_device.c M src/arch/x86/acpigen.c M src/arch/x86/include/arch/acpi_device.h M src/arch/x86/include/arch/acpigen.h M src/device/root_device.c M src/drivers/i2c/generic/generic.c M src/drivers/spi/acpi/acpi.c 7 files changed, 122 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/35036/1 diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c index 47bcc52..40e9677 100644 --- a/src/arch/x86/acpi_device.c +++ b/src/arch/x86/acpi_device.c @@ -494,20 +494,12 @@ acpi_device_fill_len(desc_length); } -/* PowerResource() with Enable and/or Reset control */ -void acpi_device_add_power_res(const struct acpi_power_res_params *params) +/* Adds _STA, _ON, and _OFF methods to a power resource, based on config */ +static void acpi_add_power_res_methods(const struct acpi_power_res_params *config) { - static const char *power_res_dev_states[] = { "_PR0", "_PR3" }; - unsigned int reset_gpio = params->reset_gpio->pins[0]; - unsigned int enable_gpio = params->enable_gpio->pins[0]; - unsigned int stop_gpio = params->stop_gpio->pins[0]; - - if (!reset_gpio && !enable_gpio && !stop_gpio) - return; - - /* PowerResource (PRIC, 0, 0) */ - acpigen_write_power_res("PRIC", 0, 0, power_res_dev_states, - ARRAY_SIZE(power_res_dev_states)); + const unsigned int reset_gpio = config->reset_gpio->pins[0]; + const unsigned int enable_gpio = config->enable_gpio->pins[0]; + const unsigned int stop_gpio = config->stop_gpio->pins[0]; /* Method (_STA, 0, NotSerialized) { Return (0x1) } */ acpigen_write_STA(0x1); @@ -515,44 +507,75 @@ /* Method (_ON, 0, Serialized) */ acpigen_write_method_serialized("_ON", 0); if (reset_gpio) - acpigen_enable_tx_gpio(params->reset_gpio); + acpigen_enable_tx_gpio(config->reset_gpio); if (enable_gpio) { - acpigen_enable_tx_gpio(params->enable_gpio); - if (params->enable_delay_ms) - acpigen_write_sleep(params->enable_delay_ms); + acpigen_enable_tx_gpio(config->enable_gpio); + if (config->enable_delay_ms) + acpigen_write_sleep(config->enable_delay_ms); } if (reset_gpio) { - acpigen_disable_tx_gpio(params->reset_gpio); - if (params->reset_delay_ms) - acpigen_write_sleep(params->reset_delay_ms); + acpigen_disable_tx_gpio(config->reset_gpio); + if (config->reset_delay_ms) + acpigen_write_sleep(config->reset_delay_ms); } if (stop_gpio) { - acpigen_disable_tx_gpio(params->stop_gpio); - if (params->stop_delay_ms) - acpigen_write_sleep(params->stop_delay_ms); + acpigen_disable_tx_gpio(config->stop_gpio); + if (config->stop_delay_ms) + acpigen_write_sleep(config->stop_delay_ms); } - acpigen_pop_len(); /* _ON method */ + + acpigen_pop_len(); /* _ON method */ /* Method (_OFF, 0, Serialized) */ acpigen_write_method_serialized("_OFF", 0); if (stop_gpio) { - acpigen_enable_tx_gpio(params->stop_gpio); - if (params->stop_off_delay_ms) - acpigen_write_sleep(params->stop_off_delay_ms); + acpigen_enable_tx_gpio(config->stop_gpio); + if (config->stop_off_delay_ms) + acpigen_write_sleep(config->stop_off_delay_ms); } if (reset_gpio) { - acpigen_enable_tx_gpio(params->reset_gpio); - if (params->reset_off_delay_ms) - acpigen_write_sleep(params->reset_off_delay_ms); + acpigen_enable_tx_gpio(config->reset_gpio); + if (config->reset_off_delay_ms) + acpigen_write_sleep(config->reset_off_delay_ms); } if (enable_gpio) { - acpigen_disable_tx_gpio(params->enable_gpio); - if (params->enable_off_delay_ms) - acpigen_write_sleep(params->enable_off_delay_ms); + acpigen_disable_tx_gpio(config->enable_gpio); + if (config->enable_off_delay_ms) + acpigen_write_sleep(config->enable_off_delay_ms); } - acpigen_pop_len(); /* _OFF method */ - acpigen_pop_len(); /* PowerResource PRIC */ + acpigen_pop_len(); /* _OFF method */ +} + +void acpi_add_power_res(const char *power_resource_name, + const struct acpi_power_res_params *config) +{ + const unsigned int reset_gpio = config->reset_gpio->pins[0]; + const unsigned int enable_gpio = config->enable_gpio->pins[0]; + const unsigned int stop_gpio = config->stop_gpio->pins[0]; + + if (!reset_gpio && !enable_gpio && !stop_gpio) + return; + + /* PowerResource (name, 0, 0) */ + acpigen_write_power_res(power_resource_name, 0, 0); + acpi_add_power_res_methods(config); + acpigen_pop_len(); /* PowerResource */ +} + +void acpi_add_power_states(const char *power_resource_name) +{ + static const char *dev_states[] = { "_PR0", "_PR3" }; + acpigen_write_power_states(power_resource_name, dev_states, 2); +} + +void acpi_add_scoped_power_res(const char *scope, + const char *name, + const struct acpi_power_res_params *config) +{ + acpigen_write_scope(scope); + acpi_add_power_res(name, config); + acpigen_pop_len(); /* Scope */ } static void acpi_dp_write_array(const struct acpi_dp *array); diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index f9af102..553c4ff 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -1107,22 +1107,26 @@ acpigen_pop_len(); } +void acpigen_write_power_states(const char *power_resource_name, + const char *power_states[], + size_t power_states_count) +{ + size_t i; + for (i = 0; i < power_states_count; i++) { + acpigen_write_name(power_states[i]); + acpigen_write_package(1); + acpigen_emit_namestring(power_resource_name); + acpigen_pop_len(); /* Package */ + } +} + /* * Name (_PRx, Package(One) { name }) * ... * PowerResource (name, level, order) */ -void acpigen_write_power_res(const char *name, uint8_t level, uint16_t order, - const char *dev_states[], size_t dev_states_count) +void acpigen_write_power_res(const char *name, uint8_t level, uint16_t order) { - size_t i; - for (i = 0; i < dev_states_count; i++) { - acpigen_write_name(dev_states[i]); - acpigen_write_package(1); - acpigen_emit_simple_namestring(name); - acpigen_pop_len(); /* Package */ - } - acpigen_emit_ext_op(POWER_RES_OP); acpigen_write_len_f(); diff --git a/src/arch/x86/include/arch/acpi_device.h b/src/arch/x86/include/arch/acpi_device.h index d74af9d..6c7993f 100644 --- a/src/arch/x86/include/arch/acpi_device.h +++ b/src/arch/x86/include/arch/acpi_device.h @@ -403,7 +403,19 @@ * Enable - Enable / disable power to device. * Stop - Stop / start operation of device. */ -void acpi_device_add_power_res(const struct acpi_power_res_params *params); +void acpi_add_power_res(const char *power_resource_name, + const struct acpi_power_res_params *config); + +/* Adds a PowerResource (as above), but in its own scope */ +void acpi_add_scoped_power_res(const char *scope, + const char *name, + const struct acpi_power_res_params *config); + +/* + * Write out _PR0 and _PR3 methods for a device, using power_resource_name + * as the PowerResource to reference +*/ +void acpi_add_power_states(const char *power_resource_name); /* * Writing Device Properties objects via _DSD diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index db003fe..242b1e1 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -359,8 +359,10 @@ void acpigen_write_mainboard_resources(const char *scope, const char *name); void acpigen_write_irq(u16 mask); void acpigen_write_uuid(const char *uuid); -void acpigen_write_power_res(const char *name, uint8_t level, uint16_t order, - const char *dev_states[], size_t dev_states_count); +void acpigen_write_power_res(const char *name, uint8_t level, uint16_t order); +void acpigen_write_power_states(const char *power_resource_name, + const char *power_states[], + size_t power_states_count); void acpigen_write_sleep(uint64_t sleep_ms); void acpigen_write_store(void); void acpigen_write_store_ops(uint8_t src, uint8_t dst); diff --git a/src/device/root_device.c b/src/device/root_device.c index f8e2907..ec24ff5 100644 --- a/src/device/root_device.c +++ b/src/device/root_device.c @@ -112,6 +112,13 @@ printk(BIOS_DEBUG, "%s %s\n", dev_path(child), child->enabled ? "enabled" : "disabled"); + + /* + * To handle cases of pseudo-devices containing a child + * device when it's not explicitly a bus, e.g., power + * resources, we recurse into them. + */ + scan_generic_bus(child); } } diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 9b4f00d..308f200 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -23,6 +23,7 @@ #include <stdint.h> #include <string.h> #include "chip.h" +#include "drivers/generic/power_resource/chip.h" #if CONFIG(HAVE_ACPI_TABLES) @@ -59,7 +60,13 @@ void (*callback)(struct device *dev), struct drivers_i2c_generic_config *config) { - const char *scope = acpi_device_scope(dev); + const int parent_is_power_resource = + (dev->bus && dev->bus->children == dev && + dev->bus->dev->chip_ops == &drivers_generic_power_resource_ops); + const char *pr_scope = parent_is_power_resource ? + acpi_device_scope(dev->bus->dev) : + NULL; + const char *scope = (pr_scope == NULL) ? acpi_device_scope(dev) : pr_scope; struct acpi_i2c i2c = { .address = dev->path.i2c.device, .mode_10bit = dev->path.i2c.mode_10bit, @@ -157,7 +164,11 @@ config->stop_delay_ms, config->stop_off_delay_ms }; - acpi_device_add_power_res(&power_res_params); + acpi_add_power_res("PRIC", &power_res_params); + acpi_add_power_states("PRIC"); + } else if (parent_is_power_resource) { + /* Parent device is a power resource, so set up _PR0/_PR3 */ + acpi_add_power_states(acpi_device_path(dev->bus->dev)); } /* Callback if any. */ diff --git a/src/drivers/spi/acpi/acpi.c b/src/drivers/spi/acpi/acpi.c index 7c8a887..f7cb2e1 100644 --- a/src/drivers/spi/acpi/acpi.c +++ b/src/drivers/spi/acpi/acpi.c @@ -23,6 +23,7 @@ #include <stdint.h> #include <string.h> #include "chip.h" +#include "drivers/generic/power_resource/chip.h" static int spi_acpi_get_bus(const struct device *dev) { @@ -73,13 +74,19 @@ static void spi_acpi_fill_ssdt_generator(struct device *dev) { + const int parent_is_power_resource = + (dev->bus && dev->bus->children == dev && + dev->bus->dev->chip_ops == &drivers_generic_power_resource_ops); + const char *pr_scope = parent_is_power_resource ? + acpi_device_scope(dev->bus->dev) : + NULL; struct drivers_spi_acpi_config *config = dev->chip_info; const char *scope = acpi_device_scope(dev); const char *path = acpi_device_path(dev); struct acpi_spi spi = { .device_select = dev->path.spi.cs, .speed = config->speed ? : 1 * MHz, - .resource = scope, + .resource = (pr_scope != NULL) ? pr_scope : scope, .device_select_polarity = SPI_POLARITY_LOW, .wire_mode = SPI_4_WIRE_MODE, .data_bit_length = 8, @@ -178,7 +185,11 @@ config->stop_delay_ms, config->stop_off_delay_ms }; - acpi_device_add_power_res(&power_res_params); + acpi_add_power_res("PRIC", &power_res_params); + acpi_add_power_states("PRIC"); + } else if (parent_is_power_resource) { + /* Parent device is a power resource, so set up _PR0/_PR3 */ + acpi_add_power_states(acpi_device_path(dev->bus->dev)); } acpigen_pop_len(); /* Device */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I358c48f4d4e4c4ef591ecf09ea9e9488c2652c96 Gerrit-Change-Number: 35036 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

3 16

Change in ...coreboot[master]: TEMP: NOT FOR REVIEW: Use absolute jump address
by Nitheesh Sekar (Code Review) 11 Mar '20

11 Mar '20

Nitheesh Sekar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32388 Change subject: TEMP: NOT FOR REVIEW: Use absolute jump address ...................................................................... TEMP: NOT FOR REVIEW: Use absolute jump address When the qcs405 soc jumps from qc_sec to bootblock, the pc is at 0x0 address mapped to actual SRAM address(0x8c30000). The mapping happens in a hardware block 'boot-remapper' only for a maximum of 128K possible. If the bootflow continues from the 0x0 address, bootblock references variable beyond 128K crashing the boot. So change the PC to start execting from the absolute address instead. Change-Id: I004798ac73c14a431f2d561099a30295c5675abc Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/arch/arm64/armv8/bootblock.S 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/32388/1 diff --git a/src/arch/arm64/armv8/bootblock.S b/src/arch/arm64/armv8/bootblock.S index e5758bc..7dc8b0f 100644 --- a/src/arch/arm64/armv8/bootblock.S +++ b/src/arch/arm64/armv8/bootblock.S @@ -23,7 +23,9 @@ ENTRY(_start) /* Initialize PSTATE, SCTLR and caches to clean state, set up stack. */ - bl arm64_init_cpu + ldr x15, =arm64_init_cpu + blr x15 - bl main + ldr x15, =main + blr x15 ENDPROC(_start) -- To view, visit https://review.coreboot.org/c/coreboot/+/32388 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I004798ac73c14a431f2d561099a30295c5675abc Gerrit-Change-Number: 32388 Gerrit-PatchSet: 1 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: qcs405: Add 500 ms delay
by Nitheesh Sekar (Code Review) 11 Mar '20

11 Mar '20

Nitheesh Sekar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34931 ) Change subject: qcs405: Add 500 ms delay ...................................................................... qcs405: Add 500 ms delay Add 500 ms delay before writing the ddr training data to the spi flash. Actual delay has to be calculated based on the calibrations taken during waveforms. Change-Id: Ic956d73ad39481beadc0f3496c2f643b12694702 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/common/qclib.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/34931/1 diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c index ac80a76..f8be4f3 100644 --- a/src/soc/qualcomm/common/qclib.c +++ b/src/soc/qualcomm/common/qclib.c @@ -16,6 +16,7 @@ #include <console/cbmem_console.h> #include <cbmem.h> #include <boardid.h> +#include <delay.h> #include <string.h> #include <fmap.h> #include <assert.h> @@ -82,6 +83,8 @@ } else if (!strncmp(QCLIB_TE_DDR_TRAINING_DATA, te->name, sizeof(te->name))) { + mdelay(500); //Add 500 ms delay + assert(fmap_overwrite_area(QCLIB_FR_DDR_TRAINING_DATA, (const void *)te->blob_address, te->size)); -- To view, visit https://review.coreboot.org/c/coreboot/+/34931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic956d73ad39481beadc0f3496c2f643b12694702 Gerrit-Change-Number: 34931 Gerrit-PatchSet: 1 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-MessageType: newchange

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