coreboot-gerrit July 2019

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Change in ...coreboot[master]: src/mainboard/asus/am1i-a/buildOpts.c: uncomment the RAM speed-relate...
by Mike Banon (Code Review) 11 Apr '20

11 Apr '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33918 Change subject: src/mainboard/asus/am1i-a/buildOpts.c: uncomment the RAM speed-related defines ...................................................................... src/mainboard/asus/am1i-a/buildOpts.c: uncomment the RAM speed-related defines Not sure why they have been commented out. Bringing them back does not affect a system operation, and they may be useful later while fixing the low RAM speeds. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Ic0468d329c6efa9abffc8859a542aae0cf702863 --- M src/mainboard/asus/am1i-a/buildOpts.c 1 file changed, 25 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/33918/1 diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index 643b306..cba0894 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -265,31 +265,31 @@ #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -//#define DDR400_FREQUENCY 200 ///< DDR 400 -//#define DDR533_FREQUENCY 266 ///< DDR 533 -//#define DDR667_FREQUENCY 333 ///< DDR 667 -//#define DDR800_FREQUENCY 400 ///< DDR 800 -//#define DDR1066_FREQUENCY 533 ///< DDR 1066 -//#define DDR1333_FREQUENCY 667 ///< DDR 1333 -//#define DDR1600_FREQUENCY 800 ///< DDR 1600 -//#define DDR1866_FREQUENCY 933 ///< DDR 1866 -//#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -//#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -//#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency -// -///* QUANDRANK_TYPE*/ -//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM -// -///* USER_MEMORY_TIMING_MODE */ -//#define TIMING_MODE_AUTO 0 ///< Use best rate possible -//#define TIMING_MODE_LIMITED 1 ///< Set user top limit -//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed -// -///* POWER_DOWN_MODE */ -//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define DDR2100_FREQUENCY 1050 ///< DDR 2100 +#define DDR2133_FREQUENCY 1066 ///< DDR 2133 +#define DDR2400_FREQUENCY 1200 ///< DDR 2400 +#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency + +/* QUANDRANK_TYPE*/ +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM + +/* USER_MEMORY_TIMING_MODE */ +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed + +/* POWER_DOWN_MODE */ +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode /* * Agesa optional capabilities selection. -- To view, visit https://review.coreboot.org/c/coreboot/+/33918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0468d329c6efa9abffc8859a542aae0cf702863 Gerrit-Change-Number: 33918 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/mainboard/sony: Add Sony VPCEH2K1E
by Angel Pons (Code Review) 10 Apr '20

10 Apr '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30973 Change subject: src/mainboard/sony: Add Sony VPCEH2K1E ...................................................................... src/mainboard/sony: Add Sony VPCEH2K1E Run autoport. It has a Nvidia graphics card and a Nuvoton NPCE795 EC. Change-Id: Ibf324f1276611ab06d5906cab87ad538bfad7218 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/sony/vpceh2k1e/Kconfig A src/mainboard/sony/vpceh2k1e/Kconfig.name A src/mainboard/sony/vpceh2k1e/Makefile.inc A src/mainboard/sony/vpceh2k1e/acpi/ec.asl A src/mainboard/sony/vpceh2k1e/acpi/platform.asl A src/mainboard/sony/vpceh2k1e/acpi/superio.asl A src/mainboard/sony/vpceh2k1e/acpi_tables.c A src/mainboard/sony/vpceh2k1e/board_info.txt A src/mainboard/sony/vpceh2k1e/devicetree.cb A src/mainboard/sony/vpceh2k1e/dsdt.asl A src/mainboard/sony/vpceh2k1e/gpio.c A src/mainboard/sony/vpceh2k1e/hda_verb.c A src/mainboard/sony/vpceh2k1e/mainboard.c A src/mainboard/sony/vpceh2k1e/romstage.c 14 files changed, 700 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/30973/1 diff --git a/src/mainboard/sony/vpceh2k1e/Kconfig b/src/mainboard/sony/vpceh2k1e/Kconfig new file mode 100644 index 0000000..7d1f6ca --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/Kconfig @@ -0,0 +1,44 @@ +if BOARD_SONY_VPCEH2K1E + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_4096 + select CPU_INTEL_SOCKET_RPGA989 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default sony_corporation/vpceh2k1e + +config MAINBOARD_PART_NUMBER + string + default "VPCEH2K1E" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x908b + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x104d + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/sony/vpceh2k1e/Kconfig.name b/src/mainboard/sony/vpceh2k1e/Kconfig.name new file mode 100644 index 0000000..3de2fcc --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SONY_VPCEH2K1E + bool "VPCEH2K1E" diff --git a/src/mainboard/sony/vpceh2k1e/Makefile.inc b/src/mainboard/sony/vpceh2k1e/Makefile.inc new file mode 100644 index 0000000..3dae61e --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/Makefile.inc @@ -0,0 +1 @@ +romstage-y += gpio.c diff --git a/src/mainboard/sony/vpceh2k1e/acpi/ec.asl b/src/mainboard/sony/vpceh2k1e/acpi/ec.asl new file mode 100644 index 0000000..9988369 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/acpi/ec.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 23) +/* FIXME: EC support */ +} diff --git a/src/mainboard/sony/vpceh2k1e/acpi/platform.asl b/src/mainboard/sony/vpceh2k1e/acpi/platform.asl new file mode 100644 index 0000000..15d53d9 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/acpi/platform.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + /* FIXME: EC support */ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/sony/vpceh2k1e/acpi/superio.asl b/src/mainboard/sony/vpceh2k1e/acpi/superio.asl new file mode 100644 index 0000000..8bfc1a0 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/acpi/superio.asl @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/sony/vpceh2k1e/acpi_tables.c b/src/mainboard/sony/vpceh2k1e/acpi_tables.c new file mode 100644 index 0000000..7d634a0 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/acpi_tables.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/sony/vpceh2k1e/board_info.txt b/src/mainboard/sony/vpceh2k1e/board_info.txt new file mode 100644 index 0000000..689ca8f --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/board_info.txt @@ -0,0 +1,5 @@ +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n diff --git a/src/mainboard/sony/vpceh2k1e/devicetree.cb b/src/mainboard/sony/vpceh2k1e/devicetree.cb new file mode 100644 index 0000000..d96ae12 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/devicetree.cb @@ -0,0 +1,63 @@ +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.ndid" = "3" + device cpu_cluster 0x0 on + chip cpu/intel/socket_rPGA989 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + device domain 0x0 on + subsystemid 0x104d 0x908b inherit + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "1" + register "gen1_dec" = "0x000c0601" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x00040069" + register "gpi7_routing" = "2" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x9" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge PCI-LPC bridge + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 off end # Internal graphics + end +end diff --git a/src/mainboard/sony/vpceh2k1e/dsdt.asl b/src/mainboard/sony/vpceh2k1e/dsdt.asl new file mode 100644 index 0000000..675703b --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/dsdt.asl @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/sony/vpceh2k1e/gpio.c b/src/mainboard/sony/vpceh2k1e/gpio.c new file mode 100644 index 0000000..5a16e8e --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/gpio.c @@ -0,0 +1,235 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio2 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio5 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio9 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio11 = GPIO_INVERT, + .gpio12 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, + .gpio15 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio49 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/sony/vpceh2k1e/hda_verb.c b/src/mainboard/sony/vpceh2k1e/hda_verb.c new file mode 100644 index 0000000..d2c4fa3 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/hda_verb.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x14f1506e, /* Codec Vendor / Device ID: Conexant */ + 0x104d5a00, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x104d5a00), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x0, 0x19, 0x03211040), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x400001f0), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x03a15030), + + /* NID 0x1c. */ + AZALIA_PIN_CFG(0x0, 0x1c, 0x400001f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x400001f0), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x400001f0), + + /* NID 0x1f. */ + AZALIA_PIN_CFG(0x0, 0x1f, 0x90170110), + + /* NID 0x20. */ + AZALIA_PIN_CFG(0x0, 0x20, 0x400001f0), + + /* NID 0x22. */ + AZALIA_PIN_CFG(0x0, 0x22, 0x400001f0), + + /* NID 0x23. */ + AZALIA_PIN_CFG(0x0, 0x23, 0x90a70150), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/sony/vpceh2k1e/mainboard.c b/src/mainboard/sony/vpceh2k1e/mainboard.c new file mode 100644 index 0000000..08cb738 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/mainboard.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/acpi/ec.h> +#include <console/console.h> +#include <pc80/keyboard.h> + +static void mainboard_init(struct device *dev) +{ + /* FIXME: trim this down or remove if necessary */ + if (0) { + int i; + const u8 dmp[256] = { + /* 00 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x94, 0x94, 0x94, 0x94, 0x94, 0x94, + /* 10 */ 0x94, 0x94, 0x05, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x14, 0xc0, 0x00, + /* 40 */ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x2d, 0x29, 0x00, 0x31, 0x00, 0x00, 0x00, 0x00, + /* 60 */ 0x41, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x6e, 0x0a, 0x28, 0x0a, 0x01, 0x01, 0x26, 0x00, 0x00, 0x00, + /* 70 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 80 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 90 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* a0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* b0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* c0 */ 0x10, 0x02, 0x00, 0x00, 0x09, 0x4a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, + /* d0 */ 0x00, 0xff, 0x00, 0x00, 0x01, 0x00, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x0b, 0x1a, + /* e0 */ 0x28, 0x28, 0x28, 0x00, 0x00, 0x00, 0x58, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* f0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + + printk(BIOS_DEBUG, "Replaying EC dump ..."); + for (i = 0; i < 256; i++) + ec_write (i, dmp[i]); + printk(BIOS_DEBUG, "done\n"); + } + pc_keyboard_init(NO_AUX_DEVICE); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/sony/vpceh2k1e/romstage.c b/src/mainboard/sony/vpceh2k1e/romstage.c new file mode 100644 index 0000000..0e1c365 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/romstage.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1c01); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0601); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 2 }, + { 0, 1, -1 }, + { 1, 1, 3 }, + { 0, 0, -1 }, + { 0, 0, -1 }, + { 0, 0, -1 }, + { 0, 1, -1 }, + { 1, 0, -1 }, + { 0, 0, -1 }, + { 0, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/30973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf324f1276611ab06d5906cab87ad538bfad7218 Gerrit-Change-Number: 30973 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 20

Change in ...coreboot[master]: SKL: Add ACPI brightness control
by Matthew Garrett (Code Review) 28 Mar '20

28 Mar '20

Matthew Garrett has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32549 Change subject: SKL: Add ACPI brightness control ...................................................................... SKL: Add ACPI brightness control Hook up the generic src/drivers/intel/gma ACPI backlight control for Skylake. Based on a patch by Matt DeVillier <matt.devillier(a)gmail.com>. Signed-off-by: Matthew Garrett <mjg59(a)google.com> Change-Id: I993770fdcd0a28cee756df2bd6a795498f175952 --- M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/include/intelblocks/graphics.h M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/pch.asl M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/graphics.c M src/soc/intel/skylake/include/soc/nvs.h 7 files changed, 40 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/32549/1 diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 5d3b4a1..6489e8e 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -33,6 +33,10 @@ pci_dev_init(dev); } +__weak void gma_ssdt(struct device *dev) +{ +} + static uintptr_t graphics_get_bar(unsigned long index) { struct device *dev = SA_DEV_IGD; @@ -104,6 +108,7 @@ .init = graphics_soc_init, .ops_pci = &pci_dev_ops_pci, .write_acpi_tables = graphics_soc_write_acpi_opregion, + .acpi_fill_ssdt_generator = gma_ssdt, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/common/block/include/intelblocks/graphics.h b/src/soc/intel/common/block/include/intelblocks/graphics.h index 6be7661..077f0db 100644 --- a/src/soc/intel/common/block/include/intelblocks/graphics.h +++ b/src/soc/intel/common/block/include/intelblocks/graphics.h @@ -51,4 +51,7 @@ void graphics_gtt_rmw(unsigned long reg, uint32_t andmask, uint32_t ormask); uintptr_t graphics_get_memory_base(void); +void gma_ssdt(struct device *dev); +struct i915_gpu_controller_info *intel_igd_get_controller_info(void); + #endif /* SOC_INTEL_COMMON_BLOCK_GRAPHICS_H */ diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index c4544e8..6963f70 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -70,6 +70,9 @@ EPCS, 8, // 0x43 - SGX Enabled status EMNA, 64, // 0x44 - 0x4B EPC base address ELNG, 64, // 0x4C - 0x53 EPC Length + BRTL, 32, // 0x54 - 0x57 Brightness Level + CSTE, 16, // 0x58 - 0x59 Current display state + NSTE, 16, // 0x5a - 0x5b Next display state /* IGD OpRegion */ Offset (0xb4), diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index 0aba2e7..f0095bc 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -56,6 +56,9 @@ /* USB XHCI 0:14.0 */ #include "xhci.asl" +/* Graphics */ +#include <drivers/intel/gma/acpi/pch.asl> + Method (_OSC, 4) { /* Check for proper GUID */ diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 57d51e7..51bb740 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -22,6 +22,7 @@ #include <arch/acpi_device.h> #include <device/i2c_simple.h> #include <drivers/i2c/designware/dw_i2c.h> +#include <drivers/intel/gma/i915.h> #include <intelblocks/chip.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> @@ -580,6 +581,8 @@ /* Enable/Disable Sata power optimization */ u8 SataPwrOptEnable; + + struct i915_gpu_controller_info gfx; }; typedef struct soc_intel_skylake_config config_t; diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index 07ee67a..1be5f9d 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -122,3 +122,22 @@ printk(BIOS_DEBUG, "current = %lx\n", current); return current; } + +struct i915_gpu_controller_info *intel_igd_get_controller_info(void) +{ + struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2, 0)); + if (!dev) + return NULL; + struct soc_intel_skylake_config *chip = dev->chip_info; + return &chip->gfx; +} + +void gma_ssdt(struct device *dev) +{ + struct i915_gpu_controller_info *gfx = intel_igd_get_controller_info(); + + if (!gfx) + return; + + drivers_intel_gma_displays_ssdt_generate(gfx); +} diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index 72b1ac9..5a2ca38 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -60,7 +60,10 @@ u8 ecps; /* 0x43 - SGX Enabled status */ u64 emna; /* 0x44 - 0x4B EPC base address */ u64 elng; /* 0x4C - 0x53 EPC Length */ - u8 rsvd[96]; + u32 brtl; /* 0x54 - 0x57 Brightness Level */ + u16 cste; /* 0x58 - 0x59 Current display state */ + u16 nste; /* 0x5a - 0x5b Next display state */ + u8 rsvd[88]; /* IGD OpRegion */ u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I993770fdcd0a28cee756df2bd6a795498f175952 Gerrit-Change-Number: 32549 Gerrit-PatchSet: 1 Gerrit-Owner: Matthew Garrett <mjg59(a)google.com> Gerrit-MessageType: newchange

8 23

Change in ...coreboot[master]: Disable SeaBIOS options not supported by hardware: scripts to apply t...
by Mike Banon (Code Review) 28 Mar '20

28 Mar '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33885 Change subject: Disable SeaBIOS options not supported by hardware: scripts to apply the patches ...................................................................... Disable SeaBIOS options not supported by hardware: scripts to apply the patches These scripts will help you to securely and conveniently apply CB:33870 and CB:33871 to disable SeaBIOS options not supported by G505S and AM1I-A hardware. Save to ./coreboot/ then run ./get_cfgsb_patches.sh , ./check... and ./apply... https://review.coreboot.org/c/coreboot/+/33870 src/mainboard/lenovo/g505s: Disable SeaBIOS options not supported by hardware https://review.coreboot.org/c/coreboot/+/33871 src/mainboard/asus/am1i-a: Disable SeaBIOS options not supported by hardware Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I64e50be0454b3a7e0a89a77e6846f8a7d9cf0a5e --- A apply_cfgsb_patches.sh A check_cfgsb_patches.sh A get_cfgsb_patches.sh A sha256sums_cfgsb_correct.txt 4 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/33885/1 diff --git a/apply_cfgsb_patches.sh b/apply_cfgsb_patches.sh new file mode 100755 index 0000000..c1212bf --- /dev/null +++ b/apply_cfgsb_patches.sh @@ -0,0 +1,12 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/33870 +### src/mainboard/lenovo/g505s: Disable SeaBIOS options not supported by hardware +### +patch -p1 < "./053e2ea.diff" +### +### https://review.coreboot.org/c/coreboot/+/33871 +### src/mainboard/asus/am1i-a: Disable SeaBIOS options not supported by hardware +### +patch -p1 < "./0cd2b7a.diff" +### diff --git a/check_cfgsb_patches.sh b/check_cfgsb_patches.sh new file mode 100755 index 0000000..5e4c1ef --- /dev/null +++ b/check_cfgsb_patches.sh @@ -0,0 +1,13 @@ +#!/bin/sh +rm -f "./sha256sums_cfgsb_my.txt" +sha256sum "./053e2ea.diff" > "./sha256sums_cfgsb_my.txt" +sha256sum "./0cd2b7a.diff" >> "./sha256sums_cfgsb_my.txt" +if cmp -s "./sha256sums_cfgsb_my.txt" "./sha256sums_cfgsb_correct.txt" +then + echo "SHA256 checksums are correct, please run ./apply_cfgsb_patches.sh" + exit 0 +else + echo "! MISMATCH ! See ./sha256sums_cfgsb_my.txt and ./sha256sums_cfgsb_correct.txt" + exit 1 +fi +# diff --git a/get_cfgsb_patches.sh b/get_cfgsb_patches.sh new file mode 100755 index 0000000..0ce0113c --- /dev/null +++ b/get_cfgsb_patches.sh @@ -0,0 +1,16 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/33870 +### src/mainboard/lenovo/g505s: Disable SeaBIOS options not supported by hardware +### +rm -f "./053e2ea.diff" +wget "https://review.coreboot.org/changes/33870/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./053e2ea.diff" +### +### https://review.coreboot.org/c/coreboot/+/33871 +### src/mainboard/asus/am1i-a: Disable SeaBIOS options not supported by hardware +### +rm -f "./0cd2b7a.diff" +wget "https://review.coreboot.org/changes/33871/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./0cd2b7a.diff" +### diff --git a/sha256sums_cfgsb_correct.txt b/sha256sums_cfgsb_correct.txt new file mode 100644 index 0000000..5135520 --- /dev/null +++ b/sha256sums_cfgsb_correct.txt @@ -0,0 +1,2 @@ +ed3f92502e35897256e364e146ad7515414552c4e4e87031bfaae1f30ecdad1d ./053e2ea.diff +6c5fd1060ccf3b84687eb76594ed63a76472c573ea968d9efec40f4c3eccb53d ./0cd2b7a.diff -- To view, visit https://review.coreboot.org/c/coreboot/+/33885 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64e50be0454b3a7e0a89a77e6846f8a7d9cf0a5e Gerrit-Change-Number: 33885 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/mainboard/asus/am1i-a: Disable SeaBIOS options not supported by h...
by Mike Banon (Code Review) 28 Mar '20

28 Mar '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33871 Change subject: src/mainboard/asus/am1i-a: Disable SeaBIOS options not supported by hardware ...................................................................... src/mainboard/asus/am1i-a: Disable SeaBIOS options not supported by hardware AM1I-A does not have any SAS or NVMe controllers, so it makes sense to disable the related SeaBIOS options for this motherboard. This reduces the size of compiled SeaBIOS by 129344-124096 = 5248 bytes. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I5ddf695f4f349697d08a685fa04c90d3afd723c5 --- M src/mainboard/asus/am1i-a/Kconfig A src/mainboard/asus/am1i-a/config_seabios 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/33871/1 diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig index d50edbe..6d88992 100644 --- a/src/mainboard/asus/am1i-a/Kconfig +++ b/src/mainboard/asus/am1i-a/Kconfig @@ -54,4 +54,8 @@ bool default n +config PAYLOAD_CONFIGFILE + string + default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" if PAYLOAD_SEABIOS + endif # BOARD_ASUS_AM1I_A diff --git a/src/mainboard/asus/am1i-a/config_seabios b/src/mainboard/asus/am1i-a/config_seabios new file mode 100644 index 0000000..0ee9cea --- /dev/null +++ b/src/mainboard/asus/am1i-a/config_seabios @@ -0,0 +1,6 @@ +### +### SeaBIOS custom configuration for ASUS AM1I-A +### +# CONFIG_MEGASAS is not set +# CONFIG_NVME is not set +# -- To view, visit https://review.coreboot.org/c/coreboot/+/33871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ddf695f4f349697d08a685fa04c90d3afd723c5 Gerrit-Change-Number: 33871 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: G505S dGPU support: scripts for applying the unofficial (not-merged-y...
by Mike Banon (Code Review) 27 Mar '20

27 Mar '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33874 Change subject: G505S dGPU support: scripts for applying the unofficial (not-merged-yet) patches ...................................................................... G505S dGPU support: scripts for applying the unofficial (not-merged-yet) patches These scripts will help you to securely and conveniently apply two changes CB:31448 and CB:31450 to add the discrete GPU support for AMD Lenovo G505S. Save to ./coreboot/ then run ./get_dgpu_patches.sh , ./check... and ./apply... https://review.coreboot.org/c/coreboot/+/31448 src/device/pci: Add support for discrete VGA initialization and OpROM loading https://review.coreboot.org/c/coreboot/+/31450 lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I2452a75d425f8f647e81314111c462d1195d595d --- A apply_dgpu_patches.sh A check_dgpu_patches.sh A get_dgpu_patches.sh A sha256sums_dgpu_correct.txt 4 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/33874/1 diff --git a/apply_dgpu_patches.sh b/apply_dgpu_patches.sh new file mode 100755 index 0000000..aca4adb --- /dev/null +++ b/apply_dgpu_patches.sh @@ -0,0 +1,12 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/31448 +### src/device/pci: Add support for discrete VGA initialization and OpROM loading +### +patch -p1 < "./8e35cfe.diff" +### +### https://review.coreboot.org/c/coreboot/+/31450 +### lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop +### +patch -p1 < "./b7d4266.diff" +### diff --git a/check_dgpu_patches.sh b/check_dgpu_patches.sh new file mode 100755 index 0000000..6137cc4 --- /dev/null +++ b/check_dgpu_patches.sh @@ -0,0 +1,13 @@ +#!/bin/sh +rm -f "./sha256sums_dgpu_my.txt" +sha256sum "./8e35cfe.diff" > "./sha256sums_dgpu_my.txt" +sha256sum "./b7d4266.diff" >> "./sha256sums_dgpu_my.txt" +if cmp -s "./sha256sums_dgpu_my.txt" "./sha256sums_dgpu_correct.txt" +then + echo "SHA256 checksums are correct, please run ./apply_dgpu_patches.sh" + exit 0 +else + echo "! MISMATCH ! See ./sha256sums_dgpu_my.txt and ./sha256sums_dgpu_correct.txt" + exit 1 +fi +# diff --git a/get_dgpu_patches.sh b/get_dgpu_patches.sh new file mode 100755 index 0000000..e0d4a2a --- /dev/null +++ b/get_dgpu_patches.sh @@ -0,0 +1,16 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/31448 +### src/device/pci: Add support for discrete VGA initialization and OpROM loading +### +rm -f "./8e35cfe.diff" +wget "https://review.coreboot.org/changes/31448/revisions/17/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./8e35cfe.diff" +### +### https://review.coreboot.org/c/coreboot/+/31450 +### lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop +### +rm -f "./b7d4266.diff" +wget "https://review.coreboot.org/changes/31450/revisions/12/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./b7d4266.diff" +### diff --git a/sha256sums_dgpu_correct.txt b/sha256sums_dgpu_correct.txt new file mode 100644 index 0000000..b607b61 --- /dev/null +++ b/sha256sums_dgpu_correct.txt @@ -0,0 +1,2 @@ +284cb0908c498c730dd8ed994c65ffd186d1dd34b4bc3432c9e7ccf7f40313e2 ./8e35cfe.diff +0edfa4f1bb2310220f0d6be2228f0be15d2ab0256e63fa1ed6fecc1650e1f938 ./b7d4266.diff -- To view, visit https://review.coreboot.org/c/coreboot/+/33874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2452a75d425f8f647e81314111c462d1195d595d Gerrit-Change-Number: 33874 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/sarien: Modify Melfas touchscreen reset delay
by Ivy Jian (Code Review) 27 Mar '20

27 Mar '20

Ivy Jian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34162 ) Change subject: mb/google/sarien: Modify Melfas touchscreen reset delay ...................................................................... mb/google/sarien: Modify Melfas touchscreen reset delay Modify reset_delay_ms as 115ms to waiting for Melfas device I2C interface ready after touch fw AU and rebind driver. BUG=b:136560969 BRANCH=sarien TEST=Touchscreen works fine after touch FW auto updated. Signed-off-by: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Change-Id: I45bd93bb841c7dd49705a9d6b61cb9f66f7d7bcb Signed-off-by: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> --- M src/mainboard/google/sarien/variants/sarien/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/34162/1 diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 739a849..53189ce 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -343,7 +343,7 @@ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" register "probed" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" - register "reset_delay_ms" = "10" + register "reset_delay_ms" = "115" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" register "enable_delay_ms" = "55" register "has_power_resource" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/34162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45bd93bb841c7dd49705a9d6b61cb9f66f7d7bcb Gerrit-Change-Number: 34162 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/intel/gma: Add `new-pch.asl` for Skylake+
by Nico Huber (Code Review) 25 Mar '20

25 Mar '20

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31503 Change subject: drivers/intel/gma: Add `new-pch.asl` for Skylake+ ...................................................................... drivers/intel/gma: Add `new-pch.asl` for Skylake+ This should work as `pch.asl` equivalent for Skylake and later platforms. Untested. Change-Id: I0b21d9a0288f0f8d6cb0a4776909bffdae7576f5 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- A src/drivers/intel/gma/acpi/new-pch.asl 1 file changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/31503/1 diff --git a/src/drivers/intel/gma/acpi/new-pch.asl b/src/drivers/intel/gma/acpi/new-pch.asl new file mode 100644 index 0000000..b24a350 --- /dev/null +++ b/src/drivers/intel/gma/acpi/new-pch.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (GFX0) +{ + Name (_ADR, 0x00020000) + + OperationRegion (GFXC, PCI_Config, 0x00, 0x0100) + Field (GFXC, DWordAcc, NoLock, Preserve) + { + Offset (0x10), + BAR0, 64, + Offset (0xe4), + ASLE, 32, + Offset (0xfc), + ASLS, 32, + } + + OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000) + Field (GFRG, DWordAcc, NoLock, Preserve) + { + Offset (0xc8254), + BCLV, 16, + BCLM, 16 + } + +#include "configure_brightness_levels.asl" +#include "common.asl" +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b21d9a0288f0f8d6cb0a4776909bffdae7576f5 Gerrit-Change-Number: 31503 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Set correct serirq mode based on SERIRQ_CONTINU...
by Jeremy Soller (Code Review) 17 Mar '20

17 Mar '20

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31536 Change subject: soc/intel/cannonlake: Set correct serirq mode based on SERIRQ_CONTINUOUS_MODE ...................................................................... soc/intel/cannonlake: Set correct serirq mode based on SERIRQ_CONTINUOUS_MODE Change-Id: I9ad4f5a6c7391fc6e813ec1306c708f449a69f59 --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/fsp_params.c 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/31536/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index cd8819d..3716640 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -172,6 +172,13 @@ default 24 if SOC_INTEL_CANNONLAKE_PCH_H default 16 +config SERIRQ_CONTINUOUS_MODE + bool + default n + help + If you set this option to y, the serial IRQ machine will be + operated in continuous mode. + config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index c276c86..c95a68f 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -246,6 +246,12 @@ /* Set TccActivationOffset */ tconfig->TccActivationOffset = config->tcc_offset; + + /* Set correct Sirq mode based on config */ + if (IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)) + params->PchSirqMode = 1; + else + params->PchSirqMode = 0; } /* Mainboard GPIO Configuration */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ad4f5a6c7391fc6e813ec1306c708f449a69f59 Gerrit-Change-Number: 31536 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Soller <jackpot51(a)gmail.com> Gerrit-MessageType: newchange

7 22

Change in ...coreboot[master]: nb/intel/i945: Correct mask for CxDRT1
by HAOUAS Elyes (Code Review) 16 Mar '20

16 Mar '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31144 Change subject: nb/intel/i945: Correct mask for CxDRT1 ...................................................................... nb/intel/i945: Correct mask for CxDRT1 [27:24] and [31:30] are reserved, so we shouldn't change them. Tested on i945G-M4 board. Change-Id: I0cac9160c756405838706edb0461575241faae35 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/31144/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index f3c3df6..2a62ca3 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -1475,7 +1475,7 @@ /* Calculate DRT1 */ - temp_drt = MCHBAR32(C0DRT1) & 0x00020088; + temp_drt = MCHBAR32(C0DRT1) & 0xcf020088; /* DRAM RASB Precharge */ temp_drt |= (sysinfo->trp - 2) << 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/31144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cac9160c756405838706edb0461575241faae35 Gerrit-Change-Number: 31144 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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