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Change in coreboot[master]: [TESTONLY] arch/x86: Default INSTALL_SMM off
by Kyösti Mälkki (Code Review) 30 Jul '20

30 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34258 ) Change subject: [TESTONLY] arch/x86: Default INSTALL_SMM off ...................................................................... [TESTONLY] arch/x86: Default INSTALL_SMM off Change-Id: Id1e05a3477da73f03fb5653b61a0b4723b8d0503 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/34258/1 diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 25eee72..9f68663 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -88,7 +88,7 @@ config INSTALL_SMM bool - default y + default n depends on HAVE_SMI_HANDLER config HAVE_SMI_HANDLER -- To view, visit https://review.coreboot.org/c/coreboot/+/34258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1e05a3477da73f03fb5653b61a0b4723b8d0503 Gerrit-Change-Number: 34258 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: commonlib: Add header for multiboot
by Kyösti Mälkki (Code Review) 30 Jul '20

30 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34064 ) Change subject: commonlib: Add header for multiboot ...................................................................... commonlib: Add header for multiboot Copied file from grub2 repository. Change-Id: I1e593b5bb55881cbab87d2c59ff615f546711445 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- A src/commonlib/include/commonlib/multiboot.h 1 file changed, 274 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/34064/1 diff --git a/src/commonlib/include/commonlib/multiboot.h b/src/commonlib/include/commonlib/multiboot.h new file mode 100644 index 0000000..7e5ac69 --- /dev/null +++ b/src/commonlib/include/commonlib/multiboot.h @@ -0,0 +1,274 @@ +/* multiboot.h - Multiboot header file. */ +/* Copyright (C) 1999,2003,2007,2008,2009,2010 Free Software Foundation, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ANY + * DEVELOPER OR DISTRIBUTOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR + * IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef MULTIBOOT_HEADER +#define MULTIBOOT_HEADER 1 + +/* How many bytes from the start of the file we search for the header. */ +#define MULTIBOOT_SEARCH 8192 +#define MULTIBOOT_HEADER_ALIGN 4 + +/* The magic field should contain this. */ +#define MULTIBOOT_HEADER_MAGIC 0x1BADB002 + +/* This should be in %eax. */ +#define MULTIBOOT_BOOTLOADER_MAGIC 0x2BADB002 + +/* Alignment of multiboot modules. */ +#define MULTIBOOT_MOD_ALIGN 0x00001000 + +/* Alignment of the multiboot info structure. */ +#define MULTIBOOT_INFO_ALIGN 0x00000004 + +/* Flags set in the 'flags' member of the multiboot header. */ + +/* Align all boot modules on i386 page (4KB) boundaries. */ +#define MULTIBOOT_PAGE_ALIGN 0x00000001 + +/* Must pass memory information to OS. */ +#define MULTIBOOT_MEMORY_INFO 0x00000002 + +/* Must pass video information to OS. */ +#define MULTIBOOT_VIDEO_MODE 0x00000004 + +/* This flag indicates the use of the address fields in the header. */ +#define MULTIBOOT_AOUT_KLUDGE 0x00010000 + +/* Flags to be set in the 'flags' member of the multiboot info structure. */ + +/* is there basic lower/upper memory information? */ +#define MULTIBOOT_INFO_MEMORY 0x00000001 +/* is there a boot device set? */ +#define MULTIBOOT_INFO_BOOTDEV 0x00000002 +/* is the command-line defined? */ +#define MULTIBOOT_INFO_CMDLINE 0x00000004 +/* are there modules to do something with? */ +#define MULTIBOOT_INFO_MODS 0x00000008 + +/* These next two are mutually exclusive */ + +/* is there a symbol table loaded? */ +#define MULTIBOOT_INFO_AOUT_SYMS 0x00000010 +/* is there an ELF section header table? */ +#define MULTIBOOT_INFO_ELF_SHDR 0X00000020 + +/* is there a full memory map? */ +#define MULTIBOOT_INFO_MEM_MAP 0x00000040 + +/* Is there drive info? */ +#define MULTIBOOT_INFO_DRIVE_INFO 0x00000080 + +/* Is there a config table? */ +#define MULTIBOOT_INFO_CONFIG_TABLE 0x00000100 + +/* Is there a boot loader name? */ +#define MULTIBOOT_INFO_BOOT_LOADER_NAME 0x00000200 + +/* Is there a APM table? */ +#define MULTIBOOT_INFO_APM_TABLE 0x00000400 + +/* Is there video information? */ +#define MULTIBOOT_INFO_VBE_INFO 0x00000800 +#define MULTIBOOT_INFO_FRAMEBUFFER_INFO 0x00001000 + +#ifndef ASM_FILE + +typedef unsigned char multiboot_uint8_t; +typedef unsigned short multiboot_uint16_t; +typedef unsigned int multiboot_uint32_t; +typedef unsigned long long multiboot_uint64_t; + +struct multiboot_header +{ + /* Must be MULTIBOOT_MAGIC - see above. */ + multiboot_uint32_t magic; + + /* Feature flags. */ + multiboot_uint32_t flags; + + /* The above fields plus this one must equal 0 mod 2^32. */ + multiboot_uint32_t checksum; + + /* These are only valid if MULTIBOOT_AOUT_KLUDGE is set. */ + multiboot_uint32_t header_addr; + multiboot_uint32_t load_addr; + multiboot_uint32_t load_end_addr; + multiboot_uint32_t bss_end_addr; + multiboot_uint32_t entry_addr; + + /* These are only valid if MULTIBOOT_VIDEO_MODE is set. */ + multiboot_uint32_t mode_type; + multiboot_uint32_t width; + multiboot_uint32_t height; + multiboot_uint32_t depth; +}; + +/* The symbol table for a.out. */ +struct multiboot_aout_symbol_table +{ + multiboot_uint32_t tabsize; + multiboot_uint32_t strsize; + multiboot_uint32_t addr; + multiboot_uint32_t reserved; +}; +typedef struct multiboot_aout_symbol_table multiboot_aout_symbol_table_t; + +/* The section header table for ELF. */ +struct multiboot_elf_section_header_table +{ + multiboot_uint32_t num; + multiboot_uint32_t size; + multiboot_uint32_t addr; + multiboot_uint32_t shndx; +}; +typedef struct multiboot_elf_section_header_table multiboot_elf_section_header_table_t; + +struct multiboot_info +{ + /* Multiboot info version number */ + multiboot_uint32_t flags; + + /* Available memory from BIOS */ + multiboot_uint32_t mem_lower; + multiboot_uint32_t mem_upper; + + /* "root" partition */ + multiboot_uint32_t boot_device; + + /* Kernel command line */ + multiboot_uint32_t cmdline; + + /* Boot-Module list */ + multiboot_uint32_t mods_count; + multiboot_uint32_t mods_addr; + + union + { + multiboot_aout_symbol_table_t aout_sym; + multiboot_elf_section_header_table_t elf_sec; + } u; + + /* Memory Mapping buffer */ + multiboot_uint32_t mmap_length; + multiboot_uint32_t mmap_addr; + + /* Drive Info buffer */ + multiboot_uint32_t drives_length; + multiboot_uint32_t drives_addr; + + /* ROM configuration table */ + multiboot_uint32_t config_table; + + /* Boot Loader Name */ + multiboot_uint32_t boot_loader_name; + + /* APM table */ + multiboot_uint32_t apm_table; + + /* Video */ + multiboot_uint32_t vbe_control_info; + multiboot_uint32_t vbe_mode_info; + multiboot_uint16_t vbe_mode; + multiboot_uint16_t vbe_interface_seg; + multiboot_uint16_t vbe_interface_off; + multiboot_uint16_t vbe_interface_len; + + multiboot_uint64_t framebuffer_addr; + multiboot_uint32_t framebuffer_pitch; + multiboot_uint32_t framebuffer_width; + multiboot_uint32_t framebuffer_height; + multiboot_uint8_t framebuffer_bpp; +#define MULTIBOOT_FRAMEBUFFER_TYPE_INDEXED 0 +#define MULTIBOOT_FRAMEBUFFER_TYPE_RGB 1 +#define MULTIBOOT_FRAMEBUFFER_TYPE_EGA_TEXT 2 + multiboot_uint8_t framebuffer_type; + union + { + struct + { + multiboot_uint32_t framebuffer_palette_addr; + multiboot_uint16_t framebuffer_palette_num_colors; + }; + struct + { + multiboot_uint8_t framebuffer_red_field_position; + multiboot_uint8_t framebuffer_red_mask_size; + multiboot_uint8_t framebuffer_green_field_position; + multiboot_uint8_t framebuffer_green_mask_size; + multiboot_uint8_t framebuffer_blue_field_position; + multiboot_uint8_t framebuffer_blue_mask_size; + }; + }; +}; +typedef struct multiboot_info multiboot_info_t; + +struct multiboot_color +{ + multiboot_uint8_t red; + multiboot_uint8_t green; + multiboot_uint8_t blue; +}; + +struct multiboot_mmap_entry +{ + multiboot_uint32_t size; + multiboot_uint64_t addr; + multiboot_uint64_t len; +#define MULTIBOOT_MEMORY_AVAILABLE 1 +#define MULTIBOOT_MEMORY_RESERVED 2 +#define MULTIBOOT_MEMORY_ACPI_RECLAIMABLE 3 +#define MULTIBOOT_MEMORY_NVS 4 +#define MULTIBOOT_MEMORY_BADRAM 5 + multiboot_uint32_t type; +} GRUB_PACKED; +typedef struct multiboot_mmap_entry multiboot_memory_map_t; + +struct multiboot_mod_list +{ + /* the memory used goes from bytes 'mod_start' to 'mod_end-1' inclusive */ + multiboot_uint32_t mod_start; + multiboot_uint32_t mod_end; + + /* Module command line */ + multiboot_uint32_t cmdline; + + /* padding to take it to 16 bytes (must be zero) */ + multiboot_uint32_t pad; +}; +typedef struct multiboot_mod_list multiboot_module_t; + +/* APM BIOS info. */ +struct multiboot_apm_info +{ + grub_uint16_t version; + grub_uint16_t cseg; + grub_uint32_t offset; + grub_uint16_t cseg_16; + grub_uint16_t dseg; + grub_uint16_t flags; + grub_uint16_t cseg_len; + grub_uint16_t cseg_16_len; + grub_uint16_t dseg_len; +}; + +#endif /* ! ASM_FILE */ + +#endif /* ! MULTIBOOT_HEADER */ -- To view, visit https://review.coreboot.org/c/coreboot/+/34064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e593b5bb55881cbab87d2c59ff615f546711445 Gerrit-Change-Number: 34064 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: commonlib: Apply coding style for multiboot.h
by Kyösti Mälkki (Code Review) 30 Jul '20

30 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34065 ) Change subject: commonlib: Apply coding style for multiboot.h ...................................................................... commonlib: Apply coding style for multiboot.h Add includes, change whitespace. Remove multiboot_ prefixes and some typedefs. Change-Id: I4ebc83c3c737349bf9bc10d141a9ce9047eda1ac Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/commonlib/include/commonlib/multiboot.h 1 file changed, 124 insertions(+), 131 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/34065/1 diff --git a/src/commonlib/include/commonlib/multiboot.h b/src/commonlib/include/commonlib/multiboot.h index 7e5ac69..2aae2ea 100644 --- a/src/commonlib/include/commonlib/multiboot.h +++ b/src/commonlib/include/commonlib/multiboot.h @@ -22,6 +22,8 @@ #ifndef MULTIBOOT_HEADER #define MULTIBOOT_HEADER 1 +#include <stdint.h> + /* How many bytes from the start of the file we search for the header. */ #define MULTIBOOT_SEARCH 8192 #define MULTIBOOT_HEADER_ALIGN 4 @@ -89,186 +91,177 @@ #define MULTIBOOT_INFO_VBE_INFO 0x00000800 #define MULTIBOOT_INFO_FRAMEBUFFER_INFO 0x00001000 -#ifndef ASM_FILE - -typedef unsigned char multiboot_uint8_t; -typedef unsigned short multiboot_uint16_t; -typedef unsigned int multiboot_uint32_t; -typedef unsigned long long multiboot_uint64_t; - struct multiboot_header { - /* Must be MULTIBOOT_MAGIC - see above. */ - multiboot_uint32_t magic; + /* Must be MULTIBOOT_MAGIC - see above. */ + uint32_t magic; - /* Feature flags. */ - multiboot_uint32_t flags; + /* Feature flags. */ + uint32_t flags; - /* The above fields plus this one must equal 0 mod 2^32. */ - multiboot_uint32_t checksum; + /* The above fields plus this one must equal 0 mod 2^32. */ + uint32_t checksum; - /* These are only valid if MULTIBOOT_AOUT_KLUDGE is set. */ - multiboot_uint32_t header_addr; - multiboot_uint32_t load_addr; - multiboot_uint32_t load_end_addr; - multiboot_uint32_t bss_end_addr; - multiboot_uint32_t entry_addr; + /* These are only valid if MULTIBOOT_AOUT_KLUDGE is set. */ + uint32_t header_addr; + uint32_t load_addr; + uint32_t load_end_addr; + uint32_t bss_end_addr; + uint32_t entry_addr; - /* These are only valid if MULTIBOOT_VIDEO_MODE is set. */ - multiboot_uint32_t mode_type; - multiboot_uint32_t width; - multiboot_uint32_t height; - multiboot_uint32_t depth; + /* These are only valid if MULTIBOOT_VIDEO_MODE is set. */ + uint32_t mode_type; + uint32_t width; + uint32_t height; + uint32_t depth; }; /* The symbol table for a.out. */ struct multiboot_aout_symbol_table { - multiboot_uint32_t tabsize; - multiboot_uint32_t strsize; - multiboot_uint32_t addr; - multiboot_uint32_t reserved; + uint32_t tabsize; + uint32_t strsize; + uint32_t addr; + uint32_t reserved; }; -typedef struct multiboot_aout_symbol_table multiboot_aout_symbol_table_t; /* The section header table for ELF. */ struct multiboot_elf_section_header_table { - multiboot_uint32_t num; - multiboot_uint32_t size; - multiboot_uint32_t addr; - multiboot_uint32_t shndx; + uint32_t num; + uint32_t size; + uint32_t addr; + uint32_t shndx; }; -typedef struct multiboot_elf_section_header_table multiboot_elf_section_header_table_t; struct multiboot_info { - /* Multiboot info version number */ - multiboot_uint32_t flags; + /* Multiboot info version number */ + uint32_t flags; - /* Available memory from BIOS */ - multiboot_uint32_t mem_lower; - multiboot_uint32_t mem_upper; + /* Available memory from BIOS */ + uint32_t mem_lower; + uint32_t mem_upper; - /* "root" partition */ - multiboot_uint32_t boot_device; + /* "root" partition */ + uint32_t boot_device; - /* Kernel command line */ - multiboot_uint32_t cmdline; + /* Kernel command line */ + uint32_t cmdline; - /* Boot-Module list */ - multiboot_uint32_t mods_count; - multiboot_uint32_t mods_addr; + /* Boot-Module list */ + uint32_t mods_count; + uint32_t mods_addr; - union - { - multiboot_aout_symbol_table_t aout_sym; - multiboot_elf_section_header_table_t elf_sec; - } u; + union + { + struct multiboot_aout_symbol_table aout_sym; + struct multiboot_elf_section_header_table elf_sec; + } u; - /* Memory Mapping buffer */ - multiboot_uint32_t mmap_length; - multiboot_uint32_t mmap_addr; + /* Memory Mapping buffer */ + uint32_t mmap_length; + uint32_t mmap_addr; - /* Drive Info buffer */ - multiboot_uint32_t drives_length; - multiboot_uint32_t drives_addr; + /* Drive Info buffer */ + uint32_t drives_length; + uint32_t drives_addr; - /* ROM configuration table */ - multiboot_uint32_t config_table; + /* ROM configuration table */ + uint32_t config_table; - /* Boot Loader Name */ - multiboot_uint32_t boot_loader_name; + /* Boot Loader Name */ + uint32_t boot_loader_name; - /* APM table */ - multiboot_uint32_t apm_table; + /* APM table */ + uint32_t apm_table; - /* Video */ - multiboot_uint32_t vbe_control_info; - multiboot_uint32_t vbe_mode_info; - multiboot_uint16_t vbe_mode; - multiboot_uint16_t vbe_interface_seg; - multiboot_uint16_t vbe_interface_off; - multiboot_uint16_t vbe_interface_len; + /* Video */ + uint32_t vbe_control_info; + uint32_t vbe_mode_info; + uint16_t vbe_mode; + uint16_t vbe_interface_seg; + uint16_t vbe_interface_off; + uint16_t vbe_interface_len; - multiboot_uint64_t framebuffer_addr; - multiboot_uint32_t framebuffer_pitch; - multiboot_uint32_t framebuffer_width; - multiboot_uint32_t framebuffer_height; - multiboot_uint8_t framebuffer_bpp; -#define MULTIBOOT_FRAMEBUFFER_TYPE_INDEXED 0 -#define MULTIBOOT_FRAMEBUFFER_TYPE_RGB 1 + uint64_t framebuffer_addr; + uint32_t framebuffer_pitch; + uint32_t framebuffer_width; + uint32_t framebuffer_height; + uint8_t framebuffer_bpp; + +#define MULTIBOOT_FRAMEBUFFER_TYPE_INDEXED 0 +#define MULTIBOOT_FRAMEBUFFER_TYPE_RGB 1 #define MULTIBOOT_FRAMEBUFFER_TYPE_EGA_TEXT 2 - multiboot_uint8_t framebuffer_type; - union - { - struct - { - multiboot_uint32_t framebuffer_palette_addr; - multiboot_uint16_t framebuffer_palette_num_colors; - }; - struct - { - multiboot_uint8_t framebuffer_red_field_position; - multiboot_uint8_t framebuffer_red_mask_size; - multiboot_uint8_t framebuffer_green_field_position; - multiboot_uint8_t framebuffer_green_mask_size; - multiboot_uint8_t framebuffer_blue_field_position; - multiboot_uint8_t framebuffer_blue_mask_size; - }; - }; -}; -typedef struct multiboot_info multiboot_info_t; - -struct multiboot_color -{ - multiboot_uint8_t red; - multiboot_uint8_t green; - multiboot_uint8_t blue; + uint8_t framebuffer_type; + union + { + struct + { + uint32_t framebuffer_palette_addr; + uint16_t framebuffer_palette_num_colors; + }; + struct + { + uint8_t framebuffer_red_field_position; + uint8_t framebuffer_red_mask_size; + uint8_t framebuffer_green_field_position; + uint8_t framebuffer_green_mask_size; + uint8_t framebuffer_blue_field_position; + uint8_t framebuffer_blue_mask_size; + }; + }; }; -struct multiboot_mmap_entry +struct color { - multiboot_uint32_t size; - multiboot_uint64_t addr; - multiboot_uint64_t len; + uint8_t red; + uint8_t green; + uint8_t blue; +}; + +struct mmap_entry +{ + uint32_t size; + uint64_t addr; + uint64_t len; #define MULTIBOOT_MEMORY_AVAILABLE 1 #define MULTIBOOT_MEMORY_RESERVED 2 #define MULTIBOOT_MEMORY_ACPI_RECLAIMABLE 3 #define MULTIBOOT_MEMORY_NVS 4 #define MULTIBOOT_MEMORY_BADRAM 5 - multiboot_uint32_t type; -} GRUB_PACKED; -typedef struct multiboot_mmap_entry multiboot_memory_map_t; + uint32_t type; +} __packed; -struct multiboot_mod_list +struct mod_list { - /* the memory used goes from bytes 'mod_start' to 'mod_end-1' inclusive */ - multiboot_uint32_t mod_start; - multiboot_uint32_t mod_end; + /* the memory used goes from bytes + * 'mod_start' to 'mod_end-1' inclusive + */ + uint32_t mod_start; + uint32_t mod_end; - /* Module command line */ - multiboot_uint32_t cmdline; + /* Module command line */ + uint32_t cmdline; - /* padding to take it to 16 bytes (must be zero) */ - multiboot_uint32_t pad; + /* padding to take it to 16 bytes (must be zero) */ + uint32_t pad; }; -typedef struct multiboot_mod_list multiboot_module_t; +#if 0 /* APM BIOS info. */ -struct multiboot_apm_info +struct apm_info { - grub_uint16_t version; - grub_uint16_t cseg; - grub_uint32_t offset; - grub_uint16_t cseg_16; - grub_uint16_t dseg; - grub_uint16_t flags; - grub_uint16_t cseg_len; - grub_uint16_t cseg_16_len; - grub_uint16_t dseg_len; + grub_uint16_t version; + grub_uint16_t cseg; + grub_uint32_t offset; + grub_uint16_t cseg_16; + grub_uint16_t dseg; + grub_uint16_t flags; + grub_uint16_t cseg_len; + grub_uint16_t cseg_16_len; + grub_uint16_t dseg_len; }; - -#endif /* ! ASM_FILE */ +#endif #endif /* ! MULTIBOOT_HEADER */ -- To view, visit https://review.coreboot.org/c/coreboot/+/34065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ebc83c3c737349bf9bc10d141a9ce9047eda1ac Gerrit-Change-Number: 34065 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86: Add MULTIBOOT run-time info
by Kyösti Mälkki (Code Review) 30 Jul '20

30 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34066 ) Change subject: arch/x86: Add MULTIBOOT run-time info ...................................................................... arch/x86: Add MULTIBOOT run-time info Change-Id: Ia14a49e37e308b05cde4dbadf0e4596bbebc9933 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M payloads/Kconfig M src/arch/x86/Makefile.inc M src/arch/x86/boot.c A src/arch/x86/multiboot.c M src/arch/x86/tables.c M src/commonlib/include/commonlib/cbmem_id.h M src/commonlib/include/commonlib/multiboot.h M src/lib/coreboot_table.c 8 files changed, 182 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/34066/1 diff --git a/payloads/Kconfig b/payloads/Kconfig index d0f8a44..a7a16ef 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -114,6 +114,15 @@ In order to reduce the size secondary payloads take up in the ROM chip they can be compressed using the LZMA algorithm. +config MULTIBOOT_RUNTIME + bool "Fill MultiBoot runtime info for payload" + depends on ARCH_X86 + default n + +config MULTIBOOT_RUNTIME_CMDLINE + string "Commandline passed to payload in MultiBoot runtime info" + depends on MULTIBOOT_RUNTIME + menu "Secondary Payloads" config COREINFO_SECONDARY_PAYLOAD diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 025b933..290b7ed 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -312,6 +312,7 @@ ramstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c ramstage-$(CONFIG_ACPI_BERT) += acpi_bert_storage.c ramstage-y += boot.c +ramstage-y += multiboot.c ramstage-y += c_start.S ramstage-y += cbmem.c ramstage-y += cpu.c diff --git a/src/arch/x86/boot.c b/src/arch/x86/boot.c index 5f60f13..41a5eff 100644 --- a/src/arch/x86/boot.c +++ b/src/arch/x86/boot.c @@ -11,10 +11,13 @@ * GNU General Public License for more details. */ +#include <cbmem.h> #include <commonlib/helpers.h> +#include <commonlib/multiboot.h> #include <console/console.h> #include <program_loading.h> #include <ip_checksum.h> +#include <stdint.h> #include <symbols.h> int payload_arch_usable_ram_quirk(uint64_t start, uint64_t size) @@ -30,6 +33,18 @@ void arch_prog_run(struct prog *prog) { + uint32_t eax = 0, ebx = 0; + + if (ENV_PAYLOAD_LOADER && (prog_type(prog) == PROG_PAYLOAD)) { + if (CONFIG(MULTIBOOT_RUNTIME)) { + void *info = cbmem_find(CBMEM_ID_MULTIBOOT); + if (info) { + eax = MULTIBOOT_BOOTLOADER_MAGIC; + ebx = (uintptr_t)info; + } + } + } + __asm__ volatile ( #ifdef __x86_64__ "jmp *%%rdi\n" @@ -37,6 +52,6 @@ "jmp *%%edi\n" #endif - :: "D"(prog_entry(prog)) + :: "D"(prog_entry(prog)), "a" (eax), "b" (ebx) ); } diff --git a/src/arch/x86/multiboot.c b/src/arch/x86/multiboot.c new file mode 100644 index 0000000..56822a4 --- /dev/null +++ b/src/arch/x86/multiboot.c @@ -0,0 +1,139 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootmem.h> +#include <cbmem.h> +#include <commonlib/helpers.h> +#include <commonlib/multiboot.h> +#include <memrange.h> +#include <string.h> + +#define MAX_MMAP_ENTRIES 32 +#define MAX_CMDLINE_LEN 100 + +/* Memory reserved for CBMEM may grow here, do this step early. */ +void alloc_multiboot_info(void) +{ + struct multiboot_info *info; + uintptr_t current, cmdline_offset, mmap_offset; + + current = sizeof(*info); + current = ALIGN_UP(current, 8); + + /* Static reserver for command line. */ + cmdline_offset = current; + current += MAX_CMDLINE_LEN; + current = ALIGN_UP(current, 8); + + /* Static reserve of mmap entries. */ + mmap_offset = current; + current += MAX_MMAP_ENTRIES * sizeof(struct mmap_entry); + current = ALIGN_UP(current, 8); + + info = cbmem_add(CBMEM_ID_MULTIBOOT, current); + if (!info) + return; + + memset(info, 0, sizeof(*info)); + info->cmdline = (uintptr_t)(char *)info + cmdline_offset; + info->mmap_addr = (uintptr_t)(char *)info + mmap_offset; +} + +static bool add_mmap_entry(const struct range_entry *r, void *arg) +{ + struct multiboot_info *info = arg; + struct mmap_entry *m; + uintptr_t new_entry; + + if (info->mmap_length >= MAX_MMAP_ENTRIES * sizeof(*m)) + return false; + + new_entry = info->mmap_addr + info->mmap_length; + info->mmap_length += sizeof(*m); + + m = (void *)new_entry; + m->size = sizeof(*m) - sizeof(m->size); + m->addr = range_entry_base(r); + m->len = range_entry_size(r); + + /* Don't differentiate between unavailable ranges. */ + if (range_entry_tag(r) != BM_MEM_RAM) { + m->type = MULTIBOOT_MEMORY_RESERVED; + return true; + } + + m->type = MULTIBOOT_MEMORY_AVAILABLE; + + /* Range crossing or starting at 1 MiB boundary determines + * available upper memory. */ + if ((m->addr <= 1 * MiB) && (m->addr + m->len > 1 * MiB)) + info->mem_upper = (m->addr + m->len - 1 * MiB) / KiB; + + /* Specs says to report max 640 KiB of lower memory, + * report that if we have any memory at all. */ + info->mem_lower = 640; + + return true; +} + +static void fill_memory(struct multiboot_info *info) +{ + if (!info || !info->mmap_addr) + return; + + bootmem_walk_os_mem(add_mmap_entry, info); + + if (info->mem_lower || info->mem_upper) + info->flags |= MULTIBOOT_INFO_MEMORY; + + if (info->mmap_length) + info->flags |= MULTIBOOT_INFO_MEM_MAP; +} + +const char *__weak multiboot_runtime_cmdline(void) +{ + return CONFIG_MULTIBOOT_RUNTIME_CMDLINE; +} + +static void fill_cmdline(struct multiboot_info *info) +{ + const char *s; + size_t len; + + if (!info || !info->cmdline) + return; + + s = multiboot_runtime_cmdline(); + if (!s) + return; + + /* Do not allow partial lines. */ + len = strnlen(s, 2 * MAX_CMDLINE_LEN); + if (len >= MAX_CMDLINE_LEN) + return; + + memcpy((char *)(uintptr_t)info->cmdline, s, len); + info->flags |= MULTIBOOT_INFO_CMDLINE; +} + +void fill_multiboot_info(void) +{ + struct multiboot_info *info; + + info = cbmem_find(CBMEM_ID_MULTIBOOT); + if (!info) + return; + + fill_memory(info); + fill_cmdline(info); +} diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 0baa58e..58f7fa3 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include <commonlib/multiboot.h> #include <console/console.h> #include <bootmem.h> #include <bootstate.h> @@ -260,6 +261,10 @@ /* Align up to page boundary for historical consistency. */ forwarding_table = ALIGN_UP(forwarding_table, 4*KiB); + /* We need to do this before bootmem generation. */ + if (CONFIG(MULTIBOOT_RUNTIME)) + alloc_multiboot_info(); + /* Tell static analysis we know value is left unused. */ (void)rom_table_end; } diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 2236c95..ff21a13 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -45,6 +45,7 @@ #define CBMEM_ID_MRCDATA 0x4d524344 #define CBMEM_ID_VAR_MRCDATA 0x4d524345 #define CBMEM_ID_MTC 0xcb31d31c +#define CBMEM_ID_MULTIBOOT 0x2badb002 #define CBMEM_ID_NONE 0x00000000 #define CBMEM_ID_PIRQ 0x49525154 #define CBMEM_ID_POWER_STATE 0x50535454 @@ -108,6 +109,7 @@ { CBMEM_ID_MRCDATA, "MRC DATA " }, \ { CBMEM_ID_VAR_MRCDATA, "VARMRC DATA" }, \ { CBMEM_ID_MTC, "MTC " }, \ + { CBMEM_ID_MULTIBOOT, "MULTIBOOT " }, \ { CBMEM_ID_PIRQ, "IRQ TABLE " }, \ { CBMEM_ID_POWER_STATE, "POWER STATE" }, \ { CBMEM_ID_RAM_OOPS, "RAMOOPS " }, \ diff --git a/src/commonlib/include/commonlib/multiboot.h b/src/commonlib/include/commonlib/multiboot.h index 2aae2ea..8f338e8 100644 --- a/src/commonlib/include/commonlib/multiboot.h +++ b/src/commonlib/include/commonlib/multiboot.h @@ -264,4 +264,8 @@ }; #endif +void alloc_multiboot_info(void); +void fill_multiboot_info(void); +const char *multiboot_runtime_cmdline(void); + #endif /* ! MULTIBOOT_HEADER */ diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index df75698..fc42ef7 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -16,6 +16,7 @@ */ #include <arch/cbconfig.h> +#include <commonlib/multiboot.h> #include <console/console.h> #include <console/uart.h> #include <ip_checksum.h> @@ -599,6 +600,11 @@ /* Add all cbmem entries into the coreboot tables. */ cbmem_add_records_to_cbtable(head); + /* We need to do this before checksum is calculated. + * FIXME: Find better place for the call. */ + if (CONFIG(MULTIBOOT_RUNTIME)) + fill_multiboot_info(); + /* Remember where my valid memory ranges are */ return lb_table_fini(head); } -- To view, visit https://review.coreboot.org/c/coreboot/+/34066 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia14a49e37e308b05cde4dbadf0e4596bbebc9933 Gerrit-Change-Number: 34066 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: [TESTONLY] arch/x86: experiment with SMM defaults
by Kyösti Mälkki (Code Review) 30 Jul '20

30 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34128 ) Change subject: [TESTONLY] arch/x86: experiment with SMM defaults ...................................................................... [TESTONLY] arch/x86: experiment with SMM defaults Change-Id: I332a80ffd9c5dff3efe33e14eabe334cb248296c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/Kconfig M src/cpu/x86/Kconfig M src/mainboard/hp/pavilion_m6_1035dx/Kconfig M src/mainboard/lenovo/g505s/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/fsp_baytrail/Kconfig M src/soc/intel/fsp_broadwell_de/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/skylake/Kconfig M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/lynxpoint/Kconfig 23 files changed, 4 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/34128/1 diff --git a/src/Kconfig b/src/Kconfig index 778f169..38209ee 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -543,10 +543,6 @@ file containing NVRAM/CMOS bit definitions. It defaults to 'n' but can be selected in mainboard/*/Kconfig. -config HAVE_SMI_HANDLER - bool - default n - config PCI_IO_CFG_EXT bool default n diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 608afd7..b7ca154 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -98,6 +98,10 @@ bool default y +config HAVE_SMI_HANDLER + bool + default n + config SMM_TSEG bool default n diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig index 7fa04ee..0398e01 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig +++ b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig @@ -26,7 +26,6 @@ select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_ACPI_RESUME - select HAVE_SMI_HANDLER select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index b80019e..e5d6f8e 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -25,7 +25,6 @@ select HAVE_OPTION_TABLE select HAVE_MP_TABLE select HAVE_ACPI_RESUME - select HAVE_SMI_HANDLER select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 select GFXUMA diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index a930f60..70552b0 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -56,7 +56,6 @@ select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select PARALLEL_MP select PARALLEL_MP_AP_WORK - select HAVE_SMI_HANDLER select SMM_TSEG select POSTCAR_STAGE select POSTCAR_CONSOLE diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index ba82565..76eb7b1 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -64,7 +64,6 @@ select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select PARALLEL_MP select PARALLEL_MP_AP_WORK - select HAVE_SMI_HANDLER select SMM_TSEG select POSTCAR_STAGE select POSTCAR_CONSOLE diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 1f819ea..8080e9d 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -46,7 +46,6 @@ select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS select GENERIC_GPIO_LIB select INTEL_DESCRIPTOR_MODE_CAPABLE - select HAVE_SMI_HANDLER select MRC_SETTINGS_PROTECT select MRC_SETTINGS_VARIABLE_DATA select NO_FIXED_XIP_ROM_SIZE diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 43c2906..73c2c66 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -16,7 +16,6 @@ select CACHE_MRC_SETTINGS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select SUPPORT_CPU_UCODE_IN_CBFS - select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_RESET select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 920179f83..7fc5632 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -20,7 +20,6 @@ select MICROCODE_BLOB_NOT_IN_BLOB_REPO select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select HAVE_MONOTONIC_TIMER - select HAVE_SMI_HANDLER select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP select PCIEXP_ASPM diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 801800c..7865726 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -19,7 +19,6 @@ select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_MONOTONIC_TIMER - select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_RESET select HAVE_USBDEBUG select IOAPIC diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 5e405db..9620df3 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -67,7 +67,6 @@ select HAVE_FSP_GOP select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_MONOTONIC_TIMER - select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 273ce30..9af407d 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -36,7 +36,6 @@ select POSTCAR_STAGE select C_ENVIRONMENT_BOOTBLOCK select IOAPIC - select HAVE_SMI_HANDLER select SMM_TSEG select CACHE_MRC_SETTINGS select PARALLEL_MP diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 5228bb7..c28bdc8 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -28,7 +28,6 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_RESET select NO_RELOCATABLE_RAMSTAGE select PARALLEL_MP diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index f71148f..3a94dc29 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -22,7 +22,6 @@ select SUPPORT_CPU_UCODE_IN_CBFS select INTEL_DESCRIPTOR_MODE_CAPABLE select SMM_TSEG - select HAVE_SMI_HANDLER select TSC_MONOTONIC_TIMER select TSC_CONSTANT_RATE select HAVE_FSP_BIN diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index f0b2918..7359814 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -24,7 +24,6 @@ select HAVE_FSP_GOP select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_MONOTONIC_TIMER - select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index fb455d2..dbeb5dc 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -39,7 +39,6 @@ select HAVE_FSP_GOP select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_MONOTONIC_TIMER - select HAVE_SMI_HANDLER select INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select IOAPIC diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index fc3e9fc..0c9dde0 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -32,7 +32,6 @@ select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select IOAPIC select HAVE_USBDEBUG_OPTIONS - select HAVE_SMI_HANDLER select USE_WATCHDOG_ON_BOOT select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index 12640b3..944fdd8 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -18,7 +18,6 @@ bool select ACPI_INTEL_HARDWARE_SLEEP_VALUES select IOAPIC - select HAVE_SMI_HANDLER select HAVE_USBDEBUG select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 2d6e938..f250a76 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -20,7 +20,6 @@ select IOAPIC select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT - select HAVE_SMI_HANDLER select COMMON_FADT select SOUTHBRIDGE_INTEL_COMMON_GPIO select SOUTHBRIDGE_INTEL_COMMON_SMBUS diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 5edb8a1..48ce9c3 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -23,7 +23,6 @@ select IOAPIC select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT - select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS select SOUTHBRIDGE_INTEL_COMMON_GPIO select SOUTHBRIDGE_INTEL_COMMON_SMM diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index b423eca..43c4280 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -24,7 +24,6 @@ select IOAPIC select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT - select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS select SOUTHBRIDGE_INTEL_COMMON_GPIO select INTEL_DESCRIPTOR_MODE_CAPABLE diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 00eb413..e67f5f7 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -23,7 +23,6 @@ select ACPI_INTEL_HARDWARE_SLEEP_VALUES select IOAPIC select HAVE_USBDEBUG - select HAVE_SMI_HANDLER select USE_WATCHDOG_ON_BOOT select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 67e20be..2697120 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -28,7 +28,6 @@ select SOUTHBRIDGE_INTEL_COMMON_FINALIZE select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select IOAPIC - select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS select USE_WATCHDOG_ON_BOOT select PCIEXP_ASPM -- To view, visit https://review.coreboot.org/c/coreboot/+/34128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I332a80ffd9c5dff3efe33e14eabe334cb248296c Gerrit-Change-Number: 34128 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

2 10

Change in coreboot[master]: arch/x86: Drop some HAVE_SMI_HANDLER guards
by Kyösti Mälkki (Code Review) 30 Jul '20

30 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34158 ) Change subject: arch/x86: Drop some HAVE_SMI_HANDLER guards ...................................................................... arch/x86: Drop some HAVE_SMI_HANDLER guards Change-Id: I4f7196febd091325eddceb77870acd40dbe332f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/picasso/Makefile.inc M src/soc/amd/stoneyridge/Makefile.inc M src/soc/intel/denverton_ns/Makefile.inc M src/soc/intel/fsp_broadwell_de/Makefile.inc M src/southbridge/amd/agesa/hudson/Makefile.inc M src/southbridge/amd/pi/hudson/Makefile.inc M src/southbridge/intel/lynxpoint/Makefile.inc 7 files changed, 12 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/34158/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 93a8bbb..7e84e41 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -56,7 +56,7 @@ romstage-y += tsc_freq.c romstage-y += southbridge.c romstage-$(CONFIG_SPI_FLASH) += spi.c -romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c +romstage-y += smi_util.c verstage-y += gpio.c verstage-y += i2c.c @@ -89,7 +89,7 @@ ramstage-y += smbus.c ramstage-y += ramtop.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c +ramstage-y += smi_util.c ramstage-$(CONFIG_PICASSO_UART) += uart.c ramstage-y += usb.c ramstage-y += tsc_freq.c diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index babd878..230640a 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -50,7 +50,7 @@ bootblock-y += southbridge.c bootblock-y += nb_util.c bootblock-$(CONFIG_SPI_FLASH) += spi.c -bootblock-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c +bootblock-y += smi_util.c romstage-y += BiosCallOuts.c romstage-y += i2c.c @@ -68,7 +68,7 @@ romstage-y += southbridge.c romstage-y += nb_util.c romstage-$(CONFIG_SPI_FLASH) += spi.c -romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c +romstage-y += smi_util.c verstage-y += gpio.c verstage-y += i2c.c @@ -105,7 +105,7 @@ ramstage-y += smbus.c ramstage-y += ramtop.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c +ramstage-y += smi_util.c ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c ramstage-y += usb.c ramstage-y += tsc_freq.c diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc index cfd8149..1f12db7 100644 --- a/src/soc/intel/denverton_ns/Makefile.inc +++ b/src/soc/intel/denverton_ns/Makefile.inc @@ -67,7 +67,7 @@ ramstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c +ramstage-y += pmutil.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c diff --git a/src/soc/intel/fsp_broadwell_de/Makefile.inc b/src/soc/intel/fsp_broadwell_de/Makefile.inc index 1aba88b..d957778 100644 --- a/src/soc/intel/fsp_broadwell_de/Makefile.inc +++ b/src/soc/intel/fsp_broadwell_de/Makefile.inc @@ -29,7 +29,7 @@ ramstage-y += gpio.c ramstage-y += iou_complto.c ramstage-y += smmrelocate.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c +ramstage-y += pmutil.c ramstage-y += vtd.c smm-y += pmutil.c smm-y += smihandler.c diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index cd0a1d5..5603a20 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -32,7 +32,8 @@ ramstage-y += imc.c smm-y += smihandler.c smi_util.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c +ramstage-y += smi_util.c # ROMSIG At ROMBASE + 0x20000: # +-----------+---------------+----------------+------------+ diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index c8949b0..ac198aa 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -56,7 +56,7 @@ ramstage-y += sd.c ramstage-y += sm.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c +ramstage-y += smi_util.c ramstage-$(CONFIG_HUDSON_UART) += uart.c ramstage-y += usb.c diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index e53ed8d..8be9234 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -38,10 +38,11 @@ ramstage-y += rcba.c ramstage-y += me_status.c ramstage-y += acpi.c +ramstage-y += pmutil.c ramstage-$(CONFIG_ELOG) += elog.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c pmutil.c +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-y += smihandler.c me_9.x.c pch.c smm-y += pmutil.c usb_ehci.c usb_xhci.c -- To view, visit https://review.coreboot.org/c/coreboot/+/34158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f7196febd091325eddceb77870acd40dbe332f9 Gerrit-Change-Number: 34158 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 5

Change in ...coreboot[master]: [WIP] AGESA: Fix CAR_GLOBAL use for AP CPUs
by Kyösti Mälkki (Code Review) 30 Jul '20

30 Jul '20

Hello Marshall Dawson, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31361 to review the following change. Change subject: [WIP] AGESA: Fix CAR_GLOBAL use for AP CPUs ...................................................................... [WIP] AGESA: Fix CAR_GLOBAL use for AP CPUs The memory between _car_region_start .. _car_region_end has to be set up as WB in MTRRs for all the cores executing through bootblock, verstage and romstage. Otherwise CAR_GLOBALs may fail on AP CPUs. Fixes combination of CBMEM_CONSOLE=y with SQUELCH_EARLY_SMP=n, which previously did not boot at all. Does not fix family14. Change-Id: I3a8a389ca0d7a88c779f27f4ead0d9581465edfd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/vendorcode/amd/agesa/f12/gcccar.inc M src/vendorcode/amd/agesa/f14/gcccar.inc M src/vendorcode/amd/agesa/f15tn/gcccar.inc M src/vendorcode/amd/agesa/f16kb/gcccar.inc 4 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/31361/1 diff --git a/src/vendorcode/amd/agesa/f12/gcccar.inc b/src/vendorcode/amd/agesa/f12/gcccar.inc index 95dd74d..e6dba6a 100644 --- a/src/vendorcode/amd/agesa/f12/gcccar.inc +++ b/src/vendorcode/amd/agesa/f12/gcccar.inc @@ -1451,6 +1451,13 @@ 0: _WRMSR # + # All cores must see BSP stack region that is also used to + # communicate global variables before DRAM is up. + mov $AMD_MTRR_FIX64k_00000, %ecx # MSR:0000_0250 + _RDMSR + or $0x1e000000, %eax + _WRMSR + # Enable MTRR defaults as UC type mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF _RDMSR # Read-modify-write the MSR diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc index 95dd74d..e6dba6a 100644 --- a/src/vendorcode/amd/agesa/f14/gcccar.inc +++ b/src/vendorcode/amd/agesa/f14/gcccar.inc @@ -1451,6 +1451,13 @@ 0: _WRMSR # + # All cores must see BSP stack region that is also used to + # communicate global variables before DRAM is up. + mov $AMD_MTRR_FIX64k_00000, %ecx # MSR:0000_0250 + _RDMSR + or $0x1e000000, %eax + _WRMSR + # Enable MTRR defaults as UC type mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF _RDMSR # Read-modify-write the MSR diff --git a/src/vendorcode/amd/agesa/f15tn/gcccar.inc b/src/vendorcode/amd/agesa/f15tn/gcccar.inc index b13e02a..e96c7f7 100644 --- a/src/vendorcode/amd/agesa/f15tn/gcccar.inc +++ b/src/vendorcode/amd/agesa/f15tn/gcccar.inc @@ -1767,6 +1767,13 @@ 0: _WRMSR # + # All cores must see BSP stack region that is also used to + # communicate global variables before DRAM is up. + mov $AMD_MTRR_FIX64k_00000, %ecx # MSR:0000_0250 + _RDMSR + or $0x1e000000, %eax + _WRMSR + # Enable MTRR defaults as UC type mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF _RDMSR # Read-modify-write the MSR diff --git a/src/vendorcode/amd/agesa/f16kb/gcccar.inc b/src/vendorcode/amd/agesa/f16kb/gcccar.inc index c818d97..26745c9 100644 --- a/src/vendorcode/amd/agesa/f16kb/gcccar.inc +++ b/src/vendorcode/amd/agesa/f16kb/gcccar.inc @@ -1131,6 +1131,13 @@ 0: _WRMSR # + # All cores must see BSP stack region that is also used to + # communicate global variables before DRAM is up. + mov $AMD_MTRR_FIX64k_00000, %ecx # MSR:0000_0250 + _RDMSR + or $0x1e000000, %eax + _WRMSR + # Enable MTRR defaults as UC type mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF _RDMSR # Read-modify-write the MSR -- To view, visit https://review.coreboot.org/c/coreboot/+/31361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a8a389ca0d7a88c779f27f4ead0d9581465edfd Gerrit-Change-Number: 31361 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: [WIP] arch/x86: Drop TSC_SYNC_MFENCE and TSC_SYNC_LFENCE
by Kyösti Mälkki (Code Review) 30 Jul '20

30 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34229 ) Change subject: [WIP] arch/x86: Drop TSC_SYNC_MFENCE and TSC_SYNC_LFENCE ...................................................................... [WIP] arch/x86: Drop TSC_SYNC_MFENCE and TSC_SYNC_LFENCE Change-Id: Ib712fa2c10931da90062bd853318079d5c144f48 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/amd/agesa/Kconfig M src/cpu/amd/family_10h-family_15h/Kconfig M src/cpu/amd/pi/Kconfig M src/cpu/intel/fsp_model_406dx/Kconfig M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_1067x/Kconfig M src/cpu/intel/model_106cx/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_6ex/Kconfig M src/cpu/intel/model_6fx/Kconfig M src/cpu/x86/Kconfig M src/include/cpu/x86/tsc.h M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/fsp_baytrail/Kconfig M src/soc/intel/skylake/Kconfig 21 files changed, 4 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/34229/1 diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 2b8a8c7..af6605e 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -25,7 +25,6 @@ select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select DRIVERS_AMD_PI - select TSC_SYNC_LFENCE select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME select POSTCAR_STAGE diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig index 98be6f6..eff4e18 100644 --- a/src/cpu/amd/family_10h-family_15h/Kconfig +++ b/src/cpu/amd/family_10h-family_15h/Kconfig @@ -5,7 +5,6 @@ select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select SSE2 - select TSC_SYNC_LFENCE select SUPPORT_CPU_UCODE_IN_CBFS select CPU_MICROCODE_MULTIPLE_FILES select ACPI_HUGE_LOWMEM_BACKUP diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index 099f54c..d760cf9 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -24,7 +24,6 @@ select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select DRIVERS_AMD_PI - select TSC_SYNC_LFENCE select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME select POSTCAR_STAGE if !BINARYPI_LEGACY_WRAPPER diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index 0aab0a2..2627265 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -31,7 +31,6 @@ select SUPPORT_CPU_UCODE_IN_CBFS select MICROCODE_BLOB_NOT_IN_BLOB_REPO select PARALLEL_CPU_INIT - select TSC_SYNC_MFENCE select TSC_MONOTONIC_TIMER select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 84a2241..127e8ce 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -16,7 +16,6 @@ select TSC_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS #select AP_IN_SIPI_WAIT - select TSC_SYNC_MFENCE select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select PARALLEL_MP select CPU_INTEL_COMMON diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 2399c41..f1033fa 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -7,7 +7,6 @@ select SMP select SSE2 select TSC_MONOTONIC_TIMER - select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 2d6a387..8333e1d 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -9,7 +9,6 @@ select TSC_MONOTONIC_TIMER select SIPI_VECTOR_IN_ROM select AP_IN_SIPI_WAIT - select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS select SERIALIZED_SMM_INITIALIZATION select CPU_INTEL_COMMON diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 6c65907..8c9c5a1 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -15,7 +15,6 @@ select SUPPORT_CPU_UCODE_IN_CBFS select PARALLEL_CPU_INIT #select AP_IN_SIPI_WAIT - select TSC_SYNC_MFENCE select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE select NO_FIXED_XIP_ROM_SIZE diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 4ed1119..6117480 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -15,7 +15,6 @@ select TSC_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS #select AP_IN_SIPI_WAIT - select TSC_SYNC_MFENCE select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig index 49f4302..a4c3ce2 100644 --- a/src/cpu/intel/model_6ex/Kconfig +++ b/src/cpu/intel/model_6ex/Kconfig @@ -8,7 +8,6 @@ select SSE2 select TSC_MONOTONIC_TIMER select AP_IN_SIPI_WAIT - select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index b31b01d..3724cc1 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -8,7 +8,6 @@ select SSE2 select TSC_MONOTONIC_TIMER select AP_IN_SIPI_WAIT - select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 0bf2f0d..dd7c8d9 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -30,22 +30,6 @@ help Expose monotonic time using the TSC. -config TSC_SYNC_LFENCE - bool - default n - help - The CPU driver should select this if the CPU needs - to execute an lfence instruction in order to synchronize - rdtsc. This is true for all modern AMD CPUs. - -config TSC_SYNC_MFENCE - bool - default n - help - The CPU driver should select this if the CPU needs - to execute an mfence instruction in order to synchronize - rdtsc. This is true for all modern Intel CPUs. - config NO_FIXED_XIP_ROM_SIZE bool default n diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index 23b74b2..8b7807b 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -3,10 +3,12 @@ #include <stdint.h> -#if CONFIG(TSC_SYNC_MFENCE) +#if CONFIG(CPU_INTEL_COMMON) #define TSC_SYNC "mfence\n" -#elif CONFIG(TSC_SYNC_LFENCE) +#elif CONFIG(DRIVERS_AMD_PI) || CONFIG(CPU_AMD_MODEL_10XXX) #define TSC_SYNC "lfence\n" +#elif CONFIG(TSC_MONOTONIC_TIMER) +#error "Undefined rdtsc() fence" #else #define TSC_SYNC #endif diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index d654e94..6f46706 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -35,7 +35,6 @@ select IOAPIC select HAVE_USBDEBUG_OPTIONS select SPI_FLASH if HAVE_ACPI_RESUME - select TSC_SYNC_LFENCE select COLLECT_TIMESTAMPS select SOC_AMD_PI select SOC_AMD_COMMON diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 465df60..622fad9 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -39,7 +39,6 @@ select IOAPIC select HAVE_USBDEBUG_OPTIONS select SPI_FLASH if HAVE_ACPI_RESUME - select TSC_SYNC_LFENCE select COLLECT_TIMESTAMPS select SOC_AMD_PI select SOC_AMD_COMMON diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 46ef898..29be910 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -28,7 +28,6 @@ select SPI_FLASH select SSE2 select TSC_MONOTONIC_TIMER - select TSC_SYNC_MFENCE select SOC_INTEL_COMMON select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SPI_CONSOLE_SUPPORT diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 5d2a776..bf8133b 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -37,7 +37,6 @@ select SPI_FLASH select SSE2 select TSC_MONOTONIC_TIMER - select TSC_SYNC_MFENCE select USE_GENERIC_FSP_CAR_INC select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SPI_CONSOLE_SUPPORT diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 6bec847..663dbdc 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -28,7 +28,6 @@ select SMP select SPI_FLASH select SSE2 - select TSC_SYNC_MFENCE select SOC_INTEL_COMMON select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 3bf608e..d9b86b9 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -53,7 +53,6 @@ select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_PCR select TSC_MONOTONIC_TIMER - select TSC_SYNC_MFENCE select UDK_2015_BINDING select CPU_INTEL_FIRMWARE_INTERFACE_TABLE diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 38777c5..820b396 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -36,7 +36,6 @@ select SMP select SPI_FLASH select SSE2 - select TSC_SYNC_MFENCE select TSC_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS select MICROCODE_BLOB_NOT_HOOKED_UP diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 3d7a530..94b6585 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -75,7 +75,6 @@ select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER - select TSC_SYNC_MFENCE config CPU_INTEL_NUM_FIT_ENTRIES int -- To view, visit https://review.coreboot.org/c/coreboot/+/34229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib712fa2c10931da90062bd853318079d5c144f48 Gerrit-Change-Number: 34229 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

1 3

Change in coreboot[master]: [WIP] arch/x86: Use udelay() from monotonic timer
by Kyösti Mälkki (Code Review) 30 Jul '20

30 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34204 ) Change subject: [WIP] arch/x86: Use udelay() from monotonic timer ...................................................................... [WIP] arch/x86: Use udelay() from monotonic timer Change-Id: I2e768346b21758a386064346aff2ee8592a8e991 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/Kconfig M src/cpu/amd/agesa/Kconfig M src/cpu/amd/family_10h-family_15h/Kconfig M src/cpu/amd/pi/00630F01/fixme.c M src/cpu/amd/pi/00660F01/fixme.c M src/cpu/amd/pi/00730F01/fixme.c M src/cpu/amd/pi/Kconfig M src/cpu/intel/fsp_model_406dx/Kconfig M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_1067x/Kconfig M src/cpu/intel/model_106cx/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_6ex/Kconfig M src/cpu/intel/model_6fx/Kconfig M src/cpu/intel/socket_mPGA604/Kconfig M src/cpu/qemu-x86/Kconfig M src/cpu/via/nano/Kconfig M src/cpu/x86/Kconfig M src/cpu/x86/lapic/Makefile.inc M src/cpu/x86/lapic/apic_timer.c M src/cpu/x86/tsc/Makefile.inc M src/cpu/x86/tsc/delay_tsc.c M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/fsp_baytrail/Kconfig M src/soc/intel/fsp_broadwell_de/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/quark/Kconfig M src/soc/intel/skylake/Kconfig 35 files changed, 15 insertions(+), 100 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/34204/1 diff --git a/src/Kconfig b/src/Kconfig index ec0f35b..4a879e3 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -514,7 +514,7 @@ config GENERIC_UDELAY bool depends on HAVE_MONOTONIC_TIMER - default y if !ARCH_X86 + default y help The board/chipset uses a generic udelay function utilizing the monotonic timer. diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 4c5463c..2b8a8c7 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -26,7 +26,6 @@ select ARCH_RAMSTAGE_X86_32 select DRIVERS_AMD_PI select TSC_SYNC_LFENCE - select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME select POSTCAR_STAGE diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig index df65499..98be6f6 100644 --- a/src/cpu/amd/family_10h-family_15h/Kconfig +++ b/src/cpu/amd/family_10h-family_15h/Kconfig @@ -6,7 +6,6 @@ select ARCH_RAMSTAGE_X86_32 select SSE2 select TSC_SYNC_LFENCE - select UDELAY_LAPIC select SUPPORT_CPU_UCODE_IN_CBFS select CPU_MICROCODE_MULTIPLE_FILES select ACPI_HUGE_LOWMEM_BACKUP diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c index 10fd9f5..1923b08 100644 --- a/src/cpu/amd/pi/00630F01/fixme.c +++ b/src/cpu/amd/pi/00630F01/fixme.c @@ -88,7 +88,7 @@ MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - if (CONFIG(UDELAY_LAPIC)){ + if (CONFIG(LAPIC_MONOTONIC_TIMER)) { LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); MsrReg |= 1 << 11; LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c index 2cbeab8..b4719a3 100644 --- a/src/cpu/amd/pi/00660F01/fixme.c +++ b/src/cpu/amd/pi/00660F01/fixme.c @@ -94,7 +94,7 @@ MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - if (CONFIG(UDELAY_LAPIC)) { + if (CONFIG(LAPIC_MONOTONIC_TIMER)) { LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); MsrReg |= 1 << 11; LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c index 3769319..761c716 100644 --- a/src/cpu/amd/pi/00730F01/fixme.c +++ b/src/cpu/amd/pi/00730F01/fixme.c @@ -99,7 +99,7 @@ MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - if (CONFIG(UDELAY_LAPIC)) { + if (CONFIG(LAPIC_MONOTONIC_TIMER)) { LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); MsrReg |= 1 << 11; LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index a902089..099f54c 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -25,7 +25,6 @@ select ARCH_RAMSTAGE_X86_32 select DRIVERS_AMD_PI select TSC_SYNC_LFENCE - select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME select POSTCAR_STAGE if !BINARYPI_LEGACY_WRAPPER diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index 8649777..0aab0a2 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -28,7 +28,6 @@ select SMP select MMX select SSE2 - select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS select MICROCODE_BLOB_NOT_IN_BLOB_REPO select PARALLEL_CPU_INIT diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index d8d8b97..84a2241 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -13,7 +13,6 @@ select SMP select MMX select SSE2 - select UDELAY_TSC select TSC_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS #select AP_IN_SIPI_WAIT diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 0c74c69..cdf7991 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -6,7 +6,6 @@ select ARCH_RAMSTAGE_X86_32 select SMP select SSE2 - select UDELAY_TSC select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index dbfda01..2f22bed 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -6,7 +6,6 @@ select ARCH_RAMSTAGE_X86_32 select SMP select SSE2 - select UDELAY_TSC select SIPI_VECTOR_IN_ROM select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index f098526..6c65907 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -11,7 +11,6 @@ select ARCH_RAMSTAGE_X86_32 select SMP select SSE2 - select UDELAY_TSC select TSC_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS select PARALLEL_CPU_INIT diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 72f04da..4ed1119 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -12,7 +12,6 @@ select SMP select MMX select SSE2 - select UDELAY_TSC select TSC_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS #select AP_IN_SIPI_WAIT diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig index 29ef306..c06922b 100644 --- a/src/cpu/intel/model_6ex/Kconfig +++ b/src/cpu/intel/model_6ex/Kconfig @@ -6,7 +6,6 @@ select ARCH_RAMSTAGE_X86_32 select SMP select SSE2 - select UDELAY_TSC select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index df67f51..3b58463 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -6,7 +6,6 @@ select ARCH_RAMSTAGE_X86_32 select SMP select SSE2 - select UDELAY_TSC select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index a2ebeb2..e4dcba3 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -8,7 +8,6 @@ select CPU_INTEL_MODEL_F2X select MMX select SSE - select UDELAY_TSC select TSC_MONOTONIC_TIMER select SIPI_VECTOR_IN_ROM select C_ENVIRONMENT_BOOTBLOCK diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index d586125..9385684 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -20,7 +20,6 @@ select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select SMP - select UDELAY_TSC select TSC_MONOTONIC_TIMER select C_ENVIRONMENT_BOOTBLOCK select SMM_ASEG diff --git a/src/cpu/via/nano/Kconfig b/src/cpu/via/nano/Kconfig index aeb81ac..ad1f612 100644 --- a/src/cpu/via/nano/Kconfig +++ b/src/cpu/via/nano/Kconfig @@ -25,7 +25,6 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select UDELAY_TSC select TSC_MONOTONIC_TIMER select MMX select SSE2 diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 24dc1f4..0bf2f0d 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -17,26 +17,16 @@ Allow APs to do other work after initialization instead of going to sleep. -config UDELAY_LAPIC - bool - default n - config LAPIC_MONOTONIC_TIMER def_bool n - depends on UDELAY_LAPIC help Expose monotonic time using the local APIC. config UDELAY_LAPIC_FIXED_FSB int -config UDELAY_TSC - bool - default n - config TSC_MONOTONIC_TIMER def_bool n - depends on UDELAY_TSC help Expose monotonic time using the TSC. diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index 9454f8f..058e25b 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -1,9 +1,9 @@ ramstage-y += lapic.c ramstage-y += lapic_cpu_init.c ramstage-$(CONFIG_SMP) += secondary.S -romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c -ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c -postcar-$(CONFIG_UDELAY_LAPIC) += apic_timer.c +romstage-$(CONFIG_LAPIC_MONOTONIC_TIMER) += apic_timer.c +ramstage-$(CONFIG_LAPIC_MONOTONIC_TIMER) += apic_timer.c +postcar-$(CONFIG_LAPIC_MONOTONIC_TIMER) += apic_timer.c bootblock-y += boot_cpu.c verstage-y += boot_cpu.c romstage-y += boot_cpu.c diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 2e0583b..639a89a 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -22,6 +22,7 @@ #include <arch/early_variables.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> +#include <timer.h> void init_timer(void) { @@ -38,33 +39,6 @@ set_timer_fsb(); } -void udelay(u32 usecs) -{ - u32 start, value, ticks, timer_fsb; - - if (!thread_yield_microseconds(usecs)) - return; - - timer_fsb = get_timer_fsb(); - if (!timer_fsb || (lapic_read(LAPIC_LVTT) & - (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED)) != - (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED)) { - init_timer(); - timer_fsb = get_timer_fsb(); - } - - /* Calculate the number of ticks to run, our FSB runs at timer_fsb Mhz - */ - ticks = usecs * timer_fsb; - start = lapic_read(LAPIC_TMCCT); - do { - value = lapic_read(LAPIC_TMCCT); - } while ((start - value) < ticks); -} - -#if CONFIG(LAPIC_MONOTONIC_TIMER) -#include <timer.h> - static struct monotonic_counter { int initialized; struct mono_time time; @@ -108,4 +82,3 @@ /* Save result. */ *mt = mono_counter->time; } -#endif diff --git a/src/cpu/x86/tsc/Makefile.inc b/src/cpu/x86/tsc/Makefile.inc index b3925b5..592acb3 100644 --- a/src/cpu/x86/tsc/Makefile.inc +++ b/src/cpu/x86/tsc/Makefile.inc @@ -1,6 +1,6 @@ -bootblock-$(CONFIG_UDELAY_TSC) += delay_tsc.c -ramstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c -romstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c -verstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c -postcar-$(CONFIG_UDELAY_TSC) += delay_tsc.c -smm-$(CONFIG_UDELAY_TSC) += delay_tsc.c +bootblock-$(CONFIG_TSC_MONOTONIC_TIMER) += delay_tsc.c +ramstage-$(CONFIG_TSC_MONOTONIC_TIMER) += delay_tsc.c +romstage-$(CONFIG_TSC_MONOTONIC_TIMER) += delay_tsc.c +verstage-$(CONFIG_TSC_MONOTONIC_TIMER) += delay_tsc.c +postcar-$(CONFIG_TSC_MONOTONIC_TIMER) += delay_tsc.c +smm-$(CONFIG_TSC_MONOTONIC_TIMER) += delay_tsc.c diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index 515919a..7789c7a 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -16,6 +16,7 @@ #include <smp/spinlock.h> #include <delay.h> #include <thread.h> +#include <timer.h> static unsigned long clocks_per_usec CAR_GLOBAL; @@ -31,28 +32,6 @@ return car_get_var(clocks_per_usec); } -void udelay(unsigned int us) -{ - unsigned long long start; - unsigned long long current; - unsigned long long clocks; - - if (!thread_yield_microseconds(us)) - return; - - start = rdtscll(); - clocks = us; - clocks *= get_clocks_per_usec(); - current = rdtscll(); - while ((current - start) < clocks) { - cpu_relax(); - current = rdtscll(); - } -} - -#if CONFIG(TSC_MONOTONIC_TIMER) -#include <timer.h> - static struct monotonic_counter { int initialized; struct mono_time time; @@ -94,4 +73,3 @@ /* Save result. */ *mt = mono_counter->time; } -#endif diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 78b89e3..465df60 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -36,7 +36,6 @@ select COLLECT_TIMESTAMPS_NO_TSC select DRIVERS_I2C_DESIGNWARE select GENERIC_GPIO_LIB - select GENERIC_UDELAY select IOAPIC select HAVE_USBDEBUG_OPTIONS select SPI_FLASH if HAVE_ACPI_RESUME diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 36b3b82..04cfef1 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -98,7 +98,6 @@ select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_CSE - select UDELAY_TSC select TSC_MONOTONIC_TIMER select PLATFORM_USES_FSP2_0 select UDK_2015_BINDING if !SOC_INTEL_GLK diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 251f4fb..46ef898 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -29,7 +29,6 @@ select SSE2 select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE - select UDELAY_TSC select SOC_INTEL_COMMON select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SPI_CONSOLE_SUPPORT diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index a33ac2f..5d2a776 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -38,7 +38,6 @@ select SSE2 select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE - select UDELAY_TSC select USE_GENERIC_FSP_CAR_INC select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SPI_CONSOLE_SUPPORT diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 4b59aaa..6bec847 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -29,7 +29,6 @@ select SPI_FLASH select SSE2 select TSC_SYNC_MFENCE - select UDELAY_TSC select SOC_INTEL_COMMON select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index cc502f9..4750c6b 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -103,7 +103,6 @@ select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER - select UDELAY_TSC select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO select FSP_T_XIP if FSP_CAR diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index bee6e88..3bf608e 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -54,7 +54,6 @@ select SOC_INTEL_COMMON_BLOCK_PCR select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE - select UDELAY_TSC select UDK_2015_BINDING select CPU_INTEL_FIRMWARE_INTERFACE_TABLE diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index b0da459..38777c5 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -37,7 +37,6 @@ select SPI_FLASH select SSE2 select TSC_SYNC_MFENCE - select UDELAY_TSC select TSC_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS select MICROCODE_BLOB_NOT_HOOKED_UP diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index 8e301df..38c7941 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -18,7 +18,6 @@ select PARALLEL_MP select SMP select IOAPIC - select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index ad80abc..b9dce1e 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -56,7 +56,6 @@ select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER - select UDELAY_TSC select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO select HECI_DISABLE_USING_SMM diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index bb73780..ee2e791 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -34,7 +34,6 @@ select SOC_SETS_MSRS select SPI_FLASH select UART_OVERRIDE_REFCLK - select UDELAY_TSC select UNCOMPRESSED_RAMSTAGE select USE_MARCH_586 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 04c8bd9..3d7a530 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -76,7 +76,6 @@ select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE - select UDELAY_TSC config CPU_INTEL_NUM_FIT_ENTRIES int -- To view, visit https://review.coreboot.org/c/coreboot/+/34204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e768346b21758a386064346aff2ee8592a8e991 Gerrit-Change-Number: 34204 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

4 16

Change in libgfxinit[master]: gma panel: Report used timings
by Nico Huber (Code Review) 30 Jul '20

30 Jul '20

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/34472 ) Change subject: gma panel: Report used timings ...................................................................... gma panel: Report used timings Change-Id: If7a3b7ec755d85b9d570b8031ea4a2a31fe37514 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/hw-gfx-gma-panel.adb 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/72/34472/1 diff --git a/common/hw-gfx-gma-panel.adb b/common/hw-gfx-gma-panel.adb index ba91254..bc0f7b8 100644 --- a/common/hw-gfx-gma-panel.adb +++ b/common/hw-gfx-gma-panel.adb @@ -141,7 +141,15 @@ if Delays (D) = 0 then Delays (D) := Default_EDP_Delays_US (D); Override := True; + + pragma Debug (Debug.Put ("PP: Using default ")); + else + pragma Debug (Debug.Put ("PP: Using preset ")); end if; + pragma Debug (Debug.Put (Delays_Enum'Image (D))); + pragma Debug (Debug.Put (" of ")); + pragma Debug (Debug.Put_Int32 (Int32 (Delays (D)))); + pragma Debug (Debug.Put_Line (" us.")); end loop; end Check_PP_Delays; -- To view, visit https://review.coreboot.org/c/libgfxinit/+/34472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: If7a3b7ec755d85b9d570b8031ea4a2a31fe37514 Gerrit-Change-Number: 34472 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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