coreboot-gerrit June 2019

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Change in ...coreboot[master]: arch/x86/mmio: Avoid pointer aliasing in write8()
by Nico Huber (Code Review) 10 Jun '23

10 Jun '23

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31945 Change subject: arch/x86/mmio: Avoid pointer aliasing in write8() ...................................................................... arch/x86/mmio: Avoid pointer aliasing in write8() Don't literally dereference a pointer to `char`. Use array indexing instead to avoid aliasing rules. Otherwise, the compiler might treat any memory as clobbered. Change-Id: I441c27e789ad92a8125c92837244474a26250c8a Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/arch/x86/include/arch/mmio.h 1 file changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/31945/1 diff --git a/src/arch/x86/include/arch/mmio.h b/src/arch/x86/include/arch/mmio.h index f271a97..790b699 100644 --- a/src/arch/x86/include/arch/mmio.h +++ b/src/arch/x86/include/arch/mmio.h @@ -45,7 +45,15 @@ static __always_inline void write8(volatile void *addr, uint8_t value) { - *((volatile uint8_t *)(addr)) = value; + /* + * Don't literally dereference a pointer to `char`. Use array + * indexing instead to avoid aliasing rules. Otherwise, the + * compiler might treat any memory as clobbered. + */ + volatile struct { + uint8_t reg[1]; + } *const ref = addr; + ref->reg[0] = value; } static __always_inline void write16(volatile void *addr, -- To view, visit https://review.coreboot.org/c/coreboot/+/31945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I441c27e789ad92a8125c92837244474a26250c8a Gerrit-Change-Number: 31945 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: Documentation: Explain DDR3 read training
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32334 Change subject: Documentation: Explain DDR3 read training ...................................................................... Documentation: Explain DDR3 read training Add lots of colorful graphics to explain DDR3 read training in detail, what is done inside MCH and what needs to be done on firmware level. Besides read training give a short explenation what DDR3 "FlyBy" is and compare it with DDR2 DIMMs. Besides the SVG all sources files are added. Change-Id: Ib477bd332984c397289404cfc33c65a2d4469257 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/getting_started/index.md A Documentation/getting_started/ram_initialization/16delay.dia A Documentation/getting_started/ram_initialization/16delay.svg A Documentation/getting_started/ram_initialization/64delay.dia A Documentation/getting_started/ram_initialization/64delay.svg A Documentation/getting_started/ram_initialization/DRAM_data_clock_lanes_skew.dia A Documentation/getting_started/ram_initialization/DRAM_data_clock_lanes_skew.svg A Documentation/getting_started/ram_initialization/ddr3_flyby.md A Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.dia A Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.svg A Documentation/getting_started/ram_initialization/index.md A Documentation/getting_started/ram_initialization/read_training.dia A Documentation/getting_started/ram_initialization/read_training.svg A Documentation/getting_started/ram_initialization/read_training2.dia A Documentation/getting_started/ram_initialization/read_training2.svg A Documentation/getting_started/ram_initialization/read_training3.dia A Documentation/getting_started/ram_initialization/read_training3.svg A Documentation/getting_started/ram_initialization/read_training_pattern.dia A Documentation/getting_started/ram_initialization/read_training_pattern.svg A Documentation/getting_started/ram_initialization/readtraining.md A Documentation/getting_started/ram_initialization/recv_blocks.dia A Documentation/getting_started/ram_initialization/recv_blocks.svg 22 files changed, 1,989 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/32334/1 diff --git a/Documentation/getting_started/index.md b/Documentation/getting_started/index.md index 52d873e..a265c5d 100644 --- a/Documentation/getting_started/index.md +++ b/Documentation/getting_started/index.md @@ -7,3 +7,4 @@ * [Gerrit Guidelines](gerrit_guidelines.md) * [Documentation License](license.md) * [Writing Documentation](writing_documentation.md) +* [DDR3 memory initialization](ram_initialization/index.md) diff --git a/Documentation/getting_started/ram_initialization/16delay.dia b/Documentation/getting_started/ram_initialization/16delay.dia new file mode 100644 index 0000000..d0e0095 --- /dev/null +++ b/Documentation/getting_started/ram_initialization/16delay.dia Binary files differ diff --git a/Documentation/getting_started/ram_initialization/16delay.svg b/Documentation/getting_started/ram_initialization/16delay.svg new file mode 100644 index 0000000..f661ddd --- /dev/null +++ b/Documentation/getting_started/ram_initialization/16delay.svg @@ -0,0 +1,177 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.0//EN" "http://www.w3.org/TR/2001/PR-SVG-20010719/DTD/svg10.dtd"> +<svg width="38cm" height="18cm" viewBox="366 265 754 351" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"> + <g> + <rect style="fill: #ffffff" x="367.719" y="266.052" width="751.775" height="348.316"/> + <rect style="fill: none; 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As every DIMM only needs to terminate the line once at end of PCB, +the DC resistance is much lower as on DDR2 "tree" routing topology, which did +terminate on every IC. + +The disadvantage of "fly-by" is the more complex memory training that needs to +be done to find the DATA lane skew. + +After the skew has been measured, the DATA lanes needs to be delayed by the +memory controller, to make sure all signals are still synchronous to the CLK, +as seen be the memory controller (on READ) or the DRAM (on WRITE). + +![][flyby] + +[flyby]: ddr3_vs_ddr2.svg + +```eval_rst ++---------------------------+------------+----------------+ +| Feature | DDR2 | DDR3 | ++===========================+============+================+ +| Frequency | 200-533 | 400-800 | ++---------------------------+------------+----------------+ +| Routing | complex | easy | ++---------------------------+------------+----------------+ +| Termination DC resistance | very high | low | ++---------------------------+------------+----------------+ +| Memory training | easy | complex | ++---------------------------+------------+----------------+ +``` + diff --git a/Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.dia b/Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.dia new file mode 100644 index 0000000..e4b4d09 --- /dev/null +++ b/Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.dia Binary files differ diff --git a/Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.svg b/Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.svg new file mode 100644 index 0000000..0b8db34 --- /dev/null +++ b/Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.svg @@ -0,0 +1,298 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.0//EN" "http://www.w3.org/TR/2001/PR-SVG-20010719/DTD/svg10.dtd"> +<svg width="17cm" height="10cm" viewBox="507 221 325 192" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"> + <g> + <rect style="fill: #ffffff" x="508.366" y="221.748" width="323.85" height="190.069"/> + <rect style="fill: none; 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It is usually done by firmware. +As soon as the skew is known, the DATA lanes can be individually delayed +by a constant rate to synchronize the DATA arriving at the MCH. + +For read training the DIMM is placed into a special mode where it outputs +a known pattern. The pattern looks like this: + +![][pat] + +[pat]: read_training_pattern.svg + +Due to the different skew of the lanes, the data arrives at different times +on the MCH. It's no longer synchronous to the CLK or other DATA lanes: + +![][read1] + +[read1]: read_training.svg + +The MCH must delay the signals to synchronize them again. + +### Delay units +The MCH is able to delay all lanes individually or at once. The delay +circuit inside the MCH consists of a *phase delay unit* and *CLK delay units*. +The *phase delay unit* delays by a fraction of the CLK, while the +*CLK delay unit* delays in multiple of the CLK. + +They can be configured by firmware using registers inside the MCH. + +#### Phase delay +The phase delay unit might look like this: + +![][delay64] + +[delay64]: 64delay.svg + +The phase delay can be adjusted by software by writing a register that selects +the MUX input. In this example the signal can be shifted by 64 1/64 CLKs. + +Applied to the DQS as seen on READ command, the signal can be delayed to be synchronous +to the CLK as seen by the MCH: + +![][read2] + +[read2]: read_training2.svg + + +#### CLK delay +The CLK delay unit might look like this: + +![][delay16] + +[delay16]: 16delay.svg + +The CLK delay can be adjusted by software by writing a register that selects +the MUX input. In this example the signal can be delayed by 16 CLKs. + +Applied to the DQS as seen on READ command, the signal can be delayed to be synchronous +to the other DQS lanes: + +![][read3] + +[read3]: read_training3.svg + +#### Combined delay + +Both units are connected in row for each DQS/DATA lane: + +![][blocks] + +[blocks]: recv_blocks.svg + +For each lane (here 8 + 1), there's a 10bit register allowing to adjust the +delay. + +## Finding the right delay + +Assuming a 1/64th phase delay unit, the firmware guesses the initial skew and then places the phase in the alternating data pattern. It then adjest the phase and measures the sampled value. + +The following algorithm is used: + +1. Samples all lanes using 128 (64 + 1 full CLK) different phase delays. It allows to find the rising edge in the pattern. +2. In the next step the phase delay is reduced by 32 (1/2 CLK) to position the sample in a logic "low". +3. For each lane the delay is reduced by 128 (2 CLKs) until a logic "high" is sampled. That the preamble of the pattern. +4. As next step the delay is increased by 96 (1.5 CLKs) to position at the first falling edge. +5. Multiple samples in the range -0.5 to 0.5 CLKS are done to find the exact point of falling edge. + +Read training has now found the exact delay for each lane and stores the values for the next boot. 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Change in ...coreboot[master]: RFC: smbios: allow setting BIOS-version string from VPD variable
by Łukasz Siudut (Code Review) 10 Jun '23

10 Jun '23

Łukasz Siudut has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32905 Change subject: RFC: smbios: allow setting BIOS-version string from VPD variable ...................................................................... RFC: smbios: allow setting BIOS-version string from VPD variable As in the title. Such approach allows for convenient setting of the firmware version and keep it in partition that is easily readable from both - coreboot binary and already running operating system. vpd_find is used directly as it returns pointer to vpd value which, by spec, is terminated by 0x00 (VPD_TYPE_TERMINATOR) anyway. This way we avoid copying string around and coming up with temporary buffer. Change-Id: If0e9d90ed0941c4e76e3e48cdcccf830ef789458 Signed-off-by: Lukasz Siudut <lsiudut(a)gmail.com> --- M src/arch/x86/smbios.c 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/32905/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 589f4f0..2ffd2dd 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -30,6 +30,9 @@ #include <memory_info.h> #include <spd.h> #include <cbmem.h> +#if CONFIG(VPD) +#include <drivers/vpd/vpd.h> +#endif #if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -347,6 +350,15 @@ const char *__weak smbios_mainboard_bios_version(void) { +#if CONFIG(VPD) + /* size is unused for now */ + int size; + const char *coreboot_vpd_version = vpd_find("version", &size, VPD_RO); + + /* if found, vpd value will be terminated by 0x00 (VPD_TYPE_TERMINATOR) */ + if(coreboot_vpd_version) + return coreboot_vpd_version; +#endif if (strlen(CONFIG_LOCALVERSION)) return CONFIG_LOCALVERSION; else -- To view, visit https://review.coreboot.org/c/coreboot/+/32905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0e9d90ed0941c4e76e3e48cdcccf830ef789458 Gerrit-Change-Number: 32905 Gerrit-PatchSet: 1 Gerrit-Owner: Łukasz Siudut Gerrit-MessageType: newchange

6 14

Change in ...coreboot[master]: arch/riscv: Fix arch timer timebase
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33797 Change subject: arch/riscv: Fix arch timer timebase ...................................................................... arch/riscv: Fix arch timer timebase The arch timer uses a platform specific clock source. Add a Kconfig that holds this clock frequency and use it to calculate the time passed by. Tested on qemu-system-riscv: Fixes delays being ten times shorter as expected. Change-Id: I2588149e2ee32130a2c41695c4c723b57d4fa827 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/riscv/Kconfig M src/arch/riscv/arch_timer.c M src/soc/sifive/fu540/Kconfig M src/soc/ucb/riscv/Kconfig 4 files changed, 22 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/33797/1 diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index 25a3980..6b12ff0 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -72,5 +72,9 @@ bool default n +config RISCV_ARCH_TIMER_FREQ + int + depends on RISCV_USE_ARCH_TIMER + config RISCV_WORKING_HARTID int diff --git a/src/arch/riscv/arch_timer.c b/src/arch/riscv/arch_timer.c index 55b1f72..71b9771 100644 --- a/src/arch/riscv/arch_timer.c +++ b/src/arch/riscv/arch_timer.c @@ -20,9 +20,18 @@ #include <timer.h> #include <mcall.h> +/* mtime is clocked by platform specific clock source */ +static const uint32_t clocks_per_usec = CONFIG_RISCV_ARCH_TIMER_FREQ/1000000; + void timer_monotonic_get(struct mono_time *mt) { + uint64_t raw; + if (HLS()->time == NULL) die("time not set in HLS"); - mono_time_set_usecs(mt, (long)read64((void *)(HLS()->time))); + if (!clocks_per_usec) + die("Unsupported mtime clock frequency"); + + raw = read64((void *)(HLS()->time)); + mono_time_set_usecs(mt, (long)(raw / clocks_per_usec)); } diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig index 6ebde33..a10a146 100644 --- a/src/soc/sifive/fu540/Kconfig +++ b/src/soc/sifive/fu540/Kconfig @@ -49,4 +49,8 @@ int default 0 +config RISCV_ARCH_TIMER_FREQ + int + default 1000000 + endif diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig index ad48c1c..49887a4 100644 --- a/src/soc/ucb/riscv/Kconfig +++ b/src/soc/ucb/riscv/Kconfig @@ -14,6 +14,10 @@ if SOC_UCB_RISCV +config RISCV_ARCH_TIMER_FREQ + int + default 10000000 + if ARCH_RISCV_RV64 config RISCV_ARCH -- To view, visit https://review.coreboot.org/c/coreboot/+/33797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2588149e2ee32130a2c41695c4c723b57d4fa827 Gerrit-Change-Number: 33797 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

7 13

Change in ...coreboot[master]: for review d945gclf/Kconig and devicetree.cb . these files are modif...
by junaid (Code Review) 10 Jun '23

10 Jun '23

junaid has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30798 Change subject: for review d945gclf/Kconig and devicetree.cb . these files are modified according to the superIO chip Winbond w83627DHG ...................................................................... for review d945gclf/Kconig and devicetree.cb . these files are modified according to the superIO chip Winbond w83627DHG Change-Id: I1449d9351bd1b76ecad16e6d81c501c1d4dd80f5 Signed-off-by: junaid <junaidimpex(a)gmail.com> --- M src/mainboard/intel/d945gclf/Kconfig M src/mainboard/intel/d945gclf/devicetree.cb 2 files changed, 37 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/30798/1 diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig index 70fa848..906dd01 100644 --- a/src/mainboard/intel/d945gclf/Kconfig +++ b/src/mainboard/intel/d945gclf/Kconfig @@ -20,7 +20,8 @@ select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GC select SOUTHBRIDGE_INTEL_I82801GX - select SUPERIO_SMSC_LPC47M15X +## changed as per Advantech SOM 4461 + select SUPERIO_WINBOND_W83627DHG select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index 90c517f..864775a 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -65,44 +65,42 @@ device pci 1d.1 on end # USB UHCI device pci 1d.2 on end # USB UHCI device pci 1d.3 off end # USB UHCI - device pci 1d.7 on end # USB2 EHCI - device pci 1e.0 on end # PCI bridge - device pci 1e.2 off end # AC'97 Audio + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on end # PCI bridge + device pci 1e.2 off end # AC'97 Audio device pci 1e.3 off end # AC'97 Modem device pci 1f.0 on # LPC bridge - chip superio/smsc/lpc47m15x - device pnp 2e.0 off # Floppy - end - device pnp 2e.3 off # Parport - end - device pnp 2e.4 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 on - io 0x60 = 0x2f8 - irq 0x70 = 3 - irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq - end - device pnp 2e.7 on # Keyboard+Mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - irq 0xf0 = 0x82 # HW accel A20. - end - device pnp 2e.8 on # GAME - # all default - end - device pnp 2e.a on # PME - end - device pnp 2e.b on # MPU - end - end - end + chip superio/winbond/w83627dhg + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel Port + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard,Mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + #device pnp 2e.6 off end # SPI + device pnp 2e.307 off end # GPIO6 + device pnp 2e.8 off end # WDTO, PLED + device pnp 2e.009 off end # GPIO2 + device pnp 2e.109 off end # GPIO3 + device pnp 2e.209 off end # GPIO4 + device pnp 2e.309 off end # GPIO5 + device pnp 2e.A off end # ACPI + device pnp 2e.B off end # HW Monitor + end # w83627dhg + end device pci 1f.1 off end # IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - end - end + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus + end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/30798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1449d9351bd1b76ecad16e6d81c501c1d4dd80f5 Gerrit-Change-Number: 30798 Gerrit-PatchSet: 1 Gerrit-Owner: junaid <junaidimpex(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP]device/pci_rom: Add ATRM method
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31502 Change subject: [WIP]device/pci_rom: Add ATRM method ...................................................................... [WIP]device/pci_rom: Add ATRM method Add ATRM method for AMD GPUs, which is similar to _ROM. As both functions seem to have identical arguments and return values, redirect ATRM to _ROM. Don't depend on VGA devices, but display devices, as some AMD dGPUs identify themself as PCI_CLASS_DISPLAY_OTHER. Needs test on platforms with AMD display devices. Change-Id: Id2212f29f0de051f6cbd59f8332e86696c1166ab Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/device/pci_rom.c 1 file changed, 15 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/31502/1 diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 82d9a30..86c839c 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -272,8 +272,8 @@ { static size_t ngfx; - /* Only handle VGA devices */ - if ((device->class >> 8) != PCI_CLASS_DISPLAY_VGA) + /* Only handle display devices */ + if ((device->class >> 16) != PCI_BASE_CLASS_DISPLAY) return; /* Only handle enabled devices */ @@ -319,9 +319,21 @@ memcpy(cbrom, rom, cbrom_length); - /* write _ROM method */ + /* write ACPI methods */ acpigen_write_scope(scope); + + /* Nvidia uses _ROM */ acpigen_write_rom(cbrom, cbrom_length); + + /* AMD uses ATRM. Redirect ATRM to _ROM */ + acpigen_write_method_serialized("ATRM", 2); + acpigen_write_to_integer(ARG1_OP, LOCAL0_OP); + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring("_ROM"); + acpigen_emit_byte(ARG0_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_pop_len(); /* pop method */ + acpigen_pop_len(); /* pop scope */ } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2212f29f0de051f6cbd59f8332e86696c1166ab Gerrit-Change-Number: 31502 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch:[DEBUG ONLY] Assert DEVSLP in S3
by Rizwan Qureshi (Code Review) 10 Jun '23

10 Jun '23

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32078 Change subject: mb/google/hatch:[DEBUG ONLY] Assert DEVSLP in S3 ...................................................................... mb/google/hatch:[DEBUG ONLY] Assert DEVSLP in S3 It was obsevred that the DEVSLP is keeping low in S3, and SDD is drawing some power, assert DEVSLP in S3 to indicate SSD to go into low power mode. Change-Id: I001781fd0e1e5763f6865966658fc9fccc3edff8 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/32078/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 5987abc..15038b5 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -410,6 +410,7 @@ /* Default GPIO settings before entering sleep. */ static const struct pad_config default_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_E5, 1, DEEP), }; /* -- To view, visit https://review.coreboot.org/c/coreboot/+/32078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I001781fd0e1e5763f6865966658fc9fccc3edff8 Gerrit-Change-Number: 32078 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

2 1

Change in ...coreboot[master]: Updated and converted to markdown doc from wiki on porting motherboards.
by Calvin (Code Review) 10 Jun '23

10 Jun '23

Calvin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31849 Change subject: Updated and converted to markdown doc from wiki on porting motherboards. ...................................................................... Updated and converted to markdown doc from wiki on porting motherboards. Some of the documentation from the wiki (https://www.coreboot.org/Motherboard_Porting_Guide) has been ported to markdown and updated as I was able to figure things out. Still a work in progress as there is more data from that page that I will need to convert as I work through it. If I get anywhere in my project of porting coreboot to an older Chromebook, I will document more of this process as I go. Signed-off-by: calvinrempel <calvin.rempel(a)gmail.com> Change-Id: Ie3b8a99c10808c7e7ebc826b4d2f992774cc9a75 --- M Documentation/index.md A Documentation/porting/index.md A Documentation/porting/motherboard_probe.md 3 files changed, 135 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/31849/1 diff --git a/Documentation/index.md b/Documentation/index.md index dd8714c..32635f9 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -164,6 +164,7 @@ * [Rookie Guide](lessons/index.md) * [Coding Style](coding_style.md) * [Project Ideas](contributing/project_ideas.md) +* [Porting](porting/index.md) * [Code of Conduct](community/code_of_conduct.md) * [Community forums](community/forums.md) * [coreboot at conferences](community/conferences.md) diff --git a/Documentation/porting/index.md b/Documentation/porting/index.md new file mode 100644 index 0000000..ed282e8 --- /dev/null +++ b/Documentation/porting/index.md @@ -0,0 +1,3 @@ +# Porting New Boards + +* [Motherboard Probing](motherboard_probe.md) diff --git a/Documentation/porting/motherboard_probe.md b/Documentation/porting/motherboard_probe.md new file mode 100644 index 0000000..7562f7c --- /dev/null +++ b/Documentation/porting/motherboard_probe.md @@ -0,0 +1,131 @@ +Motherboard Porting Guide +========================= + +Please note that this guide is very much a work in progress. + +Finding out What You Have +------------------------- + +### Tools +To begin the process of porting a motherboard to coreboot, you first +need to determine what all is on it: the chipset (ie, North and South +Bridge), Flash Rom, etc. To do this, you will need a suite of +tools provided by the coreboot project, as well as some that can be +found more readily in various repositories. + +For the sake of this page, it will be assumed you are using Debian or +Ubuntu. + +#### Build Environment +If you have not already done so, get your basic build environment +installed: + + $ sudo apt install build-essential git cvs subversion + +#### Probing Utilities - From Repos +Next, a number of utilities will need to be installed which will be used +later for probing the system as well as some dev libraries which will be +used in building some of the tools in the next step.These should be +available in your distro's repo: + + $ sudo apt install pciutils pciutils-dev flashrom acpitool \ + usbutils acpidump + +#### Probing Utilities - From Source +Once the base build system in place and what utilities along with what +libraries you can glean from your distro's repositories, it is time to +build some tools from source. If you have not already done so, checkout +the git repo as described in "[Rookie Guide: Lesson 1]". + +Once you have synced the coreboot repo, cd into the utilities folder: + + $cd coreboot/util + +##### superiotool + + $ cd ./superiotool + $ make + $ sudo make install + $ cd .. + +##### inteltool + + $ cd ./inteltool + $ make + $ sudo make install + $ cd .. + +##### ectool + + $ cd ./ectool + $ make + $ make install + $ cd .. + +##### dmidecode + + $ cvs -z3 -d:pserver:anonymous@cvs.savannah.nongnu.org:/sources/dmidecode \ + co dmidecode + $ cd dmidecode + $ make + $ sudo make install + $ cd .. + +##### msrtool + + $ cd ./msrtool + $ ./configure + $ make + $ sudo make install + $ cd .. + +##### nvramtool + + $ cd ./nvramtool + $ make + $ sudo make install + +##### acpica-unix + + $ wget http://deb.debian.org/debian/pool/main/a/acpica-unix/acpica-unix_20181213.o… + $ tar -xaf acpica-unix_20181213.orig.tar.gz + $ cd ./acpica-unix-2018-12-13/ + $ make + $ sudo make install + +### Probe the Board +Now we will begin to probe the board to see what we can find out about +it. First, become root: + + $ sudo su + +Then load the msr module into the kernel: + + $ sudo modprobe msr + +Finally, we probe the board: + + $ lspci -nnvvvxxxx > lspci.log 2> lspci.err.log + $ lsusb -vvv > lsusb.log 2> lsusb.err.log + $ superiotool -deV > superiotool.log 2> superiotool.err.log + $ inteltool -a > inteltool.log 2> inteltool.err.log + $ ectool -i > ectool.log 2> ectool.err.log + $ msrtool > msrtool.log 2> msrtool.err.log + $ dmidecode > dmidecode.log 2> dmidecode.err.log + $ biosdecode > biosdecode.log 2> biosdecode.err.log + $ nvramtool -x > nvramtool.log 2> nvramtool.err.log + $ dmesg > dmesg.log 2> dmesg.err.log + $ acpidump > acpidump.log 2> acpidump.err.log + $ for x in /sys/class/sound/card0/hw*; do cat "$x/init_pin_configs" \ + > pin_"$(basename "$x")"; done + $ for x in /proc/asound/card0/codec#*; do cat "$x" > \ + "$(basename "$x")"; done + $ cat /proc/cpuinfo > cpuinfo.log 2> cpuinfo.err.log + $ cat /proc/ioports > ioports.log 2> ioports.err.log + $ cat /sys/class/input/input*/id/bustype > input_bustypes.log + $flashrom -V -p internal:laptop=force_I_want_a_brick > \ + flashrom_info.log 2> flashrom_info.err.log + $ flashrom -V -p internal:laptop=force_I_want_a_brick -r rom.bin > \ + flashrom_read.log 2> flashrom_read.err.log + +[Rookie Guide: Lesson 1]: https://doc.coreboot.org/lessons/lesson1.html -- To view, visit https://review.coreboot.org/c/coreboot/+/31849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3b8a99c10808c7e7ebc826b4d2f992774cc9a75 Gerrit-Change-Number: 31849 Gerrit-PatchSet: 1 Gerrit-Owner: Calvin <calvin.rempel(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Add default boards for qemu, that has VPD partitions.
by John Looney (Code Review) 10 Jun '23

10 Jun '23

John Looney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32144 Change subject: Add default boards for qemu, that has VPD partitions. ...................................................................... Add default boards for qemu, that has VPD partitions. Tested with https://review.coreboot.org/c/coreboot/+/31984 and the 'vpd' command to add VPD variables to those partitions, then checked that they were exported to userspace. Change-Id: I2aca55543cb3bdbdb77c8b421cbbafad2405d3cc --- A src/mainboard/emulation/qemu-i440fx/board.fmd A src/mainboard/emulation/qemu-q35/board.fmd 2 files changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/32144/1 diff --git a/src/mainboard/emulation/qemu-i440fx/board.fmd b/src/mainboard/emulation/qemu-i440fx/board.fmd new file mode 100644 index 0000000..a97e218 --- /dev/null +++ b/src/mainboard/emulation/qemu-i440fx/board.fmd @@ -0,0 +1,16 @@ +# layout for firmware residing at top of 4GB address space +# +-------------+ <-- 4GB - ROM_SIZE / start of flash +# | unspecified | +# +-------------+ <-- 4GB - BIOS_SIZE +# | FMAP | +# +-------------+ <-- 4GB - BIOS_SIZE + FMAP_SIZE +# | CBFS | +# +-------------+ <-- 4GB / end of flash +FLASH@4278190080 0x1000000 { + BIOS@0 0x1000000 { + FMAP@0 0x200 + RO_VPD@0x200 0x10000 + RW_VPD@0x10200 0x1000 + COREBOOT(CBFS)@0x11200 + } +} diff --git a/src/mainboard/emulation/qemu-q35/board.fmd b/src/mainboard/emulation/qemu-q35/board.fmd new file mode 100644 index 0000000..a97e218 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/board.fmd @@ -0,0 +1,16 @@ +# layout for firmware residing at top of 4GB address space +# +-------------+ <-- 4GB - ROM_SIZE / start of flash +# | unspecified | +# +-------------+ <-- 4GB - BIOS_SIZE +# | FMAP | +# +-------------+ <-- 4GB - BIOS_SIZE + FMAP_SIZE +# | CBFS | +# +-------------+ <-- 4GB / end of flash +FLASH@4278190080 0x1000000 { + BIOS@0 0x1000000 { + FMAP@0 0x200 + RO_VPD@0x200 0x10000 + RW_VPD@0x10200 0x1000 + COREBOOT(CBFS)@0x11200 + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2aca55543cb3bdbdb77c8b421cbbafad2405d3cc Gerrit-Change-Number: 32144 Gerrit-PatchSet: 1 Gerrit-Owner: John Looney <john.looney(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/mtkheader: Add a tool to extract bootload header from binary files.
by You-Cheng Syu (Code Review) 10 Jun '23

10 Jun '23

You-Cheng Syu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32333 Change subject: util/mtkheader: Add a tool to extract bootload header from binary files. ...................................................................... util/mtkheader: Add a tool to extract bootload header from binary files. Add a tool, extract-bl-img.py, which can extract MTK bootload header from binary files. This could be useful for boards (e.g., Kukui) which put the bootblock in other places (e.g., Chrome EC). Change-Id: Ib744c80bdc2adfe27d4287365e161096e3fe08c7 Signed-off-by: You-Cheng Syu <youcheng(a)google.com> --- A util/mtkheader/extract-bl-img.py 1 file changed, 55 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/32333/1 diff --git a/util/mtkheader/extract-bl-img.py b/util/mtkheader/extract-bl-img.py new file mode 100755 index 0000000..21bf9eb --- /dev/null +++ b/util/mtkheader/extract-bl-img.py @@ -0,0 +1,55 @@ +#!/usr/bin/env python +# This file is part of the coreboot project. +# +# Copyright 2019 Google LLC +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +import argparse +import struct +import sys + + +_DESCRIPTION = 'Extract MTK bootload header from a binary file.' + + +def parse_args(): + parser = argparse.ArgumentParser(description=_DESCRIPTION) + parser.add_argument('input_path', metavar='INPUT_FILE') + parser.add_argument('output_path', metavar='OUTPUT_FILE') + return parser.parse_args() + + +def main(): + args = parse_args() + + with open(args.input_path, 'rb') as f: + data = f.read() + + header = struct.pack('<8sII', 'BRLYT', 1, 2048) + + start = -1 + while True: + start = data.find(header, start + 1) + if start < 0: + raise RuntimeError('Cannot find MTK bootload header') + offset = start + len(header) + buf = struct.unpack('<II', data[offset:offset+8]) + if buf[1] == 0x42424242: + break + size = buf[0] + offset = start - 512 + + with open(args.output_path, 'wb') as f: + f.write(data[offset:offset+size]) + + +if __name__ == '__main__': + main() -- To view, visit https://review.coreboot.org/c/coreboot/+/32333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib744c80bdc2adfe27d4287365e161096e3fe08c7 Gerrit-Change-Number: 32333 Gerrit-PatchSet: 1 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-MessageType: newchange

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