June 2019 - coreboot-gerrit - mail.coreboot.org

Change in ...coreboot[master]: mb/intel/dg41wv: Inherit the subsystemid
by Arthur Heymans (Code Review) June 10, 2023

June 10, 2023

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30470 Change subject: mb/intel/dg41wv: Inherit the subsystemid ...................................................................... mb/intel/dg41wv: Inherit the subsystemid Don't reprogram the same subsystemid for each PCI device. Change-Id: Ieaeef728e200bfa826c4ae25de3e8532c493c877 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/intel/dg41wv/devicetree.cb 1 file changed, 23 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/30470/1 diff --git a/src/mainboard/intel/dg41wv/devicetree.cb b/src/mainboard/intel/dg41wv/devicetree.cb index d96ad95..da91ea2 100644 --- a/src/mainboard/intel/dg41wv/devicetree.cb +++ b/src/mainboard/intel/dg41wv/devicetree.cb @@ -24,14 +24,10 @@ end end device domain 0 on # PCI domain - subsystemid 0x1458 0x5000 inherit - device pci 0.0 on # Host Bridge - subsystemid 0x8086 0x5756 - end + subsystemid 0x8086 0x5756 inherit + device pci 0.0 on end # Host Bridge device pci 1.0 on end # PEG - device pci 2.0 on # Integrated graphics controller - subsystemid 0x8086 0x5756 - end + device pci 2.0 on end # Integrated graphics controller chip southbridge/intel/i82801gx # Southbridge register "pirqa_routing" = "0x0b" register "pirqb_routing" = "0x0b" @@ -66,39 +62,24 @@ register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant register "gpe0_en" = "0x440" - device pci 1b.0 on # Audio - subsystemid 0x8086 0x5756 + device pci 1b.0 on end # Audio + device pci 1c.0 on end # PCIe 1 + device pci 1c.1 on # PCIe 2: NIC + device pci 00.0 on end end - device pci 1c.0 on end # PCIe 1 - device pci 1c.1 on # PCIe 2: NIC - device pci 00.0 on - subsystemid 0x8086 0x5756 - end - end - device pci 1c.2 off end # PCIe 3 - device pci 1c.3 off end # PCIe 4 - device pci 1c.4 off end # PCIe 5 - device pci 1c.5 off end # PCIe 6 - device pci 1d.0 on # USB - subsystemid 0x8086 0x5756 - end - device pci 1d.1 on # USB - subsystemid 0x8086 0x5756 - end - device pci 1d.2 on # USB - subsystemid 0x8086 0x5756 - end - device pci 1d.3 on # USB - subsystemid 0x8086 0x5756 - end - device pci 1d.7 on # USB - subsystemid 0x8086 0x5756 - end - device pci 1e.0 on end # PCI bridge - device pci 1e.2 off end # AC'97 Audio Controller - device pci 1e.3 off end # AC'97 Modem Controller - device pci 1f.0 on # ISA bridge - subsystemid 0x8086 0x5756 + device pci 1c.2 off end # PCIe 3 + device pci 1c.3 off end # PCIe 4 + device pci 1c.4 off end # PCIe 5 + device pci 1c.5 off end # PCIe 6 + device pci 1d.0 on end # USB + device pci 1d.1 on end # USB + device pci 1d.2 on end # USB + device pci 1d.3 on end # USB + device pci 1d.7 on end # USB + device pci 1e.0 on end # PCI bridge + device pci 1e.2 off end # AC'97 Audio Controller + device pci 1e.3 off end # AC'97 Modem Controller + device pci 1f.0 on # ISA bridge chip superio/winbond/w83627dhg device pnp 2e.0 on # Floppy # global @@ -155,12 +136,9 @@ end end device pci 1f.1 off end # PATA/IDE - device pci 1f.2 on # SATA - subsystemid 0x8086 0x5756 - end - device pci 1f.3 on # SMbus - subsystemid 0x8086 0x5756 - chip drivers/i2c/ck505 + device pci 1f.2 on end # SATA + device pci 1f.3 on # SMbus + chip drivers/i2c/ck505 register "mask" = "{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -173,7 +151,6 @@ 0x06, 0x00, 0xea }" device i2c 69 on end end - end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/30470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaeef728e200bfa826c4ae25de3e8532c493c877 Gerrit-Change-Number: 30470 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [UNTESTED]drivers/lenovo/wacom.c: Move DOCK SIO config to SIO code
by Arthur Heymans (Code Review) June 10, 2023

June 10, 2023

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33788 Change subject: [UNTESTED]drivers/lenovo/wacom.c: Move DOCK SIO config to SIO code ...................................................................... [UNTESTED]drivers/lenovo/wacom.c: Move DOCK SIO config to SIO code This is not wacom specific code. Change-Id: I2fbcb25e78f490a65ecf4e0c8e6c84cd759a6f55 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/lenovo/lenovo.h M src/drivers/lenovo/wacom.c M src/mainboard/lenovo/x200/mainboard.c M src/mainboard/lenovo/x201/mainboard.c M src/mainboard/lenovo/x60/mainboard.c M src/superio/nsc/pc87392/superio.c 6 files changed, 66 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/33788/1 diff --git a/src/drivers/lenovo/lenovo.h b/src/drivers/lenovo/lenovo.h index 4c44119..c7e1b8f 100644 --- a/src/drivers/lenovo/lenovo.h +++ b/src/drivers/lenovo/lenovo.h @@ -1,3 +1,2 @@ int drivers_lenovo_is_wacom_present(void); -void drivers_lenovo_serial_ports_ssdt_generate(const char *scope, - int have_dock_serial); +void drivers_lenovo_serial_ports_ssdt_generate(const char *scope); diff --git a/src/drivers/lenovo/wacom.c b/src/drivers/lenovo/wacom.c index 9dcbf15..dfbd840 100644 --- a/src/drivers/lenovo/wacom.c +++ b/src/drivers/lenovo/wacom.c @@ -37,8 +37,7 @@ "2263", "2266", }; -int -drivers_lenovo_is_wacom_present(void) +int drivers_lenovo_is_wacom_present(void) { const char *pn; int i; @@ -85,9 +84,7 @@ return (result = 0); } -void -drivers_lenovo_serial_ports_ssdt_generate(const char *scope, - int have_dock_serial) +void drivers_lenovo_serial_ports_ssdt_generate(const char *scope) { acpigen_write_scope(scope); @@ -110,27 +107,5 @@ acpigen_pop_len(); } - if (have_dock_serial) { - acpigen_write_device("COMA"); - - acpigen_write_name("_HID"); - acpigen_emit_eisaid("PNP0501"); - acpigen_write_name("_UID"); - /* Byte */ - acpigen_write_byte(0x2); - - acpigen_write_name("_CRS"); - - acpigen_write_resourcetemplate_header(); - acpigen_write_io16(0x3f8, 0x3f8, 1, 8, 1); - acpigen_write_irq(1 << 4); - - acpigen_write_resourcetemplate_footer(); - - acpigen_write_STA(0xf); - - acpigen_pop_len(); - } - acpigen_pop_len(); } diff --git a/src/mainboard/lenovo/x200/mainboard.c b/src/mainboard/lenovo/x200/mainboard.c index 1510ab7..bcb94b1 100644 --- a/src/mainboard/lenovo/x200/mainboard.c +++ b/src/mainboard/lenovo/x200/mainboard.c @@ -19,7 +19,7 @@ static void fill_ssdt(struct device *device) { - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); + drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB"); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 70b393cc..8cd87aa 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -58,7 +58,7 @@ static void fill_ssdt(struct device *device) { - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); + drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB"); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 964e9c0..9febea5 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -115,7 +115,7 @@ static void fill_ssdt(struct device *device) { - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 1); + drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB"); } static void mainboard_enable(struct device *dev) diff --git a/src/superio/nsc/pc87392/superio.c b/src/superio/nsc/pc87392/superio.c index a15d0a2..bf4ee54 100644 --- a/src/superio/nsc/pc87392/superio.c +++ b/src/superio/nsc/pc87392/superio.c @@ -14,6 +14,8 @@ * GNU General Public License for more details. */ +#include <arch/acpigen.h> +#include <console/console.h> #include <device/device.h> #include <device/pnp.h> #include <stdlib.h> @@ -25,12 +27,70 @@ return; } +#if CONFIG(HAVE_ACPI_TABLES) +static void pc87392_ssdt(struct device *dev) +{ + struct resource *io_res; + struct resource *irq_res; + + const char *scope = acpi_device_path(dev); + if (!scope) { + printk(BIOS_ERR, "%s: Missing ACPI scope\n", dev_path(dev)); + return; + } + + switch (dev->path.pnp.device) { + case PC87392_SP2: + case PC87392_SP1: + io_res = find_resource(dev, PNP_IDX_IO0); + if (!io_res || !io_res->base) { + printk(BIOS_ERR, "PC87392: LDN%u IOBASE not set.\n", + dev->path.pnp.device); + break; + } + irq_res = find_resource(dev, PNP_IDX_IRQ0); + if (!irq_res || !irq_res->base) { + printk(BIOS_ERR, "PC87392: LDN%u IRQ not set.\n", + dev->path.pnp.device); + break; + } + acpigen_write_scope(scope); + const char *dev_name = dev->path.pnp.device == PC87392_SP1 + ? "COMA" : "COMB"; + acpigen_write_device(dev_name); + + acpigen_write_name("_HID"); + acpigen_emit_eisaid("PNP0501"); + acpigen_write_name("_UID"); + /* Byte */ + acpigen_write_byte(0x2); + + acpigen_write_name("_CRS"); + + acpigen_write_resourcetemplate_header(); + acpigen_write_io16(io_res->base, io_res->base, io_res->align, + io_res->size, 1); + acpigen_write_irq(irq_res->base); + acpigen_write_resourcetemplate_footer(); + + /* TODO, This likely depends on dock status */ + acpigen_write_STA(0xf); + + acpigen_pop_len(); /* pop scope */ + } +} +#endif + + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_enable, .init = init, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt_generator = pc87392_ssdt, +#endif }; static struct pnp_info pnp_dev_info[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/33788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2fbcb25e78f490a65ecf4e0c8e6c84cd759a6f55 Gerrit-Change-Number: 33788 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/drivers/aspeed/common/ast_tables.h: Fix checkpatch Errors
by Abdullah Zafar (Code Review) June 10, 2023

June 10, 2023

Abdullah Zafar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31975 Change subject: src/drivers/aspeed/common/ast_tables.h: Fix checkpatch Errors ...................................................................... src/drivers/aspeed/common/ast_tables.h: Fix checkpatch Errors Fix trailing whitespace and space required after that ','. Signed-off-by: Abdullah Zafar <azafar.bee16seecs(a)seecs.edu.pk> Change-Id: I28bf4280bf49be1c0f582a73387e845173582f53 --- M src/drivers/aspeed/common/ast_tables.h 1 file changed, 53 insertions(+), 53 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/31975/1 diff --git a/src/drivers/aspeed/common/ast_tables.h b/src/drivers/aspeed/common/ast_tables.h index 6c20f36..f59e5a7 100644 --- a/src/drivers/aspeed/common/ast_tables.h +++ b/src/drivers/aspeed/common/ast_tables.h @@ -112,71 +112,71 @@ /* MD_2_3_400 */ { 0x67, - {0x00,0x03,0x00,0x02}, - {0x5f,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f, - 0x00,0x4f,0x0d,0x0e,0x00,0x00,0x00,0x00, - 0x9c,0x8e,0x8f,0x28,0x1f,0x96,0xb9,0xa3, + {0x00, 0x03, 0x00, 0x02}, + {0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, + 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, + 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07, - 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f, - 0x0c,0x00,0x0f,0x08}, - {0x00,0x00,0x00,0x00,0x00,0x10,0x0e,0x00, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, + 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, + 0x0c, 0x00, 0x0f, 0x08}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x00, 0xff} }, /* Mode12/ExtEGATable */ { 0xe3, - {0x01,0x0f,0x00,0x06}, - {0x5f,0x4f,0x50,0x82,0x55,0x81,0x0b,0x3e, - 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, - 0xe9,0x8b,0xdf,0x28,0x00,0xe7,0x04,0xe3, + {0x01, 0x0f, 0x00, 0x06}, + {0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0x0b, 0x3e, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xe9, 0x8b, 0xdf, 0x28, 0x00, 0xe7, 0x04, 0xe3, 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07, - 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f, - 0x01,0x00,0x0f,0x00}, - {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, + 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, + 0x01, 0x00, 0x0f, 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff} }, /* ExtVGATable */ { 0x2f, - {0x01,0x0f,0x00,0x0e}, - {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, - 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, - 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, + {0x01, 0x0f, 0x00, 0x0e}, + {0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xea, 0x8c, 0xdf, 0x28, 0x40, 0xe7, 0x04, 0xa3, 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, - 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, - 0x01,0x00,0x00,0x00}, - {0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0f, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x01, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0f, 0xff} }, /* ExtHiCTable */ { 0x2f, - {0x01,0x0f,0x00,0x0e}, - {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, - 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, - 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, + {0x01, 0x0f, 0x00, 0x0e}, + {0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xea, 0x8c, 0xdf, 0x28, 0x40, 0xe7, 0x04, 0xa3, 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, - 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, - 0x01,0x00,0x00,0x00}, - {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x01, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff} }, /* ExtTrueCTable */ { 0x2f, - {0x01,0x0f,0x00,0x0e}, - {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, - 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, - 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, + {0x01, 0x0f, 0x00, 0x0e}, + {0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xea, 0x8c, 0xdf, 0x28, 0x40, 0xe7, 0x04, 0xa3, 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, - 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, - 0x01,0x00,0x00,0x00}, - {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x01, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff} }, }; @@ -187,11 +187,11 @@ { 832, 640, 16, 40, 520, 480, 1, 3, VCLK31_5, /* 72Hz */ (SyncNN | HBorder | VBorder | Charx8Dot), 72, 2, 0x2E }, { 840, 640, 16, 64, 500, 480, 1, 3, VCLK31_5, /* 75Hz */ - (SyncNN | Charx8Dot) , 75, 3, 0x2E }, + (SyncNN | Charx8Dot), 75, 3, 0x2E }, { 832, 640, 56, 56, 509, 480, 1, 3, VCLK36, /* 85Hz */ - (SyncNN | Charx8Dot) , 85, 4, 0x2E }, + (SyncNN | Charx8Dot), 85, 4, 0x2E }, { 832, 640, 56, 56, 509, 480, 1, 3, VCLK36, /* end */ - (SyncNN | Charx8Dot) , 0xFF, 4, 0x2E }, + (SyncNN | Charx8Dot), 0xFF, 4, 0x2E }, }; static struct ast_vbios_enhtable res_800x600[] = { @@ -243,18 +243,18 @@ /* 16:9 */ static struct ast_vbios_enhtable res_1360x768[] = { - {1792, 1360, 64,112, 795, 768, 3, 6, VCLK85_5, /* 60Hz */ + {1792, 1360, 64, 112, 795, 768, 3, 6, VCLK85_5, /* 60Hz */ (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x39 }, - {1792, 1360, 64,112, 795, 768, 3, 6, VCLK85_5, /* end */ + {1792, 1360, 64, 112, 795, 768, 3, 6, VCLK85_5, /* end */ (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x39 }, }; static struct ast_vbios_enhtable res_1600x900[] = { {1760, 1600, 48, 32, 926, 900, 3, 5, VCLK97_75, /* 60Hz CVT RB */ (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x3A }, - {2112, 1600, 88,168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ + {2112, 1600, 88, 168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x3A }, - {2112, 1600, 88,168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ + {2112, 1600, 88, 168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x3A }, }; @@ -270,9 +270,9 @@ static struct ast_vbios_enhtable res_1280x800[] = { {1440, 1280, 48, 32, 823, 800, 3, 6, VCLK71, /* 60Hz RB */ (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x35 }, - {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ + {1680, 1280, 72, 128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x35 }, - {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ + {1680, 1280, 72, 128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x35 }, }; @@ -280,18 +280,18 @@ static struct ast_vbios_enhtable res_1440x900[] = { {1600, 1440, 48, 32, 926, 900, 3, 6, VCLK88_75, /* 60Hz RB */ (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x36 }, - {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ + {1904, 1440, 80, 152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x36 }, - {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ + {1904, 1440, 80, 152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x36 }, }; static struct ast_vbios_enhtable res_1680x1050[] = { {1840, 1680, 48, 32, 1080, 1050, 3, 6, VCLK119, /* 60Hz RB */ (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x37 }, - {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ + {2240, 1680, 104, 176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x37 }, - {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ + {2240, 1680, 104, 176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x37 }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/31975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28bf4280bf49be1c0f582a73387e845173582f53 Gerrit-Change-Number: 31975 Gerrit-PatchSet: 1 Gerrit-Owner: Abdullah Zafar <abdullahzafar4876(a)yahoo.com> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: [UNTESTED]drivers/lenovo/wacom: Move ssdt generator to nsc/pc87382
by Arthur Heymans (Code Review) June 10, 2023

June 10, 2023

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33789 Change subject: [UNTESTED]drivers/lenovo/wacom: Move ssdt generator to nsc/pc87382 ...................................................................... [UNTESTED]drivers/lenovo/wacom: Move ssdt generator to nsc/pc87382 This adds a hook to the pc87382 code to specify the ACPI _HID in the case that a wacom device is hooked up to it. TODO: - the wacom code needs to know quite a lot about the SIO and has weird Kconfig hooks to force stuff that is bound to no work. - Add a function to detect the sio and disable it, if not found. Change-Id: Ic1bfebcdaf19798e5ca2fe6c96ac1f9f4cf73e9b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/lenovo/wacom.c M src/mainboard/lenovo/x200/mainboard.c M src/mainboard/lenovo/x201/mainboard.c M src/mainboard/lenovo/x60/mainboard.c M src/superio/nsc/pc87382/pc87382.h M src/superio/nsc/pc87382/superio.c 6 files changed, 66 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/33789/1 diff --git a/src/drivers/lenovo/wacom.c b/src/drivers/lenovo/wacom.c index dfbd840..45395d3 100644 --- a/src/drivers/lenovo/wacom.c +++ b/src/drivers/lenovo/wacom.c @@ -21,6 +21,7 @@ #include <device/device.h> #include <device/pnp.h> #include <string.h> +#include <superio/nsc/pc87382/pc87382.h> #include "lenovo.h" #include "drivers/i2c/at24rf08c/lenovo.h" @@ -84,28 +85,10 @@ return (result = 0); } -void drivers_lenovo_serial_ports_ssdt_generate(const char *scope) +const char *nsc_pc87382_sp1_acpi_hid(void) { - acpigen_write_scope(scope); - - if (drivers_lenovo_is_wacom_present()) { - acpigen_write_device("DTR"); - - acpigen_write_name("_HID"); - acpigen_emit_eisaid("WACF004"); - - acpigen_write_name("_CRS"); - - acpigen_write_resourcetemplate_header(); - acpigen_write_io16(0x200, 0x200, 1, 8, 1); - acpigen_write_irq((1 << 5)); - - acpigen_write_resourcetemplate_footer(); - - acpigen_write_STA(0xf); - - acpigen_pop_len(); - } - - acpigen_pop_len(); + if (drivers_lenovo_is_wacom_present()) + return "WACF004"; + else + return "PNP0501"; } diff --git a/src/mainboard/lenovo/x200/mainboard.c b/src/mainboard/lenovo/x200/mainboard.c index bcb94b1..2e65e56 100644 --- a/src/mainboard/lenovo/x200/mainboard.c +++ b/src/mainboard/lenovo/x200/mainboard.c @@ -17,18 +17,11 @@ #include <drivers/intel/gma/int15.h> #include <drivers/lenovo/lenovo.h> -static void fill_ssdt(struct device *device) -{ - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB"); -} - static void mainboard_enable(struct device *dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 2); - - dev->ops->acpi_fill_ssdt_generator = fill_ssdt; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 8cd87aa..87a2f0e 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -56,17 +56,11 @@ printk(BIOS_SPEW, "SPI configured\n"); } -static void fill_ssdt(struct device *device) -{ - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB"); -} - static void mainboard_enable(struct device *dev) { u16 pmbase; dev->ops->init = mainboard_init; - dev->ops->acpi_fill_ssdt_generator = fill_ssdt; pmbase = pci_read_config32(pcidev_on_root(0x1f, 0), PMBASE) & 0xff80; diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 9febea5..acf63cb 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -113,15 +113,9 @@ } } -static void fill_ssdt(struct device *device) -{ - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB"); -} - static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_fill_ssdt_generator = fill_ssdt; } struct chip_operations mainboard_ops = { diff --git a/src/superio/nsc/pc87382/pc87382.h b/src/superio/nsc/pc87382/pc87382.h index 6826f45..480a646 100644 --- a/src/superio/nsc/pc87382/pc87382.h +++ b/src/superio/nsc/pc87382/pc87382.h @@ -21,4 +21,6 @@ #define PC87382_SP1 0x03 #define PC87382_GPIO 0x07 #define PC87382_DOCK 0x19 + +const char *nsc_pc87382_sp1_acpi_hid(void); #endif diff --git a/src/superio/nsc/pc87382/superio.c b/src/superio/nsc/pc87382/superio.c index 7c04023..4d270c0 100644 --- a/src/superio/nsc/pc87382/superio.c +++ b/src/superio/nsc/pc87382/superio.c @@ -14,6 +14,8 @@ * GNU General Public License for more details. */ +#include <arch/acpigen.h> +#include <console/console.h> #include <device/device.h> #include <device/pnp.h> #include <stdlib.h> @@ -33,12 +35,68 @@ } } +__weak const char *nsc_pc87382_sp1_acpi_hid(void) +{ + return "PNP0501"; +} + +#if CONFIG(HAVE_ACPI_TABLES) +static void pc87382_ssdt(struct device *dev) +{ + struct resource *io_res; + struct resource *irq_res; + + const char *scope = acpi_device_path(dev); + if (!scope) { + printk(BIOS_ERR, "%s: Missing ACPI scope\n", dev_path(dev)); + return; + } + + acpigen_write_scope(scope); + + switch (dev->path.pnp.device) { + case PC87382_SP1: + io_res = find_resource(dev, PNP_IDX_IO0); + if (!io_res || !io_res->base) { + printk(BIOS_ERR, "PC87382: LDN%u IOBASE not set.\n", + PC87382_SP1); + break; + } + irq_res = find_resource(dev, PNP_IDX_IRQ0); + if (!irq_res || !irq_res->base) { + printk(BIOS_ERR, "PC87382: LDN%u IRQ not set.\n", + PC87382_SP1); + break; + } + + acpigen_write_device("DIR"); + + acpigen_write_name("_HID"); + acpigen_emit_eisaid(nsc_pc87382_sp1_acpi_hid()); + acpigen_write_name("_CRS"); + + acpigen_write_resourcetemplate_header( ); + acpigen_write_io16(io_res->base, io_res->base, io_res->align, + io_res->size, 1); + acpigen_write_irq(irq_res->base); + acpigen_write_resourcetemplate_footer(); + acpigen_write_STA(0xf); + + break; + } + acpigen_pop_len(); +} +#endif + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_enable, .init = init, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt_generator = pc87382_ssdt, +#endif }; static struct pnp_info pnp_dev_info[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/33789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1bfebcdaf19798e5ca2fe6c96ac1f9f4cf73e9b Gerrit-Change-Number: 33789 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 7

Change in ...coreboot[master]: mb/google/hatch: Disable the eMMC controller for hatch
by V Sowmya (Code Review) June 10, 2023

June 10, 2023

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30615 Change subject: mb/google/hatch: Disable the eMMC controller for hatch ...................................................................... mb/google/hatch: Disable the eMMC controller for hatch eMMC controller is not used in hatch hence this patch adds the Kconfig option to disable the eMMC controller ACPI entries. BUG=b:120914069 BRANCH=none TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot. Change-Id: Ie52c4fa581ad2c9b14e57919a63b3128bd928596 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/google/hatch/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/30615/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 711d2e9..15fe354 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -15,6 +15,7 @@ select SOC_INTEL_CANNONLAKE_MEMCFG_INIT select SOC_INTEL_COFFEELAKE select SYSTEM_TYPE_LAPTOP + select EXCLUDE_EMMC_INTERFACE if BOARD_GOOGLE_BASEBOARD_HATCH -- To view, visit https://review.coreboot.org/c/coreboot/+/30615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie52c4fa581ad2c9b14e57919a63b3128bd928596 Gerrit-Change-Number: 30615 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: mb/google/hatch: [TEST- ONLY] Enable RMT log capture in FSP
by Aamir Bohra (Code Review) June 10, 2023

June 10, 2023

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30664 Change subject: mb/google/hatch: [TEST- ONLY] Enable RMT log capture in FSP ...................................................................... mb/google/hatch: [TEST- ONLY] Enable RMT log capture in FSP **** DO NOT MERGE **** Change-Id: I0a0865b2baa6d3606a38b9f07b1d32f13e4e7178 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/google/hatch/romstage.c 1 file changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/30664/1 diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c index 401f41f..4a47d12 100644 --- a/src/mainboard/google/hatch/romstage.c +++ b/src/mainboard/google/hatch/romstage.c @@ -19,11 +19,14 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { + FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; + mem_cfg->RMT = 1; + memupd->FspmTestConfig.BdatEnable = 1; + mem_cfg->MrcFastBoot = 0; + const struct spd_info spd = { .spd_by_index = true, .spd_spec.spd_index = variant_memory_sku(), }; - - cannonlake_memcfg_init(&memupd->FspmConfig, - variant_memory_params(), &spd); + cannonlake_memcfg_init(mem_cfg, variant_memory_params(), &spd); } -- To view, visit https://review.coreboot.org/c/coreboot/+/30664 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a0865b2baa6d3606a38b9f07b1d32f13e4e7178 Gerrit-Change-Number: 30664 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: Documentation: Update soc/intel/apollolake
by Patrick Rudolph (Code Review) June 10, 2023

June 10, 2023

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33740 Change subject: Documentation: Update soc/intel/apollolake ...................................................................... Documentation: Update soc/intel/apollolake Explaing LBPs and how to disable dual partition mode. Change-Id: I0b609f802d96aa90d0c1479ffeccf3aaaa70a85d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/soc/intel/apollolake/flash_layout.dia M Documentation/soc/intel/apollolake/flash_layout.svg A Documentation/soc/intel/apollolake/flash_layout2.dia A Documentation/soc/intel/apollolake/flash_layout2.svg M Documentation/soc/intel/apollolake/index.md 5 files changed, 272 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/33740/1 diff --git a/Documentation/soc/intel/apollolake/flash_layout.dia b/Documentation/soc/intel/apollolake/flash_layout.dia index 4ea5440..a329620 100644 --- a/Documentation/soc/intel/apollolake/flash_layout.dia +++ b/Documentation/soc/intel/apollolake/flash_layout.dia Binary files differ diff --git a/Documentation/soc/intel/apollolake/flash_layout.svg b/Documentation/soc/intel/apollolake/flash_layout.svg index 9322875..07b3a58 100644 --- a/Documentation/soc/intel/apollolake/flash_layout.svg +++ b/Documentation/soc/intel/apollolake/flash_layout.svg @@ -1,6 +1,6 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.0//EN" "http://www.w3.org/TR/2001/PR-SVG-20010719/DTD/svg10.dtd"> -<svg width="38cm" height="18cm" viewBox="118 98 744 344" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"> +<svg width="38cm" height="19cm" viewBox="118 61 744 380" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"> <g> <rect style="fill: #ffffff" x="620" y="100" width="180" height="60"/> <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="620" y="100" width="180" height="60"/> @@ -16,18 +16,18 @@ <tspan x="460" y="134.425">BIOS</tspan> </text> <g> - <rect style="fill: #ffffff" x="240" y="100" width="60" height="60"/> - <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="240" y="100" width="60" height="60"/> + <rect style="fill: #ffffff" x="227.633" y="99.4585" width="60" height="60"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="227.633" y="99.4585" width="60" height="60"/> </g> - <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="270" y="134.425"> - <tspan x="270" y="134.425">IFD</tspan> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="257.633" y="133.884"> + <tspan x="257.633" y="133.884">IFD</tspan> </text> <g> <rect style="fill: #ffffff" x="200" y="240" width="80" height="60"/> <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="200" y="240" width="80" height="60"/> </g> - <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="240" y="274.425"> - <tspan x="240" y="274.425">IFWI</tspan> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="240" y="274.238"> + <tspan x="240" y="274.238">IFWI</tspan> </text> <g> <path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 200 240 C 200,160 460,220 460,169.736"/> @@ -35,7 +35,7 @@ <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="460,162.236 465,172.236 460,169.736 455,172.236 "/> </g> <g> - <path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 700 240 C 700,160 460,220 460,169.736"/> + <path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 700.289 239.999 C 700.289,159.999 460,220 460,169.736"/> <polygon style="fill: #000000" points="460,162.236 465,172.236 460,169.736 455,172.236 "/> <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="460,162.236 465,172.236 460,169.736 455,172.236 "/> </g> @@ -65,11 +65,11 @@ <tspan x="620" y="414.425">COREBOOT(CBFS)</tspan> </text> <g> - <rect style="fill: #ffffff" x="700" y="380" width="140" height="60"/> - <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="700" y="380" width="140" height="60"/> + <rect style="fill: #d8e5e5" x="495.265" y="102.433" width="122.658" height="54.6579"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="495.265" y="102.433" width="122.658" height="54.6579"/> </g> - <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="770" y="414.425"> - <tspan x="770" y="414.425">BIOS_UNUSABLE</tspan> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="556.594" y="134.187"> + <tspan x="556.594" y="134.187">BIOS_UNUSABLE</tspan> </text> <g> <rect style="fill: #ffffff" x="380" y="380" width="60" height="60"/> @@ -79,21 +79,21 @@ <tspan x="410" y="414.425">MRC</tspan> </text> <g> - <rect style="fill: #ffffff" x="280" y="240" width="420" height="60"/> - <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="280" y="240" width="420" height="60"/> + <rect style="fill: #ffffff" x="280" y="240" width="420.151" height="60"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="280" y="240" width="420.151" height="60"/> </g> - <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="490" y="274.425"> - <tspan x="490" y="274.425">OBB</tspan> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="490.076" y="274.425"> + <tspan x="490.076" y="274.425">OBB</tspan> </text> <g> - <path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 320 380 C 320,300 490,360 490,311"/> - <polygon style="fill: #000000" points="495,311 490,301 485,311 "/> - <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="495,311 490,301 485,311 "/> + <path style="fill: none; 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fill-opacity:0; stroke-width: 2; stroke: #000000" points="245,311 240,301 235,311 "/> </g> + <text font-size="12.7998" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="385.009" y="232.505"> + <tspan x="385.009" y="232.505">Logical Boot Partition 1</tspan> + </text> + <text font-size="12.7998" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="644.3" y="90.55"> + <tspan x="644.3" y="90.55">TXE private partition</tspan> + </text> + <text font-size="12.7998" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="768" y="77.25"> + <tspan x="768" y="77.25"></tspan> + </text> + <text font-size="12.7998" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="739" y="77.25"> + <tspan x="739" y="77.25"></tspan> + </text> + <text font-size="12.7998" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="389.3" y="90.55"> + <tspan x="389.3" y="90.55">TXE / BIOS shared partition</tspan> + </text> + <g> + <rect style="fill: #ffffff" x="288.321" y="99.2493" width="11.6609" height="60"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="288.321" y="99.2493" width="11.6609" height="60"/> + </g> + <text font-size="12.7998" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="232.975" y="73.4916"> + <tspan x="232.975" y="73.4916">ME region (unused)</tspan> + </text> + <g> + <line style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" x1="295.223" y1="77.2138" x2="295.229" y2="86.6145"/> + <polygon style="fill: #000000" points="295.234,94.1145 290.228,84.1176 295.229,86.6145 300.228,84.1113 "/> + <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="295.234,94.1145 290.228,84.1176 295.229,86.6145 300.228,84.1113 "/> + </g> + <g> + <rect style="fill: #d8e5e5" x="669.038" y="243.016" width="28.5491" height="54.6579"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="669.038" y="243.016" width="28.5491" height="54.6579"/> + </g> + <g> + <rect style="fill: #d8e5e5" x="700.222" y="380.768" width="28.5491" height="58.0215"/> + <rect style="fill: none; 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fill-opacity:0; stroke-width: 3; stroke: #000000" x="620" y="100" width="180" height="60"/> + </g> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="710" y="134.425"> + <tspan x="710" y="134.425">DEVICE_EXTENSION</tspan> + </text> + <g> + <rect style="fill: #ffffff" x="300" y="100" width="320" height="60"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="300" y="100" width="320" height="60"/> + </g> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="460" y="134.425"> + <tspan x="460" y="134.425">BIOS</tspan> + </text> + <g> + <rect style="fill: #ffffff" x="227.632" y="99.4586" width="60" height="60"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="227.632" y="99.4586" width="60" height="60"/> + </g> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="257.632" y="133.884"> + <tspan x="257.632" y="133.884">IFD</tspan> + </text> + <g> + <rect style="fill: #ffffff" x="200" y="240" width="80" height="60"/> + <rect style="fill: none; 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fill-opacity:0; stroke-width: 3; stroke: #000000" x="288.32" y="99.2492" width="11.6609" height="60"/> + </g> + <text font-size="12.8" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="232.974" y="73.4916"> + <tspan x="232.974" y="73.4916">ME region (unused)</tspan> + </text> + <g> + <line style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" x1="295.224" y1="77.2138" x2="295.23" y2="86.6145"/> + <polygon style="fill: #000000" points="295.235,94.1145 290.228,84.1177 295.23,86.6145 300.228,84.1114 "/> + <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="295.235,94.1145 290.228,84.1177 295.23,86.6145 300.228,84.1114 "/> + </g> + <g> + <rect style="fill: #ffffff" x="511.814" y="240" width="188.474" height="60"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="511.814" y="240" width="188.474" height="60"/> + </g> + <g> + <rect style="fill: #ffffff" x="440.696" y="240.49" width="71.1194" height="60"/> + <rect style="fill: none; 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fill-opacity:0; stroke-width: 3; stroke: #000000" x="668.7" y="241.9" width="28.5491" height="54.6579"/> + </g> +</svg> diff --git a/Documentation/soc/intel/apollolake/index.md b/Documentation/soc/intel/apollolake/index.md index d4a5ee5..3ff0027 100644 --- a/Documentation/soc/intel/apollolake/index.md +++ b/Documentation/soc/intel/apollolake/index.md @@ -1,9 +1,7 @@ # Apollolake -## SPI flash layout -![][apl_flash_layout] - -With Apollolake Intel invented another flash layout for x86 firmware called IFWI (Intel FirmWare Image). +With Apollolake Intel invented another flash layout for x86 firmware called +IFWI (Intel FirmWare Image). Usually on x86 platforms the bootblock is stored at the end of the bios region and the Intel ME / TXE has its own IFD region. On Apollolake both have been @@ -12,6 +10,47 @@ The IFWI region can be manipulated by `ifwitool`. -[apl_flash_layout]: flash_layout.svg +## SPI flash layout +IFD regions: +* The "ME" region isn't used on production boards +* The "BIOS" region contains one or two logical boot partitions (LBP) + * The IFD controls if one or two LBP are active + * Each LBP has it's own IFWI and OBB + * The last 256 KiB of the "BIOS" region are BIOS_UNUSABLE +* The "device extension" region is used by TXE as secure filesystem + +### SPI layout with single LBP + +When configured for single LBP mode, the LBP uses the whole "BIOS" region's +flash size. + +![][apl_flash_layout] + +### SPI layout with dual LBP + +When configured for dual LBP mode, each LBP uses exactly half of the "BIOS" +region's flash size. + +![][apl_flash_layout2] + +### IFWI + +The IFWI contains the bootblock, while the OBB contains the CBFS and other +regions as specified in the FMAP. +The OBB spans the whole size from IFWI till the end of the LBP. + +**Note:** ifwitool doesn't care about LBP2! + +### Logical boot partitions + +Each LBP has their own IFWI and OBB. It allows failsafe firmware updates. + +**Note:** If configured in dual partition mode, the TXE will enter recovery +mode if LBP2 is missing. + +To disable dual partitioning mode, set bit3 in IFD at offset `0x1ff` to 1. + +[apl_flash_layout]: flash_layout.svg +[apl_flash_layout2]: flash_layout2.svg -- To view, visit https://review.coreboot.org/c/coreboot/+/33740 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b609f802d96aa90d0c1479ffeccf3aaaa70a85d Gerrit-Change-Number: 33740 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

8 36

Change in ...coreboot[master]: drivers/spi: Instrument erase operation
by Paul Menzel (Code Review) June 10, 2023

June 10, 2023

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31793 Change subject: drivers/spi: Instrument erase operation ...................................................................... drivers/spi: Instrument erase operation Verify console output contains the new string. BS: BS_DEV_INIT times (us): entry 0 run 72771 exit 0 Finalize devices... Devices finalized APIC 00: ** Enter AmdInitLate [00020004] SB800: sb_Late_Post AmdInitLate() returned AGESA_SUCCESS APIC 00: Heap in SystemMem (4) at 0x10000014 APIC 00: ** Exit AmdInitLate [00020004] APIC 00: ** Enter AmdS3Save [0002000b] Manufacturer: ef SF: Detected W25Q32_V with sector size 0x1000, total 0x400000 SF: Successfully erased 4096 bytes @ 0xffff1000 in 97754 usecs Manufacturer: ef SF: Detected W25Q32_V with sector size 0x1000, total 0x400000 SF: Successfully erased 4096 bytes @ 0xffff0000 in 121777 usecs AmdS3Save() returned AGESA_SUCCESS APIC 00: Heap in SystemMem (4) at 0x10000014 APIC 00: ** Exit AmdS3Save [0002000b] BS: BS_POST_DEVICE times (us): entry 0 run 3 exit 228371 Change-Id: I4eb8a850d7263bc3c800d97655f0b37623b78562 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M src/drivers/spi/spi_flash.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/31793/1 diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index d1f5227..7f64968 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -198,6 +198,9 @@ u32 start, end, erase_size; int ret = -1; u8 cmd[4]; + struct stopwatch sw; + + stopwatch_init(&sw); erase_size = flash->sector_size; if (offset % erase_size || len % erase_size) { @@ -234,7 +237,8 @@ goto out; } - printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n", len, start); + printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x in %ld usecs\n", + len, start, stopwatch_duration_usecs(&sw)); out: return ret; -- To view, visit https://review.coreboot.org/c/coreboot/+/31793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4eb8a850d7263bc3c800d97655f0b37623b78562 Gerrit-Change-Number: 31793 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/smctool: A tool for reading Apple SMC keys
by Evgeny Zinoviev (Code Review) June 10, 2023

June 10, 2023

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33052 Change subject: util/smctool: A tool for reading Apple SMC keys ...................................................................... util/smctool: A tool for reading Apple SMC keys SMC is an embedded controller on Apple computers. With this tool you can read SMC keys. It supports various data types and can output result in various formats. Example how to get battery capacity level: smctool -k B0FC -t ui16 # returns Full Capacity of Battery 0 smctool -k B0RM -t ui16 # returns Remaining Capacity of Batery 0 So B0RM / B0FC * 100 = battery capacity in percents. Another example, reading current fan speed, which is returned as unsigned fixed point number: sudo ./smctool -k F0Ac -t fpe2 Change-Id: I6161203e52b7f7eaa1205de06e8241d7d40a7481 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- A util/smctool/Makefile A util/smctool/description.md A util/smctool/smc.c A util/smctool/smc.h A util/smctool/smctool.c 5 files changed, 538 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/33052/1 diff --git a/util/smctool/Makefile b/util/smctool/Makefile new file mode 100644 index 0000000..ce7cca2 --- /dev/null +++ b/util/smctool/Makefile @@ -0,0 +1,38 @@ +## +## Makefile for smctool +## +## Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +CC = gcc +CFLAGS = -O2 -Wall -W +PROGRAM = smctool +INSTALL = /usr/bin/env install +PREFIX = /usr/local + +all: $(PROGRAM) + +$(PROGRAM): smc.o smctool.o + $(CC) $(CFLAGS) -o $@ $^ $(LDFLAGS) + +install: $(PROGRAM) + $(INSTALL) $(PROGRAM) $(PREFIX)/sbin + +clean: + rm -f *.o $(PROGRAM) + +distclean: clean + +%.o: %.c + $(CC) $(CFLAGS) -c $^ -I. -o $@ + +.PHONY: all install clean distclean diff --git a/util/smctool/description.md b/util/smctool/description.md new file mode 100644 index 0000000..37a2d2a --- /dev/null +++ b/util/smctool/description.md @@ -0,0 +1 @@ +Reads keys from Apple SMC. Supports various data types. `C` diff --git a/util/smctool/smc.c b/util/smctool/smc.c new file mode 100644 index 0000000..a875b2c --- /dev/null +++ b/util/smctool/smc.c @@ -0,0 +1,156 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * SMC interacting code is based on applesmc linux driver by: + * Copyright (C) 2007 Nicolas Boichat <nicolas(a)boichat.ch> + * Copyright (C) 2010 Henrik Rydberg <rydberg(a)euromail.se> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <sys/io.h> +#include <errno.h> +#include <stdio.h> +#include "smc.h" + +/* + * wait_read - Wait for a byte to appear on SMC port. Callers must + * hold applesmc_lock. + */ +int wait_read(void) +{ + uint8_t status; + int us; + for (us = APPLESMC_MIN_WAIT; us < APPLESMC_MAX_WAIT; us <<= 1) { + usleep(us); + status = inb(APPLESMC_CMD_PORT); + + /* read: wait for smc to settle */ + if (status & 0x01) + return 0; + } + + fprintf(stderr, "%s() fail: 0x%02x\n", __func__, status); + return -EIO; +} + +/* + * send_byte - Write to SMC port, retrying when necessary. Callers + * must hold applesmc_lock. + */ +int send_byte(uint8_t cmd, uint16_t port) +{ + uint8_t status; + int us; + + outb(cmd, port); + for (us = APPLESMC_MIN_WAIT; us < APPLESMC_MAX_WAIT; us <<= 1) { + usleep(us); + status = inb(APPLESMC_CMD_PORT); + /* write: wait for smc to settle */ + if (status & 0x02) + continue; + /* ready: cmd accepted, return */ + if (status & 0x04) + return 0; + /* timeout: give up */ + if (us << 1 == APPLESMC_MAX_WAIT) + break; + /* busy: long wait and resend */ + usleep(APPLESMC_RETRY_WAIT); + outb(cmd, port); + } + + fprintf(stderr, "%s(0x%02x, 0x%04x) fail: 0x%02x\n", + __func__, cmd, port, status); + return -EIO; +} + +int send_command(uint8_t cmd) +{ + return send_byte(cmd, APPLESMC_CMD_PORT); +} + +int send_argument(const char *key) +{ + int i; + + for (i = 0; i < 4; i++) + if (send_byte(key[i], APPLESMC_DATA_PORT)) + return -EIO; + return 0; +} + +int read_smc(uint8_t cmd, const char *key, uint8_t *buffer, uint8_t len) +{ + uint8_t status, data = 0; + int i; + + if (send_command(cmd) || send_argument(key)) { + fprintf(stderr, "%.4s: read arg fail\n", key); + return -EIO; + } + + /* This has no effect on newer (2012) SMCs */ + if (send_byte(len, APPLESMC_DATA_PORT)) { + fprintf(stderr, "%.4s: read len fail\n", key); + return -EIO; + } + + for (i = 0; i < len; i++) { + if (wait_read()) { + fprintf(stderr, "%.4s: read data[%d] fail\n", key, i); + return -EIO; + } + buffer[i] = inb(APPLESMC_DATA_PORT); + } + + /* Read the data port until bit0 is cleared */ + for (i = 0; i < 16; i++) { + usleep(APPLESMC_MIN_WAIT); + status = inb(APPLESMC_CMD_PORT); + if (!(status & 0x01)) + break; + data = inb(APPLESMC_DATA_PORT); + } + + if (i) + fprintf(stderr, "flushed %d bytes, last value is: %d\n", + i, data); + + return 0; +} + +int write_smc(uint8_t cmd, const char *key, const uint8_t *buffer, uint8_t len) +{ + int i; + + if (send_command(cmd) || send_argument(key)) { + fprintf(stderr, "%s: write arg fail\n", key); + return -EIO; + } + + if (send_byte(len, APPLESMC_DATA_PORT)) { + fprintf(stderr, "%.4s: write len fail\n", key); + return -EIO; + } + + for (i = 0; i < len; i++) { + if (send_byte(buffer[i], APPLESMC_DATA_PORT)) { + fprintf(stderr, "%s: write data fail\n", key); + return -EIO; + } + } + + return 0; +} diff --git a/util/smctool/smc.h b/util/smctool/smc.h new file mode 100644 index 0000000..dffd8db --- /dev/null +++ b/util/smctool/smc.h @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SMC_H +#define SMC_H + +#include <stdbool.h> +#include <unistd.h> +#include <stdint.h> + +/* data port used by Apple SMC */ +#define APPLESMC_DATA_PORT 0x300 +/* command/status port used by Apple SMC */ +#define APPLESMC_CMD_PORT 0x304 + +#define APPLESMC_MAX_DATA_LENGTH 32 + +/* wait up to 128 ms for a status change. */ +#define APPLESMC_MIN_WAIT 0x0010 +#define APPLESMC_RETRY_WAIT 0x0100 +#define APPLESMC_MAX_WAIT 0x20000 + +#define APPLESMC_READ_CMD 0x10 +#define APPLESMC_WRITE_CMD 0x11 + +int wait_read(void); +int send_byte(uint8_t cmd, uint16_t port); +int send_command(uint8_t cmd); +int send_argument(const char *key); +int read_smc(uint8_t cmd, const char *key, uint8_t *buffer, uint8_t len); +int write_smc(uint8_t cmd, const char *key, const uint8_t *buffer, uint8_t len); + +#endif /* SMC_H */ diff --git a/util/smctool/smctool.c b/util/smctool/smctool.c new file mode 100644 index 0000000..fda7904 --- /dev/null +++ b/util/smctool/smctool.c @@ -0,0 +1,298 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <getopt.h> +#include <string.h> +#include <stdlib.h> +#include <assert.h> +#include <endian.h> +#include <sys/io.h> +#include <stdio.h> +#include <errno.h> +#include "smc.h" +#include "smctool.h" + +static bool fp_bits(char c, uint8_t *dest) +{ + if ((c >= '0' && c <= '9') || (c >= 'a' && c <= 'f')) { + *dest = strtol(&c, NULL, 16); + return true; + } + return false; +} + +static void print_bits(uint8_t len, uint8_t *ptr) +{ + for (int i = len - 1; i >= 0; i--) { + for (int j = 7; j >= 0; j--) + printf("%u", (ptr[i] >> j) & 1); + + if (i > 0) + printf(" "); + } +} + +static void print_usage(const char *name) +{ + printf("usage: %s <options>\n", name); + printf("\n" + "Options:\n" + " -h, --help: print this help\n" + " -k, --key <name>: key name\n" + " -t, --type <type>: data type, see below\n" + " --output-hex\n" + " --output-bin\n" + "\n" + "Supported data types:\n" + " ui8, ui16, ui32, si8, si16, flag, fpXY, spXY\n" + "\n" + " fp and sp are unsigned and signed fixed point\n" + " data types respectively.\n" + "\n" + " The X in fp and sp data types is integer bits count\n" + " and Y is fraction bits count.\n" + "\n" + " For example,\n" + " fpe2 means 14 integer bits, 2 fraction bits,\n" + " sp78 means 7 integer bits, 8 fraction bits\n" + " (and one sign bit).\n" + "\n"); +} + + +enum output_format {dec, hex, bin}; + +enum smctype {none, ui8, ui16, ui32, si8, si16, flag, fp, sp}; +struct { + enum smctype type; + uint8_t len; + char *str; + char *decfmt; + char *hexfmt; +} types[] = { + {ui8, 1, "ui8", "%u", "0x%02x"}, + {ui16, 2, "ui16", "%u", "0x%04x"}, + {ui32, 4, "ui32", "%u", "0x%08x"}, + {si8, 1, "si8", "%d", "0x%02x"}, + {si16, 2, "si16", "%d", "0x%04x"}, + {flag, 1, "flag", "%u", "0x%01x"}, +}; + +int main(int argc, char *argv[]) +{ + bool show_help = false; + int opt, option_index = 0; + char name[KEYBUFSIZE+1] = {0}; + char typebuf[KEYBUFSIZE+1] = {0}; + uint8_t fp_int_bits = 0, fp_fraction_bits = 0; + + enum output_format of = dec; + char *ofmt = NULL; + char fmtbuf[32]; + + enum smctype type = none; + uint8_t len; + + struct option long_options[] = { + {"help", 0, 0, 'h'}, + {"key", 1, 0, 'k'}, + {"type", 1, 0, 't'}, + {"output-hex", 0, 0, 1000}, + {"output-bin", 0, 0, 1001}, + {0, 0, 0, 0} + }; + + if (argv[1] == NULL) { + print_usage(argv[0]); + exit(0); + } + + while ((opt = getopt_long(argc, argv, "hk:t:", + long_options, &option_index)) != EOF) { + switch (opt) { + case 'h': + show_help = true; + break; + + case 'k': + snprintf(name, KEYBUFSIZE, "%s", optarg); + break; + + case 't': + snprintf(typebuf, KEYBUFSIZE, "%s", optarg); + break; + + case 1000: // output-hex + of = hex; + break; + + case 1001: // output-bin + of = bin; + break; + } + } + + if (optind < argc) { + fprintf(stderr, "Error: Extra parameter found.\n"); + print_usage(argv[0]); + exit(1); + } + + if (show_help) { + print_usage(argv[0]); + exit(0); + } + + /* Validate key name */ + if (strlen(name) != 4) { + fprintf(stderr, "Key name must be 4 characters long.\n"); + exit(1); + } + + /* Validate key type */ + if ((typebuf[0] == 'f' || typebuf[0] == 's') && typebuf[1] == 'p') { + if (!fp_bits(typebuf[2], &fp_int_bits) + || !fp_bits(typebuf[3], &fp_fraction_bits)) { + fprintf(stderr, "Invalid fixed point data type.\n"); + exit(1); + } + if (typebuf[0] == 'f' && fp_int_bits + fp_fraction_bits != 16) { + fprintf(stderr, + "Invalid unsigned fixed point data type.\n"); + exit(1); + } + if (typebuf[0] == 's' && fp_int_bits + fp_fraction_bits != 15) { + fprintf(stderr, + "Invalid signed fixed point data type.\n"); + exit(1); + } + type = typebuf[0] == 'f' ? fp : sp; + len = 2; + ofmt = "%d.%u"; + } + + if (type == none) { + for (unsigned int i = 0; i < ARRAY_SIZE(types); i++) { + if (strcmp(typebuf, types[i].str)) + continue; + + type = types[i].type; + len = types[i].len; + if (of == dec) + ofmt = types[i].decfmt; + else if (of == hex) + ofmt = types[i].hexfmt; + break; + } + } + + if (type == none) { + fprintf(stderr, "Key type \"%s\" is not known.\n", typebuf); + exit(1); + } + + /* Check permissions */ + if (geteuid() != 0) { + fprintf(stderr, "You must be root.\n"); + exit(1); + } + + /* Open SMC port */ + if (ioperm(APPLESMC_DATA_PORT, 0x10, 1)) { + fprintf(stderr, "ioperm: %s\n", strerror(errno)); + exit(1); + } + + /* Read key from SMC */ + int retval; + uint32_t buf = 0; + + retval = read_smc(APPLESMC_READ_CMD, name, (uint8_t *)&buf, len); + assert(retval == 0); + + /* Handle returned value according to the requested type */ + buf = be32toh(buf); + + int32_t fp_int = 0; + uint16_t fp_fraction = 0; + bool fp_sign = false; + + switch (type) { + case flag: + buf = (buf >> 24) & 1; + break; + + case ui8: + buf = (buf >> 24) & 0xff; + break; + + case si8: + buf = (buf >> 24) & 0xff; + if (of == dec) + buf = (int8_t)buf; + break; + + case ui16: + buf = (buf >> 16) & 0xffff; + break; + + case si16: + buf = (buf >> 16) & 0xffff; + if (of == dec) + buf = (int16_t)buf; + break; + + case fp: + buf = (buf >> 16) & 0xffff; + fp_int = buf >> fp_fraction_bits; + fp_fraction = buf & (0xffff >> fp_int_bits); + break; + + case sp: + buf = (buf >> 16) & 0xffff; + fp_sign = ((buf >> 15) & 1) == 1; + + buf &= ~(1 << 15); + + fp_int = buf >> fp_fraction_bits; + fp_fraction = buf & (0xffff >> fp_int_bits); + + if (fp_sign) + fp_int *= -1; + break; + + case ui32: + case none: // to avoid gcc warning + break; + } + + /* Output the result */ + if (of != bin) { + strcpy(fmtbuf, "%s = "); + strcat(fmtbuf, ofmt); + strcat(fmtbuf, "\n"); + + if (type == fp || type == sp) + printf(fmtbuf, name, fp_int, fp_fraction); + else + printf(fmtbuf, name, buf); + } else { + printf("%s = ", name); + print_bits(len, (uint8_t *)&buf); + printf("\n"); + } + + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/33052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6161203e52b7f7eaa1205de06e8241d7d40a7481 Gerrit-Change-Number: 33052 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/ibexpeak: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB
by Patrick Rudolph (Code Review) June 10, 2023

June 10, 2023

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32316 Change subject: sb/intel/ibexpeak: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB ...................................................................... sb/intel/ibexpeak: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB Use common code to detect ACPI S3. Untested. Change-Id: I766a3f4206e6605e6b7bb9a1ff0b2deb6721eb77 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/lenovo/x201/romstage.c M src/mainboard/packardbell/ms2290/romstage.c M src/southbridge/intel/ibexpeak/Kconfig 3 files changed, 13 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/32316/1 diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 7e895b4..e65622c 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -34,6 +34,7 @@ #include "dock.h" #include <southbridge/intel/ibexpeak/pch.h> #include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/nehalem/nehalem.h> #include <northbridge/intel/nehalem/raminit.h> @@ -206,24 +207,14 @@ /* Halt if there was a built in self test failure */ report_bist_failure(bist); - /* Read PM1_CNT */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); - if (((reg32 >> 10) & 7) == 5) { - u8 reg8; - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + /* Check for S3 resume. */ + s3resume = southbridge_detect_s3_resume(); + if (s3resume) { + u8 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); printk(BIOS_DEBUG, "a2: %02x\n", reg8); if (!(reg8 & 0x20)) { - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); printk(BIOS_DEBUG, "Bad resume from S3 detected.\n"); - } else { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - s3resume = 1; - } else { - printk(BIOS_DEBUG, - "Resume from S3 detected, but disabled.\n"); - } + s3resume = 0; } } @@ -263,13 +254,5 @@ intel_early_me_status(); - if (s3resume) { - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - } - romstage_handoff_init(s3resume); } diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 8442dfa..854c835 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -34,6 +34,7 @@ #include "arch/early_variables.h" #include <southbridge/intel/ibexpeak/pch.h> #include <northbridge/intel/nehalem/nehalem.h> +#include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/nehalem/raminit.h> #include <southbridge/intel/ibexpeak/me.h> @@ -206,24 +207,14 @@ /* Halt if there was a built in self test failure */ report_bist_failure(bist); - /* Read PM1_CNT */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); - if (((reg32 >> 10) & 7) == 5) { - u8 reg8; - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + /* Check for S3 resume. */ + s3resume = southbridge_detect_s3_resume(); + if (s3resume) { + u8 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); printk(BIOS_DEBUG, "a2: %02x\n", reg8); if (!(reg8 & 0x20)) { - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); printk(BIOS_DEBUG, "Bad resume from S3 detected.\n"); - } else { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - s3resume = 1; - } else { - printk(BIOS_DEBUG, - "Resume from S3 detected, but disabled.\n"); - } + s3resume = 0; } } @@ -255,13 +246,5 @@ intel_early_me_status(); - if (s3resume) { - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - } - romstage_handoff_init(s3resume); } diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index bb6e22c..59b012e 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -32,6 +32,7 @@ select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI + select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select HAVE_USBDEBUG_OPTIONS select COMMON_FADT select ACPI_SATA_GENERATOR -- To view, visit https://review.coreboot.org/c/coreboot/+/32316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I766a3f4206e6605e6b7bb9a1ff0b2deb6721eb77 Gerrit-Change-Number: 32316 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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