coreboot-gerrit June 2019

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Change in ...coreboot[master]: src/cpu/x86 STM Support
by Name of user not set (Code Review) 20 Dec '19

20 Dec '19

Name of user not set #1002358 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33236 Change subject: src/cpu/x86 STM Support ...................................................................... src/cpu/x86 STM Support STM initialization Change-Id: I3a0adcefc0f6e22a9da5fe53952481a77737e5eb --- M src/cpu/x86/mp_init.c 1 file changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/33236/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 3889c7d..881d8a2 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -37,8 +37,12 @@ #include <symbols.h> #include <thread.h> +#include <security/intel/stm/StmApi.h> + #define MAX_APIC_IDS 256 +extern int LoadStmImage(uint32_t mseg); + struct mp_callback { void (*func)(void *); void *arg; @@ -823,6 +827,10 @@ { size_t smm_save_state_size = mp_state.smm_save_state_size; +#ifdef CONFIG_STM + uint32_t mseg; +#endif + /* Do nothing if SMM is disabled.*/ if (!is_smm_enabled()) return; @@ -839,6 +847,14 @@ printk(BIOS_ERR, "Unable to install SMM permanent handler.\n"); smm_disable(); } +#ifdef CONFIG_STM + + /* Calculate mseg location*/ + mseg = mp_state.perm_smbase + (mp_state.perm_smsize - CONFIG_MSEG_SIZE); + + /* Load the STM into the MSEG */ + LoadStmImage(mseg); +#endif /* Ensure the SMM handlers hit DRAM before performing first SMI. */ wbinvd(); @@ -1023,6 +1039,15 @@ if (ops->get_smm_info != NULL) ops->get_smm_info(&state->perm_smbase, &state->perm_smsize, &state->smm_save_state_size); +#ifdef CONFIG_STM + + /* Currently, the CPU SMM save state size is based on a simplistic + * algorithm. (set it to 1K) + * note: In the future, this will need to handle newer x86 processors + * that require 32k alignment of the save state on 32K boundries.*/ + state->smm_save_state_size += (sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR) + 0x1000) & 0xfffff000; + +#endif /* CONFIG_STM */ /* * Default to smm_initiate_relocation() if trigger callback isn't -- To view, visit https://review.coreboot.org/c/coreboot/+/33236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a0adcefc0f6e22a9da5fe53952481a77737e5eb Gerrit-Change-Number: 33236 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002358 Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/x86/smm/ STM Support
by Name of user not set (Code Review) 20 Dec '19

20 Dec '19

Name of user not set #1002358 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33235 Change subject: cpu/x86/smm/ STM Support ...................................................................... cpu/x86/smm/ STM Support SMI Handler modifications needed to setup the STM data structures Change-Id: I935cd5a8bc0bf293240324c2e3a04a655d44c69f --- M src/cpu/x86/smm/smm_module_handler.c M src/cpu/x86/smm/smm_module_loader.c M src/cpu/x86/smm/smm_stub.S M src/include/cpu/x86/smm.h 4 files changed, 92 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/33235/1 diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index f9af965..26ddd66 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -18,6 +18,15 @@ #include <cpu/x86/smm.h> #include <rmodule.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/cache.h> + +#include <security/intel/stm/StmApi.h> +#include <security/intel/stm/StmPlatformResource.h> +#include <arch/acpi.h> +#include <lib.h> +#include <security/intel/stm/SmmStm.h> + #if IS_ENABLED(CONFIG_SPI_FLASH_SMM) #include <spi-generic.h> #endif @@ -116,6 +125,10 @@ return base; } +#ifdef CONFIG_STM + static uint32_t MsegInit = 0; // used for STM/mseg initialization +#endif + asmlinkage void smm_handler_start(void *arg) { const struct smm_module_params *p; @@ -123,7 +136,16 @@ int cpu; uintptr_t actual_canary; uintptr_t expected_canary; +#ifdef CONFIG_STM + int MsegInit2 = 1; // assume that the STM has been set + /* this initialzation strategy works on the assumption that all + * processors will enter SMM at generally the same time. + * If a single processor lags then a locking/counting scheme will + * need to be implemented. */ + if (MsegInit == 0) + MsegInit2 = 0; +#endif p = arg; runtime = p->runtime; cpu = p->cpu; @@ -140,9 +162,33 @@ "Invalid CPU number assigned in SMM stub: %d\n", cpu); return; } +#ifdef CONFIG_STM + if (MsegInit == 0) { + + /* Initialize the MSEG base address for each logical processor + * and indicate that there is an STM present */ + msr_t InitMseg; + msr_t MsegChk; + + InitMseg.lo = smm_runtime->mseg | IA32_SMM_MONITOR_VALID; + InitMseg.hi = 0; + + wrmsr(IA32_SMM_MONITOR_CTL_MSR_INDEX, InitMseg); + + MsegChk = rdmsr(IA32_SMM_MONITOR_CTL_MSR_INDEX); + console_init(); + + printk(BIOS_DEBUG, "MSEG Initialized (%d) 0x%08x 0x%08x\n", + cpu, MsegChk.hi, MsegChk.lo); + } + +#endif /* Are we ok to execute the handler? */ if (!smi_obtain_lock()) { +#ifdef CONFIG_STM + void *smbase = (void *) smm_runtime->smbase; +#endif /* For security reasons we don't release the other CPUs * until the CPU with the lock is actually done */ while (smi_handler_status == SMI_LOCKED) { @@ -150,13 +196,35 @@ ".byte 0xf3, 0x90\n" /* PAUSE */ ); } +#ifdef CONFIG_STM + if (MsegInit2 == 0) { + + /* Setup an SMM Descriptor for this logical processor */ + SetupSmmDescriptor(smbase, smm_runtime->save_state_size, cpu, smm_runtime->start32_offset); + MsegInit2 = 1; + } +#endif + wbinvd(); return; } +#ifdef CONFIG_STM + + if (MsegInit == 0) { + void *smbase = (void *) smm_runtime->smbase; + + AddResourcesCmd(); + + /* Setup an SMM Descriptor for this logical processor */ + + SetupSmmDescriptor(smbase, smm_runtime->save_state_size, cpu, + smm_runtime->start32_offset); + MsegInit = 1; // flag that we are done + wbinvd(); // force the tables to memory + } +#endif smi_backup_pci_address(); - console_init(); - printk(BIOS_SPEW, "\nSMI# #%d\n", cpu); /* Allow drivers to initialize variables in SMM context. */ diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 6c16645..4f15fdd 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -18,6 +18,7 @@ #include <cpu/x86/smm.h> #include <cpu/x86/cache.h> #include <console/console.h> +#include <security/intel/stm/SmmStm.h> #define FXSAVE_SIZE 512 @@ -268,6 +269,9 @@ stub_params->fxsave_area_size = FXSAVE_SIZE; stub_params->runtime.smbase = (uintptr_t)smbase; stub_params->runtime.save_state_size = params->per_cpu_save_state_size; + + /* mseg is after the smi handler */ + stub_params->runtime.mseg = (uint32_t) params->stack_top; /* Initialize the APIC id to CPU number table to be 1:1 */ for (i = 0; i < params->num_concurrent_stacks; i++) @@ -354,7 +358,13 @@ /* Stacks start at the top of the region. */ base = smram; + +#ifdef CONFIG_STM + base += size - CONFIG_MSEG_SIZE; // take out the mseg +#else base += size; +#endif + params->stack_top = base; /* SMM module starts at offset SMM_DEFAULT_SIZE with the load alignment diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index 59eb27c..3817424 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -46,6 +46,11 @@ .long 0 save_state_size: .long 0 +mseg: +.long 0 +/* allows the STM to bring up SMM in 32-bit mode*/ +start32_offset: +.long smm_trampoline32 - _start /* apic_to_cpu_num is a table mapping the default APIC id to CPU num. If the * APIC id is found at the given index, the contiguous CPU number is index * into the table. */ @@ -92,6 +97,10 @@ /* gdt selector 0x10, flat data segment */ .word 0xffff, 0x0000 .byte 0x00, 0x93, 0xcf, 0x00 + + /* gdt selector 0x18 tr segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x8b, 0x80, 0x00 smm_relocate_gdt_end: .align 4 diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 576449d..b2d7445 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -512,6 +512,9 @@ struct smm_runtime { u32 smbase; u32 save_state_size; + u32 mseg; + /* used so that the STM can start the SMI handler in 32bit mode */ + u32 start32_offset; /* The apic_id_to_cpu provides a mapping from APIC id to CPU number. * The CPU number is indicated by the index into the array by matching * the default APIC id and value at the index. The stub loader -- To view, visit https://review.coreboot.org/c/coreboot/+/33235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I935cd5a8bc0bf293240324c2e3a04a655d44c69f Gerrit-Change-Number: 33235 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002358 Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP] Move AGESA and apufw higher in CBFS
by Kyösti Mälkki (Code Review) 19 Dec '19

19 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31076 Change subject: [WIP] Move AGESA and apufw higher in CBFS ...................................................................... [WIP] Move AGESA and apufw higher in CBFS Increases continuous free space in CBFS from 5.8 MiB to 7.1 MiB. Will not work with released binaryPI build from 3rdparty/blobs. Change-Id: I3c166102b8774499a0b21f212b5e8a66fe6c52eb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/amd/pi/hudson/Makefile.inc M src/vendorcode/amd/pi/Kconfig 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/31076/1 diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 81fe7ff..57bad38 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -75,7 +75,7 @@ ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) HUDSON_FWM_POSITION=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 0x20000 1) else -HUDSON_FWM_POSITION=0xfff20000 +HUDSON_FWM_POSITION=0xfffa0000 endif ifeq ($(CONFIG_HUDSON_PSP), y) diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig index f463b7d..3dc7052 100644 --- a/src/vendorcode/amd/pi/Kconfig +++ b/src/vendorcode/amd/pi/Kconfig @@ -96,7 +96,7 @@ config AGESA_BINARY_PI_LOCATION hex "AGESA PI binary address in ROM" - default 0xFFE00000 + default 0xFFF00000 depends on !AGESA_BINARY_PI_AS_STAGE help Specify the ROM address at which to store the binary Platform -- To view, visit https://review.coreboot.org/c/coreboot/+/31076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c166102b8774499a0b21f212b5e8a66fe6c52eb Gerrit-Change-Number: 31076 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mainboard/lenovo: remove stdlib.h when unused
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33901 Change subject: mainboard/lenovo: remove stdlib.h when unused ...................................................................... mainboard/lenovo: remove stdlib.h when unused Change-Id: I6af1d44f9a05c153b6a355318a39adc9a3d6c0c9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/lenovo/g505s/BiosCallOuts.c M src/mainboard/lenovo/g505s/buildOpts.c 2 files changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/33901/1 diff --git a/src/mainboard/lenovo/g505s/BiosCallOuts.c b/src/mainboard/lenovo/g505s/BiosCallOuts.c index 2b1ac04..afa2fce 100644 --- a/src/mainboard/lenovo/g505s/BiosCallOuts.c +++ b/src/mainboard/lenovo/g505s/BiosCallOuts.c @@ -16,10 +16,8 @@ #include <AGESA.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/state_machine.h> - #include <southbridge/amd/agesa/hudson/imc.h> #include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> -#include <stdlib.h> const BIOS_CALLOUT_STRUCT BiosCallouts[] = { diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index c3e40ce..559e1a6 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -27,8 +27,6 @@ #include "mainboard.h" -#include <stdlib.h> - #include <vendorcode/amd/agesa/f15tn/AGESA.h> /* Include the files that instantiate the configuration definitions. */ @@ -43,7 +41,6 @@ #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h> #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h> - /* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE -- To view, visit https://review.coreboot.org/c/coreboot/+/33901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6af1d44f9a05c153b6a355318a39adc9a3d6c0c9 Gerrit-Change-Number: 33901 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/arch: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32820 Change subject: src/arch: Use 'include <stdlib.h>' when appropriate ...................................................................... src/arch: Use 'include <stdlib.h>' when appropriate Change-Id: I79f065703b5249ca9630b06de7142bc52675076e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm/armv7/mmu.c M src/arch/arm/cpu.c M src/arch/mips/mmu.c M src/arch/x86/acpigen_dsm.c M src/arch/x86/cbmem.c M src/arch/x86/mmap_boot.c 6 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/32820/1 diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c index ce9d3fd..f0a5fa6 100644 --- a/src/arch/arm/armv7/mmu.c +++ b/src/arch/arm/armv7/mmu.c @@ -29,12 +29,9 @@ */ #include <assert.h> -#include <stdlib.h> #include <stdint.h> #include <symbols.h> - #include <console/console.h> - #include <arch/cache.h> #if CONFIG(ARM_LPAE) diff --git a/src/arch/arm/cpu.c b/src/arch/arm/cpu.c index fae1a37..0637bf6 100644 --- a/src/arch/arm/cpu.c +++ b/src/arch/arm/cpu.c @@ -27,7 +27,6 @@ * SUCH DAMAGE. * */ -#include <stdlib.h> #include <arch/cpu.h> /* Return the CPU struct which is at the high memory address of the stack. diff --git a/src/arch/mips/mmu.c b/src/arch/mips/mmu.c index b144fd3..2ceb2a7 100644 --- a/src/arch/mips/mmu.c +++ b/src/arch/mips/mmu.c @@ -18,7 +18,6 @@ #include <console/console.h> #include <stddef.h> #include <stdint.h> -#include <stdlib.h> #define MIN_PAGE_SIZE (4 * KiB) diff --git a/src/arch/x86/acpigen_dsm.c b/src/arch/x86/acpigen_dsm.c index 1aab90b..8c9cd350 100644 --- a/src/arch/x86/acpigen_dsm.c +++ b/src/arch/x86/acpigen_dsm.c @@ -15,7 +15,6 @@ #include <arch/acpigen.h> #include <arch/acpigen_dsm.h> -#include <stdlib.h> /* ------------------- I2C HID DSM ---------------------------- */ diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c index 648633f..abd163d 100644 --- a/src/arch/x86/cbmem.c +++ b/src/arch/x86/cbmem.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <cbmem.h> #include <arch/acpi.h> diff --git a/src/arch/x86/mmap_boot.c b/src/arch/x86/mmap_boot.c index abfa024..98b5643 100644 --- a/src/arch/x86/mmap_boot.c +++ b/src/arch/x86/mmap_boot.c @@ -15,7 +15,6 @@ #include <boot_device.h> #include <endian.h> -#include <stdlib.h> /* The ROM is memory mapped just below 4GiB. Form a pointer for the base. */ #define rom_base ((void *)(uintptr_t)(0x100000000ULL-CONFIG_ROM_SIZE)) -- To view, visit https://review.coreboot.org/c/coreboot/+/32820 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79f065703b5249ca9630b06de7142bc52675076e Gerrit-Change-Number: 32820 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33686 Change subject: soc/intel: Use 'include <stdlib.h>' when appropriate ...................................................................... soc/intel: Use 'include <stdlib.h>' when appropriate Change-Id: I71a5a6c3748d5a3910970bfb1ec3d7ecd3184cfd Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/baytrail/cpu.c M src/soc/intel/braswell/cpu.c M src/soc/intel/broadwell/me.c M src/soc/intel/cannonlake/memmap.c M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/fast_spi/fast_spi_flash.c M src/soc/intel/common/smbios.c M src/soc/intel/fsp_baytrail/cpu.c M src/soc/intel/icelake/memmap.c M src/soc/intel/quark/i2c.c M src/soc/intel/skylake/me.c 12 files changed, 18 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/33686/1 diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 9526932..681c2fe 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <console/console.h> #include <cpu/cpu.h> #include <cpu/intel/common/common.h> @@ -32,6 +31,7 @@ #include <soc/pattrs.h> #include <soc/ramstage.h> #include <soc/smm.h> +#include <stddef.h> /* Core level MSRs */ const struct reg_script core_msr_script[] = { diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 5f86a11..dd3346c 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -33,7 +33,7 @@ #include <soc/pattrs.h> #include <soc/ramstage.h> #include <soc/smm.h> -#include <stdlib.h> +#include <stddef.h> /* Core level MSRs */ static const struct reg_script core_msr_script[] = { diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index dd5e5b8..05f69b5 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -39,7 +39,7 @@ #include <soc/ramstage.h> #include <soc/rcba.h> #include <soc/intel/broadwell/chip.h> - +#include <stdlib.h> #if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 3cae54f..a5e1981 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -25,7 +25,7 @@ #include <soc/pci_devs.h> #include <soc/smm.h> #include <soc/systemagent.h> -#include <stdlib.h> +#include <stddef.h> #include "chip.h" diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index ab36c70..2777e93 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -30,7 +30,6 @@ #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> #include <intelblocks/tco.h> -#include <stdlib.h> #include <soc/gpe.h> #include <soc/gpio.h> #include <soc/iomap.h> @@ -39,6 +38,7 @@ #include <soc/pm.h> #include <soc/smbus.h> #include <security/vboot/vbnv.h> +#include <stddef.h> #include "chip.h" diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 58e7db7..f4fdb84 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -23,9 +23,9 @@ #include <intelblocks/fast_spi.h> #include <lib.h> #include <soc/pci_devs.h> +#include <stddef.h> #include <spi_flash.h> #include <spi-generic.h> -#include <stdlib.h> /* * Get the FAST_SPIBAR. diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c index 0a43442..e0b6ba9 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c @@ -19,6 +19,8 @@ #include <intelblocks/fast_spi.h> #include <soc/pci_devs.h> #include <spi_flash.h> +#include <stddef.h> +#include <stdlib.h> #include <string.h> #include <timer.h> diff --git a/src/soc/intel/common/smbios.c b/src/soc/intel/common/smbios.c index d315e15..50ba04a 100644 --- a/src/soc/intel/common/smbios.c +++ b/src/soc/intel/common/smbios.c @@ -13,11 +13,14 @@ * GNU General Public License for more details. */ -#include <smbios.h> -#include "smbios.h" -#include <string.h> #include <console/console.h> #include <device/dram/ddr3.h> +#include <smbios.h> +#include <stddef.h> +#include <stdlib.h> +#include <string.h> + +#include "smbios.h" /* Fill the SMBIOS memory information from FSP MEM_INFO_DATA_HOB in CBMEM.*/ void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type, diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index 15dc851..12dd724 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <console/console.h> #include <cpu/cpu.h> #include <cpu/intel/microcode.h> @@ -31,6 +30,7 @@ #include <soc/pattrs.h> #include <soc/ramstage.h> #include <soc/smm.h> +#include <stddef.h> /* Core level MSRs */ static const struct reg_script core_msr_script[] = { diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index f446708..917f487 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -24,7 +24,7 @@ #include <soc/pci_devs.h> #include <soc/smm.h> #include <soc/systemagent.h> -#include <stdlib.h> +#include <stddef.h> #include "chip.h" diff --git a/src/soc/intel/quark/i2c.c b/src/soc/intel/quark/i2c.c index bb1a264..929d3ff 100644 --- a/src/soc/intel/quark/i2c.c +++ b/src/soc/intel/quark/i2c.c @@ -22,6 +22,7 @@ #include <soc/i2c.h> #include <soc/ramstage.h> #include <soc/reg_access.h> +#include <stdlib.h> #include <timer.h> static void i2c_disable(I2C_REGS *regs) diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index f7aa584..c8622f7 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -22,8 +22,8 @@ #include <soc/iomap.h> #include <soc/me.h> #include <soc/pci_devs.h> +#include <stddef.h> #include <stdint.h> -#include <stdlib.h> #include <string.h> static inline u32 me_read_config32(int offset) -- To view, visit https://review.coreboot.org/c/coreboot/+/33686 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71a5a6c3748d5a3910970bfb1ec3d7ecd3184cfd Gerrit-Change-Number: 33686 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 8

Change in ...coreboot[master]: soc/{samsung,sifive}: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33689 Change subject: soc/{samsung,sifive}: Use 'include <stdlib.h>' when appropriate ...................................................................... soc/{samsung,sifive}: Use 'include <stdlib.h>' when appropriate Change-Id: I6a933295de7c41d62e6a95f955c098b49ea17f08 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/samsung/exynos5250/spi.c M src/soc/samsung/exynos5420/spi.c M src/soc/sifive/fu540/clock.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/33689/1 diff --git a/src/soc/samsung/exynos5250/spi.c b/src/soc/samsung/exynos5250/spi.c index e35f888..592cefa 100644 --- a/src/soc/samsung/exynos5250/spi.c +++ b/src/soc/samsung/exynos5250/spi.c @@ -21,7 +21,7 @@ #include <soc/clk.h> #include <soc/gpio.h> #include <soc/spi.h> -#include <stdlib.h> +#include <stddef.h> #include <symbols.h> #if defined(CONFIG_DEBUG_SPI) && CONFIG_DEBUG_SPI diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c index 1903f6b..8081b1c 100644 --- a/src/soc/samsung/exynos5420/spi.c +++ b/src/soc/samsung/exynos5420/spi.c @@ -20,7 +20,7 @@ #include <soc/cpu.h> #include <soc/spi.h> #include <spi-generic.h> -#include <stdlib.h> +#include <stddef.h> #include <string.h> #include <symbols.h> diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c index 60a8a13..0685ce6 100644 --- a/src/soc/sifive/fu540/clock.c +++ b/src/soc/sifive/fu540/clock.c @@ -17,7 +17,7 @@ #include <console/console.h> #include <soc/clock.h> #include <soc/addressmap.h> -#include <stdlib.h> +#include <stddef.h> #include <stdint.h> // 33.33 Mhz after reset -- To view, visit https://review.coreboot.org/c/coreboot/+/33689 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a933295de7c41d62e6a95f955c098b49ea17f08 Gerrit-Change-Number: 33689 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 6

Change in ...coreboot[master]: soc/{amd,cavium}: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33688 Change subject: soc/{amd,cavium}: Use 'include <stdlib.h>' when appropriate ...................................................................... soc/{amd,cavium}: Use 'include <stdlib.h>' when appropriate Change-Id: I83322e246fe81b97188be17a3fdda16d36df0678 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/amd/stoneyridge/BiosCallOuts.c M src/soc/cavium/cn81xx/spi.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/33688/1 diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c index c55e734..b797507 100644 --- a/src/soc/amd/stoneyridge/BiosCallOuts.c +++ b/src/soc/amd/stoneyridge/BiosCallOuts.c @@ -21,10 +21,10 @@ #include <console/console.h> #include <soc/southbridge.h> #include <soc/pci_devs.h> -#include <stdlib.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/dimm_spd.h> #include <amdblocks/car.h> +#include <stddef.h> #include "chip.h" diff --git a/src/soc/cavium/cn81xx/spi.c b/src/soc/cavium/cn81xx/spi.c index 2ba25a2..2089576 100644 --- a/src/soc/cavium/cn81xx/spi.c +++ b/src/soc/cavium/cn81xx/spi.c @@ -25,7 +25,7 @@ #include <soc/clock.h> #include <spi-generic.h> #include <spi_flash.h> -#include <stdlib.h> +#include <stddef.h> #include <timer.h> union cavium_spi_cfg { -- To view, visit https://review.coreboot.org/c/coreboot/+/33688 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83322e246fe81b97188be17a3fdda16d36df0678 Gerrit-Change-Number: 33688 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 6

Change in ...coreboot[master]: southbridge: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32829 Change subject: southbridge: Use 'include <stdlib.h>' when appropriate ...................................................................... southbridge: Use 'include <stdlib.h>' when appropriate Change-Id: I5728b44fdd680b21e951397a2390e24f9171ac34 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/amd/agesa/hudson/spi.c M src/southbridge/amd/amd8111/lpc.c M src/southbridge/intel/bd82x6x/me_status.c M src/southbridge/intel/common/smbus.c M src/southbridge/intel/fsp_rangeley/early_init.c M src/southbridge/intel/i82801ix/i82801ix.c M src/southbridge/intel/i82801jx/i82801jx.c M src/southbridge/intel/lynxpoint/me_status.c M src/southbridge/intel/lynxpoint/serialio.c M src/southbridge/nvidia/ck804/lpc.c M src/southbridge/nvidia/mcp55/lpc.c 11 files changed, 10 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/32829/1 diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index 9c546c5..fb9f7a1 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -12,8 +12,9 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ + +#include <stddef.h> #include <stdint.h> -#include <stdlib.h> #include <device/mmio.h> #include <console/console.h> #include <spi_flash.h> @@ -21,7 +22,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> - #include <Proc/Fch/FchPlatform.h> #define SPI_REG_OPCODE 0x0 diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c index c4a7896..11e852a 100644 --- a/src/southbridge/amd/amd8111/lpc.c +++ b/src/southbridge/amd/amd8111/lpc.c @@ -28,7 +28,6 @@ #include <arch/acpigen.h> #include <cpu/amd/powernow.h> #endif -#include <stdlib.h> #include "amd8111.h" diff --git a/src/southbridge/intel/bd82x6x/me_status.c b/src/southbridge/intel/bd82x6x/me_status.c index b202376..1225cb1 100644 --- a/src/southbridge/intel/bd82x6x/me_status.c +++ b/src/southbridge/intel/bd82x6x/me_status.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <console/console.h> + #include "me.h" #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c index af1eb60..6d901d6 100644 --- a/src/southbridge/intel/common/smbus.c +++ b/src/southbridge/intel/common/smbus.c @@ -18,12 +18,10 @@ #include <arch/io.h> #include <console/console.h> #include <device/smbus_def.h> -#include <stdlib.h> #include <types.h> #include "smbus.h" - #if CONFIG(DEBUG_SMBUS) #define dprintk(args...) printk(BIOS_DEBUG, ##args) #else diff --git a/src/southbridge/intel/fsp_rangeley/early_init.c b/src/southbridge/intel/fsp_rangeley/early_init.c index 32e3bb5..aade4db 100644 --- a/src/southbridge/intel/fsp_rangeley/early_init.c +++ b/src/southbridge/intel/fsp_rangeley/early_init.c @@ -16,7 +16,6 @@ */ #include <stdint.h> -#include <stdlib.h> #include <console/console.h> #include <arch/io.h> #include <device/mmio.h> @@ -24,6 +23,7 @@ #include <device/pci_def.h> #include <pc80/mc146818rtc.h> #include <version.h> + #include "pci_devs.h" #include "soc.h" diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index 99078dc..aa81984 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -16,12 +16,12 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <arch/io.h> #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> #include <console/console.h> + #include "i82801ix.h" typedef struct southbridge_intel_i82801ix_config config_t; diff --git a/src/southbridge/intel/i82801jx/i82801jx.c b/src/southbridge/intel/i82801jx/i82801jx.c index ec5576d..bf85f98 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.c +++ b/src/southbridge/intel/i82801jx/i82801jx.c @@ -16,12 +16,12 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <arch/io.h> #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> #include <console/console.h> + #include "i82801jx.h" typedef struct southbridge_intel_i82801jx_config config_t; diff --git a/src/southbridge/intel/lynxpoint/me_status.c b/src/southbridge/intel/lynxpoint/me_status.c index 9ca5552..d1ece5a 100644 --- a/src/southbridge/intel/lynxpoint/me_status.c +++ b/src/southbridge/intel/lynxpoint/me_status.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <console/console.h> + #include "me.h" #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index 23d8125..1557c8d 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -21,7 +21,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <stdlib.h> + #include "pch.h" #include "nvs.h" diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index 2123554..cbf5320 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -29,9 +29,9 @@ #include <arch/ioapic.h> #include <arch/acpi.h> #include <cpu/x86/lapic.h> -#include <stdlib.h> #include <assert.h> #include <cpu/amd/powernow.h> + #include "chip.h" #define NMI_OFF 0 diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 1aef631..b80a524 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -31,8 +31,8 @@ #include <arch/ioapic.h> #include <cpu/x86/lapic.h> #include <arch/acpi.h> -#include <stdlib.h> #include <cpu/amd/powernow.h> + #include "mcp55.h" #define NMI_OFF 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/32829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5728b44fdd680b21e951397a2390e24f9171ac34 Gerrit-Change-Number: 32829 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 7

Change in ...coreboot[master]: src/northbridge: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33685 Change subject: src/northbridge: Use 'include <stdlib.h>' when appropriate ...................................................................... src/northbridge: Use 'include <stdlib.h>' when appropriate Change-Id: I7a214196b05d3af06c8cd742a6154b0627a0d82f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/amd/amdht/h3finit.c M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c M src/northbridge/amd/amdmct/wrappers/mcti_d.c M src/northbridge/intel/haswell/early_init.c M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/i440bx/northbridge.c M src/northbridge/intel/i440bx/raminit.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/nehalem/finalize.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/raminit_common.c 12 files changed, 14 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/33685/1 diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index cda0a28..1928b47 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -36,6 +36,7 @@ #include <device/pci_def.h> #include <northbridge/amd/amdfam10/raminit.h> #include <northbridge/amd/amdfam10/amdfam10.h> +#include <stdlib.h> #include <types.h> /*---------------------------------------------------------------------------- diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index d991002..d571816 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -30,11 +30,11 @@ #include <spi_flash.h> #include <pc80/mc146818rtc.h> #include <inttypes.h> +#include <stdlib.h> #include <types.h> #include "mct_d.h" #include "mct_d_gcc.h" - #include "s3utils.h" #define S3NV_FILE_NAME "s3nv" diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index b8042fe..5833a82 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -20,6 +20,7 @@ #include <cpu/amd/msr.h> #include <console/console.h> #include <types.h> +#include <stdlib.h> #include "mcti.h" diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index 6fef0da..8f2921a 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -15,12 +15,12 @@ */ #include <stdint.h> -#include <stdlib.h> #include <console/console.h> #include <device/mmio.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <elog.h> + #include "haswell.h" static bool peg_hidden[3]; diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index 1777006..7a82e99 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <device/pci_ops.h> + #include "haswell.h" #define PCI_DEV_HSW PCI_DEV(0, 0, 0) diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 2fd5959..23d86c4 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -25,9 +25,9 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include <stdlib.h> #include <cpu/x86/smm.h> #include <boot/tables.h> +#include <stddef.h> #include "chip.h" #include "haswell.h" diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index ef6329c..2c1ae72 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -17,8 +17,8 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <stdlib.h> #include <cpu/cpu.h> + #include "northbridge.h" #include "i440bx.h" diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index 91959c7..9998280 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -18,11 +18,11 @@ #include <spd.h> #include <delay.h> #include <stdint.h> -#include <stdlib.h> #include <device/mmio.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <console/console.h> + #include "i440bx.h" #include "raminit.h" diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index e9867d9..8a188c9 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -20,10 +20,10 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <stdlib.h> #include <cpu/cpu.h> #include <arch/acpi.h> #include <cpu/intel/smm/gen1/smi.h> + #include "i945.h" static int get_pcie_bar(u32 *base) diff --git a/src/northbridge/intel/nehalem/finalize.c b/src/northbridge/intel/nehalem/finalize.c index 97f6011..f0bb50b 100644 --- a/src/northbridge/intel/nehalem/finalize.c +++ b/src/northbridge/intel/nehalem/finalize.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <device/pci_ops.h> + #include "nehalem.h" #define PCI_DEV_SNB PCI_DEV(0, 0, 0) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 5aa06c8..a4f2dd3 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -24,11 +24,11 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <stdlib.h> #include <cpu/cpu.h> +#include <cpu/intel/smm/gen1/smi.h> + #include "chip.h" #include "sandybridge.h" -#include <cpu/intel/smm/gen1/smi.h> static int bridge_revision_id = -1; diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 4974173..3af9a62 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -23,6 +23,8 @@ #include <northbridge/intel/sandybridge/chip.h> #include <device/pci_def.h> #include <delay.h> +#include <stddef.h> +#include <stdlib.h> #include "raminit_native.h" #include "raminit_common.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/33685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a214196b05d3af06c8cd742a6154b0627a0d82f Gerrit-Change-Number: 33685 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit June 2019