coreboot-gerrit April 2019

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Change in ...coreboot[master]: soc/intel/common: Add more GPIO definition macros
by Thomas Heijligen (Code Review) 10 Mar '20

10 Mar '20

Hello Nico Huber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31350 to review the following change. Change subject: soc/intel/common: Add more GPIO definition macros ...................................................................... soc/intel/common: Add more GPIO definition macros Change-Id: Id1a3c00aa8a857afa08e745b0b6a578b01fa6d47 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/31350/1 diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 35f89c9..4d9f2be 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -236,6 +236,16 @@ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)) +#define PAD_CFG_GPI_IOSSTATE(pad, pull, rst, iosstate) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ + PAD_PULL(pull) | PAD_IOSSTATE(iosstate)) + +#define PAD_CFG_GPI_IOSSTATE_IOSTERM(pad, pull, rst, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ + PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + /* General purpose input. The following macro sets the * Host Software Pad Ownership to GPIO Driver mode. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1a3c00aa8a857afa08e745b0b6a578b01fa6d47 Gerrit-Change-Number: 31350 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/mainboard/protectli/vault: Add FW2B and FW4B boards support
by Michał Żygowski (Code Review) 09 Mar '20

09 Mar '20

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32076 Change subject: src/mainboard/protectli/vault: Add FW2B and FW4B boards support ...................................................................... src/mainboard/protectli/vault: Add FW2B and FW4B boards support Working and tested: - both HDMI (SeaBIOS + OS) - USB (SeaBIOS + OS: MSC, keyboard, mouse) - mSATA SSD (SeaBIOS detection and booting installed Debian Stretch) - Ethernet (PXE boot, OS network access) - serial debug port UART0 on SuperIO (coreboot + SeaBIOS, OS console) TODO: - mainboard documentation - Azalia configuration for audio - test mPCIe WiFi TEST=booting Debian Stretch with Linux kernel 4.9.0 on both platforms Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I553fd3a89299314a855f055014ca7645100e12e7 --- A src/mainboard/protectli/Kconfig A src/mainboard/protectli/Kconfig.name A src/mainboard/protectli/vault/Kconfig A src/mainboard/protectli/vault/Kconfig.name A src/mainboard/protectli/vault/Makefile.inc A src/mainboard/protectli/vault/acpi/ec.asl A src/mainboard/protectli/vault/acpi/mainboard.asl A src/mainboard/protectli/vault/acpi/superio.asl A src/mainboard/protectli/vault/acpi_tables.c A src/mainboard/protectli/vault/board_info.txt A src/mainboard/protectli/vault/boardid.c A src/mainboard/protectli/vault/cmos.layout A src/mainboard/protectli/vault/dsdt.asl A src/mainboard/protectli/vault/fadt.c A src/mainboard/protectli/vault/gpio.c A src/mainboard/protectli/vault/hda_verb.c A src/mainboard/protectli/vault/irqroute.c A src/mainboard/protectli/vault/irqroute.h A src/mainboard/protectli/vault/mainboard.c A src/mainboard/protectli/vault/onboard.h A src/mainboard/protectli/vault/ramstage.c A src/mainboard/protectli/vault/romstage.c A src/mainboard/protectli/vault/smihandler.c A src/mainboard/protectli/vault/variants/fw2b/devicetree.cb A src/mainboard/protectli/vault/variants/fw4b/devicetree.cb 25 files changed, 1,519 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/32076/1 diff --git a/src/mainboard/protectli/Kconfig b/src/mainboard/protectli/Kconfig new file mode 100644 index 0000000..3a1b7a4 --- /dev/null +++ b/src/mainboard/protectli/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_PROTECTLI + +choice + prompt "Mainboard model" + +source "src/mainboard/protectli/*/Kconfig.name" + +endchoice + +source "src/mainboard/protectli/*/Kconfig" + +config MAINBOARD_VENDOR + string "Mainboard Vendor" + default "Protectli" + +endif # VENDOR_PROTECTLI diff --git a/src/mainboard/protectli/Kconfig.name b/src/mainboard/protectli/Kconfig.name new file mode 100644 index 0000000..adc7f05 --- /dev/null +++ b/src/mainboard/protectli/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_PROTECTLI + bool "Protectli" diff --git a/src/mainboard/protectli/vault/Kconfig b/src/mainboard/protectli/vault/Kconfig new file mode 100644 index 0000000..d35f941 --- /dev/null +++ b/src/mainboard/protectli/vault/Kconfig @@ -0,0 +1,72 @@ +if BOARD_PROTECTLI_FW2B || BOARD_PROTECTLI_FW4B + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select SOC_INTEL_BRASWELL + select PCIEXP_L1_SUB_STATE + select CACHE_MRC_SETTINGS + select SUPERIO_ITE_IT8613E + +config MAINBOARD_DIR + string + default protectli/vault + +config VARIANT_DIR + string + default "fw2b" if BOARD_PROTECTLI_FW2B + default "fw4b" if BOARD_PROTECTLI_FW4B + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config MAINBOARD_PART_NUMBER + string + default "FW2B" if BOARD_PROTECTLI_FW2B + default "FW4B" if BOARD_PROTECTLI_FW4B + +config MAINBOARD_VENDOR + string + default "Protectli" + +config DIMM_MAX + int + default 1 + +config DIMM_SPD_SIZE + int + default 256 + +config MAX_CPUS + int + default 2 if BOARD_PROTECTLI_FW2B + default 4 if BOARD_PROTECTLI_FW4B + +config PXE_ROM_ID + string + default "8086,1539" if BOARD_PROTECTLI_FW2B + default "8086,157b" if BOARD_PROTECTLI_FW4B + +if !RUN_FSP_GOP +config VGA_BIOS_FILE + string + default "3rdparty/blobs/mainboard/protectli/vault/vgabios.bin" + help + The C0 version of the video bios gets computed from this name + so that they can both be added. Only the correct one for the + system will be run. + +config VGA_BIOS_ID + string + default "8086,22b0" + help + The VGA_BIOS_ID for the C0 version of the video bios is hardcoded + in soc/intel/braswell/Makefile.inc as 8086,22b1 + +endif #RUN_FSP_GOP + +endif # BOARD_PROTECTLI_FW2B diff --git a/src/mainboard/protectli/vault/Kconfig.name b/src/mainboard/protectli/vault/Kconfig.name new file mode 100644 index 0000000..2255371 --- /dev/null +++ b/src/mainboard/protectli/vault/Kconfig.name @@ -0,0 +1,5 @@ +config BOARD_PROTECTLI_FW2B + bool "FW2B" + +config BOARD_PROTECTLI_FW4B + bool "FW4B" diff --git a/src/mainboard/protectli/vault/Makefile.inc b/src/mainboard/protectli/vault/Makefile.inc new file mode 100644 index 0000000..507941d --- /dev/null +++ b/src/mainboard/protectli/vault/Makefile.inc @@ -0,0 +1,25 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2015 Intel Corp. +## Copyright (C) 2016 Andreas Galauner <andreas(a)galauner.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += boardid.c +ramstage-y += gpio.c +ramstage-y += irqroute.c +ramstage-y += ramstage.c +ramstage-y += hda_verb.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + diff --git a/src/mainboard/protectli/vault/acpi/ec.asl b/src/mainboard/protectli/vault/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/protectli/vault/acpi/ec.asl diff --git a/src/mainboard/protectli/vault/acpi/mainboard.asl b/src/mainboard/protectli/vault/acpi/mainboard.asl new file mode 100644 index 0000000..b43c757 --- /dev/null +++ b/src/mainboard/protectli/vault/acpi/mainboard.asl @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "onboard.h" + +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + Name (_UID, 1) + } +} + +Scope (\_SB.PCI0.I2C2) +{ + /* Realtek Audio Codec */ + Device (RTEK) + { + Name (_ADR, 0) // _ADR: Address + Name (_HID, AUDIO_CODEC_HID) // _HID: Hardware ID + Name (_CID, AUDIO_CODEC_CID) // _CID: Compatible ID + Name (_DDN, AUDIO_CODEC_DDN) // _DDN: DOS Device Name + Name (_UID, 1) // _UID: Unique ID + + Method(_CRS, 0x0, NotSerialized) + { + Name(SBUF,ResourceTemplate () + { + I2CSerialBus( + AUDIO_CODEC_I2C_ADDR, + ControllerInitiated, + 400000, + AddressingMode7Bit, + "\\_SB.PCI0.I2C2", + ) + GpioInt (Edge, ActiveHigh, ExclusiveAndWake, + PullNone, , "\\_SB.GPSE") + { JACK_DETECT_GPIO_INDEX } + } ) + Return (SBUF) + } + + Method (_STA) + { + Return (0xF) + } + + } +} + +Scope (\_SB.PCI0.LPEA) +{ + Name (GBUF, ResourceTemplate () + { + /* Jack Detect (index 0) */ + GpioInt (Edge, ActiveHigh, ExclusiveAndWake, PullNone,, + "\\_SB.GPSE") { JACK_DETECT_GPIO_INDEX } + }) +} + +Scope (\_SB.GPNC) +{ + Method (_AEI, 0, Serialized) // _AEI: ACPI Event Interrupts + { + Name (RBUF, ResourceTemplate () + { + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPNC") { BOARD_SCI_GPIO_INDEX } + }) + Return (RBUF) + } + + Method (_E0F, 0, NotSerialized) // _Exx: Edge-Triggered GPE + { + } +} diff --git a/src/mainboard/protectli/vault/acpi/superio.asl b/src/mainboard/protectli/vault/acpi/superio.asl new file mode 100644 index 0000000..efa9b3e --- /dev/null +++ b/src/mainboard/protectli/vault/acpi/superio.asl @@ -0,0 +1,24 @@ +#include "onboard.h" + +Device (COM1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, One) + Name (_ADR, 0) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () { + FixedIO (0x03F8, 0x08) + IRQNoFlags () {4} + }) + + Name (_PRS, ResourceTemplate () { + StartDependentFn (0, 0) { + FixedIO (0x03F8, 0x08) + IRQNoFlags () {4} + } + EndDependentFn () + }) +} diff --git a/src/mainboard/protectli/vault/acpi_tables.c b/src/mainboard/protectli/vault/acpi_tables.c new file mode 100644 index 0000000..e3275ed --- /dev/null +++ b/src/mainboard/protectli/vault/acpi_tables.c @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2017 Andreas Galauner <andreas(a)galauner.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/ioapic.h> +#include <arch/smp/mpspec.h> +#include <cbmem.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/acpi.h> +#include <soc/iomap.h> +#include <soc/nvs.h> +#include <string.h> +#include <types.h> +#include <boardid.h> +#include "onboard.h" + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset(gnvs, 0, sizeof(*gnvs)); + + acpi_init_gnvs(gnvs); + + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + gnvs->s3u1 = 1; + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* Disable DPTF */ + gnvs->dpte = 0; + + /* PMIC is configured in I2C0, hidden it from OS */ + gnvs->dev.lpss_en[LPSS_NVS_I2C1] = 0; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + current = acpi_madt_irq_overrides(current); + + return current; +} diff --git a/src/mainboard/protectli/vault/board_info.txt b/src/mainboard/protectli/vault/board_info.txt new file mode 100644 index 0000000..141a0e1 --- /dev/null +++ b/src/mainboard/protectli/vault/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Protectli +Board name: Vault +Category: sbc +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/protectli/vault/boardid.c b/src/mainboard/protectli/vault/boardid.c new file mode 100644 index 0000000..810be7e --- /dev/null +++ b/src/mainboard/protectli/vault/boardid.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright(C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2017 Andreas Galauner <andreas(a)galauner.de> + * Copyright (C) 2018 3mdeb Embedded Systems Consulting + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <stdlib.h> + +uint32_t board_id(void) +{ + MAYBE_STATIC int id = -1; + + return (uint32_t) id; +} diff --git a/src/mainboard/protectli/vault/cmos.layout b/src/mainboard/protectli/vault/cmos.layout new file mode 100644 index 0000000..ae46e10 --- /dev/null +++ b/src/mainboard/protectli/vault/cmos.layout @@ -0,0 +1,133 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2015 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/protectli/vault/dsdt.asl b/src/mainboard/protectli/vault/dsdt.asl new file mode 100644 index 0000000..c965115 --- /dev/null +++ b/src/mainboard/protectli/vault/dsdt.asl @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2017 Andreas Galauner <andreas(a)galauner.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 // OEM revision +) +{ + /* Some generic macros */ + #include <acpi/platform.asl> + + /* global NVS and variables */ + #include <acpi/globalnvs.asl> + + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <acpi/southcluster.asl> + } + } + Scope (\_SB.PCI0) + { + Device (RP03) + { + Name (_ADR, 0x001C0002) // _ADR: Address + OperationRegion(RPXX, PCI_Config, 0x00, 0x10) + } + } + + /* Chipset specific sleep states */ + #include <acpi/sleepstates.asl> + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/protectli/vault/fadt.c b/src/mainboard/protectli/vault/fadt.c new file mode 100644 index 0000000..38ccd78 --- /dev/null +++ b/src/mainboard/protectli/vault/fadt.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2017 Andreas Galauner <andreas(a)galauner.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/acpi.h> +#include <string.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + acpi_fill_in_fadt(fadt); + + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES; + + fadt->pstate_cnt = 0x80; + fadt->cst_cnt = 0x85; + fadt->p_lvl2_lat = 0x65; + fadt->p_lvl3_lat = 0x3e9; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/protectli/vault/gpio.c b/src/mainboard/protectli/vault/gpio.c new file mode 100644 index 0000000..687d93b --- /dev/null +++ b/src/mainboard/protectli/vault/gpio.c @@ -0,0 +1,265 @@ +/* + * This file is part of the coreboot project. + * + * Copyright(C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2017 Andreas Galauner <andreas(a)galauner.de> + * Copyright (C) 2019 Protectli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "irqroute.h" +#include <soc/gpio.h> +#include <stdlib.h> +#include <boardid.h> +#include "onboard.h" +#include "gpio.h" + +/* South East Community */ +static const struct soc_gpio_map gpse_gpio_map[] = { + GPIO_NC, /* 00 MF_PLT_CLK0 */ + GPIO_NC, /* 01 PWM1 */ + GPIO_NC, /* 02 MF_PLT_CLK1 */ + GPIO_INPUT_PD_20K, /* 03 MF_PLT_CLK4 */ + GPIO_NC, /* 04 MF_PLT_CLK3 */ + GPIO_NC, /* 05 PWM0*/ + GPIO_INPUT_PD_20K, /* 06 MF_PLT_CLK5 */ + GPIO_INPUT_PD_20K, /* 07 MF_PLT_CLK2 */ + GPIO_NC, /* 15 SDMMC2_D3_CD_B */ + GPIO_NC, /* 16 SDMMC1_CLK */ + GPIO_NC, /* 17 SDMMC1_D0 */ + GPIO_NC, /* 18 SDMMC2_D1 */ + GPIO_NC, /* 19 SDMMC2_CLK */ + GPIO_NC, /* 20 SDMMC1_D2 */ + GPIO_NC, /* 21 SDMMC2_D2 */ + GPIO_NC, /* 22 SDMMC2_CMD */ + GPIO_NC, /* 23 SDMMC1_CMD */ + GPIO_NC, /* 24 SDMMC1_D1 */ + GPIO_NC, /* 25 SDMMC2_D0 */ + GPIO_NC, /* 26 SDMMC1_D3_CD_B */ + GPIO_NC, /* 30 SDMMC3_D1 */ + GPIO_NC, /* 31 SDMMC3_CLK */ + GPIO_NC, /* 32 SDMMC3_D3 */ + GPIO_NC, /* 33 SDMMC3_D2 */ + GPIO_NC, /* 34 SDMMC3_CMD */ + GPIO_NC, /* 35 SDMMC3_D0 */ + NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */ + NATIVE_PU20K(1), /* 46 LPC_CLKRUNB */ + NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */ + NATIVE_PU20K(1), /* 48 LPC_FRAMEB */ + NATIVE_PD20K(1), /* 49 MF_LPC_CLKOUT1 */ + NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */ + Native_M1, /* 51 MF_LPC_CLKOUT0 */ + NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */ + GPIO_NC, /* 60 SPI1_MISO */ + GPIO_NC, /* 61 SPI1_CS0_B */ + GPIO_NC, /* 62 SPI1_CLK */ + GPIO_NC, /* 63 MMC1_D6 */ + GPIO_NC, /* 64 SPI1_MOSI */ + GPIO_NC, /* 65 MMC1_D5 */ + GPIO_NC, /* 66 SPI1_CS1_B */ + GPIO_NC, /* 67 MMC1_D4_SD_WE */ + GPIO_NC, /* 68 MMC1_D7 */ + GPIO_NC, /* 69 MMC1_RCLK */ + NATIVE_PU20K(1), /* 75 USB_OC1_B */ + NATIVE_PU20K(1), /* 76 PMU_RESETBUTTON_B */ + GPI(trig_level_low, L2, P_20K_H, non_maskable, en_rx_data, NA, NA), + /* 77 GPIO_ALERT */ + GPIO_NC, /* 78 SDMMC3_PWR_EN_B */ + NATIVE_PU20K(1), /* 79 ILB_SERIRQ */ + NATIVE_PU20K(1), /* 80 USB_OC0_B */ + GPIO_NC, /* 81 SDMMC3_CD_B */ + NATIVE_PU20K(1), /* 82 SPKR */ + NATIVE_PD20K(1), /* 83 SUSPWRDNACK */ + GPIO_NC, /* 84 SDMMC1_RCLK */ + GPIO_NC, /* 85 SDMMC3_1P8_EN */ + GPIO_END +}; + +/* South West Community */ +static const struct soc_gpio_map gpsw_gpio_map[] = { + NATIVE_PU20K(1), /* 00 FST_SPI_D2 */ + NATIVE_PU20K(1), /* 01 FST_SPI_D0 */ + NATIVE_PU20K(1), /* 02 FST_SPI_CLK */ + NATIVE_PU20K(1), /* 03 FST_SPI_D3 */ + GPO_FUNC(P_20K_H, 1), /* 04 FST_SPI_CS1_B */ + NATIVE_PU20K(1), /* 05 FST_SPI_D1 */ + NATIVE_PU20K(1), /* 06 FST_SPI_CS0_B */ + GPO_FUNC(P_5K_L, 0), /* 07 FST_SPI_CS2_B */ + GPIO_NC, /* 15 UART1_RTS_B */ + GPIO_NC, /* 16 UART1_RXD */ + GPIO_NC, /* 17 UART2_RXD */ + GPIO_NC, /* 18 UART1_CTS_B */ + GPIO_NC, /* 19 UART2_RTS_B */ + GPIO_NC, /* 20 UART1_TXD */ + GPIO_NC, /* 21 UART2_TXD */ + NATIVE_PD20K(1), /* 22 UART2_CTS_B */ + NATIVE_PD20K(2), /* 30 MF_HDA_CLK */ + NATIVE_PD20K(2), /* 31 GPIO_SW31/MF_HDA_RSTB */ + NATIVE_PD20K(2), /* 32 GPIO_SW32 /MF_HDA_SDI0 */ + NATIVE_PD20K(2), /* 33 MF_HDA_SDO */ + GPO_FUNC(P_20K_L, 1), /* 34 MF_HDA_DOCKRSTB */ + NATIVE_PD20K(2), /* 35 MF_HDA_SYNC */ + NATIVE_PD20K(2), /* 36 GPIO_SW36 MF_HDA_SDI1 */ + GPIO_INPUT_PD_20K, /* 37 MF_HDA_DOCKENB */ + NATIVE_PU1K_INVTX(1), /* 45 I2C5_SDA */ + NATIVE_PU1K(1), /* 46 I2C4_SDA */ + NATIVE_PU1K_INVTX(1), /* 47 I2C6_SDA */ + NATIVE_PU1K_INVTX(1), /* 48 I2C5_SCL */ + NATIVE_FUNC(1, P_20K_H, inv_tx_enable), /* 49 I2C_NFC_SDA */ + NATIVE_PU1K(1), /* 50 I2C4_SCL */ + NATIVE_PU1K_INVTX(1), /* 51 I2C6_SCL */ + NATIVE_FUNC(1, P_20K_H, inv_tx_enable), /* 52 I2C_NFC_SCL */ + NATIVE_PU1K_INVTX(1), /* 60 I2C1_SDA */ + NATIVE_PU1K_INVTX(1), /* 61 I2C0_SDA */ + NATIVE_PU1K_INVTX(1), /* 62 I2C2_SDA */ + NATIVE_PU1K_INVTX(1), /* 63 I2C1_SCL */ + NATIVE_PU1K_INVTX(1), /* 64 I2C3_SDA */ + NATIVE_PU1K_INVTX(1), /* 65 I2C0_SCL */ + NATIVE_PU1K_INVTX(1), /* 66 I2C2_SCL */ + NATIVE_PU1K_INVTX(1), /* 67 I2C3_SCL */ + GPIO_NC, /* 75 SATA_GP0 */ + GPIO_NC, /* 76 SATA_GP1 */ + NATIVE_PD20K(1), /* 77 SATA_LEDN */ + NATIVE_PD20K(1), /* 78 SATA_GP2 */ + NATIVE_PU20K(1), /* 79 MF_SMB_ALERTB */ + NATIVE_PD20K(1), /* 80 SATA_GP3 */ + NATIVE_PU20K(1), /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + NATIVE_PU20K(1), /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ + NATIVE_PU20K(1), /* 90 PCIE_CLKREQ0B */ + NATIVE_PU20K(1), /* 91 PCIE_CLKREQ1B */ + NATIVE_PD20K(1), /* 92 GP_SSP_2_CLK */ + NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B */ + NATIVE_PD20K(1), /* 94 GP_SSP_2_RXD */ + NATIVE_PU20K(1), /* 95 PCIE_CLKREQ3B */ + NATIVE_PD20K(1), /* 96 GP_SSP_2_FS */ + NATIVE_FUNC(1, P_20K_L, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ + GPIO_END +}; + + +/* North Community */ +static const struct soc_gpio_map gpn_gpio_map[] = { + NATIVE_PD20K(5), /* 00 GPIO_DFX0 */ + NATIVE_FUNC(5, P_20K_L, 0), /* 01 GPIO_DFX3 */ + GPO_FUNC(P_20K_H, 1), /* 02 GPIO_DFX7 */ + NATIVE_PD20K(5), /* 03 GPIO_DFX1 */ + GPO_FUNC(P_20K_H, 1), /* 04 GPIO_DFX5 */ + GPO_FUNC(P_20K_L, 1), /* 05 GPIO_DFX4 */ + NATIVE_PU20K(1), /* 06 GPIO_DFX8 */ + NATIVE_PD20K(5), /* 07 GPIO_DFX2 */ + NATIVE_PU20K(8), /* 08 GPIO_DFX6 */ + GPI(trig_edge_low, L8, P_20K_L, non_maskable, en_edge_rx_data, + UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ + GPO_FUNC(P_20K_L, 1), /* 16 SEC_GPIO_SUS10 */ + NATIVE_PD20K(1), /* 17 GPIO_SUS3 */ + GPI(trig_edge_low, L15, P_20K_H, non_maskable, en_edge_rx_data, NA, + SMI), /* 18 GPIO_SUS7 */ + NATIVE_PD20K(1), /* 19 GPIO_SUS1 */ + GPIO_INPUT_PU_20K, /* 20 GPIO_SUS5 */ + GPI(trig_edge_high, L2, P_20K_L, non_maskable, en_edge_rx_data, NA, + NA), /* 21 SEC_GPIO_SUS11 */ + NATIVE_PU20K(1), /* 22 GPIO_SUS4 */ + GPI(trig_level_high, L3, P_20K_H, non_maskable, en_rx_data, NA, NA), + /* 23 SEC_GPIO_SUS8 */ + NATIVE_PU20K(1), /* 24 GPIO_SUS2 */ + GPI(trig_edge_low, L14, P_20K_H, non_maskable, en_edge_rx_data, NA, + SCI), /* 25 GPIO_SUS6 */ + NATIVE_PU5K(1), /* 26 CX_PREQ_B */ + GPIO_INPUT_PD_20K, /* 27 SEC_GPIO_SUS9 */ + NATIVE_PU5K(1), /* 30 TRST_B */ + NATIVE_PD5K(1), /* 31 TCK */ + GPIO_SKIP, /* 32 PROCHOT_B */ + GPIO_SKIP, /* 33 SVID0_DATA */ + NATIVE_PU5K(1), /* 34 TMS */ + NATIVE_PU5K(1), /* 35 CX_PRDY_B_2 */ + Native_M1, /* 36 TDO_2 */ + NATIVE_PU5K(1), /* 37 CX_PRDY_B */ + GPIO_SKIP, /* 38 SVID0_ALERT_B */ + Native_M1, /* 39 TDO */ + GPIO_SKIP, /* 40 SVID0_CLK */ + NATIVE_PU5K(1), /* 41 TDI */ + GPIO_NC, /* 45 GP_CAMERASB05 */ + GPIO_NC, /* 46 GP_CAMERASB02 */ + GPIO_INPUT_PD_20K, /* 47 GP_CAMERASB08 */ + GPIO_NC, /* 48 GP_CAMERASB00 */ + GPIO_NC, /* 49 GP_CAMERASBO6 */ + GPIO_NC, /* 50 GP_CAMERASB10 */ + GPIO_NC, /* 51 GP_CAMERASB03 */ + GPIO_INPUT_PD_20K, /* 52 GP_CAMERASB09 */ + GPIO_NC, /* 53 GP_CAMERASB01 */ + GPIO_NC, /* 54 GP_CAMERASB07 */ + GPIO_INPUT_PD_20K, /* 55 GP_CAMERASB11 */ + GPIO_NC, /* 56 GP_CAMERASB04 */ + GPIO_OUT_HIGH, /* 60 PANEL0_BKLTEN */ + NATIVE_FUNC_TX_RX(en_edge_rx_data, 1, NA, inv_tx_enable), + /* 61 HV_DDI0_HPD */ + NATIVE_PU20K(1), /* 62 HV_DDI2_DDC_SDA */ + Native_M1, /* 63 PANEL1_BKLTCTL */ + NATIVE_FUNC_TX_RX(en_edge_rx_data, 1, NA, inv_tx_enable), + /* 64 HV_DDI1_HPD */ + GPIO_OUT_HIGH, /* 65 PANEL0_BKLTCTL */ + NATIVE_PU20K(1), /* 66 HV_DDI0_DDC_SDA */ + NATIVE_PU20K(1), /* 67 HV_DDI2_DDC_SCL */ + NATIVE_FUNC_TX_RX(en_edge_rx_data, 1, NA, inv_tx_enable), + /* 68 HV_DDI2_HPD */ + Native_M1, /* 69 PANEL1_VDDEN */ + Native_M1, /* 70 PANEL1_BKLTEN */ + NATIVE_PU20K(1), /* 71 HV_DDI0_DDC_SCL */ + GPIO_OUT_HIGH, /* 72 PANEL0_VDDEN */ + GPIO_END +}; + + +/* East Community */ +static const struct soc_gpio_map gpe_gpio_map[] = { + NATIVE_PU20K(1), /* 00 PMU_SLP_S3_B */ + NATIVE_PU20K(1), /* 01 PMU_BATLOW_B */ + NATIVE_PU20K(1), /* 02 SUS_STAT_B */ + NATIVE_PU20K(1), /* 03 PMU_SLP_S0IX_B */ + NATIVE_PD20K(1), /* 04 PMU_AC_PRESENT */ + NATIVE_PU20K(1), /* 05 PMU_PLTRST_B */ + NATIVE_PD20K(1), /* 06 PMU_SUSCLK */ + NATIVE_PU20K(1), /* 07 PMU_SLP_LAN_B */ + NATIVE_PU20K(1), /* 08 PMU_PWRBTN_B */ + NATIVE_PU20K(1), /* 09 PMU_SLP_S4_B */ + NATIVE_FUNC_TX_RX(en_rx_data << 2, 1, P_1K_H, NA), /* 10 PMU_WAKE_B */ + GPIO_NC, /* 11 PMU_WAKE_LAN_B */ + NATIVE_PD20K(1), /* 15 MF_GPIO_3 */ + GPO_FUNC(P_20K_L, 1), /* 16 MF_GPIO_7 */ + NATIVE_PU20K(1), /* 17 MF_I2C1_SCL */ + NATIVE_PD20K(1), /* 18 MF_GPIO_1 */ + GPO_FUNC(P_20K_L, 0), /* 19 MF_GPIO_5 */ + NATIVE_PU20K(1), /* 20 MF_GPIO_9 */ + NATIVE_PD20K(1), /* 21 MF_GPIO_0 */ + GPI(trig_level_low, L0, P_20K_H, NA, en_rx_data, NA, NA), + /* 22 MF_GPIO_4 */ + NATIVE_PU20K(1), /* 23 MF_GPIO_8 */ + NATIVE_PD20K(1), /* 24 MF_GPIO_2 */ + NATIVE_PD20K(1), /* 25 MF_GPIO_6 */ + NATIVE_PU20K(1), /* 26 MF_I2C1_SDA */ + GPIO_END +}; + + +static struct soc_gpio_config gpio_config = { + /* BSW */ + .north = gpn_gpio_map, + .southeast = gpse_gpio_map, + .southwest = gpsw_gpio_map, + .east = gpe_gpio_map +}; + +struct soc_gpio_config *mainboard_get_gpios(void) +{ + + return &gpio_config; +} diff --git a/src/mainboard/protectli/vault/hda_verb.c b/src/mainboard/protectli/vault/hda_verb.c new file mode 100644 index 0000000..ac10ef9 --- /dev/null +++ b/src/mainboard/protectli/vault/hda_verb.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Protectli + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[0] = {}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/protectli/vault/irqroute.c b/src/mainboard/protectli/vault/irqroute.c new file mode 100644 index 0000000..35a8fcc --- /dev/null +++ b/src/mainboard/protectli/vault/irqroute.c @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2017 Andreas Galauner <andreas(a)galauner.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "irqroute.h" + +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/protectli/vault/irqroute.h b/src/mainboard/protectli/vault/irqroute.h new file mode 100644 index 0000000..250b227 --- /dev/null +++ b/src/mainboard/protectli/vault/irqroute.h @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2019 Protectli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/irq.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> + +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, D, B, C, A), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, C, A, A) + +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, 11), \ + PIRQ_PIC(B, 5), \ + PIRQ_PIC(C, 5), \ + PIRQ_PIC(D, 11), \ + PIRQ_PIC(E, 11), \ + PIRQ_PIC(F, 5), \ + PIRQ_PIC(G, 11), \ + PIRQ_PIC(H, 11) diff --git a/src/mainboard/protectli/vault/mainboard.c b/src/mainboard/protectli/vault/mainboard.c new file mode 100644 index 0000000..87f913b --- /dev/null +++ b/src/mainboard/protectli/vault/mainboard.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Protectli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/mmio.h> +#include <device/device.h> +#include <soc/iomap.h> + +#define BIOS_CONTROL_REG 0xFC +#define BIOS_CONTROL_WPD (1 << 0) + +#define IRQEN_REG 0x88 +#define UART_IRQ4_EN 0x10 + +static void mainboard_enable(struct device *dev) +{ + volatile void *addr = (void *)(SPI_BASE_ADDRESS + BIOS_CONTROL_REG); + + /* set Bios Write Protect Disable bit to allow saving MRC cache */ + write8(addr, read8(addr) | BIOS_CONTROL_WPD); + + /* Enable COM1 IRQ4 */ + addr = (void *)(ILB_BASE_ADDRESS + IRQEN_REG); + write8(addr, read8(addr) | UART_IRQ4_EN); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/protectli/vault/onboard.h b/src/mainboard/protectli/vault/onboard.h new file mode 100644 index 0000000..81170bd --- /dev/null +++ b/src/mainboard/protectli/vault/onboard.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2017 Andreas Galauner <andreas(a)galauner.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +/* + * Calculation of gpio based irq. + * Gpio banks ordering : GPSW, GPNC, GPEC, GPSE + * Max direct irq (MAX_DIRECT_IRQ) is 114. + * Size of gpio banks are + * GPSW_SIZE = 98 + * GPNC_SIZE = 73 + * GPEC_SIZE = 27 + * GPSE_SIZE = 86 + */ + + +/* Audio: Gpio index in SW bank */ +#define JACK_DETECT_GPIO_INDEX 77 + +/* SCI: Gpio index in N bank */ +#define BOARD_SCI_GPIO_INDEX 15 + +#define SDCARD_CD 81 + +#define AUDIO_CODEC_HID "10EC5670" +#define AUDIO_CODEC_CID "10EC5670" +#define AUDIO_CODEC_DDN "RTEK Codec Controller " +#define AUDIO_CODEC_I2C_ADDR 0x1C + +#define BCRD2_PMIC_I2C_BUS 0x01 + +#endif diff --git a/src/mainboard/protectli/vault/ramstage.c b/src/mainboard/protectli/vault/ramstage.c new file mode 100644 index 0000000..4d09f71 --- /dev/null +++ b/src/mainboard/protectli/vault/ramstage.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Intel Corporation + * Copyright (C) 2017 Andreas Galauner <andreas(a)galauner.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> +#include <boardid.h> +#include "onboard.h" + +void mainboard_silicon_init_params(SILICON_INIT_UPD *params) +{ + //enable turbo mode + params->PcdTurboMode = 1; +} diff --git a/src/mainboard/protectli/vault/romstage.c b/src/mainboard/protectli/vault/romstage.c new file mode 100644 index 0000000..52260f4 --- /dev/null +++ b/src/mainboard/protectli/vault/romstage.c @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2017 Andreas Galauner <andreas(a)galauner.de> + * Copyright (C) 2019 Protectli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <device/pci_ops.h> +#include <fsp/car.h> +#include <soc/lpc.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8613e/it8613e.h> + +#define SERIAL1_DEV PNP_DEV(0x2e, IT8613E_SP1) +#define CLKIN_DEV PNP_DEV(0x2e, IT8613E_GPIO) + +/* Copy SPD data for on-board memory */ +void mainboard_fill_spd_data(struct pei_data *ps) +{ + struct spd_block blk = { + .addr_map = { 0x50 }, + }; + + get_spd_smbus(&blk); + + if (blk.spd_array[0][0] == 0) + die("No SPD present. Check DIMM!"); + + dump_spd_info(&blk); + + /* + * Set SPD and memory configuration: + * Memory type: 0=DimmInstalled, + * 1=SolderDownMemory, + * 2=DimmDisabled + */ + ps->spd_data_ch0 = blk.spd_array[0]; + ps->spd_ch0_config = 1; + ps->spd_ch1_config = 2; +} + +void car_mainboard_pre_console_init(void) +{ + ite_reg_write(CLKIN_DEV, 0x2c, 0x41); // disable K8 power seq + ite_reg_write(CLKIN_DEV, 0x2d, 0x02); // PCICLK 25MHz + ite_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); +} + +void mainboard_romstage_entry(struct romstage_params *rp) +{ + struct pei_data *ps = rp->pei_data; + + mainboard_fill_spd_data(ps); + + /* Call back into chipset code with platform values updated. */ + romstage_common(rp); + + /* + * FSP Memory Init enables built-in serial legacy port. + * Disable it and reconfigure serial port on SuperIO. + */ + pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, (u32) 0); + ite_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); +} + +void mainboard_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *memory_params) +{ + /* Update SPD data */ + memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0; + memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config; + memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config; +} diff --git a/src/mainboard/protectli/vault/smihandler.c b/src/mainboard/protectli/vault/smihandler.c new file mode 100644 index 0000000..d2cea20 --- /dev/null +++ b/src/mainboard/protectli/vault/smihandler.c @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2017 Andreas Galauner <andreas(a)galauner.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> + +#include <soc/nvs.h> +#include <soc/pm.h> +#include <soc/gpio.h> + +#include "onboard.h" + +/* The wake gpio is SUS_GPIO[0]. */ +#define WAKE_GPIO_EN SUS_GPIO_EN0 + +int mainboard_io_trap_handler(int smif) +{ + switch (smif) { + case 0x99: + printk(BIOS_DEBUG, "Sample\n"); + smm_get_gnvs()->smif = 0; + break; + default: + return 0; + } + + /* + * On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + //gnvs->smif = 0; + return 1; +} + +/* + * The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that + * this includes the enable bits in the lower 16 bits. + */ +void mainboard_smi_gpi(uint32_t alt_gpio_smi) +{ +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + if (alt_gpio_smi & (1 << EC_SMI_GPI)) { + /* Process all pending events */ + while (mainboard_smi_ec() != 0) + ; + } +#endif +} + +void mainboard_smi_sleep(uint8_t slp_typ) +{ + /* Disable USB charging if required */ + switch (slp_typ) { + case ACPI_S3: + /* Enable wake pin in GPE block. */ + enable_gpe(WAKE_GPIO_EN); + break; + case ACPI_S5: + break; + } + +} + +int mainboard_smi_apmc(uint8_t apmc) +{ + switch (apmc) { + case APM_CNT_ACPI_ENABLE: + break; + case APM_CNT_ACPI_DISABLE: + break; + } + return 0; +} diff --git a/src/mainboard/protectli/vault/variants/fw2b/devicetree.cb b/src/mainboard/protectli/vault/variants/fw2b/devicetree.cb new file mode 100644 index 0000000..d9fd57e --- /dev/null +++ b/src/mainboard/protectli/vault/variants/fw2b/devicetree.cb @@ -0,0 +1,151 @@ +chip soc/intel/braswell + + ############################################################ + # Set the parameters for MemoryInit + ############################################################ + + register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB + + register "PcdMrcInitMmioSize" = "0x0800" + register "PcdMrcInitSpdAddr1" = "0xa0" + register "PcdMrcInitSpdAddr2" = "0xa2" + register "PcdIgdDvmt50PreAlloc" = "1" + register "PcdApertureSize" = "2" + register "PcdGttSize" = "1" + register "PcdDvfsEnable" = "0" + register "PcdCaMirrorEn" = "1" + + ############################################################ + # Set the parameters for SiliconInit + ############################################################ + + register "PcdSdcardMode" = "PCH_DISABLED" + register "PcdEnableHsuart0" = "0" + register "PcdEnableHsuart1" = "0" + register "PcdEnableAzalia" = "1" + register "PcdEnableXhci" = "1" + register "PcdEnableLpe" = "1" + register "PcdEnableDma0" = "1" + register "PcdEnableDma1" = "1" + register "PcdEnableI2C0" = "1" + register "PcdEnableI2C1" = "1" + register "PcdEnableI2C2" = "0" + register "PcdEnableI2C3" = "0" + register "PcdEnableI2C4" = "0" + register "PcdEnableI2C5" = "0" + register "PcdEnableI2C6" = "0" + register "PunitPwrConfigDisable" = "0" # Enable SVID + register "ChvSvidConfig" = "3" + register "PcdEmmcMode" = "PCH_DISABLED" + register "PcdUsb3ClkSsc" = "1" + register "PcdDispClkSsc" = "1" + register "PcdSataClkSsc" = "1" + register "PcdEnableSata" = "1" + register "Usb2Port0PerPortPeTxiSet" = "7" + register "Usb2Port0PerPortTxiSet" = "6" + register "Usb2Port0IUsbTxEmphasisEn" = "3" + register "Usb2Port0PerPortTxPeHalf" = "1" + register "Usb2Port1PerPortPeTxiSet" = "7" + register "Usb2Port1PerPortTxiSet" = "6" + register "Usb2Port1IUsbTxEmphasisEn" = "3" + register "Usb2Port1PerPortTxPeHalf" = "1" + register "Usb2Port2PerPortPeTxiSet" = "7" + register "Usb2Port2PerPortTxiSet" = "6" + register "Usb2Port2IUsbTxEmphasisEn" = "3" + register "Usb2Port2PerPortTxPeHalf" = "1" + register "Usb2Port3PerPortPeTxiSet" = "7" + register "Usb2Port3PerPortTxiSet" = "6" + register "Usb2Port3IUsbTxEmphasisEn" = "3" + register "Usb2Port3PerPortTxPeHalf" = "1" + register "Usb2Port4PerPortPeTxiSet" = "7" + register "Usb2Port4PerPortTxiSet" = "6" + register "Usb2Port4IUsbTxEmphasisEn" = "3" + register "Usb2Port4PerPortTxPeHalf" = "1" + register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a" + register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" + register "PcdSataInterfaceSpeed" = "3" + register "PcdPchSsicEnable" = "0" + register "PcdPchUsbSsicPort" = "0" + register "PcdPchUsbHsicPort" = "0" + register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM + register "PMIC_I2CBus" = "0" + register "ISPEnable" = "0" # Disable IUNIT + register "ISPPciDevConfig" = "3" + register "PcdSdDetectChk" = "0" # Disable SD card detect + # Follow Intel recommendation to set BSW D-stepping PERPORTRXISET 2 (low strength) + register "D0Usb2Port0PerPortRXISet" = "2" + register "D0Usb2Port1PerPortRXISet" = "2" + register "D0Usb2Port2PerPortRXISet" = "2" + register "D0Usb2Port3PerPortRXISet" = "2" + register "D0Usb2Port4PerPortRXISet" = "2" + + # LPE audio codec settings + register "lpe_codec_clk_src" = "LPE_CLK_SRC_PLL" # 19.2MHz clock + + # Disable devices in ACPI mode + register "lpss_acpi_mode" = "0" + register "emmc_acpi_mode" = "0" + register "sd_acpi_mode" = "0" + register "lpe_acpi_mode" = "0" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # 8086 2280 - SoC transaction router + device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display + device pci 03.0 off end # 8086 22b8 - Camera and Image Processor + device pci 0b.0 off end # 8086 22dc - PUNIT/DPTF + device pci 10.0 off end # 8086 2294 - MMC Port + device pci 12.0 off end # 8086 2296 - SD Port + device pci 13.0 on end # 8086 22a3 - Sata controller + device pci 14.0 on end # 8086 22b5 - USB XHCI + device pci 15.0 on end # 8086 22a8 - LP Engine Audio + device pci 16.0 off end # 8086 22b7 - USB device + device pci 18.0 on end # 8086 22c0 - SIO - DMA + device pci 18.1 on end # 8086 22c1 - I2C Port 1 + device pci 18.2 on end # 8086 22c2 - I2C Port 2 + device pci 18.3 off end # 8086 22c3 - I2C Port 3 + device pci 18.4 off end # 8086 22c4 - I2C Port 4 + device pci 18.5 off end # 8086 22c5 - I2C Port 5 + device pci 18.6 off end # 8086 22c6 - I2C Port 6 + device pci 18.7 off end # 8086 22c7 - I2C Port 7 + device pci 1a.0 on end # 8086 2298 - Trusted Execution Engine + device pci 1b.0 on end # 8086 2284 - HD Audio + device pci 1c.0 on end # 8086 22c8 - PCIe Root Port 1 + device pci 1c.1 on end # 8086 22ca - PCIe Root Port 2 + device pci 1c.2 on end # 8086 22cc - PCIe Root Port 3 + device pci 1c.3 on end # 8086 22ce - PCIe Root Port 4 + device pci 1e.0 on end # 8086 2286 - SIO - DMA + device pci 1e.3 off end # 8086 228a - HSUART 1 + device pci 1e.4 off end # 8086 228c - HSUART 2 + device pci 1f.0 on # 8086 229c - LPC bridge + chip superio/ite/it8613e + device pnp 2e.0 off end + device pnp 2e.1 on # COM 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 off # Environment Controller + end + device pnp 2e.5 off # Keyboard + end + device pnp 2e.6 off # Mouse + end + device pnp 2e.7 off # GPIO + end + device pnp 2e.a off # CIR + end + end + end + device pci 1f.3 on end # 8086 2292 - SMBus 0 + end +end diff --git a/src/mainboard/protectli/vault/variants/fw4b/devicetree.cb b/src/mainboard/protectli/vault/variants/fw4b/devicetree.cb new file mode 100644 index 0000000..1fd5c0c --- /dev/null +++ b/src/mainboard/protectli/vault/variants/fw4b/devicetree.cb @@ -0,0 +1,146 @@ +chip soc/intel/braswell + + ############################################################ + # Set the parameters for MemoryInit + ############################################################ + + register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB + + register "PcdMrcInitMmioSize" = "0x0800" + register "PcdMrcInitSpdAddr1" = "0xa0" + register "PcdMrcInitSpdAddr2" = "0xa2" + register "PcdIgdDvmt50PreAlloc" = "1" + register "PcdApertureSize" = "2" + register "PcdGttSize" = "1" + register "PcdDvfsEnable" = "0" + register "PcdCaMirrorEn" = "1" + + ############################################################ + # Set the parameters for SiliconInit + ############################################################ + + register "PcdSdcardMode" = "PCH_DISABLED" + register "PcdEnableHsuart0" = "0" + register "PcdEnableHsuart1" = "0" + register "PcdEnableAzalia" = "1" + register "PcdEnableXhci" = "1" + register "PcdEnableLpe" = "1" + register "PcdEnableDma0" = "1" + register "PcdEnableDma1" = "1" + register "PcdEnableI2C0" = "1" + register "PcdEnableI2C1" = "1" + register "PcdEnableI2C2" = "0" + register "PcdEnableI2C3" = "0" + register "PcdEnableI2C4" = "0" + register "PcdEnableI2C5" = "0" + register "PcdEnableI2C6" = "0" + register "PunitPwrConfigDisable" = "0" # Enable SVID + register "ChvSvidConfig" = "3" + register "PcdEmmcMode" = "PCH_DISABLED" + register "PcdUsb3ClkSsc" = "1" + register "PcdDispClkSsc" = "1" + register "PcdSataClkSsc" = "1" + register "PcdEnableSata" = "1" + register "Usb2Port0PerPortPeTxiSet" = "7" + register "Usb2Port0PerPortTxiSet" = "6" + register "Usb2Port0IUsbTxEmphasisEn" = "3" + register "Usb2Port0PerPortTxPeHalf" = "1" + register "Usb2Port1PerPortPeTxiSet" = "7" + register "Usb2Port1PerPortTxiSet" = "6" + register "Usb2Port1IUsbTxEmphasisEn" = "3" + register "Usb2Port1PerPortTxPeHalf" = "1" + register "Usb2Port2PerPortPeTxiSet" = "7" + register "Usb2Port2PerPortTxiSet" = "6" + register "Usb2Port2IUsbTxEmphasisEn" = "3" + register "Usb2Port2PerPortTxPeHalf" = "1" + register "Usb2Port3PerPortPeTxiSet" = "7" + register "Usb2Port3PerPortTxiSet" = "6" + register "Usb2Port3IUsbTxEmphasisEn" = "3" + register "Usb2Port3PerPortTxPeHalf" = "1" + register "Usb2Port4PerPortPeTxiSet" = "7" + register "Usb2Port4PerPortTxiSet" = "6" + register "Usb2Port4IUsbTxEmphasisEn" = "3" + register "Usb2Port4PerPortTxPeHalf" = "1" + register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a" + register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" + register "PcdSataInterfaceSpeed" = "3" + register "PcdPchSsicEnable" = "0" + register "PcdPchUsbSsicPort" = "0" + register "PcdPchUsbHsicPort" = "0" + register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM + register "PMIC_I2CBus" = "0" + register "ISPEnable" = "0" # Disable IUNIT + register "ISPPciDevConfig" = "3" + register "PcdSdDetectChk" = "0" # Disable SD card detect + register "DptfDisable" = "1" + + # LPE audio codec settings + register "lpe_codec_clk_src" = "LPE_CLK_SRC_PLL" # 19.2MHz clock + + # Disable devices in ACPI mode + register "lpss_acpi_mode" = "0" + register "emmc_acpi_mode" = "0" + register "sd_acpi_mode" = "0" + register "lpe_acpi_mode" = "0" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # 8086 2280 - SoC transaction router + device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display + device pci 03.0 off end # 8086 22b8 - Camera and Image Processor + device pci 0b.0 off end # 8086 22dc - PUNIT/DPTF + device pci 10.0 off end # 8086 2294 - MMC Port + device pci 12.0 off end # 8086 2296 - SD Port + device pci 13.0 on end # 8086 22a3 - Sata controller + device pci 14.0 on end # 8086 22b5 - USB XHCI + device pci 15.0 on end # 8086 22a8 - LP Engine Audio + device pci 16.0 off end # 8086 22b7 - USB device + device pci 18.0 on end # 8086 22c0 - SIO - DMA + device pci 18.1 on end # 8086 22c1 - I2C Port 1 + device pci 18.2 on end # 8086 22c2 - I2C Port 2 + device pci 18.3 off end # 8086 22c3 - I2C Port 3 + device pci 18.4 off end # 8086 22c4 - I2C Port 4 + device pci 18.5 off end # 8086 22c5 - I2C Port 5 + device pci 18.6 off end # 8086 22c6 - I2C Port 6 + device pci 18.7 off end # 8086 22c7 - I2C Port 7 + device pci 1a.0 on end # 8086 2298 - Trusted Execution Engine + device pci 1b.0 on end # 8086 2284 - HD Audio + device pci 1c.0 on end # 8086 22c8 - PCIe Root Port 1 + device pci 1c.1 on end # 8086 22ca - PCIe Root Port 2 + device pci 1c.2 on end # 8086 22cc - PCIe Root Port 3 + device pci 1c.3 on end # 8086 22ce - PCIe Root Port 4 + device pci 1e.0 on end # 8086 2286 - SIO - DMA + device pci 1e.3 off end # 8086 228a - HSUART 1 + device pci 1e.4 off end # 8086 228c - HSUART 2 + device pci 1f.0 on # 8086 229c - LPC bridge + chip superio/ite/it8613e + device pnp 2e.0 off end + device pnp 2e.1 on # COM 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 off # Environment Controller + end + device pnp 2e.5 off # Keyboard + end + device pnp 2e.6 off # Mouse + end + device pnp 2e.7 off # GPIO + end + device pnp 2e.a off # CIR + end + end + end + device pci 1f.3 on end # 8086 2292 - SMBus 0 + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/32076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I553fd3a89299314a855f055014ca7645100e12e7 Gerrit-Change-Number: 32076 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

8 51

Change in ...coreboot[master]: soc/intel/denverton_ns: Allow using FSP repo
by Felix Singer (Code Review) 04 Mar '20

04 Mar '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30931 Change subject: soc/intel/denverton_ns: Allow using FSP repo ...................................................................... soc/intel/denverton_ns: Allow using FSP repo Change-Id: I615305da5865bef305f560f5c90482cf0937b25a Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/denverton_ns/Kconfig 2 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/30931/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 8156d18..6f5ed2a 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -85,7 +85,8 @@ bool "Use the IntelFSP based binaries" depends on ADD_FSP_BINARIES depends on SOC_INTEL_APOLLOLAKE || SOC_INTEL_SKYLAKE || \ - SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE + SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE || \ + SOC_INTEL_DENVERTON_NS help When selecting this option, the SoC must set FSP_HEADER_PATH and FSP_FD_PATH correctly so FSP splitting works. diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 1096549..dfb5c37 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -78,6 +78,16 @@ help The memory location of the Intel FSP-S binary for this platform. +config FSP_HEADER_PATH + string "Location of FSP headers" + depends on MAINBOARD_USES_FSP2_0 + default "3rdparty/fsp/DenvertonNSFspBinPkg/Include/" + +config FSP_FD_PATH + string + depends on FSP_USE_REPO + default "3rdparty/fsp/DenvertonNSFspBinPkg/FspBin/DenvertonNSFsp.fd" + # CAR memory layout on DENVERTON_NS hardware: ## CAR base address - 0xfef00000 ## CAR size 1MB - 0x100 (0xfff00) -- To view, visit https://review.coreboot.org/c/coreboot/+/30931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I615305da5865bef305f560f5c90482cf0937b25a Gerrit-Change-Number: 30931 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

8 23

Change in ...coreboot[master]: README: Spell Web site with one space
by Paul Menzel (Code Review) 03 Mar '20

03 Mar '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31384 Change subject: README: Spell Web site with one space ...................................................................... README: Spell Web site with one space Change-Id: I4119ae6df01dbafb60b2a132c887844739839de6 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M payloads/libpayload/README 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/31384/1 diff --git a/payloads/libpayload/README b/payloads/libpayload/README index fdf9b18..7348934 100644 --- a/payloads/libpayload/README +++ b/payloads/libpayload/README @@ -49,10 +49,10 @@ Please see the sample/ directory for details. -Website and Mailing List +Web site and Mailing List ------------------------ -The main website is https://www.coreboot.org/Libpayload. +The main web site is https://www.coreboot.org/Libpayload. For additional information, patches, and discussions, please join the coreboot mailing list at https://www.coreboot.org/Mailinglist, where most -- To view, visit https://review.coreboot.org/c/coreboot/+/31384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4119ae6df01dbafb60b2a132c887844739839de6 Gerrit-Change-Number: 31384 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/chromeos: Add unzip as a dependency
by Mete Balci (Code Review) 03 Mar '20

03 Mar '20

Mete Balci has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31821 Change subject: util/chromeos: Add unzip as a dependency ...................................................................... util/chromeos: Add unzip as a dependency unzip might not be installed by default, so it is added as a dependency in crosfirmware script. Change-Id: I420067b3e8ed26e6a7dccb863aae1272a3c7acbc Signed-off-by: Mete Balci <metebalci(a)gmail.com> --- M util/chromeos/crosfirmware.sh 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/31821/1 diff --git a/util/chromeos/crosfirmware.sh b/util/chromeos/crosfirmware.sh index 9d2ca84..0564106 100755 --- a/util/chromeos/crosfirmware.sh +++ b/util/chromeos/crosfirmware.sh @@ -37,6 +37,7 @@ exit_if_uninstalled "debugfs" "e2fsprogs" exit_if_uninstalled "parted" "parted" exit_if_uninstalled "curl" "curl" + exit_if_uninstalled "unzip" "unzip" } get_inventory() -- To view, visit https://review.coreboot.org/c/coreboot/+/31821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I420067b3e8ed26e6a7dccb863aae1272a3c7acbc Gerrit-Change-Number: 31821 Gerrit-PatchSet: 1 Gerrit-Owner: Mete Balci <metebalci(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: clang-format: set to 80 chars per line
by Philipp Deppenwiese (Code Review) 03 Mar '20

03 Mar '20

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31947 Change subject: clang-format: set to 80 chars per line ...................................................................... clang-format: set to 80 chars per line Change-Id: If785ff5eb5cbadab92b0c2fed67a202b6d0ed5d4 Signed-off-by: zaolin <zaolin.daisuki(a)gmail.com> --- M .clang-format 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/31947/1 diff --git a/.clang-format b/.clang-format index d853f50..c292e2f 100644 --- a/.clang-format +++ b/.clang-format @@ -7,7 +7,7 @@ IndentCaseLabels: false SortIncludes: false ContinuationIndentWidth: 8 -ColumnLimit: 0 +ColumnLimit: 80 AlwaysBreakBeforeMultilineStrings: true AllowShortLoopsOnASingleLine: false AllowShortFunctionsOnASingleLine: false -- To view, visit https://review.coreboot.org/c/coreboot/+/31947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If785ff5eb5cbadab92b0c2fed67a202b6d0ed5d4 Gerrit-Change-Number: 31947 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: x86/acpi_s3: Remove trailing dots from debug message
by Paul Menzel (Code Review) 02 Mar '20

02 Mar '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30806 Change subject: x86/acpi_s3: Remove trailing dots from debug message ...................................................................... x86/acpi_s3: Remove trailing dots from debug message The dot is not needed, as it is no sentence and followed by a line break. Change-Id: I3905853eb7039f9c6d2486a77da47a4460276624 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/arch/x86/acpi_s3.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/30806/1 diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index ad9fe00..07c0332 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -34,10 +34,10 @@ { if (acpi_slp_type < 0) { if (romstage_handoff_is_resume()) { - printk(BIOS_DEBUG, "S3 Resume.\n"); + printk(BIOS_DEBUG, "S3 Resume\n"); acpi_slp_type = ACPI_S3; } else { - printk(BIOS_DEBUG, "Normal boot.\n"); + printk(BIOS_DEBUG, "Normal boot\n"); acpi_slp_type = ACPI_S0; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/30806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3905853eb7039f9c6d2486a77da47a4460276624 Gerrit-Change-Number: 30806 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/lenovo/x1_carbon_gen1: Swap Fn-F2 and Fn-F3
by Nicola Corna (Code Review) 17 Feb '20

17 Feb '20

Nicola Corna has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31470 Change subject: mb/lenovo/x1_carbon_gen1: Swap Fn-F2 and Fn-F3 ...................................................................... mb/lenovo/x1_carbon_gen1: Swap Fn-F2 and Fn-F3 thinkpad_acpi expects the battery hotkey (KEY_BATTERY) on scancode 0x01 (Fn-F2) and the lock hotkey (KEY_COFFEE) on scancode 0x02 (Fn-F3). This is true for most of the Thinkpads, however on the X1 Carbon Gen1 (and possibly others), the battery hotkey is not present and the lock one is instead on Fn-F3. Swap the RHK calls in _Q11 (Fn-F2) and _Q12 (Fn-F3) to fix the issue, so that the lock hotkey is on F3 and the battery one is on F2 (even if it's not marked so). Change-Id: Ib2d96be1a7815d7d03e6e8c6d300fd671c8598ca Signed-off-by: Nicola Corna <nicola(a)corna.info> --- M src/ec/lenovo/h8/acpi/ec.asl M src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/31470/1 diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index 327a2cf..6ffba5e 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -197,12 +197,20 @@ Method (_Q11, 0, NotSerialized) { +#if IS_ENABLED(EC_LENOVO_H8_SWAP_FNF2_FNF3) + ^HKEY.RHK (0x03) +#else ^HKEY.RHK (0x02) +#endif } Method (_Q12, 0, NotSerialized) { +#if IS_ENABLED(EC_LENOVO_H8_SWAP_FNF2_FNF3) + ^HKEY.RHK (0x02) +#else ^HKEY.RHK (0x03) +#endif } Method (_Q64, 0, NotSerialized) diff --git a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl index 8c9bd5a..2696607 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl +++ b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl @@ -20,6 +20,7 @@ #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 +#define EC_LENOVO_H8_SWAP_FNF2_FNF3 1 #include <arch/acpi.h> DefinitionBlock( -- To view, visit https://review.coreboot.org/c/coreboot/+/31470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2d96be1a7815d7d03e6e8c6d300fd671c8598ca Gerrit-Change-Number: 31470 Gerrit-PatchSet: 1 Gerrit-Owner: Nicola Corna <nicola(a)corna.info> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: intel/apollolake: Add early smbus support
by Christian Gmeiner (Code Review) 08 Feb '20

08 Feb '20

Christian Gmeiner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31461 Change subject: intel/apollolake: Add early smbus support ...................................................................... intel/apollolake: Add early smbus support Change-Id: Ic472c71998064d09c9caddc5c80c01e85a381c69 Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/apollolake/include/soc/smbus.h 3 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/31461/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 19cd296..f7ddc6f 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -85,6 +85,7 @@ select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_P2SB select SOC_INTEL_COMMON_BLOCK_PMC + select SOC_INTEL_COMMON_BLOCK_SMBUS select SOC_INTEL_COMMON_BLOCK_SRAM select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_SA diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index cf3e839..99a9467 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -23,6 +23,7 @@ #include <intelblocks/p2sb.h> #include <intelblocks/pcr.h> #include <intelblocks/rtc.h> +#include <intelblocks/smbus.h> #include <intelblocks/systemagent.h> #include <intelblocks/pmclib.h> #include <intelblocks/tco.h> @@ -112,6 +113,9 @@ /* Program TCO Timer Halt */ tco_configure(); + /* Program SMBUS_BASE_ADDRESS and Enable it */ + smbus_common_init(); + /* Use Nx and paging to prevent the frontend from writing back dirty * cache-as-ram lines to backing store that doesn't exist when the L1I * speculatively fetches a line that is sitting in the L1D. */ diff --git a/src/soc/intel/apollolake/include/soc/smbus.h b/src/soc/intel/apollolake/include/soc/smbus.h index 4b252d6..a4ff451 100644 --- a/src/soc/intel/apollolake/include/soc/smbus.h +++ b/src/soc/intel/apollolake/include/soc/smbus.h @@ -16,6 +16,9 @@ #ifndef _SOC_APOLLOLAKE_SMBUS_H_ #define _SOC_APOLLOLAKE_SMBUS_H_ +/* PCI Configuration Space (D31:F3): SMBus */ +#define SMB_RCV_SLVA 0x09 + /* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ #define TCO1_STS 0x04 #define TCO_TIMEOUT (1 << 3) @@ -25,4 +28,7 @@ #define TCO_LOCK (1 << 12) #define TCO_TMR_HLT (1 << 11) +/* SMBus I/O bits. */ +#define SMBUS_SLAVE_ADDR 0x24 + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic472c71998064d09c9caddc5c80c01e85a381c69 Gerrit-Change-Number: 31461 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Gmeiner <christian.gmeiner(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: superio/nsc: Use common defines for NSC PC8xxxx chips
by Peter Lemenkov (Code Review) 24 Jan '20

24 Jan '20

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31427 Change subject: superio/nsc: Use common defines for NSC PC8xxxx chips ...................................................................... superio/nsc: Use common defines for NSC PC8xxxx chips * Some common NSC defines moved to superio/nsc/common * All NSC's pc8xxxx chips uses these common definitions * Lenovo T60/X60/Z61t/T400 docking updated to use these common defines * HP ProLiant DL165 G6 Fam10 updated to use this common code Build tested - Lenovo T60/X60/Z61t/T400, HP ProLiant DL165 G6 Fam10 builds fine. Change-Id: Iffdb4752f3075b1a1b391d4cf8d4416748bfe485 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/hp/dl165_g6_fam10/romstage.c M src/mainboard/lenovo/t400/dock.c M src/mainboard/lenovo/t60/dock.c M src/mainboard/lenovo/x60/dock.c M src/mainboard/lenovo/z61t/dock.c A src/superio/nsc/common/superio_defs.h D src/superio/nsc/pc87309/pc87309.h M src/superio/nsc/pc87309/superio.c D src/superio/nsc/pc87360/pc87360.h M src/superio/nsc/pc87360/superio.c D src/superio/nsc/pc87366/pc87366.h M src/superio/nsc/pc87366/superio.c D src/superio/nsc/pc87382/pc87382.h M src/superio/nsc/pc87382/superio.c D src/superio/nsc/pc87384/pc87384.h M src/superio/nsc/pc87384/superio.c D src/superio/nsc/pc87392/pc87392.h M src/superio/nsc/pc87392/superio.c M src/superio/nsc/pc87417/pc87417.h M src/superio/nsc/pc87417/superio.c 20 files changed, 219 insertions(+), 369 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/31427/1 diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 6d2eed4..7f5411e 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -34,6 +34,7 @@ #include <spd.h> #include <delay.h> #include <superio/serverengines/pilot/pilot.h> +#include <superio/nsc/common/superio_defs.h> #include <superio/nsc/pc87417/pc87417.h> #include <cpu/x86/bist.h> #include <cpu/amd/car.h> @@ -50,7 +51,7 @@ #include "cpu/amd/quadcore/quadcore.c" #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) -#define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) +#define RTC_DEV PNP_DEV(0x4e, PC8XXXX_RTC) void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); diff --git a/src/mainboard/lenovo/t400/dock.c b/src/mainboard/lenovo/t400/dock.c index 6d1a80c..58788e7 100644 --- a/src/mainboard/lenovo/t400/dock.c +++ b/src/mainboard/lenovo/t400/dock.c @@ -23,7 +23,7 @@ #include <device/pnp.h> #include <delay.h> #include "dock.h" -#include <superio/nsc/pc87382/pc87382.h> +#include <superio/nsc/common/superio_defs.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <ec/lenovo/h8/h8.h> @@ -64,8 +64,8 @@ return 0; } -static const pnp_devfn_t l_dlpc = PNP_DEV(0x164e, PC87382_DOCK); -static const pnp_devfn_t l_gpio = PNP_DEV(0x164e, PC87382_GPIO); +static const pnp_devfn_t l_dlpc = PNP_DEV(0x164e, PC8XXXX_DOCK); +static const pnp_devfn_t l_gpio = PNP_DEV(0x164e, PC8XXXX_GPIO); static int pc87382_init(pnp_devfn_t dlpc, u16 dlpc_base) { @@ -170,20 +170,18 @@ /* Docking station side. */ -#include <superio/nsc/pc87384/pc87384.h> - -static const pnp_devfn_t r_gpio = PNP_DEV(SUPERIO_DEV, PC87384_GPIO); -static const pnp_devfn_t r_serial = PNP_DEV(SUPERIO_DEV, PC87384_SP1); +static const pnp_devfn_t r_gpio = PNP_DEV(SUPERIO_DEV, PC8XXXX_GPIO); +static const pnp_devfn_t r_serial = PNP_DEV(SUPERIO_DEV, PC8XXXX_SP1); static const struct pin_config remote_gpio[] = { - {0x00, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP}, - {0x01, PC87384_GPIO_PIN_TYPE_PUSH_PULL | PC87384_GPIO_PIN_OE}, - {0x02, PC87384_GPIO_PIN_TYPE_PUSH_PULL | PC87384_GPIO_PIN_OE}, - {0x03, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP}, - {0x04, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP}, - {0x05, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP}, - {0x06, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP}, - {0x07, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP}, + {0x00, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP}, + {0x01, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | PC8XXXX_GPIO_PIN_OE}, + {0x02, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | PC8XXXX_GPIO_PIN_OE}, + {0x03, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP}, + {0x04, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP}, + {0x05, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP}, + {0x06, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP}, + {0x07, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP}, }; static int pc87384_init(void) diff --git a/src/mainboard/lenovo/t60/dock.c b/src/mainboard/lenovo/t60/dock.c index 05dd65e..57a5a00 100644 --- a/src/mainboard/lenovo/t60/dock.c +++ b/src/mainboard/lenovo/t60/dock.c @@ -18,7 +18,7 @@ #include <arch/io.h> #include <delay.h> #include "dock.h" -#include <superio/nsc/pc87384/pc87384.h> +#include <superio/nsc/common/superio_defs.h> #include "ec/acpi/ec.h" #include "ec/lenovo/pmh7/pmh7.h" #include <southbridge/intel/i82801gx/i82801gx.h> @@ -128,38 +128,38 @@ dock_write_register(0x22, 0xa9); /* enable serial port */ - dock_write_register(0x07, PC87384_SP1); + dock_write_register(0x07, PC8XXXX_SP1); dock_write_register(0x30, 0x01); - dock_write_register(0x07, PC87384_GPIO); + dock_write_register(0x07, PC8XXXX_GPIO); dock_write_register(0x60, 0x16); dock_write_register(0x61, 0x20); /* enable GPIO */ dock_write_register(0x30, 0x01); - dock_gpio_set_mode(0x00, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x00, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x01, PC87384_GPIO_PIN_TYPE_PUSH_PULL | - PC87384_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x01, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x02, PC87384_GPIO_PIN_TYPE_PUSH_PULL | - PC87384_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x02, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x03, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x03, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x04, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x04, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x05, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x05, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x06, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x06, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x07, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x07, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); /* no GPIO events enabled for PORT0 */ diff --git a/src/mainboard/lenovo/x60/dock.c b/src/mainboard/lenovo/x60/dock.c index b94d818..cf5e71d 100644 --- a/src/mainboard/lenovo/x60/dock.c +++ b/src/mainboard/lenovo/x60/dock.c @@ -20,7 +20,7 @@ #include <delay.h> #include "dock.h" #include <southbridge/intel/i82801gx/i82801gx.h> -#include <superio/nsc/pc87392/pc87392.h> +#include <superio/nsc/common/superio_defs.h> static void dlpc_write_register(int reg, int value) { @@ -165,58 +165,58 @@ dock_write_register(0x61, 0x20); /* init GPIO pins */ - dock_gpio_set_mode(0x00, PC87392_GPIO_PIN_DEBOUNCE | - PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x00, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x01, PC87392_GPIO_PIN_DEBOUNCE | - PC87392_GPIO_PIN_PULLUP, - PC87392_GPIO_PIN_TRIGGERS_SMI); + dock_gpio_set_mode(0x01, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, + PC8XXXX_GPIO_PIN_TRIGGERS_SMI); - dock_gpio_set_mode(0x02, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x03, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x04, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x05, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x06, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x07, PC87392_GPIO_PIN_PULLUP, 0x02); + dock_gpio_set_mode(0x02, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x03, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x04, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x05, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x06, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x07, PC8XXXX_GPIO_PIN_PULLUP, 0x02); - dock_gpio_set_mode(0x10, PC87392_GPIO_PIN_DEBOUNCE | - PC87392_GPIO_PIN_PULLUP, - PC87392_GPIO_PIN_TRIGGERS_SMI); + dock_gpio_set_mode(0x10, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, + PC8XXXX_GPIO_PIN_TRIGGERS_SMI); - dock_gpio_set_mode(0x11, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x12, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x13, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x14, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x15, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x16, PC87392_GPIO_PIN_PULLUP | - PC87392_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x11, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x12, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x13, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x14, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x15, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x16, PC8XXXX_GPIO_PIN_PULLUP | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x17, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x17, PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x20, PC87392_GPIO_PIN_TYPE_PUSH_PULL | - PC87392_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x20, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x21, PC87392_GPIO_PIN_TYPE_PUSH_PULL | - PC87392_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x21, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x22, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x23, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x24, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x25, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x26, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x27, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x22, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x23, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x24, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x25, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x26, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x27, PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x30, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x31, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x32, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x33, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x34, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x30, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x31, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x32, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x33, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x34, PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x35, PC87392_GPIO_PIN_PULLUP | - PC87392_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x35, PC8XXXX_GPIO_PIN_PULLUP | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x36, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x37, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x36, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x37, PC8XXXX_GPIO_PIN_PULLUP, 0x00); /* enable GPIO */ dock_write_register(0x30, 0x01); diff --git a/src/mainboard/lenovo/z61t/dock.c b/src/mainboard/lenovo/z61t/dock.c index 05dd65e..57a5a00 100644 --- a/src/mainboard/lenovo/z61t/dock.c +++ b/src/mainboard/lenovo/z61t/dock.c @@ -18,7 +18,7 @@ #include <arch/io.h> #include <delay.h> #include "dock.h" -#include <superio/nsc/pc87384/pc87384.h> +#include <superio/nsc/common/superio_defs.h> #include "ec/acpi/ec.h" #include "ec/lenovo/pmh7/pmh7.h" #include <southbridge/intel/i82801gx/i82801gx.h> @@ -128,38 +128,38 @@ dock_write_register(0x22, 0xa9); /* enable serial port */ - dock_write_register(0x07, PC87384_SP1); + dock_write_register(0x07, PC8XXXX_SP1); dock_write_register(0x30, 0x01); - dock_write_register(0x07, PC87384_GPIO); + dock_write_register(0x07, PC8XXXX_GPIO); dock_write_register(0x60, 0x16); dock_write_register(0x61, 0x20); /* enable GPIO */ dock_write_register(0x30, 0x01); - dock_gpio_set_mode(0x00, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x00, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x01, PC87384_GPIO_PIN_TYPE_PUSH_PULL | - PC87384_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x01, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x02, PC87384_GPIO_PIN_TYPE_PUSH_PULL | - PC87384_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x02, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x03, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x03, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x04, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x04, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x05, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x05, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x06, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x06, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x07, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x07, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); /* no GPIO events enabled for PORT0 */ diff --git a/src/superio/nsc/common/superio_defs.h b/src/superio/nsc/common/superio_defs.h new file mode 100644 index 0000000..cc35508 --- /dev/null +++ b/src/superio/nsc/common/superio_defs.h @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_NSC_COMMON_SUPERIO_DEFS_H +#define SUPERIO_NSC_COMMON_SUPERIO_DEFS_H + +#define PC8XXXX_FDC 0x00 /* Floppy */ +#define PC8XXXX_PP 0x01 /* Parallel port */ +#define PC8XXXX_SP2 0x02 /* COM 2 / IR */ +#define PC8XXXX_SP1 0x03 /* COM 1 */ +#define PC8XXXX_SWC 0x04 /* System wakeup control */ +//#define PC8XXXX_PM 0x04 /* Power management */ +#define PC8XXXX_KBCM 0x05 /* Mouse */ +#define PC8XXXX_KBCK 0x06 /* Keyboard */ +#define PC8XXXX_GPIO 0x07 /* General purpose IO */ +//#define PC8XXXX_HM 0x08 +#define PC8XXXX_FSD 0x08 /* Fan speed device */ +#define PC8XXXX_ACB 0x08 +#define PC8XXXX_FSCM 0x09 +#define PC8XXXX_FMC 0x09 +#define PC8XXXX_WDT 0x0A +#define PC8XXXX_GMP 0x0B +#define PC8XXXX_MIDI 0x0C +#define PC8XXXX_VLM 0x0D +#define PC8XXXX_TMS 0x0E +#define PC8XXXX_XBUS 0x0F +#define PC8XXXX_RTC 0x10 +#define PC8XXXX_MHC 0x14 +#define PC8XXXX_DOCK 0x19 + +#define PC8XXXX_GPIO_PIN_OE 0x01 +#define PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL 0x02 +#define PC8XXXX_GPIO_PIN_PULLUP 0x04 +#define PC8XXXX_GPIO_PIN_LOCK 0x08 +#define PC8XXXX_GPIO_PIN_TRIG_LEVEL 0x10 +#define PC8XXXX_GPIO_PIN_TRIG_LOW 0x20 +#define PC8XXXX_GPIO_PIN_DEBOUNCE 0x40 + +#define PC8XXXX_GPIO_PIN_TRIGGERS_IRQ 0x01 +#define PC8XXXX_GPIO_PIN_TRIGGERS_SMI 0x02 + +#endif /* SUPERIO_NSC_COMMON_SUPERIO_DEFS_H */ diff --git a/src/superio/nsc/pc87309/pc87309.h b/src/superio/nsc/pc87309/pc87309.h deleted file mode 100644 index 3b912ea..0000000 --- a/src/superio/nsc/pc87309/pc87309.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87309_H -#define SUPERIO_NSC_PC87309_H - -/* Datasheet: PC87309 SuperI/O Plug and Play Compatible Chip. */ - -#define PC87309_FDC 0x00 /* Floppy */ -#define PC87309_PP 0x01 /* Parallel port */ -#define PC87309_SP2 0x02 /* Com2 / IR */ -#define PC87309_SP1 0x03 /* Com1 */ -#define PC87309_PM 0x04 /* Power management */ -#define PC87309_KBCM 0x05 /* Mouse */ -#define PC87309_KBCK 0x06 /* Keyboard */ - -#endif /* SUPERIO_NSC_PC87309_H */ diff --git a/src/superio/nsc/pc87309/superio.c b/src/superio/nsc/pc87309/superio.c index 458c501..f63bea9 100644 --- a/src/superio/nsc/pc87309/superio.c +++ b/src/superio/nsc/pc87309/superio.c @@ -19,7 +19,7 @@ #include <device/pnp.h> #include <pc80/keyboard.h> #include <stdlib.h> -#include "pc87309.h" +#include <superio/nsc/common/superio_defs.h> static void init(struct device *dev) { @@ -28,7 +28,7 @@ return; switch (dev->path.pnp.device) { - case PC87309_KBCK: + case PC8XXXX_KBCK: pc_keyboard_init(NO_AUX_DEVICE); break; } @@ -43,14 +43,14 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87309_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87309_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87309_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, + { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, }, - { NULL, PC87309_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, /* TODO: PM. */ - { NULL, PC87309_KBCM, PNP_IRQ0, }, - { NULL, PC87309_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x7f8, }, + { NULL, PC8XXXX_KBCM, PNP_IRQ0, }, + { NULL, PC8XXXX_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x7f8, }, }; static void enable_dev(struct device *dev) diff --git a/src/superio/nsc/pc87360/pc87360.h b/src/superio/nsc/pc87360/pc87360.h deleted file mode 100644 index c969746..0000000 --- a/src/superio/nsc/pc87360/pc87360.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87360_H -#define SUPERIO_NSC_PC87360_H - -#define PC87360_FDC 0x00 /* Floppy */ -#define PC87360_PP 0x01 /* Parallel port */ -#define PC87360_SP2 0x02 /* Com2 */ -#define PC87360_SP1 0x03 /* Com1 */ -#define PC87360_SWC 0x04 -#define PC87360_KBCM 0x05 /* Mouse */ -#define PC87360_KBCK 0x06 /* Keyboard */ -#define PC87360_GPIO 0x07 -#define PC87360_ACB 0x08 -#define PC87360_FSCM 0x09 -#define PC87360_WDT 0x0A - -#endif /* SUPERIO_NSC_PC87360_H */ diff --git a/src/superio/nsc/pc87360/superio.c b/src/superio/nsc/pc87360/superio.c index cf5c7ca..85f21a2 100644 --- a/src/superio/nsc/pc87360/superio.c +++ b/src/superio/nsc/pc87360/superio.c @@ -21,7 +21,7 @@ #include <string.h> #include <pc80/keyboard.h> #include <stdlib.h> -#include "pc87360.h" +#include <superio/nsc/common/superio_defs.h> static void init(struct device *dev) { @@ -29,7 +29,7 @@ return; switch (dev->path.pnp.device) { - case PC87360_KBCK: + case PC8XXXX_KBCK: pc_keyboard_init(NO_AUX_DEVICE); break; } @@ -44,18 +44,18 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87360_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87360_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87360_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, + { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, }, - { NULL, PC87360_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, PC87360_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, - { NULL, PC87360_KBCM, PNP_IRQ0, }, - { NULL, PC87360_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, - { NULL, PC87360_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87360_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87360_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87360_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, + { NULL, PC8XXXX_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + { NULL, PC8XXXX_KBCM, PNP_IRQ0, }, + { NULL, PC8XXXX_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, + { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, }, }; static void enable_dev(struct device *dev) diff --git a/src/superio/nsc/pc87366/pc87366.h b/src/superio/nsc/pc87366/pc87366.h deleted file mode 100644 index b1df69f..0000000 --- a/src/superio/nsc/pc87366/pc87366.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87366_H -#define SUPERIO_NSC_PC87366_H - -#define PC87366_FDC 0x00 /* Floppy */ -#define PC87366_PP 0x01 /* Parallel port */ -#define PC87366_SP2 0x02 /* Com2 */ -#define PC87366_SP1 0x03 /* Com1 */ -#define PC87366_SWC 0x04 -#define PC87366_KBCM 0x05 /* Mouse */ -#define PC87366_KBCK 0x06 /* Keyboard */ -#define PC87366_GPIO 0x07 -#define PC87366_ACB 0x08 -#define PC87366_FSCM 0x09 -#define PC87366_WDT 0x0A -#define PC87366_GMP 0x0b -#define PC87366_MIDI 0x0C -#define PC87366_VLM 0x0D -#define PC87366_TMS 0x0E - -#endif /* SUPERIO_NSC_PC87366_H */ diff --git a/src/superio/nsc/pc87366/superio.c b/src/superio/nsc/pc87366/superio.c index e1cba17..60e5e23 100644 --- a/src/superio/nsc/pc87366/superio.c +++ b/src/superio/nsc/pc87366/superio.c @@ -21,7 +21,7 @@ #include <string.h> #include <pc80/keyboard.h> #include <stdlib.h> -#include "pc87366.h" +#include <superio/nsc/common/superio_defs.h> static void init(struct device *dev) { @@ -29,7 +29,7 @@ return; switch (dev->path.pnp.device) { - case PC87366_KBCK: + case PC8XXXX_KBCK: pc_keyboard_init(NO_AUX_DEVICE); break; } @@ -44,18 +44,18 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87366_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87366_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87366_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, + { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, }, - { NULL, PC87366_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, PC87366_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, - { NULL, PC87366_KBCM, PNP_IRQ0, }, - { NULL, PC87366_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, - { NULL, PC87366_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87366_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87366_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87366_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, + { NULL, PC8XXXX_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + { NULL, PC8XXXX_KBCM, PNP_IRQ0, }, + { NULL, PC8XXXX_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, + { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, }, }; static void enable_dev(struct device *dev) diff --git a/src/superio/nsc/pc87382/pc87382.h b/src/superio/nsc/pc87382/pc87382.h deleted file mode 100644 index 6826f45..0000000 --- a/src/superio/nsc/pc87382/pc87382.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87382_H -#define SUPERIO_NSC_PC87382_H - -#define PC87382_IR 0x02 -#define PC87382_SP1 0x03 -#define PC87382_GPIO 0x07 -#define PC87382_DOCK 0x19 -#endif diff --git a/src/superio/nsc/pc87382/superio.c b/src/superio/nsc/pc87382/superio.c index 688f08c..6a21f51 100644 --- a/src/superio/nsc/pc87382/superio.c +++ b/src/superio/nsc/pc87382/superio.c @@ -19,7 +19,7 @@ #include <device/pnp.h> #include <string.h> #include <stdlib.h> -#include "pc87382.h" +#include <superio/nsc/common/superio_defs.h> static void init(struct device *dev) { @@ -27,10 +27,10 @@ return; switch (dev->path.pnp.device) { - case PC87382_DOCK: + case PC8XXXX_DOCK: break; - case PC87382_GPIO: + case PC8XXXX_GPIO: break; } } @@ -44,11 +44,11 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87382_IR, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8 }, - { NULL, PC87382_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 }, - { NULL, PC87382_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0 }, - { NULL, PC87382_DOCK, PNP_IO0 | PNP_IRQ0, 0xfffe }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 }, + { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0 }, + { NULL, PC8XXXX_DOCK, PNP_IO0 | PNP_IRQ0, 0xfffe }, }; static void enable_dev(struct device *dev) diff --git a/src/superio/nsc/pc87384/pc87384.h b/src/superio/nsc/pc87384/pc87384.h deleted file mode 100644 index 2184584..0000000 --- a/src/superio/nsc/pc87384/pc87384.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87384_H -#define SUPERIO_NSC_PC87384_H - -#define PC87384_PP 0x01 -#define PC87384_SP2 0x02 -#define PC87384_SP1 0x03 -#define PC87384_GPIO 0x07 - -#define PC87384_GPIO_PIN_OE 0x01 -#define PC87384_GPIO_PIN_TYPE_PUSH_PULL 0x02 -#define PC87384_GPIO_PIN_PULLUP 0x04 -#define PC87384_GPIO_PIN_LOCK 0x08 -#define PC87384_GPIO_PIN_TRIG_LEVEL 0x10 -#define PC87384_GPIO_PIN_TRIG_LOW 0x20 -#define PC87384_GPIO_PIN_DEBOUNCE 0x40 - -#define PC87384_GPIO_PIN_TRIGGERS_IRQ 0x01 - -#endif diff --git a/src/superio/nsc/pc87384/superio.c b/src/superio/nsc/pc87384/superio.c index f34acd5..9548d2c 100644 --- a/src/superio/nsc/pc87384/superio.c +++ b/src/superio/nsc/pc87384/superio.c @@ -19,7 +19,7 @@ #include <device/pnp.h> #include <string.h> #include <stdlib.h> -#include "pc87384.h" +#include <superio/nsc/common/superio_defs.h> static struct device_operations ops = { .read_resources = pnp_read_resources, @@ -29,10 +29,10 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87384_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 }, - { NULL, PC87384_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 }, - { NULL, PC87384_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8 }, - { NULL, PC87384_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0 }, + { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 }, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8 }, + { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0 }, }; static void enable_dev(struct device *dev) diff --git a/src/superio/nsc/pc87392/pc87392.h b/src/superio/nsc/pc87392/pc87392.h deleted file mode 100644 index 5832435..0000000 --- a/src/superio/nsc/pc87392/pc87392.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87392_H -#define SUPERIO_NSC_PC87392_H - -#define PC87392_FDC 0x00 -#define PC87392_PP 0x01 -#define PC87392_SP2 0x02 -#define PC87392_SP1 0x03 -#define PC87392_GPIO 0x07 -#define PC87392_WDT 0x0A - -#define PC87392_GPIO_PIN_OE 0x01 -#define PC87392_GPIO_PIN_TYPE_PUSH_PULL 0x02 -#define PC87392_GPIO_PIN_PULLUP 0x04 -#define PC87392_GPIO_PIN_LOCK 0x08 -#define PC87392_GPIO_PIN_TRIG_LEVEL 0x10 -#define PC87392_GPIO_PIN_TRIG_LOW 0x20 -#define PC87392_GPIO_PIN_DEBOUNCE 0x40 - -#define PC87392_GPIO_PIN_TRIGGERS_IRQ 0x01 -#define PC87392_GPIO_PIN_TRIGGERS_SMI 0x02 - -#endif diff --git a/src/superio/nsc/pc87392/superio.c b/src/superio/nsc/pc87392/superio.c index edd4619..9971b5c 100644 --- a/src/superio/nsc/pc87392/superio.c +++ b/src/superio/nsc/pc87392/superio.c @@ -19,7 +19,7 @@ #include <device/pnp.h> #include <string.h> #include <stdlib.h> -#include "pc87392.h" +#include <superio/nsc/common/superio_defs.h> static void init(struct device *dev) { @@ -36,13 +36,13 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87392_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 }, - { NULL, PC87392_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 }, - { NULL, PC87392_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, + { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 }, + { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 }, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8 }, - { NULL, PC87392_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 }, - { NULL, PC87392_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8 }, - { NULL, PC87392_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 }, + { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8 }, + { NULL, PC8XXXX_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc }, }; static void enable_dev(struct device *dev) diff --git a/src/superio/nsc/pc87417/pc87417.h b/src/superio/nsc/pc87417/pc87417.h index b50a920..e6c7f79 100644 --- a/src/superio/nsc/pc87417/pc87417.h +++ b/src/superio/nsc/pc87417/pc87417.h @@ -19,17 +19,6 @@ #ifndef SUPERIO_NSC_PC87417_H #define SUPERIO_NSC_PC87417_H -#define PC87417_FDC 0x00 /* Floppy */ -#define PC87417_PP 0x01 /* Parallel Port */ -#define PC87417_SP2 0x02 /* Com2 */ -#define PC87417_SP1 0x03 /* Com1 */ -#define PC87417_SWC 0x04 /* System Wake-Up Controller (SWC) */ -#define PC87417_KBCM 0x05 /* Mouse */ -#define PC87417_KBCK 0x06 /* Keyboard */ -#define PC87417_GPIO 0x07 -#define PC87417_XBUS 0x0F -#define PC87417_RTC 0x10 - #define PC87417_GPIO_DEV PNP_DEV(0x2e, PC87417_GPIO) /* This is to get around a romcc bug */ /* #define PC87417_XBUS_DEV PNP_DEV(0x2e, PC87417_XBUS) */ diff --git a/src/superio/nsc/pc87417/superio.c b/src/superio/nsc/pc87417/superio.c index f0e0bb1..a4e8022 100644 --- a/src/superio/nsc/pc87417/superio.c +++ b/src/superio/nsc/pc87417/superio.c @@ -22,7 +22,7 @@ #include <string.h> #include <pc80/keyboard.h> #include <stdlib.h> -#include "pc87417.h" +#include <superio/nsc/common/superio_defs.h> static void init(struct device *dev) { @@ -30,7 +30,7 @@ return; switch (dev->path.pnp.device) { - case PC87417_KBCK: + case PC8XXXX_KBCK: pc_keyboard_init(NO_AUX_DEVICE); break; } @@ -45,17 +45,17 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87417_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87417_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87417_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, + { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, }, - { NULL, PC87417_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, PC87417_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, - { NULL, PC87417_KBCM, PNP_IRQ0, }, - { NULL, PC87417_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, - { NULL, PC87417_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87417_XBUS, PNP_IO0 | PNP_IRQ0, 0xffe0, }, - { NULL, PC87417_RTC, PNP_IO0 | PNP_IO1, 0xfffe, 0xfffe, }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, + { NULL, PC8XXXX_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + { NULL, PC8XXXX_KBCM, PNP_IRQ0, }, + { NULL, PC8XXXX_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, + { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_XBUS, PNP_IO0 | PNP_IRQ0, 0xffe0, }, + { NULL, PC8XXXX_RTC, PNP_IO0 | PNP_IO1, 0xfffe, 0xfffe, }, }; static void enable_dev(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/31427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffdb4752f3075b1a1b391d4cf8d4416748bfe485 Gerrit-Change-Number: 31427 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit April 2019