Change in ...coreboot[master]: arch/x86: Add option for running Romstage out of RAM
by Martin Roth (Code Review) 23 Jan '20
by Martin Roth (Code Review) 23 Jan '20
23 Jan '20
Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32414
Change subject: arch/x86: Add option for running Romstage out of RAM
......................................................................
arch/x86: Add option for running Romstage out of RAM
AMD's Picasso SOC brings up memory before releasing the X86 processor,
and jumps directly to Romstage. Add a global config option to handle
that.
TEST=None
BUG=b:130804851
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Change-Id: I678b1f74546ea30abcc655a0daed795d6cfa0034
---
M src/Kconfig
M src/arch/x86/assembly_entry.S
M src/arch/x86/memlayout.ld
3 files changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/32414/1
diff --git a/src/Kconfig b/src/Kconfig
index 62b3818..bfa0b51 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -146,6 +146,16 @@
time spent decompressing. Doesn't work for XIP stages (assume all
ARCH_X86 for now) for obvious reasons.
+config ROMSTAGE_IN_RAM
+ bool
+ depends on ARCH_X86
+ help
+ Some newer x86 processors come alive with memory enabled, and the
+ reset vector's physical address falling within DRAM. Select this
+ item to build romstage to execute in DRAM instead of XIP. Because
+ this is not a standard, the soc/ or cpu/ code must handle the reset
+ natively before jumping into the standard romstage code.
+
config COMPRESS_BOOTBLOCK
bool
help
diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S
index 4ead9ea..01c0865 100644
--- a/src/arch/x86/assembly_entry.S
+++ b/src/arch/x86/assembly_entry.S
@@ -26,6 +26,16 @@
* variables that are stage specific.
*/
.section ".text._start", "ax", @progbits
+#if ENV_ROMSTAGE && IS_ENABLED(CONFIG_ROMSTAGE_IN_RAM)
+/*
+ * Systems that run romstage in DRAM, i.e. where romstage is the first
+ * executed code, are responsible for getting the processor into protected
+ * mode, setting the stack pointer, and jumping to this location.
+ */
+.global _romstage_in_ram_continue
+_romstage_in_ram_continue:
+
+#else
.global _start
_start:
@@ -34,6 +44,7 @@
/* reset stack pointer to CAR stack */
mov $_car_stack_end, %esp
+#endif
/* clear CAR_GLOBAL area as it is not shared */
cld
diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld
index cc72552..da63b05 100644
--- a/src/arch/x86/memlayout.ld
+++ b/src/arch/x86/memlayout.ld
@@ -57,6 +57,10 @@
#endif
}
+#if ENV_ROMSTAGE && CONFIG(ROMSTAGE_IN_RAM)
+#include <soc/romstage.ld>
+#endif
+
#if ENV_BOOTBLOCK
/* Bootblock specific scripts which provide more SECTION directives. */
#include <cpu/x86/16bit/entry16.ld>
--
To view, visit https://review.coreboot.org/c/coreboot/+/32414
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I678b1f74546ea30abcc655a0daed795d6cfa0034
Gerrit-Change-Number: 32414
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-MessageType: newchange
8
40
Change in ...coreboot[master]: lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop
by mikeb mikeb (Code Review) 19 Jan '20
by mikeb mikeb (Code Review) 19 Jan '20
19 Jan '20
Hello Mike Banon,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/31450
to review the following change.
Change subject: lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop
......................................................................
lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop
Make it possible to enable CONFIG_MULTIPLE_VGA_ADAPTERS option for G505S
which is currently not used by any of coreboot-supported boards. Also
enable the discrete graphics PCI bus leading to HD 8570M (1002,6663)
or R5 M230 (1002,6665) discrete VGA and add the G505S-specific workaround
for PCI resource allocation problems to AMD AGESA vendorcode.
Based on the original patches by Hans Jürgen Kitter <eforname(a)freemail.hu>.
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
Signed-off-by: Hans Jürgen Kitter <eforname(a)freemail.hu>
Change-Id: I98793fa3b1ad8ee7d0b7962a328f7d5c1b0c2f88
---
M src/device/Kconfig
M src/mainboard/lenovo/g505s/devicetree.cb
M src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c
3 files changed, 17 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/31450/1
diff --git a/src/device/Kconfig b/src/device/Kconfig
index 33c1e5b3..5d2087e 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -247,8 +247,15 @@
Enable this option for a good compromise between security and speed.
config MULTIPLE_VGA_ADAPTERS
+ prompt "Multiple VGA Adapters"
bool
+ depends on BOARD_LENOVO_G505S
default n
+ help
+ Some motherboards may have more than one VGA adapter - for example,
+ there are versions of Lenovo G505S that have a discrete VGA adapter
+ in addition to its' integrated VGA adapter which is a part of APU.
+ Enable this option to try to initialize this discrete VGA adapter.
menu "Display"
depends on HAVE_VGA_TEXT_FRAMEBUFFER || HAVE_LINEAR_FRAMEBUFFER
diff --git a/src/mainboard/lenovo/g505s/devicetree.cb b/src/mainboard/lenovo/g505s/devicetree.cb
index 99f42d6..1f33c27 100644
--- a/src/mainboard/lenovo/g505s/devicetree.cb
+++ b/src/mainboard/lenovo/g505s/devicetree.cb
@@ -27,7 +27,7 @@
device pci 0.2 on end # IOMMU
device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX
device pci 1.1 on end # Internal Multimedia
- device pci 2.0 off end
+ device pci 2.0 on end # Discrete Graphics PCI bus 0x666X
device pci 3.0 off end
device pci 4.0 on end # PCIE MINI0
device pci 5.0 on end # PCIE MINI1
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c
index c566061..ee6d2c2 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c
@@ -437,8 +437,15 @@
RefPtr = MemPtr->ParameterListPtr;
// Memory Map/Mgt.
- // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
- RefPtr->BottomIo = 0xE0;
+ if ((IS_ENABLED(CONFIG_BOARD_LENOVO_G505S)) &&
+ (IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS))) {
+ // Set to 0xD0 instead of 0xE0 to avoid the PCI resource allocation problems
+ RefPtr->BottomIo = 0xD0;
+ }
+ else {
+ // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
+ RefPtr->BottomIo = 0xE0;
+ }
RefPtr->UmaMode = UserOptions.CfgUmaMode;
RefPtr->UmaSize = UserOptions.CfgUmaSize;
RefPtr->MemHoleRemapping = TRUE;
--
To view, visit https://review.coreboot.org/c/coreboot/+/31450
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I98793fa3b1ad8ee7d0b7962a328f7d5c1b0c2f88
Gerrit-Change-Number: 31450
Gerrit-PatchSet: 1
Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com>
Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com>
Gerrit-MessageType: newchange
7
29
Change in ...coreboot[master]: src/device/pci: Add support for discrete VGA initialization and OpROM...
by mikeb mikeb (Code Review) 05 Jan '20
by mikeb mikeb (Code Review) 05 Jan '20
05 Jan '20
Hello Mike Banon,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/31448
to review the following change.
Change subject: src/device/pci: Add support for discrete VGA initialization and OpROM loading
......................................................................
src/device/pci: Add support for discrete VGA initialization and OpROM loading
Required to make the discrete VGA working at some boards like AMD Lenovo G505S.
If CONFIG_MULTIPLE_VGA_ADAPTERS is enabled, coreboot will try to initialize the
discrete VGA and load OpROM on it. ACPI VFCT table will be created only for
discrete VGA instead of integrated, but everything seems to be working fine.
Maybe later we would find a way to make a common VFCT table for both adapters.
Based on the original patches by Hans Jürgen Kitter <eforname(a)freemail.hu>.
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
Signed-off-by: Hans Jürgen Kitter <eforname(a)freemail.hu>
Change-Id: If3269a0911e86ea07014484365c7c830485e52ec
---
M src/device/pci_device.c
M src/device/pci_rom.c
2 files changed, 68 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/31448/1
diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index 82033a6..96dec0b 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -764,7 +764,9 @@
* ROMs when coming out of an S3 resume.
*/
if (!IS_ENABLED(CONFIG_S3_VGA_ROM_RUN) && acpi_is_wakeup_s3() &&
- ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA))
+ (((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) ||
+ (IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) &&
+ ((dev->class >> 8) == PCI_CLASS_DISPLAY_OTHER))))
return 0;
if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM))
return 1;
@@ -778,25 +780,41 @@
void pci_dev_init(struct device *dev)
{
struct rom_header *rom, *ram;
+ unsigned int pci_class = (dev->class >> 8);
if (!IS_ENABLED(CONFIG_VGA_ROM_RUN))
return;
- /* Only execute VGA ROMs. */
- if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA))
- return;
+ /* Only load VGA ROMs. */
+ if (pci_class != PCI_CLASS_DISPLAY_VGA) {
+ if (!IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)) {
+ return;
+ } else if (pci_class != PCI_CLASS_DISPLAY_OTHER) {
+ return;
+ }
+ }
if (!should_load_oprom(dev))
return;
timestamp_add_now(TS_OPROM_INITIALIZE);
rom = pci_rom_probe(dev);
- if (rom == NULL)
+ if (rom == NULL) {
+ if (pci_class == PCI_CLASS_DISPLAY_VGA)
+ printk(BIOS_DEBUG, "Integrated VGA ROM probe failed\n");
+ else
+ printk(BIOS_DEBUG, "Discrete VGA ROM probe failed\n");
return;
+ }
ram = pci_rom_load(dev, rom);
- if (ram == NULL)
+ if (ram == NULL) {
+ if (pci_class == PCI_CLASS_DISPLAY_VGA)
+ printk(BIOS_DEBUG, "Integrated VGA ROM load failed\n");
+ else
+ printk(BIOS_DEBUG, "Discrete VGA ROM load failed\n");
return;
+ }
timestamp_add_now(TS_OPROM_COPY_END);
if (!should_run_oprom(dev))
@@ -804,7 +822,11 @@
run_bios(dev, (unsigned long)ram);
gfx_set_init_done(1);
- printk(BIOS_DEBUG, "VGA Option ROM was run\n");
+ if (pci_class == PCI_CLASS_DISPLAY_VGA)
+ printk(BIOS_DEBUG, "Integrated VGA Option ROM was run\n");
+ else
+ printk(BIOS_DEBUG, "Discrete VGA Option ROM was run\n");
+
timestamp_add_now(TS_OPROM_END);
}
diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c
index 82d9a30..60f9aed 100644
--- a/src/device/pci_rom.c
+++ b/src/device/pci_rom.c
@@ -179,13 +179,24 @@
/* VBIOS may be modified after oprom init so use the copy if present. */
static struct rom_header *check_initialized(struct device *dev)
{
- struct rom_header *run_rom;
+ struct rom_header *run_rom = NULL;
struct pci_data *rom_data;
if (!IS_ENABLED(CONFIG_VGA_ROM_RUN))
return NULL;
- run_rom = (struct rom_header *)(uintptr_t)PCI_VGA_RAM_IMAGE_START;
+ /* Set the start of shadow memory for this Integrated or Discrete VGA. */
+ if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) {
+ run_rom = (struct rom_header *)(uintptr_t)PCI_VGA_RAM_IMAGE_START;
+ } else if (IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)) {
+ if ((dev->class >> 8) == PCI_CLASS_DISPLAY_OTHER) {
+ run_rom = (struct rom_header *)(uintptr_t)PCI_RAM_IMAGE_START;
+ }
+ }
+
+ if (run_rom == NULL)
+ return NULL;
+
if (read_le16(&run_rom->signature) != PCI_ROM_HDR)
return NULL;
@@ -217,11 +228,22 @@
return current;
}
- printk(BIOS_DEBUG, " Copying %sVBIOS image from %p\n",
+ if (!IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)) {
+ /* Copy Integrated VGA VBIOS from CBFS to ACPI VFCT. */
+ printk(BIOS_DEBUG, " Copying %sVBIOS image from %p\n",
rom == (struct rom_header *)
(uintptr_t)PCI_VGA_RAM_IMAGE_START ?
"initialized " : "",
rom);
+ } else {
+ /* Copy Discrete VGA VBIOS from CBFS to ACPI VFCT. */
+ printk(BIOS_DEBUG, " Copying %sVBIOS image from %p\n",
+ rom == (struct rom_header *)
+ (uintptr_t)PCI_RAM_IMAGE_START ?
+ "initialized " : "",
+ rom);
+ /* TODO: do this also for Integrated VGA VBIOS. */
+ }
header->DeviceID = device->device;
header->VendorID = device->vendor;
@@ -243,8 +265,20 @@
struct rom_header *rom;
/* Only handle VGA devices */
- if ((device->class >> 8) != PCI_CLASS_DISPLAY_VGA)
- return current;
+
+ if (!IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)) {
+ if ((device->class >> 8) != PCI_CLASS_DISPLAY_VGA) {
+ return current;
+ }
+ } else {
+ /* Write ACPI VFCT only for Discrete VGA. */
+ if ((device->class >> 8) == PCI_CLASS_DISPLAY_OTHER) {
+ ;
+ } else {
+ return current;
+ }
+ /* TODO: do this also for Integrated VGA. */
+ }
/* Only handle enabled devices */
if (!device->enabled)
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If3269a0911e86ea07014484365c7c830485e52ec
Gerrit-Change-Number: 31448
Gerrit-PatchSet: 1
Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com>
Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com>
Gerrit-MessageType: newchange
7
53
Change in ...coreboot[master]: src: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 31 Dec '19
by HAOUAS Elyes (Code Review) 31 Dec '19
31 Dec '19
HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32023
Change subject: src: Use 'include <stdlib.h>' when appropriate
......................................................................
src: Use 'include <stdlib.h>' when appropriate
Change-Id: Id89751c600bad2ddb4b5aa9822adc5c5097787aa
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
M src/arch/arm/armv7/mmu.c
M src/arch/arm/cpu.c
M src/arch/arm64/armv8/mmu.c
M src/arch/arm64/fit_payload.c
M src/arch/mips/mmu.c
M src/arch/x86/acpi_device.c
M src/arch/x86/acpigen_dsm.c
M src/arch/x86/cbmem.c
M src/arch/x86/include/arch/acpigen.h
M src/arch/x86/include/arch/early_variables.h
M src/arch/x86/mmap_boot.c
M src/commonlib/fsp_relocate.c
M src/commonlib/include/commonlib/mem_pool.h
M src/commonlib/mem_pool.c
M src/commonlib/region.c
M src/commonlib/storage/bouncebuf.c
M src/commonlib/storage/bouncebuf.h
M src/commonlib/storage/sdhci.c
M src/commonlib/storage/sdhci_adma.c
M src/cpu/allwinner/a10/clock.c
M src/cpu/amd/family_10h-family_15h/fidvid.c
M src/cpu/amd/family_10h-family_15h/init_cpus.h
M src/cpu/amd/family_10h-family_15h/processor_name.c
M src/cpu/intel/haswell/finalize.c
M src/cpu/intel/model_2065x/finalize.c
M src/cpu/intel/model_206ax/finalize.c
M src/cpu/ti/am335x/gpio.c
M src/cpu/ti/am335x/uart.c
M src/cpu/x86/lapic/lapic_cpu_init.c
M src/cpu/x86/mirror_payload.c
M src/cpu/x86/mtrr/mtrr.c
M src/device/device_util.c
M src/device/i2c_bus.c
M src/device/oprom/realmode/x86.c
M src/device/oprom/yabel/vbe.c
M src/device/pci_class.c
M src/device/pnp_device.c
M src/drivers/aspeed/ast2050/ast2050.c
M src/drivers/emulation/qemu/bochs.c
M src/drivers/emulation/qemu/cirrus.c
M src/drivers/i2c/rtd2132/rtd2132.c
M src/drivers/intel/fsp1_1/stack.c
M src/drivers/intel/fsp2_0/include/fsp/info_header.h
M src/drivers/intel/gma/intel_ddi.c
M src/drivers/net/ne2k.c
M src/drivers/parade/ps8625/ps8625.c
M src/drivers/sil/3114/sil_sata.c
M src/drivers/spi/spi-generic.c
M src/drivers/spi/spi_flash.c
M src/drivers/uart/uart8250io.c
M src/drivers/vpd/vpd.c
M src/drivers/xgi/common/xgi_coreboot.c
M src/drivers/xgi/common/xgi_coreboot.h
M src/ec/compal/ene932/ec.c
M src/ec/google/chromeec/ec_lpc.c
M src/ec/google/chromeec/vstore.c
M src/ec/google/wilco/chip.c
M src/ec/google/wilco/mailbox.c
M src/ec/kontron/it8516e/ec.c
M src/ec/lenovo/h8/h8.c
M src/ec/lenovo/pmh7/pmh7.c
M src/ec/quanta/ene_kb3940q/ec.c
M src/ec/quanta/it8518/ec.c
M src/ec/roda/it8518/ec.c
M src/include/bootstate.h
M src/include/device/i2c_bus.h
M src/include/string.h
M src/lib/bootmem.c
M src/lib/cbfs.c
M src/lib/coreboot_table.c
M src/lib/fit.c
M src/lib/fit_payload.c
M src/lib/hardwaremain.c
M src/lib/imd.c
M src/lib/imd_cbmem.c
M src/lib/prog_loaders.c
M src/lib/rmodule.c
M src/lib/selfboot.c
M src/lib/thread.c
M src/mainboard/advansus/a785e-i/get_bus_conf.c
M src/mainboard/amd/bettong/BiosCallOuts.c
M src/mainboard/amd/bimini_fam10/get_bus_conf.c
M src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
M src/mainboard/amd/gardenia/BiosCallOuts.c
M src/mainboard/amd/gardenia/gpio.c
M src/mainboard/amd/inagua/BiosCallOuts.c
M src/mainboard/amd/inagua/buildOpts.c
M src/mainboard/amd/lamar/BiosCallOuts.c
M src/mainboard/amd/mahogany_fam10/get_bus_conf.c
M src/mainboard/amd/olivehill/BiosCallOuts.c
M src/mainboard/amd/olivehill/buildOpts.c
M src/mainboard/amd/olivehillplus/BiosCallOuts.c
M src/mainboard/amd/parmer/BiosCallOuts.c
M src/mainboard/amd/parmer/buildOpts.c
M src/mainboard/amd/persimmon/BiosCallOuts.c
M src/mainboard/amd/persimmon/buildOpts.c
M src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
M src/mainboard/amd/south_station/BiosCallOuts.c
M src/mainboard/amd/south_station/buildOpts.c
M src/mainboard/amd/thatcher/BiosCallOuts.c
M src/mainboard/amd/thatcher/buildOpts.c
M src/mainboard/amd/tilapia_fam10/get_bus_conf.c
M src/mainboard/amd/torpedo/BiosCallOuts.c
M src/mainboard/amd/torpedo/buildOpts.c
M src/mainboard/amd/union_station/BiosCallOuts.c
M src/mainboard/amd/union_station/buildOpts.c
M src/mainboard/asrock/e350m1/BiosCallOuts.c
M src/mainboard/asrock/e350m1/buildOpts.c
M src/mainboard/asrock/imb-a180/BiosCallOuts.c
M src/mainboard/asrock/imb-a180/buildOpts.c
M src/mainboard/asus/am1i-a/BiosCallOuts.c
M src/mainboard/asus/am1i-a/buildOpts.c
M src/mainboard/asus/f2a85-m/BiosCallOuts.c
M src/mainboard/asus/f2a85-m/buildOpts.c
M src/mainboard/asus/kcma-d8/get_bus_conf.c
M src/mainboard/asus/kfsn4-dre/get_bus_conf.c
M src/mainboard/asus/kgpe-d16/get_bus_conf.c
M src/mainboard/asus/m4a78-em/get_bus_conf.c
M src/mainboard/asus/m4a785-m/get_bus_conf.c
M src/mainboard/asus/m5a88-v/get_bus_conf.c
M src/mainboard/avalue/eax-785e/get_bus_conf.c
M src/mainboard/bap/ode_e20XX/BiosCallOuts.c
M src/mainboard/bap/ode_e20XX/buildOpts.c
M src/mainboard/bap/ode_e21XX/BiosCallOuts.c
M src/mainboard/biostar/a68n_5200/BiosCallOuts.c
M src/mainboard/biostar/a68n_5200/buildOpts.c
M src/mainboard/biostar/am1ml/BiosCallOuts.c
M src/mainboard/biostar/am1ml/buildOpts.c
M src/mainboard/cavium/cn8100_sff_evb/romstage.c
M src/mainboard/elmex/pcm205400/BiosCallOuts.c
M src/mainboard/elmex/pcm205400/buildOpts.c
M src/mainboard/emulation/qemu-i440fx/fw_cfg.c
M src/mainboard/esd/atom15/gpio.c
M src/mainboard/gigabyte/ma785gm/get_bus_conf.c
M src/mainboard/gigabyte/ma785gmt/get_bus_conf.c
M src/mainboard/gigabyte/ma78gm/get_bus_conf.c
M src/mainboard/gizmosphere/gizmo/BiosCallOuts.c
M src/mainboard/gizmosphere/gizmo/buildOpts.c
M src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c
M src/mainboard/gizmosphere/gizmo2/buildOpts.c
M src/mainboard/google/beltino/romstage.c
M src/mainboard/google/beltino/variants/mccloud/hda_verb.c
M src/mainboard/google/beltino/variants/monroe/hda_verb.c
M src/mainboard/google/beltino/variants/panther/hda_verb.c
M src/mainboard/google/beltino/variants/tricky/hda_verb.c
M src/mainboard/google/beltino/variants/zako/hda_verb.c
M src/mainboard/google/cyan/variants/banon/gpio.c
M src/mainboard/google/cyan/variants/celes/gpio.c
M src/mainboard/google/cyan/variants/cyan/gpio.c
M src/mainboard/google/cyan/variants/edgar/gpio.c
M src/mainboard/google/cyan/variants/kefka/gpio.c
M src/mainboard/google/cyan/variants/reks/gpio.c
M src/mainboard/google/cyan/variants/relm/gpio.c
M src/mainboard/google/cyan/variants/setzer/gpio.c
M src/mainboard/google/cyan/variants/terra/gpio.c
M src/mainboard/google/cyan/variants/ultima/gpio.c
M src/mainboard/google/cyan/variants/wizpig/gpio.c
M src/mainboard/google/daisy/memory.c
M src/mainboard/google/foster/pmic.c
M src/mainboard/google/gale/boardid.c
M src/mainboard/google/glados/mainboard.c
M src/mainboard/google/gru/boardid.c
M src/mainboard/google/kahlee/variants/baseboard/gpio.c
M src/mainboard/google/link/i915.c
M src/mainboard/google/link/i915io.c
M src/mainboard/google/nyan/pmic.c
M src/mainboard/google/nyan_big/boardid.c
M src/mainboard/google/nyan_big/pmic.c
M src/mainboard/google/nyan_blaze/boardid.c
M src/mainboard/google/nyan_blaze/pmic.c
M src/mainboard/google/oak/boardid.c
M src/mainboard/google/oak/sdram_configs.c
M src/mainboard/google/peach_pit/mainboard.c
M src/mainboard/google/peach_pit/memory.c
M src/mainboard/google/peach_pit/romstage.c
M src/mainboard/google/rambi/variants/banjo/gpio.c
M src/mainboard/google/rambi/variants/candy/gpio.c
M src/mainboard/google/rambi/variants/clapper/gpio.c
M src/mainboard/google/rambi/variants/enguarde/gpio.c
M src/mainboard/google/rambi/variants/glimmer/gpio.c
M src/mainboard/google/rambi/variants/gnawty/gpio.c
M src/mainboard/google/rambi/variants/heli/gpio.c
M src/mainboard/google/rambi/variants/kip/gpio.c
M src/mainboard/google/rambi/variants/ninja/gpio.c
M src/mainboard/google/rambi/variants/orco/gpio.c
M src/mainboard/google/rambi/variants/quawks/gpio.c
M src/mainboard/google/rambi/variants/rambi/gpio.c
M src/mainboard/google/rambi/variants/squawks/gpio.c
M src/mainboard/google/rambi/variants/sumo/gpio.c
M src/mainboard/google/rambi/variants/swanky/gpio.c
M src/mainboard/google/rambi/variants/winky/gpio.c
M src/mainboard/google/slippy/variants/falco/romstage.c
M src/mainboard/google/slippy/variants/leon/romstage.c
M src/mainboard/google/slippy/variants/peppy/romstage.c
M src/mainboard/google/slippy/variants/wolf/romstage.c
M src/mainboard/google/smaug/boardid.c
M src/mainboard/google/smaug/pmic.c
M src/mainboard/google/storm/boardid.c
M src/mainboard/google/urara/boardid.c
M src/mainboard/google/veyron/boardid.c
M src/mainboard/google/veyron/romstage.c
M src/mainboard/google/veyron_mickey/boardid.c
M src/mainboard/google/veyron_mickey/romstage.c
M src/mainboard/google/veyron_rialto/boardid.c
M src/mainboard/google/veyron_rialto/romstage.c
M src/mainboard/hp/abm/BiosCallOuts.c
M src/mainboard/hp/abm/buildOpts.c
M src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c
M src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c
M src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
M src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c
M src/mainboard/intel/bayleybay_fsp/gpio.c
M src/mainboard/intel/kblrvp/mainboard.c
M src/mainboard/intel/kunimitsu/mainboard.c
M src/mainboard/intel/minnowmax/gpio.c
M src/mainboard/intel/strago/gpio.c
M src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
M src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
M src/mainboard/jetway/pa78vm5/get_bus_conf.c
M src/mainboard/lenovo/g505s/BiosCallOuts.c
M src/mainboard/lenovo/g505s/buildOpts.c
M src/mainboard/lippert/frontrunner-af/BiosCallOuts.c
M src/mainboard/lippert/frontrunner-af/buildOpts.c
M src/mainboard/lippert/frontrunner-af/mainboard.c
M src/mainboard/lippert/frontrunner-af/sema.c
M src/mainboard/lippert/toucan-af/BiosCallOuts.c
M src/mainboard/lippert/toucan-af/buildOpts.c
M src/mainboard/lippert/toucan-af/mainboard.c
M src/mainboard/msi/ms7721/BiosCallOuts.c
M src/mainboard/msi/ms7721/buildOpts.c
M src/mainboard/msi/ms9652_fam10/get_bus_conf.c
M src/mainboard/opencellular/elgon/romstage.c
M src/mainboard/opencellular/rotundu/variants/rotundu/gpio.c
M src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c
M src/mainboard/pcengines/apu1/BiosCallOuts.c
M src/mainboard/pcengines/apu1/buildOpts.c
M src/mainboard/pcengines/apu2/BiosCallOuts.c
M src/mainboard/roda/rk886ex/m3885.c
M src/mainboard/roda/rk9/mainboard.c
M src/mainboard/scaleway/tagada/bmcinfo.c
M src/mainboard/siemens/mc_tcu3/gpio.c
M src/mainboard/sifive/hifive-unleashed/fixup_fdt.c
M src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c
M src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
M src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c
M src/mainboard/ti/beaglebone/leds.c
M src/mainboard/tyan/s2912_fam10/get_bus_conf.c
M src/northbridge/amd/agesa/family12/dimmSpd.c
M src/northbridge/amd/agesa/family12/northbridge.c
M src/northbridge/amd/agesa/family14/dimmSpd.c
M src/northbridge/amd/agesa/family14/northbridge.c
M src/northbridge/amd/agesa/family15tn/dimmSpd.c
M src/northbridge/amd/agesa/family16kb/dimmSpd.c
M src/northbridge/amd/amdht/comlib.h
M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
M src/northbridge/amd/amdmct/wrappers/mcti.h
M src/northbridge/amd/pi/00660F01/dimmSpd.c
M src/northbridge/intel/e7505/debug.c
M src/northbridge/intel/e7505/northbridge.c
M src/northbridge/intel/e7505/raminit.c
M src/northbridge/intel/fsp_rangeley/northbridge.c
M src/northbridge/intel/gm45/northbridge.c
M src/northbridge/intel/haswell/early_init.c
M src/northbridge/intel/haswell/finalize.c
M src/northbridge/intel/haswell/gma.c
M src/northbridge/intel/haswell/minihd.c
M src/northbridge/intel/haswell/northbridge.c
M src/northbridge/intel/i440bx/northbridge.c
M src/northbridge/intel/i440bx/raminit.c
M src/northbridge/intel/i945/early_init.c
M src/northbridge/intel/i945/northbridge.c
M src/northbridge/intel/nehalem/early_init.c
M src/northbridge/intel/nehalem/finalize.c
M src/northbridge/intel/nehalem/northbridge.c
M src/northbridge/intel/pineview/early_init.c
M src/northbridge/intel/pineview/northbridge.c
M src/northbridge/intel/sandybridge/early_init.c
M src/northbridge/intel/sandybridge/finalize.c
M src/northbridge/intel/sandybridge/northbridge.c
M src/northbridge/intel/x4x/northbridge.c
M src/northbridge/via/vx900/chrome9hd.c
M src/security/tpm/tspi/tspi.c
M src/security/tpm/tss/tcg-2.0/tss_marshaling.c
M src/security/vboot/secdata_mock.c
M src/security/vboot/secdata_tpm.c
M src/security/vboot/vboot_handoff.c
M src/soc/amd/stoneyridge/BiosCallOuts.c
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/amd/stoneyridge/sm.c
M src/soc/amd/stoneyridge/spi.c
M src/soc/cavium/cn81xx/cbmem.c
M src/soc/cavium/cn81xx/spi.c
M src/soc/imgtec/pistachio/cbmem.c
M src/soc/imgtec/pistachio/spi.c
M src/soc/intel/baytrail/cpu.c
M src/soc/intel/baytrail/gfx.c
M src/soc/intel/baytrail/ramstage.c
M src/soc/intel/baytrail/smihandler.c
M src/soc/intel/braswell/cpu.c
M src/soc/intel/braswell/ramstage.c
M src/soc/intel/braswell/smihandler.c
M src/soc/intel/broadwell/finalize.c
M src/soc/intel/broadwell/igd.c
M src/soc/intel/broadwell/me.c
M src/soc/intel/broadwell/me_status.c
M src/soc/intel/broadwell/minihd.c
M src/soc/intel/broadwell/pei_data.c
M src/soc/intel/broadwell/ramstage.c
M src/soc/intel/broadwell/romstage/cpu.c
M src/soc/intel/broadwell/romstage/power_state.c
M src/soc/intel/broadwell/romstage/systemagent.c
M src/soc/intel/broadwell/serialio.c
M src/soc/intel/broadwell/systemagent.c
M src/soc/intel/cannonlake/finalize.c
M src/soc/intel/cannonlake/memmap.c
M src/soc/intel/cannonlake/pmutil.c
M src/soc/intel/common/acpi_wake_source.c
M src/soc/intel/common/block/fast_spi/fast_spi.c
M src/soc/intel/common/block/smm/smihandler.c
M src/soc/intel/denverton_ns/csme_ie_kt.c
M src/soc/intel/denverton_ns/smihandler.c
M src/soc/intel/denverton_ns/systemagent.c
M src/soc/intel/fsp_baytrail/cpu.c
M src/soc/intel/fsp_baytrail/gfx.c
M src/soc/intel/fsp_baytrail/include/soc/i2c.h
M src/soc/intel/fsp_baytrail/ramstage.c
M src/soc/intel/fsp_baytrail/smihandler.c
M src/soc/intel/fsp_broadwell_de/cpu.c
M src/soc/intel/fsp_broadwell_de/ramstage.c
M src/soc/intel/icelake/finalize.c
M src/soc/intel/icelake/memmap.c
M src/soc/intel/icelake/pmutil.c
M src/soc/intel/skylake/finalize.c
M src/soc/intel/skylake/me.c
M src/soc/intel/skylake/memmap.c
M src/soc/intel/skylake/pei_data.c
M src/soc/intel/skylake/pmutil.c
M src/soc/mediatek/common/spi.c
M src/soc/mediatek/mt8173/ddp.c
M src/soc/mediatek/mt8173/flash_controller.c
M src/soc/mediatek/mt8173/include/soc/gpio.h
M src/soc/nvidia/tegra/i2c.c
M src/soc/nvidia/tegra124/clock.c
M src/soc/nvidia/tegra124/display.c
M src/soc/nvidia/tegra124/dma.c
M src/soc/nvidia/tegra124/dp.c
M src/soc/nvidia/tegra124/include/soc/clock.h
M src/soc/nvidia/tegra124/sdram.c
M src/soc/nvidia/tegra124/sdram_lp0.c
M src/soc/nvidia/tegra124/sor.c
M src/soc/nvidia/tegra124/spi.c
M src/soc/nvidia/tegra124/verstage.c
M src/soc/nvidia/tegra210/addressmap.c
M src/soc/nvidia/tegra210/arm_tf.c
M src/soc/nvidia/tegra210/clock.c
M src/soc/nvidia/tegra210/dc.c
M src/soc/nvidia/tegra210/dma.c
M src/soc/nvidia/tegra210/dp.c
M src/soc/nvidia/tegra210/dsi.c
M src/soc/nvidia/tegra210/include/soc/clock.h
M src/soc/nvidia/tegra210/include/soc/mipi-phy.h
M src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.c
M src/soc/nvidia/tegra210/mipi-phy.c
M src/soc/nvidia/tegra210/mipi.c
M src/soc/nvidia/tegra210/mipi_dsi.c
M src/soc/nvidia/tegra210/mmu_operations.c
M src/soc/nvidia/tegra210/sdram.c
M src/soc/nvidia/tegra210/sdram_lp0.c
M src/soc/nvidia/tegra210/sor.c
M src/soc/nvidia/tegra210/spi.c
M src/soc/qualcomm/ipq40xx/i2c.c
M src/soc/qualcomm/ipq40xx/qup.c
M src/soc/qualcomm/ipq40xx/spi.c
M src/soc/qualcomm/ipq40xx/uart.c
M src/soc/qualcomm/ipq806x/i2c.c
M src/soc/qualcomm/ipq806x/qup.c
M src/soc/qualcomm/ipq806x/spi.c
M src/soc/qualcomm/ipq806x/uart.c
M src/soc/rockchip/common/edp.c
M src/soc/rockchip/common/gpio.c
M src/soc/rockchip/common/i2c.c
M src/soc/rockchip/common/include/soc/edp.h
M src/soc/rockchip/common/pwm.c
M src/soc/rockchip/common/rk808.c
M src/soc/rockchip/common/spi.c
M src/soc/rockchip/common/vop.c
M src/soc/rockchip/rk3288/clock.c
M src/soc/rockchip/rk3288/display.c
M src/soc/rockchip/rk3288/gpio.c
M src/soc/rockchip/rk3288/hdmi.c
M src/soc/rockchip/rk3288/include/soc/hdmi.h
M src/soc/rockchip/rk3288/soc.c
M src/soc/rockchip/rk3288/tsadc.c
M src/soc/rockchip/rk3399/clock.c
M src/soc/rockchip/rk3399/display.c
M src/soc/rockchip/rk3399/gpio.c
M src/soc/rockchip/rk3399/include/soc/mipi.h
M src/soc/rockchip/rk3399/mipi.c
M src/soc/rockchip/rk3399/saradc.c
M src/soc/rockchip/rk3399/soc.c
M src/soc/rockchip/rk3399/tsadc.c
M src/soc/samsung/exynos5250/alternate_cbfs.c
M src/soc/samsung/exynos5250/clock.c
M src/soc/samsung/exynos5250/cpu.c
M src/soc/samsung/exynos5250/fb.c
M src/soc/samsung/exynos5250/spi.c
M src/soc/samsung/exynos5420/alternate_cbfs.c
M src/soc/samsung/exynos5420/clock.c
M src/soc/samsung/exynos5420/cpu.c
M src/soc/samsung/exynos5420/dp.c
M src/soc/samsung/exynos5420/dp_lowlevel.c
M src/soc/samsung/exynos5420/pinmux.c
M src/soc/samsung/exynos5420/smp.c
M src/soc/samsung/exynos5420/spi.c
M src/soc/sifive/fu540/clock.c
M src/southbridge/amd/agesa/hudson/sm.c
M src/southbridge/amd/agesa/hudson/spi.c
M src/southbridge/amd/amd8111/lpc.c
M src/southbridge/amd/cimx/sb800/smbus_spd.c
M src/southbridge/amd/cimx/sb800/spi.c
M src/southbridge/amd/pi/hudson/sm.c
M src/southbridge/amd/sb700/sm.c
M src/southbridge/amd/sb700/spi.c
M src/southbridge/amd/sb800/sm.c
M src/southbridge/intel/bd82x6x/me_status.c
M src/southbridge/intel/common/smbus.c
M src/southbridge/intel/fsp_rangeley/early_init.c
M src/southbridge/intel/i82801ix/i82801ix.c
M src/southbridge/intel/i82801jx/i82801jx.c
M src/southbridge/intel/lynxpoint/me_9.x.c
M src/southbridge/intel/lynxpoint/me_status.c
M src/southbridge/intel/lynxpoint/serialio.c
M src/southbridge/nvidia/ck804/lpc.c
M src/southbridge/nvidia/mcp55/lpc.c
M src/superio/fintek/f71805f/superio.c
M src/superio/fintek/f71808a/superio.c
M src/superio/fintek/f71859/superio.c
M src/superio/fintek/f71863fg/superio.c
M src/superio/fintek/f71869ad/superio.c
M src/superio/fintek/f71872/superio.c
M src/superio/fintek/f81216h/superio.c
M src/superio/fintek/f81865f/superio.c
M src/superio/fintek/f81866d/superio.c
M src/superio/intel/i8900/superio.c
M src/superio/ite/common/env_ctrl.c
M src/superio/ite/it8528e/superio.c
M src/superio/ite/it8623e/superio.c
M src/superio/ite/it8671f/superio.c
M src/superio/ite/it8712f/superio.c
M src/superio/ite/it8716f/superio.c
M src/superio/ite/it8718f/superio.c
M src/superio/ite/it8721f/superio.c
M src/superio/ite/it8728f/superio.c
M src/superio/ite/it8772f/superio.c
M src/superio/nsc/pc87309/superio.c
M src/superio/nsc/pc87360/superio.c
M src/superio/nsc/pc87366/superio.c
M src/superio/nsc/pc87382/superio.c
M src/superio/nsc/pc87384/superio.c
M src/superio/nsc/pc87392/superio.c
M src/superio/nsc/pc87417/superio.c
M src/superio/nsc/pc97317/superio.c
M src/superio/nuvoton/nct5104d/superio.c
M src/superio/nuvoton/nct5572d/superio.c
M src/superio/nuvoton/nct6776/superio.c
M src/superio/nuvoton/nct6779d/superio.c
M src/superio/nuvoton/nct6791d/superio.c
M src/superio/nuvoton/npcd378/superio.c
M src/superio/nuvoton/wpcm450/superio.c
M src/superio/renesas/m3885x/superio.c
M src/superio/smsc/dme1737/superio.c
M src/superio/smsc/fdc37n972/superio.c
M src/superio/smsc/kbc1100/superio.c
M src/superio/smsc/lpc47b272/superio.c
M src/superio/smsc/lpc47b397/superio.c
M src/superio/smsc/lpc47m10x/superio.c
M src/superio/smsc/lpc47m15x/superio.c
M src/superio/smsc/lpc47n207/early_serial.c
M src/superio/smsc/lpc47n217/superio.c
M src/superio/smsc/lpc47n227/superio.c
M src/superio/smsc/mec1308/superio.c
M src/superio/smsc/sch4037/superio.c
M src/superio/smsc/sio1036/superio.c
M src/superio/smsc/sio10n268/superio.c
M src/superio/smsc/smscsuperio/superio.c
M src/superio/via/vt1211/superio.c
M src/superio/winbond/w83627dhg/superio.c
M src/superio/winbond/w83627ehg/superio.c
M src/superio/winbond/w83627hf/superio.c
M src/superio/winbond/w83627uhg/superio.c
M src/superio/winbond/w83667hg-a/superio.c
M src/superio/winbond/w83697hf/superio.c
M src/superio/winbond/w83977tf/superio.c
M src/superio/winbond/wpcd376i/superio.c
494 files changed, 27 insertions(+), 485 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/32023/1
diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c
index 14f5f7a..284b222 100644
--- a/src/arch/arm/armv7/mmu.c
+++ b/src/arch/arm/armv7/mmu.c
@@ -29,12 +29,9 @@
*/
#include <assert.h>
-#include <stdlib.h>
#include <stdint.h>
#include <symbols.h>
-
#include <console/console.h>
-
#include <arch/cache.h>
#if CONFIG(ARM_LPAE)
diff --git a/src/arch/arm/cpu.c b/src/arch/arm/cpu.c
index fae1a37..0637bf6 100644
--- a/src/arch/arm/cpu.c
+++ b/src/arch/arm/cpu.c
@@ -27,7 +27,6 @@
* SUCH DAMAGE.
*
*/
-#include <stdlib.h>
#include <arch/cpu.h>
/* Return the CPU struct which is at the high memory address of the stack.
diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c
index 67dca48..bdec55c 100644
--- a/src/arch/arm64/armv8/mmu.c
+++ b/src/arch/arm64/armv8/mmu.c
@@ -28,7 +28,6 @@
*/
#include <assert.h>
-#include <stdlib.h>
#include <stdint.h>
#include <string.h>
#include <symbols.h>
diff --git a/src/arch/arm64/fit_payload.c b/src/arch/arm64/fit_payload.c
index c4bbcee..14f429b 100644
--- a/src/arch/arm64/fit_payload.c
+++ b/src/arch/arm64/fit_payload.c
@@ -15,7 +15,6 @@
#include <console/console.h>
#include <bootmem.h>
-#include <stdlib.h>
#include <program_loading.h>
#include <string.h>
#include <commonlib/compression.h>
diff --git a/src/arch/mips/mmu.c b/src/arch/mips/mmu.c
index b144fd3..2ceb2a7 100644
--- a/src/arch/mips/mmu.c
+++ b/src/arch/mips/mmu.c
@@ -18,7 +18,6 @@
#include <console/console.h>
#include <stddef.h>
#include <stdint.h>
-#include <stdlib.h>
#define MIN_PAGE_SIZE (4 * KiB)
diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c
index c57ba48..31b6038 100644
--- a/src/arch/x86/acpi_device.c
+++ b/src/arch/x86/acpi_device.c
@@ -22,6 +22,7 @@
#if CONFIG(GENERIC_GPIO_LIB)
#include <gpio.h>
#endif
+#include <stdlib.h>
#define ACPI_DP_UUID "daffd814-6eba-4d8c-8a91-bc9bbf4aa301"
#define ACPI_DP_CHILD_UUID "dbb8e3e6-5886-4ba6-8795-1319f52a966b"
diff --git a/src/arch/x86/acpigen_dsm.c b/src/arch/x86/acpigen_dsm.c
index 1aab90b..8c9cd350 100644
--- a/src/arch/x86/acpigen_dsm.c
+++ b/src/arch/x86/acpigen_dsm.c
@@ -15,7 +15,6 @@
#include <arch/acpigen.h>
#include <arch/acpigen_dsm.h>
-#include <stdlib.h>
/* ------------------- I2C HID DSM ---------------------------- */
diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c
index 648633f..abd163d 100644
--- a/src/arch/x86/cbmem.c
+++ b/src/arch/x86/cbmem.c
@@ -11,7 +11,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <cbmem.h>
#include <arch/acpi.h>
diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h
index d9379eb..84034d5 100644
--- a/src/arch/x86/include/arch/acpigen.h
+++ b/src/arch/x86/include/arch/acpigen.h
@@ -19,7 +19,6 @@
#define LIBACPI_H
#include <assert.h>
-#include <stdlib.h>
#include <stdint.h>
#include <arch/acpi.h>
#include <arch/acpi_device.h>
diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h
index 9ea1537..1a678cd 100644
--- a/src/arch/x86/include/arch/early_variables.h
+++ b/src/arch/x86/include/arch/early_variables.h
@@ -17,7 +17,6 @@
#define ARCH_EARLY_VARIABLES_H
#include <arch/symbols.h>
-#include <stdlib.h>
#if ENV_CACHE_AS_RAM && !CONFIG(NO_CAR_GLOBAL_MIGRATION)
asm(".section .car.global_data,\"w\",@nobits");
diff --git a/src/arch/x86/mmap_boot.c b/src/arch/x86/mmap_boot.c
index abfa024..98b5643 100644
--- a/src/arch/x86/mmap_boot.c
+++ b/src/arch/x86/mmap_boot.c
@@ -15,7 +15,6 @@
#include <boot_device.h>
#include <endian.h>
-#include <stdlib.h>
/* The ROM is memory mapped just below 4GiB. Form a pointer for the base. */
#define rom_base ((void *)(uintptr_t)(0x100000000ULL-CONFIG_ROM_SIZE))
diff --git a/src/commonlib/fsp_relocate.c b/src/commonlib/fsp_relocate.c
index 32e6b6d..21e1c00 100644
--- a/src/commonlib/fsp_relocate.c
+++ b/src/commonlib/fsp_relocate.c
@@ -31,7 +31,6 @@
#pragma pack(pop)
#include <commonlib/helpers.h>
-#include <stdlib.h>
#include <stdint.h>
#include <string.h>
diff --git a/src/commonlib/include/commonlib/mem_pool.h b/src/commonlib/include/commonlib/mem_pool.h
index c21fa0e..acfcaea 100644
--- a/src/commonlib/include/commonlib/mem_pool.h
+++ b/src/commonlib/include/commonlib/mem_pool.h
@@ -18,6 +18,7 @@
#include <stddef.h>
#include <stdint.h>
+#include <stdlib.h>
/*
* The memory pool allows one to allocate memory from a fixed size buffer
diff --git a/src/commonlib/mem_pool.c b/src/commonlib/mem_pool.c
index cb3e726..c97cb9a 100644
--- a/src/commonlib/mem_pool.c
+++ b/src/commonlib/mem_pool.c
@@ -15,6 +15,7 @@
#include <commonlib/helpers.h>
#include <commonlib/mem_pool.h>
+#include <stdlib.h>
void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
{
diff --git a/src/commonlib/region.c b/src/commonlib/region.c
index 541a125..e993ecd 100644
--- a/src/commonlib/region.c
+++ b/src/commonlib/region.c
@@ -16,6 +16,7 @@
#include <commonlib/helpers.h>
#include <commonlib/region.h>
#include <string.h>
+#include <stdlib.h>
static inline size_t region_end(const struct region *r)
{
diff --git a/src/commonlib/storage/bouncebuf.c b/src/commonlib/storage/bouncebuf.c
index 5d98c74..42eb01d 100644
--- a/src/commonlib/storage/bouncebuf.c
+++ b/src/commonlib/storage/bouncebuf.c
@@ -16,10 +16,12 @@
*/
#include <arch/cache.h>
+#include <commonlib/stdlib.h>
+#include <string.h>
+#include <stdlib.h>
+
#include "bouncebuf.h"
#include "storage.h"
-#include <string.h>
-#include <commonlib/stdlib.h>
static int addr_aligned(struct bounce_buffer *state)
{
diff --git a/src/commonlib/storage/bouncebuf.h b/src/commonlib/storage/bouncebuf.h
index 27d92e8..88dcced 100644
--- a/src/commonlib/storage/bouncebuf.h
+++ b/src/commonlib/storage/bouncebuf.h
@@ -20,7 +20,6 @@
#include <stddef.h>
#include <stdint.h>
-#include <stdlib.h>
/*
* GEN_BB_READ -- Data are read from the buffer eg. by DMA hardware.
diff --git a/src/commonlib/storage/sdhci.c b/src/commonlib/storage/sdhci.c
index 1370a91..737aeed 100644
--- a/src/commonlib/storage/sdhci.c
+++ b/src/commonlib/storage/sdhci.c
@@ -18,17 +18,19 @@
*/
#include <assert.h>
-#include "bouncebuf.h"
#include <commonlib/sd_mmc_ctrlr.h>
#include <commonlib/sdhci.h>
#include <commonlib/storage.h>
#include <delay.h>
#include <endian.h>
+#include <timer.h>
+#include <commonlib/stdlib.h>
+#include <stdlib.h>
+
+#include "bouncebuf.h"
#include "sdhci.h"
#include "sd_mmc.h"
#include "storage.h"
-#include <timer.h>
-#include <commonlib/stdlib.h>
#define DMA_AVAILABLE ((CONFIG_SDHCI_ADMA_IN_BOOTBLOCK && ENV_BOOTBLOCK) \
|| (CONFIG_SDHCI_ADMA_IN_VERSTAGE && ENV_VERSTAGE) \
diff --git a/src/commonlib/storage/sdhci_adma.c b/src/commonlib/storage/sdhci_adma.c
index 1bae3fb..06e9532 100644
--- a/src/commonlib/storage/sdhci_adma.c
+++ b/src/commonlib/storage/sdhci_adma.c
@@ -23,6 +23,7 @@
#include <delay.h>
#include <endian.h>
#include <string.h>
+#include <stdlib.h>
#include "sdhci.h"
#include "sd_mmc.h"
diff --git a/src/cpu/allwinner/a10/clock.c b/src/cpu/allwinner/a10/clock.c
index 76198b7..9e4e93d 100644
--- a/src/cpu/allwinner/a10/clock.c
+++ b/src/cpu/allwinner/a10/clock.c
@@ -22,7 +22,6 @@
#include <console/console.h>
#include <delay.h>
#include <lib.h>
-#include <stdlib.h>
static struct a10_ccm *const ccm = (void *)A1X_CCM_BASE;
diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c
index db58f5d..0e19353 100644
--- a/src/cpu/amd/family_10h-family_15h/fidvid.c
+++ b/src/cpu/amd/family_10h-family_15h/fidvid.c
@@ -92,6 +92,7 @@
#include <cpu/amd/msr.h>
#include <inttypes.h>
#include <northbridge/amd/amdht/AsPsDefs.h>
+#include <stdlib.h>
static inline void print_debug_fv(const char *str, u32 val)
{
diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.h b/src/cpu/amd/family_10h-family_15h/init_cpus.h
index d09fc82..3459178 100644
--- a/src/cpu/amd/family_10h-family_15h/init_cpus.h
+++ b/src/cpu/amd/family_10h-family_15h/init_cpus.h
@@ -16,7 +16,6 @@
#ifndef INIT_CPUS_H
#define INIT_CPUS_H
-#include <stdlib.h>
#include <console/console.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/mtrr.h>
diff --git a/src/cpu/amd/family_10h-family_15h/processor_name.c b/src/cpu/amd/family_10h-family_15h/processor_name.c
index 5672efd..3a5e2e2 100644
--- a/src/cpu/amd/family_10h-family_15h/processor_name.c
+++ b/src/cpu/amd/family_10h-family_15h/processor_name.c
@@ -32,6 +32,7 @@
#include <device/pci.h>
#include <device/pnp.h>
#include <device/pci_ops.h>
+#include <stdlib.h>
/* The maximum length of CPU names is 48 bytes, including the final NULL byte.
* If you change these names your BIOS will _NOT_ pass the AMD validation and
diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c
index cc2d1a4..16e54d7 100644
--- a/src/cpu/intel/haswell/finalize.c
+++ b/src/cpu/intel/haswell/finalize.c
@@ -15,7 +15,6 @@
*/
#include <stdint.h>
-#include <stdlib.h>
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include "haswell.h"
diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c
index 5b85601..724e09c 100644
--- a/src/cpu/intel/model_2065x/finalize.c
+++ b/src/cpu/intel/model_2065x/finalize.c
@@ -15,7 +15,6 @@
*/
#include <stdint.h>
-#include <stdlib.h>
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <cpu/intel/speedstep.h>
diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c
index 30b00bb..98ce555 100644
--- a/src/cpu/intel/model_206ax/finalize.c
+++ b/src/cpu/intel/model_206ax/finalize.c
@@ -15,7 +15,6 @@
*/
#include <stdint.h>
-#include <stdlib.h>
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <cpu/intel/speedstep.h>
diff --git a/src/cpu/ti/am335x/gpio.c b/src/cpu/ti/am335x/gpio.c
index e1c6967..6262651 100644
--- a/src/cpu/ti/am335x/gpio.c
+++ b/src/cpu/ti/am335x/gpio.c
@@ -16,7 +16,6 @@
#include <console/console.h>
#include <cpu/ti/am335x/gpio.h>
#include <stdint.h>
-#include <stdlib.h>
static struct am335x_gpio_regs *gpio_regs_and_bit(unsigned gpio, uint32_t *bit)
{
diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c
index c482a85..4e9d012 100644
--- a/src/cpu/ti/am335x/uart.c
+++ b/src/cpu/ti/am335x/uart.c
@@ -12,7 +12,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <types.h>
#include <console/uart.h>
#include <device/mmio.h>
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index 3ad1f0a..3abf396 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -35,6 +35,7 @@
#include <cpu/cpu.h>
#include <cpu/intel/speedstep.h>
#include <thread.h>
+#include <stdlib.h>
/* This is a lot more paranoid now, since Linux can NOT handle
* being told there is a CPU when none exists. So any errors
diff --git a/src/cpu/x86/mirror_payload.c b/src/cpu/x86/mirror_payload.c
index 5f0493a..3207baf 100644
--- a/src/cpu/x86/mirror_payload.c
+++ b/src/cpu/x86/mirror_payload.c
@@ -14,7 +14,6 @@
*/
#include <stdint.h>
-#include <stdlib.h>
#include <string.h>
#include <console/console.h>
#include <bootmem.h>
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index d87c3d4..91ff14a 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -22,7 +22,6 @@
*/
#include <stddef.h>
-#include <stdlib.h>
#include <string.h>
#include <bootstate.h>
#include <console/console.h>
diff --git a/src/device/device_util.c b/src/device/device_util.c
index 5c4f911..03f147f 100644
--- a/src/device/device_util.c
+++ b/src/device/device_util.c
@@ -24,6 +24,7 @@
#include <device/pci_def.h>
#include <device/resource.h>
#include <string.h>
+#include <stdlib.h>
/**
* Given a Local APIC ID, find the device structure.
diff --git a/src/device/i2c_bus.c b/src/device/i2c_bus.c
index 30bb80c..ebc021d 100644
--- a/src/device/i2c_bus.c
+++ b/src/device/i2c_bus.c
@@ -11,7 +11,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <stdint.h>
#include <console/console.h>
#include <device/smbus.h>
diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c
index a7631a1..e002c47 100644
--- a/src/device/oprom/realmode/x86.c
+++ b/src/device/oprom/realmode/x86.c
@@ -28,6 +28,7 @@
#include <lib/jpeg.h>
#include <pc80/i8259.h>
#include <pc80/i8254.h>
+#include <stdlib.h>
#include <string.h>
#include <vbe.h>
diff --git a/src/device/oprom/yabel/vbe.c b/src/device/oprom/yabel/vbe.c
index 682bf00..9cfea73 100644
--- a/src/device/oprom/yabel/vbe.c
+++ b/src/device/oprom/yabel/vbe.c
@@ -33,6 +33,7 @@
*****************************************************************************/
#include <string.h>
+#include <stdlib.h>
#include <types.h>
#if CONFIG(FRAMEBUFFER_SET_VESA_MODE)
#include <boot/coreboot_tables.h>
diff --git a/src/device/pci_class.c b/src/device/pci_class.c
index d9c3a4f..6ab1ddc 100644
--- a/src/device/pci_class.c
+++ b/src/device/pci_class.c
@@ -18,7 +18,6 @@
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
-#include <stdlib.h>
typedef struct {
const unsigned char subclass_id;
diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c
index 402e5d1..eeaf106 100644
--- a/src/device/pnp_device.c
+++ b/src/device/pnp_device.c
@@ -20,7 +20,6 @@
*/
#include <console/console.h>
-#include <stdlib.h>
#include <stdint.h>
#include <arch/io.h>
#include <device/device.h>
diff --git a/src/drivers/aspeed/ast2050/ast2050.c b/src/drivers/aspeed/ast2050/ast2050.c
index 631372d..58cea42 100644
--- a/src/drivers/aspeed/ast2050/ast2050.c
+++ b/src/drivers/aspeed/ast2050/ast2050.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <arch/io.h>
#include <edid.h>
#include <console/console.h>
diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c
index 22095ef..a26fc60 100644
--- a/src/drivers/emulation/qemu/bochs.c
+++ b/src/drivers/emulation/qemu/bochs.c
@@ -13,7 +13,6 @@
#include <stdint.h>
#include <edid.h>
-#include <stdlib.h>
#include <arch/io.h>
#include <boot/coreboot_tables.h>
#include <console/console.h>
diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c
index ed5a4f4..42b8869 100644
--- a/src/drivers/emulation/qemu/cirrus.c
+++ b/src/drivers/emulation/qemu/cirrus.c
@@ -16,7 +16,6 @@
#include <stdint.h>
#include <edid.h>
-#include <stdlib.h>
#include <boot/coreboot_tables.h>
#include <console/console.h>
#include <device/device.h>
diff --git a/src/drivers/i2c/rtd2132/rtd2132.c b/src/drivers/i2c/rtd2132/rtd2132.c
index 2aaa234..64796b7 100644
--- a/src/drivers/i2c/rtd2132/rtd2132.c
+++ b/src/drivers/i2c/rtd2132/rtd2132.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <console/console.h>
#include <delay.h>
#include <device/device.h>
diff --git a/src/drivers/intel/fsp1_1/stack.c b/src/drivers/intel/fsp1_1/stack.c
index 88ff36a..7e1e81f 100644
--- a/src/drivers/intel/fsp1_1/stack.c
+++ b/src/drivers/intel/fsp1_1/stack.c
@@ -21,7 +21,6 @@
#include <fsp/memmap.h>
#include <fsp/romstage.h>
#include <fsp/stack.h>
-#include <stdlib.h>
#include <program_loading.h>
/*
diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h
index e065924..6739310 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h
@@ -14,7 +14,6 @@
#define _FSP2_0_INFO_HEADER_H_
#include <stdint.h>
-#include <stdlib.h>
#include <types.h>
#define FSP_HDR_OFFSET 0x94
diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c
index 471a5d2..4220209 100644
--- a/src/drivers/intel/gma/intel_ddi.c
+++ b/src/drivers/intel/gma/intel_ddi.c
@@ -27,7 +27,6 @@
*/
#include <types.h>
-#include <stdlib.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
diff --git a/src/drivers/net/ne2k.c b/src/drivers/net/ne2k.c
index e3dd948..e60896c 100644
--- a/src/drivers/net/ne2k.c
+++ b/src/drivers/net/ne2k.c
@@ -33,7 +33,6 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include <stdlib.h>
#include <ip_checksum.h>
#include "ns8390.h"
diff --git a/src/drivers/parade/ps8625/ps8625.c b/src/drivers/parade/ps8625/ps8625.c
index 3e90cbb..7369d48 100644
--- a/src/drivers/parade/ps8625/ps8625.c
+++ b/src/drivers/parade/ps8625/ps8625.c
@@ -15,7 +15,6 @@
#include <device/i2c_simple.h>
#include <stdint.h>
-#include <stdlib.h>
#include "ps8625.h"
diff --git a/src/drivers/sil/3114/sil_sata.c b/src/drivers/sil/3114/sil_sata.c
index dd6481a..3e49a2b 100644
--- a/src/drivers/sil/3114/sil_sata.c
+++ b/src/drivers/sil/3114/sil_sata.c
@@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/drivers/spi/spi-generic.c b/src/drivers/spi/spi-generic.c
index 84a42d1..3f0fa6a 100644
--- a/src/drivers/spi/spi-generic.c
+++ b/src/drivers/spi/spi-generic.c
@@ -17,6 +17,7 @@
#include <assert.h>
#include <spi-generic.h>
#include <string.h>
+#include <stdlib.h>
int spi_claim_bus(const struct spi_slave *slave)
{
diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c
index 82398dd..244e499 100644
--- a/src/drivers/spi/spi_flash.c
+++ b/src/drivers/spi/spi_flash.c
@@ -11,7 +11,6 @@
#include <assert.h>
#include <boot_device.h>
#include <cpu/x86/smm.h>
-#include <stdlib.h>
#include <string.h>
#include <spi-generic.h>
#include <spi_flash.h>
diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c
index 62671e2..be93e1a 100644
--- a/src/drivers/uart/uart8250io.c
+++ b/src/drivers/uart/uart8250io.c
@@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <arch/io.h>
#include <boot/coreboot_tables.h>
#include <console/uart.h>
diff --git a/src/drivers/vpd/vpd.c b/src/drivers/vpd/vpd.c
index e620b58..9924bb2 100644
--- a/src/drivers/vpd/vpd.c
+++ b/src/drivers/vpd/vpd.c
@@ -7,7 +7,6 @@
#include <console/console.h>
#include <cbmem.h>
#include <fmap.h>
-#include <stdlib.h>
#include <string.h>
#include <timestamp.h>
diff --git a/src/drivers/xgi/common/xgi_coreboot.c b/src/drivers/xgi/common/xgi_coreboot.c
index 5aba472..46b3e52 100644
--- a/src/drivers/xgi/common/xgi_coreboot.c
+++ b/src/drivers/xgi/common/xgi_coreboot.c
@@ -16,7 +16,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <vbe.h>
#include <console/console.h>
#include <device/device.h>
diff --git a/src/drivers/xgi/common/xgi_coreboot.h b/src/drivers/xgi/common/xgi_coreboot.h
index 41952d6..65e6cac 100644
--- a/src/drivers/xgi/common/xgi_coreboot.h
+++ b/src/drivers/xgi/common/xgi_coreboot.h
@@ -19,7 +19,6 @@
#ifndef _XGI_COREBOOT_
#define _XGI_COREBOOT_
-#include <stdlib.h>
#include <stdint.h>
#include <arch/io.h>
#include <device/mmio.h>
diff --git a/src/ec/compal/ene932/ec.c b/src/ec/compal/ene932/ec.c
index 7d8880c..cfabd8d 100644
--- a/src/ec/compal/ene932/ec.c
+++ b/src/ec/compal/ene932/ec.c
@@ -19,7 +19,6 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pnp.h>
-#include <stdlib.h>
#include <arch/io.h>
#include <delay.h>
#include <pc80/keyboard.h>
diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c
index 7293cff..8e18654 100644
--- a/src/ec/google/chromeec/ec_lpc.c
+++ b/src/ec/google/chromeec/ec_lpc.c
@@ -20,7 +20,6 @@
#include <device/pnp.h>
#include <ec/google/common/mec.h>
#include <stdint.h>
-#include <stdlib.h>
#include "chip.h"
#include "ec.h"
diff --git a/src/ec/google/chromeec/vstore.c b/src/ec/google/chromeec/vstore.c
index 28c2603..50e964f 100644
--- a/src/ec/google/chromeec/vstore.c
+++ b/src/ec/google/chromeec/vstore.c
@@ -15,7 +15,6 @@
#include <stdint.h>
#include <string.h>
-#include <stdlib.h>
#include "ec.h"
#include "ec_commands.h"
diff --git a/src/ec/google/wilco/chip.c b/src/ec/google/wilco/chip.c
index 0858e1c..380507b 100644
--- a/src/ec/google/wilco/chip.c
+++ b/src/ec/google/wilco/chip.c
@@ -19,7 +19,6 @@
#include <ec/acpi/ec.h>
#include <pc80/keyboard.h>
#include <stdint.h>
-#include <stdlib.h>
#include "commands.h"
#include "ec.h"
diff --git a/src/ec/google/wilco/mailbox.c b/src/ec/google/wilco/mailbox.c
index d47290c..3414c4a 100644
--- a/src/ec/google/wilco/mailbox.c
+++ b/src/ec/google/wilco/mailbox.c
@@ -18,7 +18,6 @@
#include <delay.h>
#include <ec/google/common/mec.h>
#include <stdint.h>
-#include <stdlib.h>
#include <string.h>
#include <timer.h>
#include <types.h>
diff --git a/src/ec/kontron/it8516e/ec.c b/src/ec/kontron/it8516e/ec.c
index 5565382..c0042fc 100644
--- a/src/ec/kontron/it8516e/ec.c
+++ b/src/ec/kontron/it8516e/ec.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pnp.h>
diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c
index de4f2c2..d2f2a80 100644
--- a/src/ec/lenovo/h8/h8.c
+++ b/src/ec/lenovo/h8/h8.c
@@ -18,7 +18,6 @@
#include <device/device.h>
#include <device/pnp.h>
#include <ec/acpi/ec.h>
-#include <stdlib.h>
#include <string.h>
#include <smbios.h>
#include <pc80/mc146818rtc.h>
diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c
index 986abb5..1f2ad95 100644
--- a/src/ec/lenovo/pmh7/pmh7.c
+++ b/src/ec/lenovo/pmh7/pmh7.c
@@ -17,7 +17,6 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pnp.h>
-#include <stdlib.h>
#include <pc80/mc146818rtc.h>
#include <delay.h>
diff --git a/src/ec/quanta/ene_kb3940q/ec.c b/src/ec/quanta/ene_kb3940q/ec.c
index af2d378..1f8e36c 100644
--- a/src/ec/quanta/ene_kb3940q/ec.c
+++ b/src/ec/quanta/ene_kb3940q/ec.c
@@ -22,7 +22,6 @@
#include <device/pnp.h>
#include <delay.h>
#include <elog.h>
-#include <stdlib.h>
#include <pc80/keyboard.h>
#include "ec.h"
diff --git a/src/ec/quanta/it8518/ec.c b/src/ec/quanta/it8518/ec.c
index e293f7c..5b9ba9f 100644
--- a/src/ec/quanta/it8518/ec.c
+++ b/src/ec/quanta/it8518/ec.c
@@ -20,7 +20,6 @@
#include <device/device.h>
#include <device/pnp.h>
#include <pc80/keyboard.h>
-#include <stdlib.h>
#include "ec.h"
#include "chip.h"
diff --git a/src/ec/roda/it8518/ec.c b/src/ec/roda/it8518/ec.c
index 4e69d11..09ff480 100644
--- a/src/ec/roda/it8518/ec.c
+++ b/src/ec/roda/it8518/ec.c
@@ -18,7 +18,6 @@
#include <device/pnp.h>
#include <pc80/keyboard.h>
#include <ec/acpi/ec.h>
-#include <stdlib.h>
#include <delay.h>
#include "chip.h"
diff --git a/src/include/bootstate.h b/src/include/bootstate.h
index 26038c6..c53884e 100644
--- a/src/include/bootstate.h
+++ b/src/include/bootstate.h
@@ -16,7 +16,6 @@
#define BOOTSTATE_H
#include <string.h>
-#include <stdlib.h>
#include <stddef.h>
#include <stdint.h>
/* Only declare main() when in ramstage. */
diff --git a/src/include/device/i2c_bus.h b/src/include/device/i2c_bus.h
index 6aa4f9b..022f71e 100644
--- a/src/include/device/i2c_bus.h
+++ b/src/include/device/i2c_bus.h
@@ -14,7 +14,6 @@
#ifndef _DEVICE_I2C_BUS_H_
#define _DEVICE_I2C_BUS_H_
-#include <stdlib.h>
#include <stdint.h>
#include <device/i2c.h>
#include <device/device.h>
diff --git a/src/include/string.h b/src/include/string.h
index 4a2f5e9..81afcf0 100644
--- a/src/include/string.h
+++ b/src/include/string.h
@@ -2,7 +2,6 @@
#define STRING_H
#include <stddef.h>
-#include <stdlib.h>
#if !defined(__ROMCC__)
#include <console/vtxprintf.h>
diff --git a/src/lib/bootmem.c b/src/lib/bootmem.c
index 01ad3e8..7eff46d 100644
--- a/src/lib/bootmem.c
+++ b/src/lib/bootmem.c
@@ -19,7 +19,6 @@
#include <bootmem.h>
#include <cbmem.h>
#include <device/resource.h>
-#include <stdlib.h>
#include <symbols.h>
#include <assert.h>
diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c
index 728674f..61d90c6 100644
--- a/src/lib/cbfs.c
+++ b/src/lib/cbfs.c
@@ -16,7 +16,6 @@
#include <assert.h>
#include <string.h>
-#include <stdlib.h>
#include <boot_device.h>
#include <cbfs.h>
#include <commonlib/compression.h>
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index 6e44f5d..fa7b793 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -27,7 +27,6 @@
#include <boardid.h>
#include <device/device.h>
#include <fmap.h>
-#include <stdlib.h>
#include <cbfs.h>
#include <cbmem.h>
#include <bootmem.h>
diff --git a/src/lib/fit.c b/src/lib/fit.c
index 4e2b75c..dc17c59 100644
--- a/src/lib/fit.c
+++ b/src/lib/fit.c
@@ -19,14 +19,12 @@
#include <endian.h>
#include <stdint.h>
#include <bootmem.h>
-#include <stdlib.h>
#include <string.h>
#include <program_loading.h>
#include <memrange.h>
#include <fit.h>
#include <boardid.h>
#include <commonlib/cbfs_serialized.h>
-#include <commonlib/include/commonlib/stdlib.h>
static struct list_node image_nodes;
static struct list_node config_nodes;
diff --git a/src/lib/fit_payload.c b/src/lib/fit_payload.c
index e0158f2..97d8723 100644
--- a/src/lib/fit_payload.c
+++ b/src/lib/fit_payload.c
@@ -19,7 +19,6 @@
#include <bootmem.h>
#include <cbmem.h>
#include <device/resource.h>
-#include <stdlib.h>
#include <commonlib/region.h>
#include <fit.h>
#include <program_loading.h>
diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c
index 2881162..608b683 100644
--- a/src/lib/hardwaremain.c
+++ b/src/lib/hardwaremain.c
@@ -28,7 +28,6 @@
#include <device/device.h>
#include <device/pci.h>
#include <delay.h>
-#include <stdlib.h>
#include <boot/tables.h>
#include <program_loading.h>
#if CONFIG(HAVE_ACPI_RESUME)
diff --git a/src/lib/imd.c b/src/lib/imd.c
index 17ec2d9..a50aa79 100644
--- a/src/lib/imd.c
+++ b/src/lib/imd.c
@@ -17,7 +17,6 @@
#include <cbmem.h>
#include <console/console.h>
#include <imd.h>
-#include <stdlib.h>
#include <string.h>
/* For more details on implementation and usage please see the imd.h header. */
diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c
index c458e5e..0b97cb5 100644
--- a/src/lib/imd_cbmem.c
+++ b/src/lib/imd_cbmem.c
@@ -18,7 +18,6 @@
#include <console/console.h>
#include <cbmem.h>
#include <imd.h>
-#include <stdlib.h>
#include <arch/early_variables.h>
/*
diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c
index 3b77712..a9539c9 100644
--- a/src/lib/prog_loaders.c
+++ b/src/lib/prog_loaders.c
@@ -14,7 +14,6 @@
*/
-#include <stdlib.h>
#include <cbfs.h>
#include <cbmem.h>
#include <console/console.h>
diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c
index 56529d2..e33df81 100644
--- a/src/lib/rmodule.c
+++ b/src/lib/rmodule.c
@@ -16,7 +16,6 @@
#include <cbmem.h>
#include <cbfs.h>
#include <stdint.h>
-#include <stdlib.h>
#include <string.h>
#include <console/console.h>
#include <program_loading.h>
diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c
index 9aa4741..8d5bb13 100644
--- a/src/lib/selfboot.c
+++ b/src/lib/selfboot.c
@@ -19,7 +19,6 @@
#include <commonlib/endian.h>
#include <console/console.h>
#include <stdint.h>
-#include <stdlib.h>
#include <string.h>
#include <symbols.h>
#include <cbfs.h>
diff --git a/src/lib/thread.c b/src/lib/thread.c
index 281885f..a786b9f 100644
--- a/src/lib/thread.c
+++ b/src/lib/thread.c
@@ -15,7 +15,6 @@
#include <stddef.h>
#include <stdint.h>
-#include <stdlib.h>
#include <arch/cpu.h>
#include <bootstate.h>
#include <console/console.h>
diff --git a/src/mainboard/advansus/a785e-i/get_bus_conf.c b/src/mainboard/advansus/a785e-i/get_bus_conf.c
index 6b5ae68..7aca540 100644
--- a/src/mainboard/advansus/a785e-i/get_bus_conf.c
+++ b/src/mainboard/advansus/a785e-i/get_bus_conf.c
@@ -15,7 +15,6 @@
#include <device/pci.h>
#include <stdint.h>
-#include <stdlib.h>
#include <cpu/amd/multicore.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c
index 040de9b..f4ecbd1 100644
--- a/src/mainboard/amd/bettong/BiosCallOuts.c
+++ b/src/mainboard/amd/bettong/BiosCallOuts.c
@@ -19,7 +19,6 @@
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <northbridge/amd/pi/00660F01/chip.h>
#include <FchPlatform.h>
-#include <stdlib.h>
#include <string.h>
#include <northbridge/amd/pi/dimmSpd.h>
#include <northbridge/amd/pi/agesawrapper.h>
diff --git a/src/mainboard/amd/bimini_fam10/get_bus_conf.c b/src/mainboard/amd/bimini_fam10/get_bus_conf.c
index 4021c51..a9db67a 100644
--- a/src/mainboard/amd/bimini_fam10/get_bus_conf.c
+++ b/src/mainboard/amd/bimini_fam10/get_bus_conf.c
@@ -15,7 +15,6 @@
#include <device/pci.h>
#include <stdint.h>
-#include <stdlib.h>
#include <cpu/amd/multicore.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
index c6e575d..b7ef7e3 100644
--- a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
+++ b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
@@ -18,7 +18,6 @@
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <device/azalia.h>
#include <FchPlatform.h>
-#include <stdlib.h>
#include "imc.h"
#include "hudson.h"
diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.c b/src/mainboard/amd/gardenia/BiosCallOuts.c
index d4fb55a..ee92326 100644
--- a/src/mainboard/amd/gardenia/BiosCallOuts.c
+++ b/src/mainboard/amd/gardenia/BiosCallOuts.c
@@ -16,7 +16,6 @@
#include <amdblocks/agesawrapper.h>
#include <amdblocks/BiosCallOuts.h>
#include <soc/southbridge.h>
-#include <stdlib.h>
void platform_FchParams_env(FCH_DATA_BLOCK *FchParams_env)
{
diff --git a/src/mainboard/amd/gardenia/gpio.c b/src/mainboard/amd/gardenia/gpio.c
index 7c5f47b..837d031 100644
--- a/src/mainboard/amd/gardenia/gpio.c
+++ b/src/mainboard/amd/gardenia/gpio.c
@@ -14,7 +14,6 @@
*/
#include <soc/southbridge.h>
-#include <stdlib.h>
#include <soc/gpio.h>
#include "gpio.h"
diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c
index b6267a6..0a24def 100644
--- a/src/mainboard/amd/inagua/BiosCallOuts.c
+++ b/src/mainboard/amd/inagua/BiosCallOuts.c
@@ -18,7 +18,6 @@
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <SB800.h>
#include <southbridge/amd/cimx/sb800/gpio_oem.h>
-#include <stdlib.h>
static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr);
diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c
index fe6fac0..f1e46c9 100644
--- a/src/mainboard/amd/inagua/buildOpts.c
+++ b/src/mainboard/amd/inagua/buildOpts.c
@@ -25,7 +25,6 @@
*
*/
-#include <stdlib.h>
/* Select the CPU family. */
diff --git a/src/mainboard/amd/lamar/BiosCallOuts.c b/src/mainboard/amd/lamar/BiosCallOuts.c
index 8891abb..a226cf5 100644
--- a/src/mainboard/amd/lamar/BiosCallOuts.c
+++ b/src/mainboard/amd/lamar/BiosCallOuts.c
@@ -16,7 +16,6 @@
#include <AGESA.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <FchPlatform.h>
-#include <stdlib.h>
#include <device/azalia.h>
#include "imc.h"
diff --git a/src/mainboard/amd/mahogany_fam10/get_bus_conf.c b/src/mainboard/amd/mahogany_fam10/get_bus_conf.c
index ee2a6ca..24e44e6 100644
--- a/src/mainboard/amd/mahogany_fam10/get_bus_conf.c
+++ b/src/mainboard/amd/mahogany_fam10/get_bus_conf.c
@@ -15,7 +15,6 @@
#include <device/pci.h>
#include <stdint.h>
-#include <stdlib.h>
#include <cpu/amd/multicore.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/amd/olivehill/BiosCallOuts.c b/src/mainboard/amd/olivehill/BiosCallOuts.c
index b6a8a3a..1865034 100644
--- a/src/mainboard/amd/olivehill/BiosCallOuts.c
+++ b/src/mainboard/amd/olivehill/BiosCallOuts.c
@@ -17,7 +17,6 @@
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <FchPlatform.h>
-#include <stdlib.h>
#include "imc.h"
diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c
index 65b86b8..bb8527d 100644
--- a/src/mainboard/amd/olivehill/buildOpts.c
+++ b/src/mainboard/amd/olivehill/buildOpts.c
@@ -25,7 +25,6 @@
*
*/
-#include <stdlib.h>
#include <AGESA.h>
#define INSTALL_FT3_SOCKET_SUPPORT TRUE
diff --git a/src/mainboard/amd/olivehillplus/BiosCallOuts.c b/src/mainboard/amd/olivehillplus/BiosCallOuts.c
index a6f4267..fa74188 100644
--- a/src/mainboard/amd/olivehillplus/BiosCallOuts.c
+++ b/src/mainboard/amd/olivehillplus/BiosCallOuts.c
@@ -16,7 +16,6 @@
#include <AGESA.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <FchPlatform.h>
-#include <stdlib.h>
#include "imc.h"
#include "hudson.h"
diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c
index 0c54211..89062b6 100644
--- a/src/mainboard/amd/parmer/BiosCallOuts.c
+++ b/src/mainboard/amd/parmer/BiosCallOuts.c
@@ -17,7 +17,6 @@
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <FchPlatform.h>
-#include <stdlib.h>
#include "imc.h"
diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c
index 7ff6caa..93fcd35 100644
--- a/src/mainboard/amd/parmer/buildOpts.c
+++ b/src/mainboard/amd/parmer/buildOpts.c
@@ -25,7 +25,6 @@
*
*/
-#include <stdlib.h>
#include <AGESA.h>
/* Select the CPU family. */
diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c
index 60ce3ee..b1403ec 100644
--- a/src/mainboard/amd/persimmon/BiosCallOuts.c
+++ b/src/mainboard/amd/persimmon/BiosCallOuts.c
@@ -17,7 +17,6 @@
#include <amdlib.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <SB800.h>
-#include <stdlib.h>
static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr);
diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c
index d99cc81..9212ec1 100644
--- a/src/mainboard/amd/persimmon/buildOpts.c
+++ b/src/mainboard/amd/persimmon/buildOpts.c
@@ -25,7 +25,6 @@
*
*/
-#include <stdlib.h>
/* Select the CPU family. */
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
index e1f2409..04d0500 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
@@ -21,7 +21,6 @@
#include <cpu/amd/amdfam10_sysconf.h>
-#include <stdlib.h>
#include "mb_sysconf.h"
/* Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables */
diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c
index ecb7e1c..9cfb646 100644
--- a/src/mainboard/amd/south_station/BiosCallOuts.c
+++ b/src/mainboard/amd/south_station/BiosCallOuts.c
@@ -18,7 +18,6 @@
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <SB800.h>
#include <southbridge/amd/cimx/sb800/gpio_oem.h>
-#include <stdlib.h>
static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr);
diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c
index 244229d..929408f 100644
--- a/src/mainboard/amd/south_station/buildOpts.c
+++ b/src/mainboard/amd/south_station/buildOpts.c
@@ -25,7 +25,6 @@
*
*/
-#include <stdlib.h>
/* Select the CPU family. */
diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c
index f23161d..cc56a9a 100644
--- a/src/mainboard/amd/thatcher/BiosCallOuts.c
+++ b/src/mainboard/amd/thatcher/BiosCallOuts.c
@@ -17,7 +17,6 @@
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <FchPlatform.h>
-#include <stdlib.h>
#include "imc.h"
diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c
index 96847a7..cc1069d 100644
--- a/src/mainboard/amd/thatcher/buildOpts.c
+++ b/src/mainboard/amd/thatcher/buildOpts.c
@@ -25,7 +25,6 @@
*
*/
-#include <stdlib.h>
#include <AGESA.h>
/* Select the CPU family. */
diff --git a/src/mainboard/amd/tilapia_fam10/get_bus_conf.c b/src/mainboard/amd/tilapia_fam10/get_bus_conf.c
index 37a3774..382834b 100644
--- a/src/mainboard/amd/tilapia_fam10/get_bus_conf.c
+++ b/src/mainboard/amd/tilapia_fam10/get_bus_conf.c
@@ -15,7 +15,6 @@
#include <device/pci.h>
#include <stdint.h>
-#include <stdlib.h>
#include <cpu/amd/multicore.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.c b/src/mainboard/amd/torpedo/BiosCallOuts.c
index e7b0e29..5002354 100644
--- a/src/mainboard/amd/torpedo/BiosCallOuts.c
+++ b/src/mainboard/amd/torpedo/BiosCallOuts.c
@@ -17,7 +17,6 @@
#include <amdlib.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "Hudson-2.h"
-#include <stdlib.h>
#include <southbridge/amd/cimx/sb900/gpio_oem.h>
static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
diff --git a/src/mainboard/amd/torpedo/buildOpts.c b/src/mainboard/amd/torpedo/buildOpts.c
index fbeee9a..89b3810 100644
--- a/src/mainboard/amd/torpedo/buildOpts.c
+++ b/src/mainboard/amd/torpedo/buildOpts.c
@@ -25,7 +25,6 @@
*
*/
-#include <stdlib.h>
#include <AGESA.h>
diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c
index ecb7e1c..9cfb646 100644
--- a/src/mainboard/amd/union_station/BiosCallOuts.c
+++ b/src/mainboard/amd/union_station/BiosCallOuts.c
@@ -18,7 +18,6 @@
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <SB800.h>
#include <southbridge/amd/cimx/sb800/gpio_oem.h>
-#include <stdlib.h>
static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr);
diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c
index 244229d..929408f 100644
--- a/src/mainboard/amd/union_station/buildOpts.c
+++ b/src/mainboard/amd/union_station/buildOpts.c
@@ -25,7 +25,6 @@
*
*/
-#include <stdlib.h>
/* Select the CPU family. */
diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c
index 491027a..5d7211c 100644
--- a/src/mainboard/asrock/e350m1/BiosCallOuts.c
+++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c
@@ -17,7 +17,6 @@
#include <amdlib.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <SB800.h>
-#include <stdlib.h>
static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c
index 14621e0..0125b56 100644
--- a/src/mainboard/asrock/e350m1/buildOpts.c
+++ b/src/mainboard/asrock/e350m1/buildOpts.c
@@ -25,7 +25,6 @@
*
*/
-#include <stdlib.h>
#include <AGESA.h>
diff --git a/src/mainboard/asrock/imb-a180/BiosCallOuts.c b/src/mainboard/asrock/imb-a180/BiosCallOuts.c
index e05d5c0..983f9a8 100644
--- a/src/mainboard/asrock/imb-a180/BiosCallOuts.c
+++ b/src/mainboard/asrock/imb-a180/BiosCallOuts.c
@@ -18,7 +18,6 @@
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <FchPlatform.h>
-#include <stdlib.h>
const BIOS_CALLOUT_STRUCT BiosCallouts[] =
{
diff --git a/src/mainboard/asrock/imb-a180/buildOpts.c b/src/mainboard/asrock/imb-a180/buildOpts.c
index d9d62e2..caa5e3b 100644
--- a/src/mainboard/asrock/imb-a180/buildOpts.c
+++ b/src/mainboard/asrock/imb-a180/buildOpts.c
@@ -25,7 +25,6 @@
*
*/
-#include <stdlib.h>
#include <AGESA.h>
#define INSTALL_FT3_SOCKET_SUPPORT TRUE
diff --git a/src/mainboard/asus/am1i-a/BiosCallOuts.c b/src/mainboard/asus/am1i-a/BiosCallOuts.c
index a1018b3..55897bf 100644
--- a/src/mainboard/asus/am1i-a/BiosCallOuts.c
+++ b/src/mainboard/asus/am1i-a/BiosCallOuts.c
@@ -20,7 +20,6 @@
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <FchPlatform.h>
-#include <stdlib.h>
#include <pc80/mc146818rtc.h>
#include <types.h>
diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c
index 30c0699..74216f0 100644
--- a/src/mainboard/asus/am1i-a/buildOpts.c
+++ b/src/mainboard/asus/am1i-a/buildOpts.c
@@ -25,7 +25,6 @@
*
*/
-#include <stdlib.h>
#include <AGESA.h>
#define INSTALL_FT3_SOCKET_SUPPORT TRUE
diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c
index 9e60ca7..15ce47e 100644
--- a/src/mainboard/asus/f2a85-m/BiosCallOuts.c
+++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.c
@@ -18,7 +18,6 @@
#include <northbridge/amd/agesa/state_machine.h>
#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h>
-#include <stdlib.h>
const BIOS_CALLOUT_STRUCT BiosCallouts[] =
{
diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c
index dc20dc7..8a1391d 100644
--- a/src/mainboard/asus/f2a85-m/buildOpts.c
+++ b/src/mainboard/asus/f2a85-m/buildOpts.c
@@ -25,7 +25,6 @@
*
*/
-#include <stdlib.h>
#include <vendorcode/amd/agesa/f15tn/AGESA.h>
diff --git a/src/mainboard/asus/kcma-d8/get_bus_conf.c b/src/mainboard/asus/kcma-d8/get_bus_conf.c
index cc64dea..8fd10a1 100644
--- a/src/mainboard/asus/kcma-d8/get_bus_conf.c
+++ b/src/mainboard/asus/kcma-d8/get_bus_conf.c
@@ -16,7 +16,6 @@
#include <device/pci.h>
#include <stdint.h>
-#include <stdlib.h>
#include <cpu/amd/multicore.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/asus/kfsn4-dre/get_bus_conf.c b/src/mainboard/asus/kfsn4-dre/get_bus_conf.c
index dd7ebc9..ea32741 100644
--- a/src/mainboard/asus/kfsn4-dre/get_bus_conf.c
+++ b/src/mainboard/asus/kfsn4-dre/get_bus_conf.c
@@ -22,7 +22,6 @@
#include <device/pci.h>
#include <device/pci_ops.h>
#include <stdint.h>
-#include <stdlib.h>
#include <cpu/amd/multicore.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/asus/kgpe-d16/get_bus_conf.c b/src/mainboard/asus/kgpe-d16/get_bus_conf.c
index 81d0fc1..e1e07df 100644
--- a/src/mainboard/asus/kgpe-d16/get_bus_conf.c
+++ b/src/mainboard/asus/kgpe-d16/get_bus_conf.c
@@ -16,7 +16,6 @@
#include <device/pci.h>
#include <stdint.h>
-#include <stdlib.h>
#include <cpu/amd/multicore.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/asus/m4a78-em/get_bus_conf.c b/src/mainboard/asus/m4a78-em/get_bus_conf.c
index ee2a6ca..24e44e6 100644
--- a/src/mainboard/asus/m4a78-em/get_bus_conf.c
+++ b/src/mainboard/asus/m4a78-em/get_bus_conf.c
@@ -15,7 +15,6 @@
#include <device/pci.h>
#include <stdint.h>
-#include <stdlib.h>
#include <cpu/amd/multicore.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/asus/m4a785-m/get_bus_conf.c b/src/mainboard/asus/m4a785-m/get_bus_conf.c
index ee2a6ca..24e44e6 100644
--- a/src/mainboard/asus/m4a785-m/get_bus_conf.c
+++ b/src/mainboard/asus/m4a785-m/get_bus_conf.c
@@ -15,7 +15,6 @@
#include <device/pci.h>
#include <stdint.h>
-#include <stdlib.h>
#include <cpu/amd/multicore.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/asus/m5a88-v/get_bus_conf.c b/src/mainboard/asus/m5a88-v/get_bus_conf.c
index 6b5ae68..7aca540 100644
--- a/src/mainboard/asus/m5a88-v/get_bus_conf.c
+++ b/src/mainboard/asus/m5a88-v/get_bus_conf.c
@@ -15,7 +15,6 @@
#include <device/pci.h>
#include <stdint.h>
-#include <stdlib.h>
#include <cpu/amd/multicore.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/avalue/eax-785e/get_bus_conf.c b/src/mainboard/avalue/eax-785e/get_bus_conf.c
index 6b5ae68..7aca540 100644
--- a/src/mainboard/avalue/eax-785e/get_bus_conf.c
+++ b/src/mainboard/avalue/eax-785e/get_bus_conf.c
@@ -15,7 +15,6 @@
#include <device/pci.h>
#include <stdint.h>
-#include <stdlib.h>
#include <cpu/amd/multicore.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c
index 9f7fbf8..f6077c6 100644
--- a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c
+++ b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c
@@ -17,7 +17,6 @@
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <FchPlatform.h>
-#include <stdlib.h>
#include <spd_bin.h>
#include "imc.h"
diff --git a/src/mainboard/bap/ode_e20XX/buildOpts.c b/src/mainboard/bap/ode_e20XX/buildOpts.c
index 6c405cc..daf13b6 100644
--- a/src/mainboard/bap/ode_e20XX/buildOpts.c
+++ b/src/mainboard/bap/ode_e20XX/buildOpts.c
@@ -25,7 +25,6 @@
*
*/
-#include <stdlib.h>
#include <AGESA.h>
#define INSTALL_FT3_SOCKET_SUPPORT TRUE
diff --git a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c
index 362b5ba..6bc21ad 100644
--- a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c
+++ b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c
@@ -16,7 +16,6 @@
#include <AGESA.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <FchPlatform.h>
-#include <stdlib.h>
#include <spd_bin.h>
#include "imc.h"
diff --git a/src/mainboard/biostar/a68n_5200/BiosCallOuts.c b/src/mainboard/biostar/a68n_5200/BiosCallOuts.c
index 8f55fb6..cc5081b 100644
--- a/src/mainboard/biostar/a68n_5200/BiosCallOuts.c
+++ b/src/mainboard/biostar/a68n_5200/BiosCallOuts.c
@@ -17,7 +17,6 @@
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <FchPlatform.h>
-#include <stdlib.h>
#include "imc.h"
diff --git a/src/mainboard/biostar/a68n_5200/buildOpts.c b/src/mainboard/biostar/a68n_5200/buildOpts.c
index 65b86b8..bb8527d 100644
--- a/src/mainboard/biostar/a68n_5200/buildOpts.c
+++ b/src/mainboard/biostar/a68n_5200/buildOpts.c
@@ -25,7 +25,6 @@
*
*/
-#include <stdlib.h>
#include <AGESA.h>
#define INSTALL_FT3_SOCKET_SUPPORT TRUE
diff --git a/src/mainboard/biostar/am1ml/BiosCallOuts.c b/src/mainboard/biostar/am1ml/BiosCallOuts.c
index 43db0d7..0ebd4a9 100644
--- a/src/mainboard/biostar/am1ml/BiosCallOuts.c
+++ b/src/mainboard/biostar/am1ml/BiosCallOuts.c
@@ -19,7 +19,6 @@
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <FchPlatform.h>
-#include <stdlib.h>
const BIOS_CALLOUT_STRUCT BiosCallouts[] =
{
diff --git a/src/mainboard/biostar/am1ml/buildOpts.c b/src/mainboard/biostar/am1ml/buildOpts.c
index 30c0699..74216f0 100644
--- a/src/mainboard/biostar/am1ml/buildOpts.c
+++ b/src/mainboard/biostar/am1ml/buildOpts.c
@@ -25,7 +25,6 @@
*
*/
-#include <stdlib.h>
#include <AGESA.h>
#define INSTALL_FT3_SOCKET_SUPPORT TRUE
diff --git a/src/mainboard/cavium/cn8100_sff_evb/romstage.c b/src/mainboard/cavium/cn8100_sff_evb/romstage.c
index b60b9cd..81a4100 100644
--- a/src/mainboard/cavium/cn8100_sff_evb/romstage.c
+++ b/src/mainboard/cavium/cn8100_sff_evb/romstage.c
@@ -18,7 +18,6 @@
#include <soc/sdram.h>
#include <soc/timer.h>
#include <soc/mmu.h>
-#include <stdlib.h>
#include <libbdk-hal/bdk-config.h>
extern const struct bdk_devicetree_key_value devtree[];
diff --git a/src/mainboard/elmex/pcm205400/BiosCallOuts.c b/src/mainboard/elmex/pcm205400/BiosCallOuts.c
index 6e2eaed..ee0b4f2 100644
--- a/src/mainboard/elmex/pcm205400/BiosCallOuts.c
+++ b/src/mainboard/elmex/pcm205400/BiosCallOuts.c
@@ -17,7 +17,6 @@
#include <amdlib.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <SB800.h>
-#include <stdlib.h>
static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr);
diff --git a/src/mainboard/elmex/pcm205400/buildOpts.c b/src/mainboard/elmex/pcm205400/buildOpts.c
index 863a552..9ed90be 100644
--- a/src/mainboard/elmex/pcm205400/buildOpts.c
+++ b/src/mainboard/elmex/pcm205400/buildOpts.c
@@ -25,7 +25,6 @@
*
*/
-#include <stdlib.h>
/* Select the cpu family. */
diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c
index 3acb11e..474cf5d 100644
--- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c
+++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c
@@ -13,6 +13,7 @@
#include <endian.h>
#include <string.h>
+#include <stdlib.h>
#include <smbios.h>
#include <console/console.h>
#include <arch/io.h>
diff --git a/src/mainboard/esd/atom15/gpio.c b/src/mainboard/esd/atom15/gpio.c
index b9c7829..08d4e22 100644
--- a/src/mainboard/esd/atom15/gpio.c
+++ b/src/mainboard/esd/atom15/gpio.c
@@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <soc/gpio.h>
#include "irqroute.h"
diff --git a/src/mainboard/gigabyte/ma785gm/get_bus_conf.c b/src/mainboard/gigabyte/ma785gm/get_bus_conf.c
index ee2a6ca..24e44e6 100644
--- a/src/mainboard/gigabyte/ma785gm/get_bus_conf.c
+++ b/src/mainboard/gigabyte/ma785gm/get_bus_conf.c
@@ -15,7 +15,6 @@
#include <device/pci.h>
#include <stdint.h>
-#include <stdlib.h>
#include <cpu/amd/multicore.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c b/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c
index 5c53476..16fdca1 100644
--- a/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c
+++ b/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c
@@ -15,7 +15,6 @@
#include <device/pci.h>
#include <stdint.h>
-#include <stdlib.h>
#include <cpu/amd/multicore.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/gigabyte/ma78gm/get_bus_conf.c b/src/mainboard/gigabyte/ma78gm/get_bus_conf.c
index ee2a6ca..24e44e6 100644
--- a/src/mainboard/gigabyte/ma78gm/get_bus_conf.c
+++ b/src/mainboard/gigabyte/ma78gm/get_bus_conf.c
@@ -15,7 +15,6 @@
#include <device/pci.h>
#include <stdint.h>
-#include <stdlib.h>
#include <cpu/amd/multicore.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c b/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c
index 5fc1718..233c40f 100644
--- a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c
+++ b/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c
@@ -16,7 +16,6 @@
#include <AGESA.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <SB800.h>
-#include <stdlib.h>
static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
diff --git a/src/mainboard/gizmosphere/gizmo/buildOpts.c b/src/mainboard/gizmosphere/gizmo/buildOpts.c
index b934808..1c72f7c 100644
--- a/src/mainboard/gizmosphere/gizmo/buildOpts.c
+++ b/src/mainboard/gizmosphere/gizmo/buildOpts.c
@@ -26,7 +26,6 @@
*
*/
-#include <stdlib.h>
diff --git a/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c b/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c
index 99162d8..c9e27d8 100644
--- a/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c
+++ b/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c
@@ -17,7 +17,6 @@
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <FchPlatform.h>
-#include <stdlib.h>
#include "imc.h"
diff --git a/src/mainboard/gizmosphere/gizmo2/buildOpts.c b/src/mainboard/gizmosphere/gizmo2/buildOpts.c
index 6c405cc..daf13b6 100644
--- a/src/mainboard/gizmosphere/gizmo2/buildOpts.c
+++ b/src/mainboard/gizmosphere/gizmo2/buildOpts.c
@@ -25,7 +25,6 @@
*
*/
-#include <stdlib.h>
#include <AGESA.h>
#define INSTALL_FT3_SOCKET_SUPPORT TRUE
diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c
index 70a8c19..ac6cdb5 100644
--- a/src/mainboard/google/beltino/romstage.c
+++ b/src/mainboard/google/beltino/romstage.c
@@ -15,7 +15,6 @@
*/
#include <stdint.h>
-#include <stdlib.h>
#include <cpu/intel/romstage.h>
#include <cpu/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/haswell.h>
diff --git a/src/mainboard/google/beltino/variants/mccloud/hda_verb.c b/src/mainboard/google/beltino/variants/mccloud/hda_verb.c
index 4d65f36..83bcb46 100644
--- a/src/mainboard/google/beltino/variants/mccloud/hda_verb.c
+++ b/src/mainboard/google/beltino/variants/mccloud/hda_verb.c
@@ -16,7 +16,6 @@
#ifndef HDA_VERB_H
#define HDA_VERB_H
-#include <stdlib.h>
#include <device/azalia_device.h>
diff --git a/src/mainboard/google/beltino/variants/monroe/hda_verb.c b/src/mainboard/google/beltino/variants/monroe/hda_verb.c
index 8482ec3..8657263 100644
--- a/src/mainboard/google/beltino/variants/monroe/hda_verb.c
+++ b/src/mainboard/google/beltino/variants/monroe/hda_verb.c
@@ -16,7 +16,6 @@
#ifndef HDA_VERB_H
#define HDA_VERB_H
-#include <stdlib.h>
#include <device/azalia_device.h>
diff --git a/src/mainboard/google/beltino/variants/panther/hda_verb.c b/src/mainboard/google/beltino/variants/panther/hda_verb.c
index 4d65f36..83bcb46 100644
--- a/src/mainboard/google/beltino/variants/panther/hda_verb.c
+++ b/src/mainboard/google/beltino/variants/panther/hda_verb.c
@@ -16,7 +16,6 @@
#ifndef HDA_VERB_H
#define HDA_VERB_H
-#include <stdlib.h>
#include <device/azalia_device.h>
diff --git a/src/mainboard/google/beltino/variants/tricky/hda_verb.c b/src/mainboard/google/beltino/variants/tricky/hda_verb.c
index 4d65f36..83bcb46 100644
--- a/src/mainboard/google/beltino/variants/tricky/hda_verb.c
+++ b/src/mainboard/google/beltino/variants/tricky/hda_verb.c
@@ -16,7 +16,6 @@
#ifndef HDA_VERB_H
#define HDA_VERB_H
-#include <stdlib.h>
#include <device/azalia_device.h>
diff --git a/src/mainboard/google/beltino/variants/zako/hda_verb.c b/src/mainboard/google/beltino/variants/zako/hda_verb.c
index 4d65f36..83bcb46 100644
--- a/src/mainboard/google/beltino/variants/zako/hda_verb.c
+++ b/src/mainboard/google/beltino/variants/zako/hda_verb.c
@@ -16,7 +16,6 @@
#ifndef HDA_VERB_H
#define HDA_VERB_H
-#include <stdlib.h>
#include <device/azalia_device.h>
diff --git a/src/mainboard/google/cyan/variants/banon/gpio.c b/src/mainboard/google/cyan/variants/banon/gpio.c
index 6983d91..2a3e8fc 100644
--- a/src/mainboard/google/cyan/variants/banon/gpio.c
+++ b/src/mainboard/google/cyan/variants/banon/gpio.c
@@ -16,7 +16,6 @@
#include <mainboard/google/cyan/irqroute.h>
#include <soc/gpio.h>
-#include <stdlib.h>
/* South East Community */
static const struct soc_gpio_map gpse_gpio_map[] = {
diff --git a/src/mainboard/google/cyan/variants/celes/gpio.c b/src/mainboard/google/cyan/variants/celes/gpio.c
index c416053..6f53f2e 100644
--- a/src/mainboard/google/cyan/variants/celes/gpio.c
+++ b/src/mainboard/google/cyan/variants/celes/gpio.c
@@ -16,7 +16,6 @@
#include <mainboard/google/cyan/irqroute.h>
#include <soc/gpio.h>
-#include <stdlib.h>
/* South East Community */
static const struct soc_gpio_map gpse_gpio_map[] = {
diff --git a/src/mainboard/google/cyan/variants/cyan/gpio.c b/src/mainboard/google/cyan/variants/cyan/gpio.c
index c26e7b6..05ba93e 100644
--- a/src/mainboard/google/cyan/variants/cyan/gpio.c
+++ b/src/mainboard/google/cyan/variants/cyan/gpio.c
@@ -16,7 +16,6 @@
#include <mainboard/google/cyan/irqroute.h>
#include <soc/gpio.h>
-#include <stdlib.h>
/* South East Community */
static const struct soc_gpio_map gpse_gpio_map[] = {
diff --git a/src/mainboard/google/cyan/variants/edgar/gpio.c b/src/mainboard/google/cyan/variants/edgar/gpio.c
index 2010ac5..59486af 100644
--- a/src/mainboard/google/cyan/variants/edgar/gpio.c
+++ b/src/mainboard/google/cyan/variants/edgar/gpio.c
@@ -16,7 +16,6 @@
#include <mainboard/google/cyan/irqroute.h>
#include <soc/gpio.h>
-#include <stdlib.h>
/* South East Community */
static const struct soc_gpio_map gpse_gpio_map[] = {
diff --git a/src/mainboard/google/cyan/variants/kefka/gpio.c b/src/mainboard/google/cyan/variants/kefka/gpio.c
index 0ef2842..30c5680 100644
--- a/src/mainboard/google/cyan/variants/kefka/gpio.c
+++ b/src/mainboard/google/cyan/variants/kefka/gpio.c
@@ -16,7 +16,6 @@
#include <mainboard/google/cyan/irqroute.h>
#include <soc/gpio.h>
-#include <stdlib.h>
/* South East Community */
diff --git a/src/mainboard/google/cyan/variants/reks/gpio.c b/src/mainboard/google/cyan/variants/reks/gpio.c
index e0d82cf..955dc51 100644
--- a/src/mainboard/google/cyan/variants/reks/gpio.c
+++ b/src/mainboard/google/cyan/variants/reks/gpio.c
@@ -16,7 +16,6 @@
#include <mainboard/google/cyan/irqroute.h>
#include <soc/gpio.h>
-#include <stdlib.h>
/* South East Community */
static const struct soc_gpio_map gpse_gpio_map[] = {
diff --git a/src/mainboard/google/cyan/variants/relm/gpio.c b/src/mainboard/google/cyan/variants/relm/gpio.c
index 9cb80e6..dd51eb3 100644
--- a/src/mainboard/google/cyan/variants/relm/gpio.c
+++ b/src/mainboard/google/cyan/variants/relm/gpio.c
@@ -16,7 +16,6 @@
#include <mainboard/google/cyan/irqroute.h>
#include <soc/gpio.h>
-#include <stdlib.h>
/* South East Community */
diff --git a/src/mainboard/google/cyan/variants/setzer/gpio.c b/src/mainboard/google/cyan/variants/setzer/gpio.c
index 83f742e..64a0a83 100644
--- a/src/mainboard/google/cyan/variants/setzer/gpio.c
+++ b/src/mainboard/google/cyan/variants/setzer/gpio.c
@@ -16,7 +16,6 @@
#include <mainboard/google/cyan/irqroute.h>
#include <soc/gpio.h>
-#include <stdlib.h>
/* South East Community */
diff --git a/src/mainboard/google/cyan/variants/terra/gpio.c b/src/mainboard/google/cyan/variants/terra/gpio.c
index b4feebf..dc10cef 100644
--- a/src/mainboard/google/cyan/variants/terra/gpio.c
+++ b/src/mainboard/google/cyan/variants/terra/gpio.c
@@ -16,7 +16,6 @@
#include <mainboard/google/cyan/irqroute.h>
#include <soc/gpio.h>
-#include <stdlib.h>
/* South East Community */
static const struct soc_gpio_map gpse_gpio_map[] = {
diff --git a/src/mainboard/google/cyan/variants/ultima/gpio.c b/src/mainboard/google/cyan/variants/ultima/gpio.c
index fe8c934..3cae313 100644
--- a/src/mainboard/google/cyan/variants/ultima/gpio.c
+++ b/src/mainboard/google/cyan/variants/ultima/gpio.c
@@ -16,7 +16,6 @@
#include <mainboard/google/cyan/irqroute.h>
#include <soc/gpio.h>
-#include <stdlib.h>
/* South East Community */
static const struct soc_gpio_map gpse_gpio_map[] = {
diff --git a/src/mainboard/google/cyan/variants/wizpig/gpio.c b/src/mainboard/google/cyan/variants/wizpig/gpio.c
index affe893..ecd74ef 100644
--- a/src/mainboard/google/cyan/variants/wizpig/gpio.c
+++ b/src/mainboard/google/cyan/variants/wizpig/gpio.c
@@ -16,7 +16,6 @@
#include <mainboard/google/cyan/irqroute.h>
#include <soc/gpio.h>
-#include <stdlib.h>
/* South East Community */
static const struct soc_gpio_map gpse_gpio_map[] = {
diff --git a/src/mainboard/google/daisy/memory.c b/src/mainboard/google/daisy/memory.c
index 009604b..c5b752c 100644
--- a/src/mainboard/google/daisy/memory.c
+++ b/src/mainboard/google/daisy/memory.c
@@ -20,7 +20,6 @@
#include <soc/dmc.h>
#include <soc/clk.h>
#include <stddef.h>
-#include <stdlib.h>
const struct mem_timings mem_timings[] = {
{
diff --git a/src/mainboard/google/foster/pmic.c b/src/mainboard/google/foster/pmic.c
index d8b1fa0..5918d49 100644
--- a/src/mainboard/google/foster/pmic.c
+++ b/src/mainboard/google/foster/pmic.c
@@ -19,7 +19,6 @@
#include <delay.h>
#include <device/i2c_simple.h>
#include <stdint.h>
-#include <stdlib.h>
#include <reset.h>
#include "pmic.h"
diff --git a/src/mainboard/google/gale/boardid.c b/src/mainboard/google/gale/boardid.c
index 96fc936..082cc26 100644
--- a/src/mainboard/google/gale/boardid.c
+++ b/src/mainboard/google/gale/boardid.c
@@ -16,7 +16,6 @@
#include <boardid.h>
#include <gpio.h>
#include <console/console.h>
-#include <stdlib.h>
/*
* Gale boards dedicate to the board ID three GPIOs in ternary mode: 64, 65
diff --git a/src/mainboard/google/glados/mainboard.c b/src/mainboard/google/glados/mainboard.c
index 8b04a65..19dd316 100644
--- a/src/mainboard/google/glados/mainboard.c
+++ b/src/mainboard/google/glados/mainboard.c
@@ -20,7 +20,6 @@
#include <console/console.h>
#include <device/device.h>
#include <gpio.h>
-#include <stdlib.h>
#include <soc/nhlt.h>
#include <variant/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/mainboard/google/gru/boardid.c b/src/mainboard/google/gru/boardid.c
index 4630a91..efba922 100644
--- a/src/mainboard/google/gru/boardid.c
+++ b/src/mainboard/google/gru/boardid.c
@@ -16,7 +16,6 @@
#include <boardid.h>
#include <console/console.h>
#include <gpio.h>
-#include <stdlib.h>
#include <soc/saradc.h>
static const int id_readings[] = {
diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
index 9db26c7..4c2483f 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c
+++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
@@ -16,7 +16,6 @@
#include <baseboard/variants.h>
#include <soc/gpio.h>
#include <soc/southbridge.h>
-#include <stdlib.h>
#include <boardid.h>
#include <variant/gpio.h>
diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c
index e09785d..42637e7 100644
--- a/src/mainboard/google/link/i915.c
+++ b/src/mainboard/google/link/i915.c
@@ -15,7 +15,6 @@
#include <types.h>
#include <string.h>
-#include <stdlib.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
diff --git a/src/mainboard/google/link/i915io.c b/src/mainboard/google/link/i915io.c
index 5ebb42d..b669d58 100644
--- a/src/mainboard/google/link/i915io.c
+++ b/src/mainboard/google/link/i915io.c
@@ -14,7 +14,6 @@
*/
#include <stdint.h>
-#include <stdlib.h>
#include "i915io.h"
struct iodef iodefs[] = {
diff --git a/src/mainboard/google/nyan/pmic.c b/src/mainboard/google/nyan/pmic.c
index d226459..cfe0a8c 100644
--- a/src/mainboard/google/nyan/pmic.c
+++ b/src/mainboard/google/nyan/pmic.c
@@ -19,7 +19,6 @@
#include <delay.h>
#include <device/i2c_simple.h>
#include <stdint.h>
-#include <stdlib.h>
#include <reset.h>
#include "pmic.h"
diff --git a/src/mainboard/google/nyan_big/boardid.c b/src/mainboard/google/nyan_big/boardid.c
index 2a2911c..49a9938 100644
--- a/src/mainboard/google/nyan_big/boardid.c
+++ b/src/mainboard/google/nyan_big/boardid.c
@@ -16,7 +16,6 @@
#include <boardid.h>
#include <console/console.h>
#include <gpio.h>
-#include <stdlib.h>
uint32_t board_id(void)
{
diff --git a/src/mainboard/google/nyan_big/pmic.c b/src/mainboard/google/nyan_big/pmic.c
index 948d867..9e44f54 100644
--- a/src/mainboard/google/nyan_big/pmic.c
+++ b/src/mainboard/google/nyan_big/pmic.c
@@ -19,7 +19,6 @@
#include <delay.h>
#include <device/i2c_simple.h>
#include <stdint.h>
-#include <stdlib.h>
#include <reset.h>
#include "pmic.h"
diff --git a/src/mainboard/google/nyan_blaze/boardid.c b/src/mainboard/google/nyan_blaze/boardid.c
index 2a2911c..49a9938 100644
--- a/src/mainboard/google/nyan_blaze/boardid.c
+++ b/src/mainboard/google/nyan_blaze/boardid.c
@@ -16,7 +16,6 @@
#include <boardid.h>
#include <console/console.h>
#include <gpio.h>
-#include <stdlib.h>
uint32_t board_id(void)
{
diff --git a/src/mainboard/google/nyan_blaze/pmic.c b/src/mainboard/google/nyan_blaze/pmic.c
index 948d867..9e44f54 100644
--- a/src/mainboard/google/nyan_blaze/pmic.c
+++ b/src/mainboard/google/nyan_blaze/pmic.c
@@ -19,7 +19,6 @@
#include <delay.h>
#include <device/i2c_simple.h>
#include <stdint.h>
-#include <stdlib.h>
#include <reset.h>
#include "pmic.h"
diff --git a/src/mainboard/google/oak/boardid.c b/src/mainboard/google/oak/boardid.c
index 91e2df3..ada2de5 100644
--- a/src/mainboard/google/oak/boardid.c
+++ b/src/mainboard/google/oak/boardid.c
@@ -16,7 +16,6 @@
#include <boardid.h>
#include <gpio.h>
#include <console/console.h>
-#include <stdlib.h>
#include "gpio.h"
static int board_id_value = -1;
diff --git a/src/mainboard/google/oak/sdram_configs.c b/src/mainboard/google/oak/sdram_configs.c
index 65b12ce..3419108 100644
--- a/src/mainboard/google/oak/sdram_configs.c
+++ b/src/mainboard/google/oak/sdram_configs.c
@@ -16,7 +16,6 @@
#include <boardid.h>
#include <console/console.h>
#include <soc/emi.h>
-#include <stdlib.h>
static const struct mt8173_sdram_params sdram_configs[] = {
#include "sdram_inf/sdram-lpddr3-H9CCNNN8GTMLAR-2GB.inc" /* ram_code = 0000 */
diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c
index 0441e52..da958c08 100644
--- a/src/mainboard/google/peach_pit/mainboard.c
+++ b/src/mainboard/google/peach_pit/mainboard.c
@@ -33,7 +33,6 @@
#include <soc/dp.h>
#include <soc/fimd.h>
#include <soc/usb.h>
-#include <stdlib.h>
#include <string.h>
#include <symbols.h>
#include <vbe.h>
diff --git a/src/mainboard/google/peach_pit/memory.c b/src/mainboard/google/peach_pit/memory.c
index a5e3d9e..541e3b0 100644
--- a/src/mainboard/google/peach_pit/memory.c
+++ b/src/mainboard/google/peach_pit/memory.c
@@ -19,7 +19,6 @@
#include <soc/gpio.h>
#include <soc/setup.h>
#include <stddef.h>
-#include <stdlib.h>
const struct mem_timings mem_timings = {
.mem_manuf = MEM_MANUF_SAMSUNG,
diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c
index fdbe534..0c2cb3e 100644
--- a/src/mainboard/google/peach_pit/romstage.c
+++ b/src/mainboard/google/peach_pit/romstage.c
@@ -33,7 +33,6 @@
#include <soc/setup.h>
#include <soc/trustzone.h>
#include <soc/wakeup.h>
-#include <stdlib.h>
#include <timestamp.h>
#include <types.h>
diff --git a/src/mainboard/google/rambi/variants/banjo/gpio.c b/src/mainboard/google/rambi/variants/banjo/gpio.c
index bfb2c9a..e22c8db 100644
--- a/src/mainboard/google/rambi/variants/banjo/gpio.c
+++ b/src/mainboard/google/rambi/variants/banjo/gpio.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <soc/gpio.h>
#include <mainboard/google/rambi/irqroute.h>
diff --git a/src/mainboard/google/rambi/variants/candy/gpio.c b/src/mainboard/google/rambi/variants/candy/gpio.c
index 3cbfbaf..61050e5 100644
--- a/src/mainboard/google/rambi/variants/candy/gpio.c
+++ b/src/mainboard/google/rambi/variants/candy/gpio.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <soc/gpio.h>
#include <mainboard/google/rambi/irqroute.h>
diff --git a/src/mainboard/google/rambi/variants/clapper/gpio.c b/src/mainboard/google/rambi/variants/clapper/gpio.c
index 385b406..17303c3 100644
--- a/src/mainboard/google/rambi/variants/clapper/gpio.c
+++ b/src/mainboard/google/rambi/variants/clapper/gpio.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <soc/gpio.h>
#include <mainboard/google/rambi/irqroute.h>
diff --git a/src/mainboard/google/rambi/variants/enguarde/gpio.c b/src/mainboard/google/rambi/variants/enguarde/gpio.c
index 2802aa6..784ed23 100644
--- a/src/mainboard/google/rambi/variants/enguarde/gpio.c
+++ b/src/mainboard/google/rambi/variants/enguarde/gpio.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <soc/gpio.h>
#include <mainboard/google/rambi/irqroute.h>
diff --git a/src/mainboard/google/rambi/variants/glimmer/gpio.c b/src/mainboard/google/rambi/variants/glimmer/gpio.c
index 8cfe90e..504d64a 100644
--- a/src/mainboard/google/rambi/variants/glimmer/gpio.c
+++ b/src/mainboard/google/rambi/variants/glimmer/gpio.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <soc/gpio.h>
#include <mainboard/google/rambi/irqroute.h>
diff --git a/src/mainboard/google/rambi/variants/gnawty/gpio.c b/src/mainboard/google/rambi/variants/gnawty/gpio.c
index e79dc5a..7e2361c 100644
--- a/src/mainboard/google/rambi/variants/gnawty/gpio.c
+++ b/src/mainboard/google/rambi/variants/gnawty/gpio.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <soc/gpio.h>
#include <mainboard/google/rambi/irqroute.h>
diff --git a/src/mainboard/google/rambi/variants/heli/gpio.c b/src/mainboard/google/rambi/variants/heli/gpio.c
index 2a61c55..bcb1430 100644
--- a/src/mainboard/google/rambi/variants/heli/gpio.c
+++ b/src/mainboard/google/rambi/variants/heli/gpio.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <soc/gpio.h>
#include <mainboard/google/rambi/irqroute.h>
diff --git a/src/mainboard/google/rambi/variants/kip/gpio.c b/src/mainboard/google/rambi/variants/kip/gpio.c
index 3d79d37..56942bd 100644
--- a/src/mainboard/google/rambi/variants/kip/gpio.c
+++ b/src/mainboard/google/rambi/variants/kip/gpio.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <soc/gpio.h>
#include <mainboard/google/rambi/irqroute.h>
diff --git a/src/mainboard/google/rambi/variants/ninja/gpio.c b/src/mainboard/google/rambi/variants/ninja/gpio.c
index 85d565e..2d8285c 100644
--- a/src/mainboard/google/rambi/variants/ninja/gpio.c
+++ b/src/mainboard/google/rambi/variants/ninja/gpio.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <soc/gpio.h>
#include <mainboard/google/rambi/irqroute.h>
diff --git a/src/mainboard/google/rambi/variants/orco/gpio.c b/src/mainboard/google/rambi/variants/orco/gpio.c
index f2bbe8a..afa50cf 100644
--- a/src/mainboard/google/rambi/variants/orco/gpio.c
+++ b/src/mainboard/google/rambi/variants/orco/gpio.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <soc/gpio.h>
#include <mainboard/google/rambi/irqroute.h>
diff --git a/src/mainboard/google/rambi/variants/quawks/gpio.c b/src/mainboard/google/rambi/variants/quawks/gpio.c
index 3d79d37..56942bd 100644
--- a/src/mainboard/google/rambi/variants/quawks/gpio.c
+++ b/src/mainboard/google/rambi/variants/quawks/gpio.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <soc/gpio.h>
#include <mainboard/google/rambi/irqroute.h>
diff --git a/src/mainboard/google/rambi/variants/rambi/gpio.c b/src/mainboard/google/rambi/variants/rambi/gpio.c
index 3d79d37..56942bd 100644
--- a/src/mainboard/google/rambi/variants/rambi/gpio.c
+++ b/src/mainboard/google/rambi/variants/rambi/gpio.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <soc/gpio.h>
#include <mainboard/google/rambi/irqroute.h>
diff --git a/src/mainboard/google/rambi/variants/squawks/gpio.c b/src/mainboard/google/rambi/variants/squawks/gpio.c
index 3d79d37..56942bd 100644
--- a/src/mainboard/google/rambi/variants/squawks/gpio.c
+++ b/src/mainboard/google/rambi/variants/squawks/gpio.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <soc/gpio.h>
#include <mainboard/google/rambi/irqroute.h>
diff --git a/src/mainboard/google/rambi/variants/sumo/gpio.c b/src/mainboard/google/rambi/variants/sumo/gpio.c
index 0856c29..c4cc40a 100644
--- a/src/mainboard/google/rambi/variants/sumo/gpio.c
+++ b/src/mainboard/google/rambi/variants/sumo/gpio.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <soc/gpio.h>
#include <mainboard/google/rambi/irqroute.h>
diff --git a/src/mainboard/google/rambi/variants/swanky/gpio.c b/src/mainboard/google/rambi/variants/swanky/gpio.c
index a713549..3b62880 100644
--- a/src/mainboard/google/rambi/variants/swanky/gpio.c
+++ b/src/mainboard/google/rambi/variants/swanky/gpio.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <soc/gpio.h>
#include <mainboard/google/rambi/irqroute.h>
diff --git a/src/mainboard/google/rambi/variants/winky/gpio.c b/src/mainboard/google/rambi/variants/winky/gpio.c
index dcdf6f5..9c3a338 100644
--- a/src/mainboard/google/rambi/variants/winky/gpio.c
+++ b/src/mainboard/google/rambi/variants/winky/gpio.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <soc/gpio.h>
#include <mainboard/google/rambi/irqroute.h>
diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c
index 25f8d27..2ccdb05 100644
--- a/src/mainboard/google/slippy/variants/falco/romstage.c
+++ b/src/mainboard/google/slippy/variants/falco/romstage.c
@@ -15,7 +15,6 @@
*/
#include <stdint.h>
-#include <stdlib.h>
#include <string.h>
#include <cbfs.h>
#include <console/console.h>
diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c
index b95c6e1..47f45c7 100644
--- a/src/mainboard/google/slippy/variants/leon/romstage.c
+++ b/src/mainboard/google/slippy/variants/leon/romstage.c
@@ -15,7 +15,6 @@
*/
#include <stdint.h>
-#include <stdlib.h>
#include <string.h>
#include <cbfs.h>
#include <console/console.h>
diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c
index 37c7853..d121227 100644
--- a/src/mainboard/google/slippy/variants/peppy/romstage.c
+++ b/src/mainboard/google/slippy/variants/peppy/romstage.c
@@ -15,7 +15,6 @@
*/
#include <stdint.h>
-#include <stdlib.h>
#include <string.h>
#include <cbfs.h>
#include <console/console.h>
diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c
index 731b357..2d468c0 100644
--- a/src/mainboard/google/slippy/variants/wolf/romstage.c
+++ b/src/mainboard/google/slippy/variants/wolf/romstage.c
@@ -15,7 +15,6 @@
*/
#include <stdint.h>
-#include <stdlib.h>
#include <string.h>
#include <cbfs.h>
#include <console/console.h>
diff --git a/src/mainboard/google/smaug/boardid.c b/src/mainboard/google/smaug/boardid.c
index 2512f83..74f6f11 100644
--- a/src/mainboard/google/smaug/boardid.c
+++ b/src/mainboard/google/smaug/boardid.c
@@ -15,7 +15,6 @@
#include <boardid.h>
#include <soc/sdram.h>
-#include <stdlib.h>
#include "gpio.h"
diff --git a/src/mainboard/google/smaug/pmic.c b/src/mainboard/google/smaug/pmic.c
index a6e4574..bb4d25a 100644
--- a/src/mainboard/google/smaug/pmic.c
+++ b/src/mainboard/google/smaug/pmic.c
@@ -19,7 +19,6 @@
#include <delay.h>
#include <device/i2c_simple.h>
#include <stdint.h>
-#include <stdlib.h>
#include <reset.h>
#include "pmic.h"
diff --git a/src/mainboard/google/storm/boardid.c b/src/mainboard/google/storm/boardid.c
index 87f6d2a..d952155 100644
--- a/src/mainboard/google/storm/boardid.c
+++ b/src/mainboard/google/storm/boardid.c
@@ -16,7 +16,6 @@
#include <boardid.h>
#include <gpio.h>
#include <console/console.h>
-#include <stdlib.h>
/*
* Storm boards dedicate to the board ID three GPIOs in tertiary mode: 29, 30
diff --git a/src/mainboard/google/urara/boardid.c b/src/mainboard/google/urara/boardid.c
index 9a6b64e..ef5d401 100644
--- a/src/mainboard/google/urara/boardid.c
+++ b/src/mainboard/google/urara/boardid.c
@@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <string.h>
#include <boardid.h>
diff --git a/src/mainboard/google/veyron/boardid.c b/src/mainboard/google/veyron/boardid.c
index c9c68cc..bf311cf 100644
--- a/src/mainboard/google/veyron/boardid.c
+++ b/src/mainboard/google/veyron/boardid.c
@@ -16,7 +16,6 @@
#include <boardid.h>
#include <console/console.h>
#include <gpio.h>
-#include <stdlib.h>
uint32_t board_id(void)
{
diff --git a/src/mainboard/google/veyron/romstage.c b/src/mainboard/google/veyron/romstage.c
index 3870b63..eba96c4 100644
--- a/src/mainboard/google/veyron/romstage.c
+++ b/src/mainboard/google/veyron/romstage.c
@@ -27,7 +27,6 @@
#include <soc/grf.h>
#include <soc/rk808.h>
#include <soc/tsadc.h>
-#include <stdlib.h>
#include <symbols.h>
#include <timestamp.h>
#include <types.h>
diff --git a/src/mainboard/google/veyron_mickey/boardid.c b/src/mainboard/google/veyron_mickey/boardid.c
index 3833dbe..9c53e37 100644
--- a/src/mainboard/google/veyron_mickey/boardid.c
+++ b/src/mainboard/google/veyron_mickey/boardid.c
@@ -16,7 +16,6 @@
#include <boardid.h>
#include <console/console.h>
#include <gpio.h>
-#include <stdlib.h>
uint32_t board_id(void)
{
diff --git a/src/mainboard/google/veyron_mickey/romstage.c b/src/mainboard/google/veyron_mickey/romstage.c
index c8a9842..d20bdb4 100644
--- a/src/mainboard/google/veyron_mickey/romstage.c
+++ b/src/mainboard/google/veyron_mickey/romstage.c
@@ -27,7 +27,6 @@
#include <soc/grf.h>
#include <soc/rk808.h>
#include <soc/tsadc.h>
-#include <stdlib.h>
#include <symbols.h>
#include <timestamp.h>
#include <types.h>
diff --git a/src/mainboard/google/veyron_rialto/boardid.c b/src/mainboard/google/veyron_rialto/boardid.c
index 3833dbe..9c53e37 100644
--- a/src/mainboard/google/veyron_rialto/boardid.c
+++ b/src/mainboard/google/veyron_rialto/boardid.c
@@ -16,7 +16,6 @@
#include <boardid.h>
#include <console/console.h>
#include <gpio.h>
-#include <stdlib.h>
uint32_t board_id(void)
{
diff --git a/src/mainboard/google/veyron_rialto/romstage.c b/src/mainboard/google/veyron_rialto/romstage.c
index d9fc42b..ac651ef 100644
--- a/src/mainboard/google/veyron_rialto/romstage.c
+++ b/src/mainboard/google/veyron_rialto/romstage.c
@@ -27,7 +27,6 @@
#include <soc/grf.h>
#include <soc/rk808.h>
#include <soc/tsadc.h>
-#include <stdlib.h>
#include <symbols.h>
#include <timestamp.h>
#include <types.h>
diff --git a/src/mainboard/hp/abm/BiosCallOuts.c b/src/mainboard/hp/abm/BiosCallOuts.c
index 4728c59..df0cb34 100644
--- a/src/mainboard/hp/abm/BiosCallOuts.c
+++ b/src/mainboard/hp/abm/BiosCallOuts.c
@@ -18,7 +18,6 @@
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <FchPlatform.h>
-#include <stdlib.h>
const BIOS_CALLOUT_STRUCT BiosCallouts[] =
{
diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c
index bc1b172..f965d0d 100644
--- a/src/mainboard/hp/abm/buildOpts.c
+++ b/src/mainboard/hp/abm/buildOpts.c
@@ -30,7 +30,6 @@
* @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $
*/
-#include <stdlib.h>
#include <AGESA.h>
#define INSTALL_FT3_SOCKET_SUPPORT TRUE
diff --git a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c
index e217aa7..c1afed7 100644
--- a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c
+++ b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c
@@ -24,7 +24,6 @@
#include <cpu/amd/amdfam10_sysconf.h>
-#include <stdlib.h>
#include "mb_sysconf.h"
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c
index 2b1ac04..f36e11e 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c
@@ -19,7 +19,6 @@
#include <southbridge/amd/agesa/hudson/imc.h>
#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h>
-#include <stdlib.h>
const BIOS_CALLOUT_STRUCT BiosCallouts[] =
{
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
index c6d62ed..e56d513 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
@@ -27,7 +27,6 @@
#include "mainboard.h"
-#include <stdlib.h>
#include <vendorcode/amd/agesa/f15tn/AGESA.h>
diff --git a/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c b/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c
index 237ef2a..89ac836 100644
--- a/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c
+++ b/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c
@@ -15,7 +15,6 @@
#include <device/pci.h>
#include <stdint.h>
-#include <stdlib.h>
#include <cpu/amd/multicore.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/intel/bayleybay_fsp/gpio.c b/src/mainboard/intel/bayleybay_fsp/gpio.c
index 27b22c5..5517139 100644
--- a/src/mainboard/intel/bayleybay_fsp/gpio.c
+++ b/src/mainboard/intel/bayleybay_fsp/gpio.c
@@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <soc/gpio.h>
#include "irqroute.h"
diff --git a/src/mainboard/intel/kblrvp/mainboard.c b/src/mainboard/intel/kblrvp/mainboard.c
index 78c7ae4..d2e8719 100644
--- a/src/mainboard/intel/kblrvp/mainboard.c
+++ b/src/mainboard/intel/kblrvp/mainboard.c
@@ -18,7 +18,6 @@
#include <arch/acpi.h>
#include <device/device.h>
#include <gpio.h>
-#include <stdlib.h>
#include <soc/nhlt.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
diff --git a/src/mainboard/intel/kunimitsu/mainboard.c b/src/mainboard/intel/kunimitsu/mainboard.c
index 4c93051..be2f262 100644
--- a/src/mainboard/intel/kunimitsu/mainboard.c
+++ b/src/mainboard/intel/kunimitsu/mainboard.c
@@ -19,7 +19,6 @@
#include <console/console.h>
#include <device/device.h>
#include <gpio.h>
-#include <stdlib.h>
#include <soc/nhlt.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
diff --git a/src/mainboard/intel/minnowmax/gpio.c b/src/mainboard/intel/minnowmax/gpio.c
index b0f78c8..34d36a0 100644
--- a/src/mainboard/intel/minnowmax/gpio.c
+++ b/src/mainboard/intel/minnowmax/gpio.c
@@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <soc/gpio.h>
#include "irqroute.h"
diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c
index ed9ae4b..9acc8a0 100644
--- a/src/mainboard/intel/strago/gpio.c
+++ b/src/mainboard/intel/strago/gpio.c
@@ -16,7 +16,6 @@
#include "irqroute.h"
#include <soc/gpio.h>
-#include <stdlib.h>
#include <boardid.h>
#include "onboard.h"
#include "gpio.h"
diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
index 86999fb..2c99bd0 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
@@ -19,7 +19,6 @@
#include <amdlib.h>
#include <vendorcode/amd/cimx/sb800/SB800.h>
#include <stdint.h>
-#include <stdlib.h>
static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr);
static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
index 65986e2..7a797cb 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
@@ -25,7 +25,6 @@
*
*/
-#include <stdlib.h>
#include <vendorcode/amd/agesa/f14/AGESA.h>
diff --git a/src/mainboard/jetway/pa78vm5/get_bus_conf.c b/src/mainboard/jetway/pa78vm5/get_bus_conf.c
index ee2a6ca..24e44e6 100644
--- a/src/mainboard/jetway/pa78vm5/get_bus_conf.c
+++ b/src/mainboard/jetway/pa78vm5/get_bus_conf.c
@@ -15,7 +15,6 @@
#include <device/pci.h>
#include <stdint.h>
-#include <stdlib.h>
#include <cpu/amd/multicore.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/lenovo/g505s/BiosCallOuts.c b/src/mainboard/lenovo/g505s/BiosCallOuts.c
index 2b1ac04..f36e11e 100644
--- a/src/mainboard/lenovo/g505s/BiosCallOuts.c
+++ b/src/mainboard/lenovo/g505s/BiosCallOuts.c
@@ -19,7 +19,6 @@
#include <southbridge/amd/agesa/hudson/imc.h>
#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h>
-#include <stdlib.h>
const BIOS_CALLOUT_STRUCT BiosCallouts[] =
{
diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c
index c3e40ce..3adf20d9 100644
--- a/src/mainboard/lenovo/g505s/buildOpts.c
+++ b/src/mainboard/lenovo/g505s/buildOpts.c
@@ -27,7 +27,6 @@
#include "mainboard.h"
-#include <stdlib.h>
#include <vendorcode/amd/agesa/f15tn/AGESA.h>
diff --git a/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c b/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c
index eca687c..404e18d 100644
--- a/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c
+++ b/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c
@@ -17,7 +17,6 @@
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <SB800.h>
#include <southbridge/amd/cimx/sb800/gpio_oem.h>
-#include <stdlib.h>
/* Should AGESA_GNB_PCIE_SLOT_RESET use agesa_NoopSuccess?
*
diff --git a/src/mainboard/lippert/frontrunner-af/buildOpts.c b/src/mainboard/lippert/frontrunner-af/buildOpts.c
index 0563243..89d9872 100644
--- a/src/mainboard/lippert/frontrunner-af/buildOpts.c
+++ b/src/mainboard/lippert/frontrunner-af/buildOpts.c
@@ -25,7 +25,6 @@
*
*/
-#include <stdlib.h>
diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c
index 6530276..74f3aba 100644
--- a/src/mainboard/lippert/frontrunner-af/mainboard.c
+++ b/src/mainboard/lippert/frontrunner-af/mainboard.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/mainboard/lippert/frontrunner-af/sema.c b/src/mainboard/lippert/frontrunner-af/sema.c
index 757d8da..02b4544 100644
--- a/src/mainboard/lippert/frontrunner-af/sema.c
+++ b/src/mainboard/lippert/frontrunner-af/sema.c
@@ -11,7 +11,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <arch/io.h>
#include <console/console.h>
#include <device/device.h>
diff --git a/src/mainboard/lippert/toucan-af/BiosCallOuts.c b/src/mainboard/lippert/toucan-af/BiosCallOuts.c
index 4841008..963a377 100644
--- a/src/mainboard/lippert/toucan-af/BiosCallOuts.c
+++ b/src/mainboard/lippert/toucan-af/BiosCallOuts.c
@@ -17,7 +17,6 @@
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <SB800.h>
#include <southbridge/amd/cimx/sb800/gpio_oem.h>
-#include <stdlib.h>
/* Should AGESA_GNB_PCIE_SLOT_RESET use agesa_NoopSuccess?
*
diff --git a/src/mainboard/lippert/toucan-af/buildOpts.c b/src/mainboard/lippert/toucan-af/buildOpts.c
index 0563243..89d9872 100644
--- a/src/mainboard/lippert/toucan-af/buildOpts.c
+++ b/src/mainboard/lippert/toucan-af/buildOpts.c
@@ -25,7 +25,6 @@
*
*/
-#include <stdlib.h>
diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c
index b7126ea..59f140b 100644
--- a/src/mainboard/lippert/toucan-af/mainboard.c
+++ b/src/mainboard/lippert/toucan-af/mainboard.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/mainboard/msi/ms7721/BiosCallOuts.c b/src/mainboard/msi/ms7721/BiosCallOuts.c
index b3cac1d..eb3c43c 100644
--- a/src/mainboard/msi/ms7721/BiosCallOuts.c
+++ b/src/mainboard/msi/ms7721/BiosCallOuts.c
@@ -19,7 +19,6 @@
#include <northbridge/amd/agesa/state_machine.h>
#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h>
-#include <stdlib.h>
const BIOS_CALLOUT_STRUCT BiosCallouts[] =
{
diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c
index 9e57e39..2dd223d 100644
--- a/src/mainboard/msi/ms7721/buildOpts.c
+++ b/src/mainboard/msi/ms7721/buildOpts.c
@@ -25,7 +25,6 @@
*
*/
-#include <stdlib.h>
#include <vendorcode/amd/agesa/f15tn/AGESA.h>
diff --git a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c
index 74b14b4..02e191d 100644
--- a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c
+++ b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c
@@ -24,7 +24,6 @@
#include <cpu/amd/amdfam10_sysconf.h>
-#include <stdlib.h>
#include "mb_sysconf.h"
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
diff --git a/src/mainboard/opencellular/elgon/romstage.c b/src/mainboard/opencellular/elgon/romstage.c
index 94c09ec..d907351 100644
--- a/src/mainboard/opencellular/elgon/romstage.c
+++ b/src/mainboard/opencellular/elgon/romstage.c
@@ -19,7 +19,6 @@
#include <soc/sdram.h>
#include <soc/timer.h>
#include <soc/mmu.h>
-#include <stdlib.h>
#include <console/console.h>
#include <program_loading.h>
#include <libbdk-hal/bdk-config.h>
diff --git a/src/mainboard/opencellular/rotundu/variants/rotundu/gpio.c b/src/mainboard/opencellular/rotundu/variants/rotundu/gpio.c
index 78d1ad6..4751c00 100644
--- a/src/mainboard/opencellular/rotundu/variants/rotundu/gpio.c
+++ b/src/mainboard/opencellular/rotundu/variants/rotundu/gpio.c
@@ -15,7 +15,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <soc/gpio.h>
#include "../../irqroute.h"
diff --git a/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c b/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c
index c9d5426..9dc3f2c 100644
--- a/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c
+++ b/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c
@@ -15,7 +15,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <soc/gpio.h>
#include "../../irqroute.h"
diff --git a/src/mainboard/pcengines/apu1/BiosCallOuts.c b/src/mainboard/pcengines/apu1/BiosCallOuts.c
index 906ecb6..561ecf3 100644
--- a/src/mainboard/pcengines/apu1/BiosCallOuts.c
+++ b/src/mainboard/pcengines/apu1/BiosCallOuts.c
@@ -17,7 +17,6 @@
#include <spd_bin.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <SB800.h>
-#include <stdlib.h>
#include "gpio_ftns.h"
static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c
index 1f73eee..3c037e5 100644
--- a/src/mainboard/pcengines/apu1/buildOpts.c
+++ b/src/mainboard/pcengines/apu1/buildOpts.c
@@ -25,7 +25,6 @@
*
*/
-#include <stdlib.h>
/* Select the CPU family. */
diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c
index 8fc3d5a..f1a4984 100644
--- a/src/mainboard/pcengines/apu2/BiosCallOuts.c
+++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c
@@ -17,7 +17,6 @@
#include <spd_bin.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <FchPlatform.h>
-#include <stdlib.h>
#include "gpio_ftns.h"
#include "imc.h"
diff --git a/src/mainboard/roda/rk886ex/m3885.c b/src/mainboard/roda/rk886ex/m3885.c
index 60a4f48..d4e90b8 100644
--- a/src/mainboard/roda/rk886ex/m3885.c
+++ b/src/mainboard/roda/rk886ex/m3885.c
@@ -15,7 +15,6 @@
*/
#include <types.h>
-#include <stdlib.h>
#include <console/console.h>
#include <arch/io.h>
#include <delay.h>
diff --git a/src/mainboard/roda/rk9/mainboard.c b/src/mainboard/roda/rk9/mainboard.c
index 3f72398..6057901 100644
--- a/src/mainboard/roda/rk9/mainboard.c
+++ b/src/mainboard/roda/rk9/mainboard.c
@@ -14,7 +14,6 @@
*/
#include <stdint.h>
-#include <stdlib.h>
#include <arch/io.h>
#include <device/device.h>
#include <drivers/intel/gma/int15.h>
diff --git a/src/mainboard/scaleway/tagada/bmcinfo.c b/src/mainboard/scaleway/tagada/bmcinfo.c
index 237d551..cafde0c 100644
--- a/src/mainboard/scaleway/tagada/bmcinfo.c
+++ b/src/mainboard/scaleway/tagada/bmcinfo.c
@@ -15,7 +15,6 @@
*/
#include <stdint.h>
-#include <stdlib.h>
#include <arch/early_variables.h>
#include <console/console.h>
#include <console/uart.h>
diff --git a/src/mainboard/siemens/mc_tcu3/gpio.c b/src/mainboard/siemens/mc_tcu3/gpio.c
index 23c6f96..bc952f4 100644
--- a/src/mainboard/siemens/mc_tcu3/gpio.c
+++ b/src/mainboard/siemens/mc_tcu3/gpio.c
@@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <soc/gpio.h>
#include "irqroute.h"
diff --git a/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c b/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c
index ea58e02..f5895b1 100644
--- a/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c
+++ b/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c
@@ -14,6 +14,7 @@
*/
#include <stdint.h>
+#include <stdlib.h>
#include <string.h>
#include <soc/otp.h>
#include <soc/sdram.h>
diff --git a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c
index 6279d9c..26af74b 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c
@@ -24,7 +24,6 @@
#include <cpu/amd/amdfam10_sysconf.h>
-#include <stdlib.h>
#include "mb_sysconf.h"
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
diff --git a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
index f32312d..2d5d999 100644
--- a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
+++ b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
@@ -24,7 +24,6 @@
#include <cpu/amd/amdfam10_sysconf.h>
-#include <stdlib.h>
#include "mb_sysconf.h"
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
diff --git a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c
index 8bc96c2..504434b 100644
--- a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c
+++ b/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c
@@ -16,7 +16,6 @@
#include <device/pci.h>
#include <device/pci_ops.h>
#include <stdint.h>
-#include <stdlib.h>
#include <cpu/amd/multicore.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/ti/beaglebone/leds.c b/src/mainboard/ti/beaglebone/leds.c
index a4889b9..dd1471d 100644
--- a/src/mainboard/ti/beaglebone/leds.c
+++ b/src/mainboard/ti/beaglebone/leds.c
@@ -14,7 +14,6 @@
#include <assert.h>
#include <cpu/ti/am335x/gpio.h>
-#include <stdlib.h>
#include "leds.h"
diff --git a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
index f589ef6..6e7cc9e 100644
--- a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
+++ b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
@@ -24,7 +24,6 @@
#include <cpu/amd/amdfam10_sysconf.h>
-#include <stdlib.h>
#include "mb_sysconf.h"
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
diff --git a/src/northbridge/amd/agesa/family12/dimmSpd.c b/src/northbridge/amd/agesa/family12/dimmSpd.c
index 822c577..a709679 100644
--- a/src/northbridge/amd/agesa/family12/dimmSpd.c
+++ b/src/northbridge/amd/agesa/family12/dimmSpd.c
@@ -27,7 +27,6 @@
*
*/
-#include <stdlib.h>
#include <Porting.h>
#include <AGESA.h>
diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c
index 290ab16..d1ddf12 100644
--- a/src/northbridge/amd/agesa/family12/northbridge.c
+++ b/src/northbridge/amd/agesa/family12/northbridge.c
@@ -22,7 +22,6 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/hypertransport.h>
-#include <stdlib.h>
#include <string.h>
#include <lib.h>
#include <cpu/cpu.h>
diff --git a/src/northbridge/amd/agesa/family14/dimmSpd.c b/src/northbridge/amd/agesa/family14/dimmSpd.c
index 9877650..6525552 100644
--- a/src/northbridge/amd/agesa/family14/dimmSpd.c
+++ b/src/northbridge/amd/agesa/family14/dimmSpd.c
@@ -15,7 +15,6 @@
#include <device/pci_def.h>
#include <device/device.h>
-#include <stdlib.h>
#include <OEM.h> /* SMBUS0_BASE_ADDRESS */
/* warning: Porting.h includes an open #pragma pack(1) */
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index a52f7ec..e4f26f6 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -22,7 +22,6 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/hypertransport.h>
-#include <stdlib.h>
#include <string.h>
#include <lib.h>
#include <cpu/cpu.h>
diff --git a/src/northbridge/amd/agesa/family15tn/dimmSpd.c b/src/northbridge/amd/agesa/family15tn/dimmSpd.c
index 7ca4709..30fd74b 100644
--- a/src/northbridge/amd/agesa/family15tn/dimmSpd.c
+++ b/src/northbridge/amd/agesa/family15tn/dimmSpd.c
@@ -15,7 +15,6 @@
#include <device/pci_def.h>
#include <device/device.h>
-#include <stdlib.h>
/* warning: Porting.h includes an open #pragma pack(1) */
#include <Porting.h>
diff --git a/src/northbridge/amd/agesa/family16kb/dimmSpd.c b/src/northbridge/amd/agesa/family16kb/dimmSpd.c
index 8c453bb..78dc128 100644
--- a/src/northbridge/amd/agesa/family16kb/dimmSpd.c
+++ b/src/northbridge/amd/agesa/family16kb/dimmSpd.c
@@ -15,7 +15,6 @@
#include <device/pci_def.h>
#include <device/device.h>
-#include <stdlib.h>
/* warning: Porting.h includes an open #pragma pack(1) */
#include <Porting.h>
diff --git a/src/northbridge/amd/amdht/comlib.h b/src/northbridge/amd/amdht/comlib.h
index d497fd2..d7b53c3 100644
--- a/src/northbridge/amd/amdht/comlib.h
+++ b/src/northbridge/amd/amdht/comlib.h
@@ -20,7 +20,6 @@
#define FILECODE 0xF001
#include <inttypes.h>
-#include <stdlib.h>
#include "porting.h"
#ifdef AMD_DEBUG
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
index a78a752..7f72388 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
@@ -30,9 +30,10 @@
#include <spi_flash.h>
#include <pc80/mc146818rtc.h>
#include <inttypes.h>
+#include <stdlib.h>
+
#include "mct_d.h"
#include "mct_d_gcc.h"
-
#include "s3utils.h"
#define S3NV_FILE_NAME "s3nv"
diff --git a/src/northbridge/amd/amdmct/wrappers/mcti.h b/src/northbridge/amd/amdmct/wrappers/mcti.h
index 92dc0b8..baab526 100644
--- a/src/northbridge/amd/amdmct/wrappers/mcti.h
+++ b/src/northbridge/amd/amdmct/wrappers/mcti.h
@@ -19,7 +19,6 @@
#define MCTI_H
#include <inttypes.h>
-#include <stdlib.h>
#include <pc80/mc146818rtc.h>
struct DCTStatStruc;
diff --git a/src/northbridge/amd/pi/00660F01/dimmSpd.c b/src/northbridge/amd/pi/00660F01/dimmSpd.c
index 0de7654..91b276c 100644
--- a/src/northbridge/amd/pi/00660F01/dimmSpd.c
+++ b/src/northbridge/amd/pi/00660F01/dimmSpd.c
@@ -15,7 +15,6 @@
#include <device/pci_def.h>
#include <device/device.h>
-#include <stdlib.h>
/* warning: Porting.h includes an open #pragma pack(1) */
#include <Porting.h>
diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c
index 357a963..baa0bf1 100644
--- a/src/northbridge/intel/e7505/debug.c
+++ b/src/northbridge/intel/e7505/debug.c
@@ -13,7 +13,6 @@
#include <device/pci_def.h>
#include <console/console.h>
-#include <stdlib.h>
#include <arch/io.h>
#include <device/pci_ops.h>
#include <spd.h>
diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c
index e3d3faf..40c94fd 100644
--- a/src/northbridge/intel/e7505/northbridge.c
+++ b/src/northbridge/intel/e7505/northbridge.c
@@ -18,7 +18,6 @@
#include <device/device.h>
#include <device/pci.h>
#include <cpu/cpu.h>
-#include <stdlib.h>
#include "e7505.h"
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index 3bb1f67..18d3abe 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -30,7 +30,6 @@
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <lib.h>
-#include <stdlib.h>
#include <commonlib/helpers.h>
#include <console/console.h>
#include <cpu/x86/mtrr.h>
diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c
index 0c08197..a6aafa9 100644
--- a/src/northbridge/intel/fsp_rangeley/northbridge.c
+++ b/src/northbridge/intel/fsp_rangeley/northbridge.c
@@ -23,7 +23,6 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <stdlib.h>
#include <cpu/cpu.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
#include <cpu/x86/lapic.h>
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index f011cce..261fef5 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -19,7 +19,6 @@
#include <stdint.h>
#include <device/device.h>
#include <device/pci.h>
-#include <stdlib.h>
#include <cpu/cpu.h>
#include <boot/tables.h>
#include <arch/acpi.h>
diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
index 6fef0da..80d827b 100644
--- a/src/northbridge/intel/haswell/early_init.c
+++ b/src/northbridge/intel/haswell/early_init.c
@@ -15,7 +15,6 @@
*/
#include <stdint.h>
-#include <stdlib.h>
#include <console/console.h>
#include <device/mmio.h>
#include <device/pci_def.h>
diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c
index 1777006..ca36634 100644
--- a/src/northbridge/intel/haswell/finalize.c
+++ b/src/northbridge/intel/haswell/finalize.c
@@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <device/pci_ops.h>
#include "haswell.h"
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 0fd0228..7482747 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -29,7 +29,6 @@
#include <cpu/intel/haswell/haswell.h>
#include <drivers/intel/gma/opregion.h>
#include <southbridge/intel/lynxpoint/nvs.h>
-#include <stdlib.h>
#include <string.h>
#include "chip.h"
diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c
index a646071..b8d98a7 100644
--- a/src/northbridge/intel/haswell/minihd.c
+++ b/src/northbridge/intel/haswell/minihd.c
@@ -21,7 +21,6 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <device/mmio.h>
-#include <stdlib.h>
#include <southbridge/intel/lynxpoint/hda_verb.h>
static const u32 minihd_verb_table[] = {
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index 2b7afa8..067d5c1 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -25,7 +25,6 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include <stdlib.h>
#include <cpu/x86/smm.h>
#include <boot/tables.h>
diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c
index ef6329c..d23a843 100644
--- a/src/northbridge/intel/i440bx/northbridge.c
+++ b/src/northbridge/intel/i440bx/northbridge.c
@@ -17,7 +17,6 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <stdlib.h>
#include <cpu/cpu.h>
#include "northbridge.h"
#include "i440bx.h"
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index 91959c7..0f9f2f6 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -18,7 +18,6 @@
#include <spd.h>
#include <delay.h>
#include <stdint.h>
-#include <stdlib.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index d3ed277..344015f 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -14,7 +14,6 @@
*/
#include <stdint.h>
-#include <stdlib.h>
#include <console/console.h>
#include <arch/io.h>
#include <device/pci_ops.h>
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 82392f4..576343d 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -20,7 +20,6 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <stdlib.h>
#include <cpu/cpu.h>
#include <arch/acpi.h>
#include <cpu/intel/smm/gen1/smi.h>
diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c
index a5cac7b..f12416e 100644
--- a/src/northbridge/intel/nehalem/early_init.c
+++ b/src/northbridge/intel/nehalem/early_init.c
@@ -16,7 +16,6 @@
*/
#include <stdint.h>
-#include <stdlib.h>
#include <console/console.h>
#include <arch/io.h>
#include <device/pci_ops.h>
diff --git a/src/northbridge/intel/nehalem/finalize.c b/src/northbridge/intel/nehalem/finalize.c
index 97f6011..f57f21a 100644
--- a/src/northbridge/intel/nehalem/finalize.c
+++ b/src/northbridge/intel/nehalem/finalize.c
@@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <device/pci_ops.h>
#include "nehalem.h"
diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c
index 575c600..7e56a12 100644
--- a/src/northbridge/intel/nehalem/northbridge.c
+++ b/src/northbridge/intel/nehalem/northbridge.c
@@ -25,7 +25,6 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <stdlib.h>
#include <cpu/cpu.h>
#include "chip.h"
#include "nehalem.h"
diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c
index a0d5305..bd2d19c 100644
--- a/src/northbridge/intel/pineview/early_init.c
+++ b/src/northbridge/intel/pineview/early_init.c
@@ -15,7 +15,6 @@
*/
#include <stdint.h>
-#include <stdlib.h>
#include <console/console.h>
#include <arch/io.h>
#include <device/pci_ops.h>
diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c
index 4b67cfd..01d930b 100644
--- a/src/northbridge/intel/pineview/northbridge.c
+++ b/src/northbridge/intel/pineview/northbridge.c
@@ -20,7 +20,6 @@
#include <stdint.h>
#include <device/device.h>
#include <device/pci.h>
-#include <stdlib.h>
#include <cpu/cpu.h>
#include <boot/tables.h>
#include <arch/acpi.h>
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index ad579c6..08e873a 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -15,7 +15,6 @@
*/
#include <stdint.h>
-#include <stdlib.h>
#include <console/console.h>
#include <arch/io.h>
#include <device/pci_ops.h>
diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c
index 7051b24..a8f8603 100644
--- a/src/northbridge/intel/sandybridge/finalize.c
+++ b/src/northbridge/intel/sandybridge/finalize.c
@@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <device/pci_ops.h>
#include "sandybridge.h"
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 477c26e..d44c343 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -24,7 +24,6 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <stdlib.h>
#include <cpu/cpu.h>
#include "chip.h"
#include "sandybridge.h"
diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c
index b6616e1..f6e6671 100644
--- a/src/northbridge/intel/x4x/northbridge.c
+++ b/src/northbridge/intel/x4x/northbridge.c
@@ -20,7 +20,6 @@
#include <stdint.h>
#include <device/device.h>
#include <device/pci.h>
-#include <stdlib.h>
#include <cpu/cpu.h>
#include <boot/tables.h>
#include <arch/acpi.h>
diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c
index 163f6b1..bba8071 100644
--- a/src/northbridge/via/vx900/chrome9hd.c
+++ b/src/northbridge/via/vx900/chrome9hd.c
@@ -19,7 +19,6 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <pc80/vga_io.h>
-#include <stdlib.h>
#include "vx900.h"
diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c
index e466eb8..d0d1b0b 100644
--- a/src/security/tpm/tspi/tspi.c
+++ b/src/security/tpm/tspi/tspi.c
@@ -19,7 +19,6 @@
#include <console/console.h>
#include <security/tpm/tspi.h>
#include <security/tpm/tss.h>
-#include <stdlib.h>
#if CONFIG(VBOOT)
#include <vb2_api.h>
#include <assert.h>
diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c
index 62bc6a9..f06cbca 100644
--- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c
+++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c
@@ -7,7 +7,6 @@
#include <arch/early_variables.h>
#include <commonlib/iobuf.h>
#include <console/console.h>
-#include <stdlib.h>
#include <string.h>
#include "tss_marshaling.h"
diff --git a/src/security/vboot/secdata_mock.c b/src/security/vboot/secdata_mock.c
index 3075d33..53265c1 100644
--- a/src/security/vboot/secdata_mock.c
+++ b/src/security/vboot/secdata_mock.c
@@ -32,7 +32,6 @@
* stored in the TPM NVRAM.
*/
-#include <stdlib.h>
#include <security/tpm/tspi.h>
#include <vb2_api.h>
diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c
index 39cd614..58c2fbf 100644
--- a/src/security/vboot/secdata_tpm.c
+++ b/src/security/vboot/secdata_tpm.c
@@ -33,7 +33,6 @@
*/
#include <security/vboot/antirollback.h>
-#include <stdlib.h>
#include <string.h>
#include <security/tpm/tspi.h>
#include <vb2_api.h>
diff --git a/src/security/vboot/vboot_handoff.c b/src/security/vboot/vboot_handoff.c
index e64775e..7871e46 100644
--- a/src/security/vboot/vboot_handoff.c
+++ b/src/security/vboot/vboot_handoff.c
@@ -30,7 +30,6 @@
#include <console/console.h>
#include <console/vtxprintf.h>
#include <fmap.h>
-#include <stdlib.h>
#include <vboot_struct.h>
#include <security/vboot/vbnv.h>
#include <security/vboot/misc.h>
diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c
index 1027ae0..657e413 100644
--- a/src/soc/amd/stoneyridge/BiosCallOuts.c
+++ b/src/soc/amd/stoneyridge/BiosCallOuts.c
@@ -20,7 +20,6 @@
#include <amdblocks/BiosCallOuts.h>
#include <soc/southbridge.h>
#include <soc/pci_devs.h>
-#include <stdlib.h>
#include <amdblocks/agesawrapper.h>
#include <amdblocks/dimm_spd.h>
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index 927cce0..6d64c00 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -38,7 +38,6 @@
#include <soc/pci_devs.h>
#include <soc/iomap.h>
#include <stdint.h>
-#include <stdlib.h>
#include <string.h>
#include <arch/bert_storage.h>
diff --git a/src/soc/amd/stoneyridge/sm.c b/src/soc/amd/stoneyridge/sm.c
index 9344b2f..dc5adf0 100644
--- a/src/soc/amd/stoneyridge/sm.c
+++ b/src/soc/amd/stoneyridge/sm.c
@@ -20,7 +20,6 @@
#include <device/smbus.h>
#include <cpu/x86/lapic.h>
#include <arch/ioapic.h>
-#include <stdlib.h>
#include <soc/southbridge.h>
#include <soc/smbus.h>
diff --git a/src/soc/amd/stoneyridge/spi.c b/src/soc/amd/stoneyridge/spi.c
index c682d98..cc3d6e9 100644
--- a/src/soc/amd/stoneyridge/spi.c
+++ b/src/soc/amd/stoneyridge/spi.c
@@ -14,7 +14,6 @@
*/
#include <stdint.h>
-#include <stdlib.h>
#include <device/mmio.h>
#include <lib.h>
#include <timer.h>
diff --git a/src/soc/cavium/cn81xx/cbmem.c b/src/soc/cavium/cn81xx/cbmem.c
index bb6fa18..5a4ad19 100644
--- a/src/soc/cavium/cn81xx/cbmem.c
+++ b/src/soc/cavium/cn81xx/cbmem.c
@@ -17,7 +17,6 @@
#include <cbmem.h>
#include <soc/addressmap.h>
#include <soc/sdram.h>
-#include <stdlib.h>
#include <symbols.h>
void *cbmem_top(void)
diff --git a/src/soc/cavium/cn81xx/spi.c b/src/soc/cavium/cn81xx/spi.c
index 2ba25a2..6a5abb1 100644
--- a/src/soc/cavium/cn81xx/spi.c
+++ b/src/soc/cavium/cn81xx/spi.c
@@ -25,7 +25,6 @@
#include <soc/clock.h>
#include <spi-generic.h>
#include <spi_flash.h>
-#include <stdlib.h>
#include <timer.h>
union cavium_spi_cfg {
diff --git a/src/soc/imgtec/pistachio/cbmem.c b/src/soc/imgtec/pistachio/cbmem.c
index 112df7c..964300e 100644
--- a/src/soc/imgtec/pistachio/cbmem.c
+++ b/src/soc/imgtec/pistachio/cbmem.c
@@ -15,7 +15,6 @@
*/
#include <cbmem.h>
-#include <stdlib.h>
#include <symbols.h>
void *cbmem_top(void)
diff --git a/src/soc/imgtec/pistachio/spi.c b/src/soc/imgtec/pistachio/spi.c
index cd27ce1..13a404d 100644
--- a/src/soc/imgtec/pistachio/spi.c
+++ b/src/soc/imgtec/pistachio/spi.c
@@ -19,7 +19,6 @@
#include <soc/spi.h>
#include <spi_flash.h>
#include <spi-generic.h>
-#include <stdlib.h>
#include <string.h>
#include <timer.h>
diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c
index 9526932..5b55d2e 100644
--- a/src/soc/intel/baytrail/cpu.c
+++ b/src/soc/intel/baytrail/cpu.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <console/console.h>
#include <cpu/cpu.h>
#include <cpu/intel/common/common.h>
diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c
index 5d6d504..1933167 100644
--- a/src/soc/intel/baytrail/gfx.c
+++ b/src/soc/intel/baytrail/gfx.c
@@ -21,7 +21,6 @@
#include <device/pci_ids.h>
#include <drivers/intel/gma/opregion.h>
#include <reg_script.h>
-#include <stdlib.h>
#include <soc/gfx.h>
#include <soc/iosf.h>
#include <soc/nvs.h>
diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c
index 1715198..769e7ff 100644
--- a/src/soc/intel/baytrail/ramstage.c
+++ b/src/soc/intel/baytrail/ramstage.c
@@ -23,7 +23,6 @@
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
-#include <stdlib.h>
#include <string.h>
#include <soc/gpio.h>
diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c
index 1bc9ed1..3679b55 100644
--- a/src/soc/intel/baytrail/smihandler.c
+++ b/src/soc/intel/baytrail/smihandler.c
@@ -14,7 +14,6 @@
*/
#include <stdint.h>
-#include <stdlib.h>
#include <arch/io.h>
#include <device/pci_ops.h>
#include <console/console.h>
diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c
index 5f86a11..feab0c7 100644
--- a/src/soc/intel/braswell/cpu.c
+++ b/src/soc/intel/braswell/cpu.c
@@ -33,7 +33,6 @@
#include <soc/pattrs.h>
#include <soc/ramstage.h>
#include <soc/smm.h>
-#include <stdlib.h>
/* Core level MSRs */
static const struct reg_script core_msr_script[] = {
diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c
index d6a1cda..f8011fd 100644
--- a/src/soc/intel/braswell/ramstage.c
+++ b/src/soc/intel/braswell/ramstage.c
@@ -37,7 +37,6 @@
#include <soc/ramstage.h>
#include <soc/intel/common/acpi.h>
#include <boardid.h>
-#include <stdlib.h>
#include <string.h>
#define SHOW_PATTRS 1
diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c
index a723309..f9d931e 100644
--- a/src/soc/intel/braswell/smihandler.c
+++ b/src/soc/intel/braswell/smihandler.c
@@ -28,7 +28,6 @@
#include <soc/pm.h>
#include <spi-generic.h>
#include <stdint.h>
-#include <stdlib.h>
#include <soc/gpio.h>
/* GNVS needs to be set by coreboot initiating a software SMI. */
diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c
index 1adbbc8..f270f9b 100644
--- a/src/soc/intel/broadwell/finalize.c
+++ b/src/soc/intel/broadwell/finalize.c
@@ -20,7 +20,6 @@
#include <cpu/x86/smm.h>
#include <reg_script.h>
#include <spi-generic.h>
-#include <stdlib.h>
#include <soc/pci_devs.h>
#include <soc/lpc.h>
#include <soc/me.h>
diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c
index 319549d..9b0ee70 100644
--- a/src/soc/intel/broadwell/igd.c
+++ b/src/soc/intel/broadwell/igd.c
@@ -22,7 +22,6 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <stdlib.h>
#include <string.h>
#include <reg_script.h>
#include <cbmem.h>
diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c
index dd5e5b8..05f69b5 100644
--- a/src/soc/intel/broadwell/me.c
+++ b/src/soc/intel/broadwell/me.c
@@ -39,7 +39,7 @@
#include <soc/ramstage.h>
#include <soc/rcba.h>
#include <soc/intel/broadwell/chip.h>
-
+#include <stdlib.h>
#if CONFIG(CHROMEOS)
#include <vendorcode/google/chromeos/chromeos.h>
#include <vendorcode/google/chromeos/gnvs.h>
diff --git a/src/soc/intel/broadwell/me_status.c b/src/soc/intel/broadwell/me_status.c
index 08fd48f..3b2c680 100644
--- a/src/soc/intel/broadwell/me_status.c
+++ b/src/soc/intel/broadwell/me_status.c
@@ -16,7 +16,6 @@
#include <device/pci_ops.h>
#include <console/console.h>
#include <device/pci.h>
-#include <stdlib.h>
#include <string.h>
#include <soc/pci_devs.h>
#include <soc/me.h>
diff --git a/src/soc/intel/broadwell/minihd.c b/src/soc/intel/broadwell/minihd.c
index d44e153..ff12ac5 100644
--- a/src/soc/intel/broadwell/minihd.c
+++ b/src/soc/intel/broadwell/minihd.c
@@ -21,7 +21,6 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <device/mmio.h>
-#include <stdlib.h>
#include <soc/intel/common/hda_verb.h>
#include <soc/ramstage.h>
#include <soc/igd.h>
diff --git a/src/soc/intel/broadwell/pei_data.c b/src/soc/intel/broadwell/pei_data.c
index dfaf025..a3c8746 100644
--- a/src/soc/intel/broadwell/pei_data.c
+++ b/src/soc/intel/broadwell/pei_data.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <stdint.h>
#include <console/streams.h>
#include <soc/iomap.h>
diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c
index e1883f2..f380079 100644
--- a/src/soc/intel/broadwell/ramstage.c
+++ b/src/soc/intel/broadwell/ramstage.c
@@ -16,7 +16,6 @@
#include <arch/acpi.h>
#include <cbmem.h>
#include <device/device.h>
-#include <stdlib.h>
#include <string.h>
#include <soc/nvs.h>
#include <soc/pm.h>
diff --git a/src/soc/intel/broadwell/romstage/cpu.c b/src/soc/intel/broadwell/romstage/cpu.c
index f251652..5a45697 100644
--- a/src/soc/intel/broadwell/romstage/cpu.c
+++ b/src/soc/intel/broadwell/romstage/cpu.c
@@ -14,7 +14,6 @@
*/
#include <arch/cpu.h>
-#include <stdlib.h>
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <soc/cpu.h>
diff --git a/src/soc/intel/broadwell/romstage/power_state.c b/src/soc/intel/broadwell/romstage/power_state.c
index ca22b4e..1970c31 100644
--- a/src/soc/intel/broadwell/romstage/power_state.c
+++ b/src/soc/intel/broadwell/romstage/power_state.c
@@ -22,7 +22,6 @@
#include <device/pci_def.h>
#include <reg_script.h>
#include <stdint.h>
-#include <stdlib.h>
#include <string.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
diff --git a/src/soc/intel/broadwell/romstage/systemagent.c b/src/soc/intel/broadwell/romstage/systemagent.c
index 8be5b82..5c0224a 100644
--- a/src/soc/intel/broadwell/romstage/systemagent.c
+++ b/src/soc/intel/broadwell/romstage/systemagent.c
@@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c
index 12e458c..58a0444 100644
--- a/src/soc/intel/broadwell/serialio.c
+++ b/src/soc/intel/broadwell/serialio.c
@@ -20,7 +20,6 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <stdlib.h>
#include <soc/iobp.h>
#include <soc/nvs.h>
#include <soc/pci_devs.h>
diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c
index c6444b1..9af55c9 100644
--- a/src/soc/intel/broadwell/systemagent.c
+++ b/src/soc/intel/broadwell/systemagent.c
@@ -22,7 +22,6 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <stdlib.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <soc/cpu.h>
#include <soc/iomap.h>
diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c
index bc4ae02..6c02418 100644
--- a/src/soc/intel/cannonlake/finalize.c
+++ b/src/soc/intel/cannonlake/finalize.c
@@ -33,7 +33,6 @@
#include <soc/pm.h>
#include <soc/smbus.h>
#include <soc/systemagent.h>
-#include <stdlib.h>
#define CAMERA1_CLK 0x8000 /* Camera 1 Clock */
#define CAMERA2_CLK 0x8080 /* Camera 2 Clock */
diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c
index b2dd26d..e42b68f 100644
--- a/src/soc/intel/cannonlake/memmap.c
+++ b/src/soc/intel/cannonlake/memmap.c
@@ -26,7 +26,6 @@
#include <soc/pci_devs.h>
#include <soc/smm.h>
#include <soc/systemagent.h>
-#include <stdlib.h>
void smm_region(void **start, size_t *size)
{
diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c
index fadd35d..ffa446b 100644
--- a/src/soc/intel/cannonlake/pmutil.c
+++ b/src/soc/intel/cannonlake/pmutil.c
@@ -30,7 +30,6 @@
#include <intelblocks/pmclib.h>
#include <intelblocks/rtc.h>
#include <intelblocks/tco.h>
-#include <stdlib.h>
#include <soc/gpe.h>
#include <soc/gpio.h>
#include <soc/iomap.h>
diff --git a/src/soc/intel/common/acpi_wake_source.c b/src/soc/intel/common/acpi_wake_source.c
index f66706c..389807e 100644
--- a/src/soc/intel/common/acpi_wake_source.c
+++ b/src/soc/intel/common/acpi_wake_source.c
@@ -19,7 +19,6 @@
#include <console/console.h>
#include <soc/nvs.h>
#include <stdint.h>
-#include <stdlib.h>
#include "acpi.h"
__weak int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0)
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index 455b13c..4143866 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -25,7 +25,6 @@
#include <soc/pci_devs.h>
#include <spi_flash.h>
#include <spi-generic.h>
-#include <stdlib.h>
/*
* Get the FAST_SPIBAR.
diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c
index 7aa69c5..39be081 100644
--- a/src/soc/intel/common/block/smm/smihandler.c
+++ b/src/soc/intel/common/block/smm/smihandler.c
@@ -35,7 +35,6 @@
#include <soc/smbus.h>
#include <spi-generic.h>
#include <stdint.h>
-#include <stdlib.h>
/* GNVS needs to be set by coreboot initiating a software SMI. */
static struct global_nvs_t *gnvs;
diff --git a/src/soc/intel/denverton_ns/csme_ie_kt.c b/src/soc/intel/denverton_ns/csme_ie_kt.c
index 5967840..143e7b6 100644
--- a/src/soc/intel/denverton_ns/csme_ie_kt.c
+++ b/src/soc/intel/denverton_ns/csme_ie_kt.c
@@ -15,7 +15,6 @@
*/
#include <stdint.h>
-#include <stdlib.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <console/console.h>
diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c
index 4d748b2..d8e967f 100644
--- a/src/soc/intel/denverton_ns/smihandler.c
+++ b/src/soc/intel/denverton_ns/smihandler.c
@@ -16,7 +16,6 @@
*/
#include <stdint.h>
-#include <stdlib.h>
#include <arch/hlt.h>
#include <arch/io.h>
#include <device/pci_ops.h>
diff --git a/src/soc/intel/denverton_ns/systemagent.c b/src/soc/intel/denverton_ns/systemagent.c
index cc1d696..215dfdc 100644
--- a/src/soc/intel/denverton_ns/systemagent.c
+++ b/src/soc/intel/denverton_ns/systemagent.c
@@ -23,7 +23,6 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <stdlib.h>
#include <timer.h>
#include <soc/iomap.h>
diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c
index 15dc851..82a528c 100644
--- a/src/soc/intel/fsp_baytrail/cpu.c
+++ b/src/soc/intel/fsp_baytrail/cpu.c
@@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <console/console.h>
#include <cpu/cpu.h>
#include <cpu/intel/microcode.h>
diff --git a/src/soc/intel/fsp_baytrail/gfx.c b/src/soc/intel/fsp_baytrail/gfx.c
index dab9972..7029067 100644
--- a/src/soc/intel/fsp_baytrail/gfx.c
+++ b/src/soc/intel/fsp_baytrail/gfx.c
@@ -19,7 +19,6 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <reg_script.h>
-#include <stdlib.h>
#include <soc/gfx.h>
#include <soc/iosf.h>
#include <soc/pci_devs.h>
diff --git a/src/soc/intel/fsp_baytrail/include/soc/i2c.h b/src/soc/intel/fsp_baytrail/include/soc/i2c.h
index 7b3a3c8..ebe6a69 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/i2c.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/i2c.h
@@ -18,7 +18,6 @@
#include <console/console.h>
#include <device/pci_def.h>
-#include <stdlib.h>
/* SMBus controller settings in PCI configuration space */
#define I2C_PCI_VENDOR_ID 0x8086
diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c
index 754c5f5..b895067 100644
--- a/src/soc/intel/fsp_baytrail/ramstage.c
+++ b/src/soc/intel/fsp_baytrail/ramstage.c
@@ -23,7 +23,6 @@
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
-#include <stdlib.h>
#include <string.h>
#include <soc/gpio.h>
diff --git a/src/soc/intel/fsp_baytrail/smihandler.c b/src/soc/intel/fsp_baytrail/smihandler.c
index f2abd99..0364758f 100644
--- a/src/soc/intel/fsp_baytrail/smihandler.c
+++ b/src/soc/intel/fsp_baytrail/smihandler.c
@@ -14,7 +14,6 @@
*/
#include <stdint.h>
-#include <stdlib.h>
#include <arch/io.h>
#include <device/pci_ops.h>
#include <console/console.h>
diff --git a/src/soc/intel/fsp_broadwell_de/cpu.c b/src/soc/intel/fsp_broadwell_de/cpu.c
index 0b933c5..4814596 100644
--- a/src/soc/intel/fsp_broadwell_de/cpu.c
+++ b/src/soc/intel/fsp_broadwell_de/cpu.c
@@ -15,7 +15,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <console/console.h>
#include <cpu/cpu.h>
#include <cpu/intel/microcode.h>
diff --git a/src/soc/intel/fsp_broadwell_de/ramstage.c b/src/soc/intel/fsp_broadwell_de/ramstage.c
index 96b3888..e892c5b 100644
--- a/src/soc/intel/fsp_broadwell_de/ramstage.c
+++ b/src/soc/intel/fsp_broadwell_de/ramstage.c
@@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <arch/cpu.h>
#include <console/console.h>
#include <cpu/intel/microcode.h>
diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c
index 3ada73d..b13c88a 100644
--- a/src/soc/intel/icelake/finalize.c
+++ b/src/soc/intel/icelake/finalize.c
@@ -32,7 +32,6 @@
#include <soc/pm.h>
#include <soc/smbus.h>
#include <soc/systemagent.h>
-#include <stdlib.h>
#define CAMERA1_CLK 0x8000 /* Camera 1 Clock */
#define CAMERA2_CLK 0x8080 /* Camera 2 Clock */
diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c
index 821162e..97c42c3 100644
--- a/src/soc/intel/icelake/memmap.c
+++ b/src/soc/intel/icelake/memmap.c
@@ -25,7 +25,6 @@
#include <soc/pci_devs.h>
#include <soc/smm.h>
#include <soc/systemagent.h>
-#include <stdlib.h>
void smm_region(void **start, size_t *size)
{
diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c
index 96ff52d..58000ac 100644
--- a/src/soc/intel/icelake/pmutil.c
+++ b/src/soc/intel/icelake/pmutil.c
@@ -29,7 +29,6 @@
#include <intelblocks/pmclib.h>
#include <intelblocks/rtc.h>
#include <intelblocks/tco.h>
-#include <stdlib.h>
#include <soc/gpe.h>
#include <soc/gpio.h>
#include <soc/iomap.h>
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index c69dffb..06118f5 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -38,7 +38,6 @@
#include <soc/smbus.h>
#include <soc/systemagent.h>
#include <soc/thermal.h>
-#include <stdlib.h>
#include <timer.h>
#define PSF_BASE_ADDRESS 0xA00
diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c
index f7aa584..9a61102 100644
--- a/src/soc/intel/skylake/me.c
+++ b/src/soc/intel/skylake/me.c
@@ -23,7 +23,6 @@
#include <soc/me.h>
#include <soc/pci_devs.h>
#include <stdint.h>
-#include <stdlib.h>
#include <string.h>
static inline u32 me_read_config32(int offset)
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c
index 60a7070..35137b8 100644
--- a/src/soc/intel/skylake/memmap.c
+++ b/src/soc/intel/skylake/memmap.c
@@ -27,7 +27,6 @@
#include <soc/msr.h>
#include <soc/pci_devs.h>
#include <soc/systemagent.h>
-#include <stdlib.h>
size_t mmap_region_granularity(void)
{
diff --git a/src/soc/intel/skylake/pei_data.c b/src/soc/intel/skylake/pei_data.c
index a2887ac..1dfb570 100644
--- a/src/soc/intel/skylake/pei_data.c
+++ b/src/soc/intel/skylake/pei_data.c
@@ -18,7 +18,6 @@
#include <console/streams.h>
#include <device/device.h>
#include <device/pci_def.h>
-#include <stdlib.h>
#include <stdint.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c
index 7d0dc0a..3a1ff44 100644
--- a/src/soc/intel/skylake/pmutil.c
+++ b/src/soc/intel/skylake/pmutil.c
@@ -29,7 +29,6 @@
#include <intelblocks/pmclib.h>
#include <intelblocks/lpc_lib.h>
#include <intelblocks/tco.h>
-#include <stdlib.h>
#include <soc/gpe.h>
#include <soc/gpio.h>
#include <soc/iomap.h>
diff --git a/src/soc/mediatek/common/spi.c b/src/soc/mediatek/common/spi.c
index 3e7186a..568cf1d 100644
--- a/src/soc/mediatek/common/spi.c
+++ b/src/soc/mediatek/common/spi.c
@@ -16,7 +16,6 @@
#include <device/mmio.h>
#include <assert.h>
#include <endian.h>
-#include <stdlib.h>
#include <soc/pll.h>
#include <soc/spi.h>
#include <timer.h>
diff --git a/src/soc/mediatek/mt8173/ddp.c b/src/soc/mediatek/mt8173/ddp.c
index 0b78c3e..d750c0e 100644
--- a/src/soc/mediatek/mt8173/ddp.c
+++ b/src/soc/mediatek/mt8173/ddp.c
@@ -15,7 +15,6 @@
#include <device/mmio.h>
#include <edid.h>
-#include <stdlib.h>
#include <stddef.h>
#include <soc/addressmap.h>
#include <soc/ddp.h>
diff --git a/src/soc/mediatek/mt8173/flash_controller.c b/src/soc/mediatek/mt8173/flash_controller.c
index bca2ecf..fcaf24a 100644
--- a/src/soc/mediatek/mt8173/flash_controller.c
+++ b/src/soc/mediatek/mt8173/flash_controller.c
@@ -21,7 +21,6 @@
#include <spi_flash.h>
#include <spi-generic.h>
#include <stdint.h>
-#include <stdlib.h>
#include <string.h>
#include <symbols.h>
#include <timer.h>
diff --git a/src/soc/mediatek/mt8173/include/soc/gpio.h b/src/soc/mediatek/mt8173/include/soc/gpio.h
index ec08334..8a6e13a 100644
--- a/src/soc/mediatek/mt8173/include/soc/gpio.h
+++ b/src/soc/mediatek/mt8173/include/soc/gpio.h
@@ -16,7 +16,6 @@
#define SOC_MEDIATEK_MT8173_GPIO_H
#include <stdint.h>
-#include <stdlib.h>
#include <soc/addressmap.h>
#include <soc/gpio_common.h>
diff --git a/src/soc/nvidia/tegra/i2c.c b/src/soc/nvidia/tegra/i2c.c
index 9dbfde8..90bcfd9 100644
--- a/src/soc/nvidia/tegra/i2c.c
+++ b/src/soc/nvidia/tegra/i2c.c
@@ -17,7 +17,6 @@
#include <console/console.h>
#include <delay.h>
#include <device/i2c_simple.h>
-#include <stdlib.h>
#include <string.h>
#include <soc/addressmap.h>
#include "i2c.h"
diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c
index 6877c04..3c8ddb2 100644
--- a/src/soc/nvidia/tegra124/clock.c
+++ b/src/soc/nvidia/tegra124/clock.c
@@ -24,7 +24,6 @@
#include <soc/maincpu.h>
#include <soc/pmc.h>
#include <soc/sysctr.h>
-#include <stdlib.h>
#include <symbols.h>
static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c
index 51f7215..6fa3bdf 100644
--- a/src/soc/nvidia/tegra124/display.c
+++ b/src/soc/nvidia/tegra124/display.c
@@ -26,7 +26,6 @@
#include <soc/nvidia/tegra/dc.h>
#include <soc/nvidia/tegra/pwm.h>
#include <stdint.h>
-#include <stdlib.h>
#include <string.h>
#include "chip.h"
diff --git a/src/soc/nvidia/tegra124/dma.c b/src/soc/nvidia/tegra124/dma.c
index 73d050f..a0bd5c0 100644
--- a/src/soc/nvidia/tegra124/dma.c
+++ b/src/soc/nvidia/tegra124/dma.c
@@ -21,7 +21,6 @@
#include <soc/addressmap.h>
#include <soc/dma.h>
#include <stddef.h>
-#include <stdlib.h>
struct apb_dma * const apb_dma = (struct apb_dma *)TEGRA_APB_DMA_BASE;
diff --git a/src/soc/nvidia/tegra124/dp.c b/src/soc/nvidia/tegra124/dp.c
index b9fa0ea..fbbc49b 100644
--- a/src/soc/nvidia/tegra124/dp.c
+++ b/src/soc/nvidia/tegra124/dp.c
@@ -27,7 +27,6 @@
#include <soc/nvidia/tegra/dc.h>
#include <soc/nvidia/tegra/displayport.h>
#include <soc/sor.h>
-#include <stdlib.h>
#include <string.h>
#include "chip.h"
diff --git a/src/soc/nvidia/tegra124/include/soc/clock.h b/src/soc/nvidia/tegra124/include/soc/clock.h
index 00744ce..5538b78 100644
--- a/src/soc/nvidia/tegra124/include/soc/clock.h
+++ b/src/soc/nvidia/tegra124/include/soc/clock.h
@@ -22,7 +22,6 @@
#include <device/mmio.h>
#include <soc/clk_rst.h>
#include <stdint.h>
-#include <stdlib.h>
enum {
CLK_L_CPU = 0x1 << 0,
diff --git a/src/soc/nvidia/tegra124/sdram.c b/src/soc/nvidia/tegra124/sdram.c
index 9af116c..7c5d304 100644
--- a/src/soc/nvidia/tegra124/sdram.c
+++ b/src/soc/nvidia/tegra124/sdram.c
@@ -22,7 +22,6 @@
#include <soc/mc.h>
#include <soc/pmc.h>
#include <soc/sdram.h>
-#include <stdlib.h>
#include <symbols.h>
diff --git a/src/soc/nvidia/tegra124/sdram_lp0.c b/src/soc/nvidia/tegra124/sdram_lp0.c
index 731fc61..aade07c 100644
--- a/src/soc/nvidia/tegra124/sdram_lp0.c
+++ b/src/soc/nvidia/tegra124/sdram_lp0.c
@@ -20,7 +20,6 @@
#include <soc/clk_rst.h>
#include <soc/pmc.h>
#include <soc/sdram.h>
-#include <stdlib.h>
/*
* This function reads SDRAM parameters (and a few CLK_RST register values) from
diff --git a/src/soc/nvidia/tegra124/sor.c b/src/soc/nvidia/tegra124/sor.c
index 9188f83..8c03a7e 100644
--- a/src/soc/nvidia/tegra124/sor.c
+++ b/src/soc/nvidia/tegra124/sor.c
@@ -29,7 +29,6 @@
#include <soc/nvidia/tegra/displayport.h>
#include <soc/sor.h>
#include <stdint.h>
-#include <stdlib.h>
#include "chip.h"
diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c
index 45159c2..620edca 100644
--- a/src/soc/nvidia/tegra124/spi.c
+++ b/src/soc/nvidia/tegra124/spi.c
@@ -27,7 +27,6 @@
#include <spi-generic.h>
#include <spi_flash.h>
#include <stdint.h>
-#include <stdlib.h>
#include <symbols.h>
#include <timer.h>
diff --git a/src/soc/nvidia/tegra124/verstage.c b/src/soc/nvidia/tegra124/verstage.c
index 2495351..9899fcb 100644
--- a/src/soc/nvidia/tegra124/verstage.c
+++ b/src/soc/nvidia/tegra124/verstage.c
@@ -20,7 +20,6 @@
#include <program_loading.h>
#include <soc/cache.h>
#include <soc/early_configs.h>
-#include <stdlib.h>
#include <symbols.h>
#include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/soc/nvidia/tegra210/addressmap.c b/src/soc/nvidia/tegra210/addressmap.c
index 4f11d4e..983ecad 100644
--- a/src/soc/nvidia/tegra210/addressmap.c
+++ b/src/soc/nvidia/tegra210/addressmap.c
@@ -21,7 +21,6 @@
#include <soc/id.h>
#include <soc/mc.h>
#include <soc/sdram.h>
-#include <stdlib.h>
#include <symbols.h>
#include <soc/nvidia/tegra/types.h>
diff --git a/src/soc/nvidia/tegra210/arm_tf.c b/src/soc/nvidia/tegra210/arm_tf.c
index bd34185..ebed7d0 100644
--- a/src/soc/nvidia/tegra210/arm_tf.c
+++ b/src/soc/nvidia/tegra210/arm_tf.c
@@ -18,7 +18,6 @@
#include <assert.h>
#include <soc/addressmap.h>
#include <soc/console_uart.h>
-#include <stdlib.h>
#include <symbols.h>
typedef struct bl31_plat_params {
diff --git a/src/soc/nvidia/tegra210/clock.c b/src/soc/nvidia/tegra210/clock.c
index 55ee50b..236a450 100644
--- a/src/soc/nvidia/tegra210/clock.c
+++ b/src/soc/nvidia/tegra210/clock.c
@@ -18,7 +18,6 @@
#include <assert.h>
#include <console/console.h>
#include <delay.h>
-#include <stdlib.h>
#include <soc/addressmap.h>
#include <soc/clk_rst.h>
#include <soc/clock.h>
diff --git a/src/soc/nvidia/tegra210/dc.c b/src/soc/nvidia/tegra210/dc.c
index ceffb41..21e90ee 100644
--- a/src/soc/nvidia/tegra210/dc.c
+++ b/src/soc/nvidia/tegra210/dc.c
@@ -15,7 +15,6 @@
#include <console/console.h>
#include <device/mmio.h>
#include <stdint.h>
-#include <stdlib.h>
#include <edid.h>
#include <device/device.h>
#include <soc/nvidia/tegra/dc.h>
diff --git a/src/soc/nvidia/tegra210/dma.c b/src/soc/nvidia/tegra210/dma.c
index 03c5e67..bbc5c8f 100644
--- a/src/soc/nvidia/tegra210/dma.c
+++ b/src/soc/nvidia/tegra210/dma.c
@@ -21,7 +21,6 @@
#include <soc/addressmap.h>
#include <soc/dma.h>
#include <stddef.h>
-#include <stdlib.h>
struct apb_dma * const apb_dma = (struct apb_dma *)TEGRA_APB_DMA_BASE;
diff --git a/src/soc/nvidia/tegra210/dp.c b/src/soc/nvidia/tegra210/dp.c
index b0c0846..104ef04 100644
--- a/src/soc/nvidia/tegra210/dp.c
+++ b/src/soc/nvidia/tegra210/dp.c
@@ -20,7 +20,6 @@
#include <device/device.h>
#include <device/i2c_simple.h>
#include <edid.h>
-#include <stdlib.h>
#include <string.h>
#include <delay.h>
#include <soc/addressmap.h>
diff --git a/src/soc/nvidia/tegra210/dsi.c b/src/soc/nvidia/tegra210/dsi.c
index 76054f0..5861113 100644
--- a/src/soc/nvidia/tegra210/dsi.c
+++ b/src/soc/nvidia/tegra210/dsi.c
@@ -15,7 +15,6 @@
#include <console/console.h>
#include <device/mmio.h>
#include <stdint.h>
-#include <stdlib.h>
#include <delay.h>
#include <timer.h>
#include <soc/addressmap.h>
diff --git a/src/soc/nvidia/tegra210/include/soc/clock.h b/src/soc/nvidia/tegra210/include/soc/clock.h
index 6d8c338..3694285 100644
--- a/src/soc/nvidia/tegra210/include/soc/clock.h
+++ b/src/soc/nvidia/tegra210/include/soc/clock.h
@@ -22,7 +22,6 @@
#include <device/mmio.h>
#include <soc/clk_rst.h>
#include <stdint.h>
-#include <stdlib.h>
enum {
CLK_L_CPU = 0x1 << 0,
diff --git a/src/soc/nvidia/tegra210/include/soc/mipi-phy.h b/src/soc/nvidia/tegra210/include/soc/mipi-phy.h
index 852c5a3..e9b5797 100644
--- a/src/soc/nvidia/tegra210/include/soc/mipi-phy.h
+++ b/src/soc/nvidia/tegra210/include/soc/mipi-phy.h
@@ -15,7 +15,6 @@
#ifndef _TEGRA_MIPI_PHY_H
#define _TEGRA_MIPI_PHY_H
-#include <stdlib.h>
/*
* Macros for calculating the phy timings
diff --git a/src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.c b/src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.c
index a9101b8..223f7a0 100644
--- a/src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.c
+++ b/src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.c
@@ -14,7 +14,6 @@
*/
#include <console/console.h>
#include <stdint.h>
-#include <stdlib.h>
#include <delay.h>
#include <soc/addressmap.h>
#include <soc/clock.h>
diff --git a/src/soc/nvidia/tegra210/mipi-phy.c b/src/soc/nvidia/tegra210/mipi-phy.c
index 4e6bdf0..00891c4 100644
--- a/src/soc/nvidia/tegra210/mipi-phy.c
+++ b/src/soc/nvidia/tegra210/mipi-phy.c
@@ -14,7 +14,6 @@
*/
#include <stdint.h>
-#include <stdlib.h>
#include <soc/addressmap.h>
#include <soc/clock.h>
diff --git a/src/soc/nvidia/tegra210/mipi.c b/src/soc/nvidia/tegra210/mipi.c
index f863496..ada23a7 100644
--- a/src/soc/nvidia/tegra210/mipi.c
+++ b/src/soc/nvidia/tegra210/mipi.c
@@ -17,7 +17,6 @@
#include <console/console.h>
#include <device/mmio.h>
#include <stdint.h>
-#include <stdlib.h>
#include <delay.h>
#include <soc/addressmap.h>
#include <soc/clock.h>
diff --git a/src/soc/nvidia/tegra210/mipi_dsi.c b/src/soc/nvidia/tegra210/mipi_dsi.c
index 23d9274..825cbff 100644
--- a/src/soc/nvidia/tegra210/mipi_dsi.c
+++ b/src/soc/nvidia/tegra210/mipi_dsi.c
@@ -41,7 +41,6 @@
#include <console/console.h>
#include <stdint.h>
-#include <stdlib.h>
#include <string.h>
#include <soc/addressmap.h>
#include <soc/clock.h>
diff --git a/src/soc/nvidia/tegra210/mmu_operations.c b/src/soc/nvidia/tegra210/mmu_operations.c
index 9cee6b2..1424d97 100644
--- a/src/soc/nvidia/tegra210/mmu_operations.c
+++ b/src/soc/nvidia/tegra210/mmu_operations.c
@@ -17,7 +17,6 @@
#include <assert.h>
#include <soc/addressmap.h>
#include <soc/mmu_operations.h>
-#include <stdlib.h>
#include <stdint.h>
#include <symbols.h>
diff --git a/src/soc/nvidia/tegra210/sdram.c b/src/soc/nvidia/tegra210/sdram.c
index e1d91fd..c609921 100644
--- a/src/soc/nvidia/tegra210/sdram.c
+++ b/src/soc/nvidia/tegra210/sdram.c
@@ -23,7 +23,6 @@
#include <soc/mc.h>
#include <soc/pmc.h>
#include <soc/sdram.h>
-#include <stdlib.h>
#include <soc/nvidia/tegra/apbmisc.h>
static void sdram_patch(uintptr_t addr, uint32_t value)
diff --git a/src/soc/nvidia/tegra210/sdram_lp0.c b/src/soc/nvidia/tegra210/sdram_lp0.c
index 9eaf5f0..09747ea 100644
--- a/src/soc/nvidia/tegra210/sdram_lp0.c
+++ b/src/soc/nvidia/tegra210/sdram_lp0.c
@@ -19,7 +19,6 @@
#include <soc/addressmap.h>
#include <soc/pmc.h>
#include <soc/sdram.h>
-#include <stdlib.h>
/*
* This function reads SDRAM parameters from the common BCT format and
diff --git a/src/soc/nvidia/tegra210/sor.c b/src/soc/nvidia/tegra210/sor.c
index 3055b29..8caf050 100644
--- a/src/soc/nvidia/tegra210/sor.c
+++ b/src/soc/nvidia/tegra210/sor.c
@@ -18,7 +18,6 @@
#include <console/console.h>
#include <stdint.h>
-#include <stdlib.h>
#include <delay.h>
#include <soc/addressmap.h>
#include <device/device.h>
diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c
index edb052d..ad2f234 100644
--- a/src/soc/nvidia/tegra210/spi.c
+++ b/src/soc/nvidia/tegra210/spi.c
@@ -27,7 +27,6 @@
#include <soc/dma.h>
#include <soc/spi.h>
#include <stdint.h>
-#include <stdlib.h>
#include <symbols.h>
#if defined(CONFIG_DEBUG_SPI) && CONFIG_DEBUG_SPI
diff --git a/src/soc/qualcomm/ipq40xx/i2c.c b/src/soc/qualcomm/ipq40xx/i2c.c
index f5c9943..fbabc53 100644
--- a/src/soc/qualcomm/ipq40xx/i2c.c
+++ b/src/soc/qualcomm/ipq40xx/i2c.c
@@ -32,7 +32,6 @@
#include <assert.h>
#include <console/console.h>
#include <device/i2c_simple.h>
-#include <stdlib.h>
#include <string.h>
#include <soc/blsp.h>
#include <soc/qup.h>
diff --git a/src/soc/qualcomm/ipq40xx/qup.c b/src/soc/qualcomm/ipq40xx/qup.c
index 9d1f92d..bc98a3a 100644
--- a/src/soc/qualcomm/ipq40xx/qup.c
+++ b/src/soc/qualcomm/ipq40xx/qup.c
@@ -33,7 +33,6 @@
#include <console/console.h>
#include <delay.h>
#include <soc/iomap.h>
-#include <stdlib.h>
#include <soc/qup.h>
#define TIMEOUT_CNT 100
diff --git a/src/soc/qualcomm/ipq40xx/spi.c b/src/soc/qualcomm/ipq40xx/spi.c
index 109eda9..3aaebd4 100644
--- a/src/soc/qualcomm/ipq40xx/spi.c
+++ b/src/soc/qualcomm/ipq40xx/spi.c
@@ -33,7 +33,6 @@
#include <gpio.h>
#include <soc/iomap.h>
#include <soc/spi.h>
-#include <stdlib.h>
static const struct blsp_spi spi_reg[] = {
/* BLSP0 registers for SPI interface */
diff --git a/src/soc/qualcomm/ipq40xx/uart.c b/src/soc/qualcomm/ipq40xx/uart.c
index eb3731b..d17a926 100644
--- a/src/soc/qualcomm/ipq40xx/uart.c
+++ b/src/soc/qualcomm/ipq40xx/uart.c
@@ -37,7 +37,6 @@
#include <soc/blsp.h>
#include <soc/ipq_uart.h>
#include <stdint.h>
-#include <stdlib.h>
#define FIFO_DATA_SIZE 4
diff --git a/src/soc/qualcomm/ipq806x/i2c.c b/src/soc/qualcomm/ipq806x/i2c.c
index cd57591..145b3a4 100644
--- a/src/soc/qualcomm/ipq806x/i2c.c
+++ b/src/soc/qualcomm/ipq806x/i2c.c
@@ -30,7 +30,6 @@
#include <assert.h>
#include <console/console.h>
#include <device/i2c_simple.h>
-#include <stdlib.h>
#include <string.h>
#include <soc/gsbi.h>
#include <soc/qup.h>
diff --git a/src/soc/qualcomm/ipq806x/qup.c b/src/soc/qualcomm/ipq806x/qup.c
index 872b264..e2881d9 100644
--- a/src/soc/qualcomm/ipq806x/qup.c
+++ b/src/soc/qualcomm/ipq806x/qup.c
@@ -31,7 +31,6 @@
#include <console/console.h>
#include <delay.h>
#include <soc/iomap.h>
-#include <stdlib.h>
#include <soc/qup.h>
#define TIMEOUT_CNT 100000
diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c
index 6577345..24b8492 100644
--- a/src/soc/qualcomm/ipq806x/spi.c
+++ b/src/soc/qualcomm/ipq806x/spi.c
@@ -19,7 +19,6 @@
#include <gpio.h>
#include <soc/iomap.h>
#include <soc/spi.h>
-#include <stdlib.h>
#define SUCCESS 0
diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c
index fe2d673..04cc7eb 100644
--- a/src/soc/qualcomm/ipq806x/uart.c
+++ b/src/soc/qualcomm/ipq806x/uart.c
@@ -41,7 +41,6 @@
#include <soc/gsbi.h>
#include <soc/ipq_uart.h>
#include <stdint.h>
-#include <stdlib.h>
#define FIFO_DATA_SIZE 4
diff --git a/src/soc/rockchip/common/edp.c b/src/soc/rockchip/common/edp.c
index 98381a0..ef35db7 100644
--- a/src/soc/rockchip/common/edp.c
+++ b/src/soc/rockchip/common/edp.c
@@ -19,7 +19,6 @@
#include <delay.h>
#include <device/device.h>
#include <edid.h>
-#include <stdlib.h>
#include <stdint.h>
#include <string.h>
#include <soc/addressmap.h>
diff --git a/src/soc/rockchip/common/gpio.c b/src/soc/rockchip/common/gpio.c
index fa0990b..6df0143 100644
--- a/src/soc/rockchip/common/gpio.c
+++ b/src/soc/rockchip/common/gpio.c
@@ -19,7 +19,6 @@
#include <soc/gpio.h>
#include <soc/grf.h>
#include <soc/soc.h>
-#include <stdlib.h>
static void gpio_set_dir(gpio_t gpio, enum gpio_dir dir)
{
diff --git a/src/soc/rockchip/common/i2c.c b/src/soc/rockchip/common/i2c.c
index e5f5a9a..4df6e0e 100644
--- a/src/soc/rockchip/common/i2c.c
+++ b/src/soc/rockchip/common/i2c.c
@@ -23,7 +23,6 @@
#include <soc/soc.h>
#include <soc/i2c.h>
#include <soc/clock.h>
-#include <stdlib.h>
#define RETRY_COUNT 3
/* 100000us = 100ms */
diff --git a/src/soc/rockchip/common/include/soc/edp.h b/src/soc/rockchip/common/include/soc/edp.h
index a9ebbc5..58986d1 100644
--- a/src/soc/rockchip/common/include/soc/edp.h
+++ b/src/soc/rockchip/common/include/soc/edp.h
@@ -17,7 +17,6 @@
#define __RK_DP_H
#include <edid.h>
-#include <stdlib.h>
struct rk_edp_regs {
u8 res0[0x10];
diff --git a/src/soc/rockchip/common/pwm.c b/src/soc/rockchip/common/pwm.c
index ad0453b..9be4878 100644
--- a/src/soc/rockchip/common/pwm.c
+++ b/src/soc/rockchip/common/pwm.c
@@ -20,7 +20,6 @@
#include <soc/soc.h>
#include <soc/pwm.h>
#include <soc/clock.h>
-#include <stdlib.h>
#include <timer.h>
struct pwm_ctl {
diff --git a/src/soc/rockchip/common/rk808.c b/src/soc/rockchip/common/rk808.c
index 58d910c..66a085c 100644
--- a/src/soc/rockchip/common/rk808.c
+++ b/src/soc/rockchip/common/rk808.c
@@ -21,7 +21,6 @@
#include <rtc.h>
#include <soc/rk808.h>
#include <stdint.h>
-#include <stdlib.h>
#if CONFIG_PMIC_BUS < 0
#error "PMIC_BUS must be set in mainboard's Kconfig."
diff --git a/src/soc/rockchip/common/spi.c b/src/soc/rockchip/common/spi.c
index 98016c0..0349ab6 100644
--- a/src/soc/rockchip/common/spi.c
+++ b/src/soc/rockchip/common/spi.c
@@ -23,7 +23,6 @@
#include <soc/clock.h>
#include <spi-generic.h>
#include <spi_flash.h>
-#include <stdlib.h>
#include <timer.h>
struct rockchip_spi_slave {
diff --git a/src/soc/rockchip/common/vop.c b/src/soc/rockchip/common/vop.c
index 9c70b78..f617b4a 100644
--- a/src/soc/rockchip/common/vop.c
+++ b/src/soc/rockchip/common/vop.c
@@ -14,7 +14,6 @@
*/
#include <device/mmio.h>
-#include <stdlib.h>
#include <stddef.h>
#include <soc/addressmap.h>
#include <soc/clock.h>
diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c
index cee1ee2..6e0c139 100644
--- a/src/soc/rockchip/rk3288/clock.c
+++ b/src/soc/rockchip/rk3288/clock.c
@@ -24,7 +24,6 @@
#include <soc/i2c.h>
#include <soc/soc.h>
#include <stdint.h>
-#include <stdlib.h>
#include <string.h>
struct pll_div {
diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c
index 04a5992..a66b2d4 100644
--- a/src/soc/rockchip/rk3288/display.c
+++ b/src/soc/rockchip/rk3288/display.c
@@ -20,7 +20,6 @@
#include <delay.h>
#include <edid.h>
#include <gpio.h>
-#include <stdlib.h>
#include <stddef.h>
#include <string.h>
#include <soc/addressmap.h>
diff --git a/src/soc/rockchip/rk3288/gpio.c b/src/soc/rockchip/rk3288/gpio.c
index 0f9d85c..8eeed88 100644
--- a/src/soc/rockchip/rk3288/gpio.c
+++ b/src/soc/rockchip/rk3288/gpio.c
@@ -18,7 +18,6 @@
#include <soc/grf.h>
#include <soc/pmu.h>
#include <soc/soc.h>
-#include <stdlib.h>
struct rockchip_gpio_regs *gpio_port[] = {
(struct rockchip_gpio_regs *)0xff750000,
diff --git a/src/soc/rockchip/rk3288/hdmi.c b/src/soc/rockchip/rk3288/hdmi.c
index 425d302..56f6a8f 100644
--- a/src/soc/rockchip/rk3288/hdmi.c
+++ b/src/soc/rockchip/rk3288/hdmi.c
@@ -25,7 +25,6 @@
#include <delay.h>
#include <edid.h>
#include <gpio.h>
-#include <stdlib.h>
#include <stdint.h>
#include <soc/addressmap.h>
#include <soc/hdmi.h>
diff --git a/src/soc/rockchip/rk3288/include/soc/hdmi.h b/src/soc/rockchip/rk3288/include/soc/hdmi.h
index fb20b4a..3089949 100644
--- a/src/soc/rockchip/rk3288/include/soc/hdmi.h
+++ b/src/soc/rockchip/rk3288/include/soc/hdmi.h
@@ -19,7 +19,6 @@
#define __SOC_HDMI_H__
#include <types.h>
-#include <stdlib.h>
#define HDMI_EDID_BLOCK_SIZE 128
diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c
index bda9553..31c9998 100644
--- a/src/soc/rockchip/rk3288/soc.c
+++ b/src/soc/rockchip/rk3288/soc.c
@@ -22,7 +22,6 @@
#include <soc/soc.h>
#include <soc/sdram.h>
#include <stddef.h>
-#include <stdlib.h>
#include <symbols.h>
#include "chip.h"
diff --git a/src/soc/rockchip/rk3288/tsadc.c b/src/soc/rockchip/rk3288/tsadc.c
index a34105d..cfd1658 100644
--- a/src/soc/rockchip/rk3288/tsadc.c
+++ b/src/soc/rockchip/rk3288/tsadc.c
@@ -20,7 +20,6 @@
#include <soc/pmu.h>
#include <soc/tsadc.h>
#include <stdint.h>
-#include <stdlib.h>
struct rk3288_tsadc_regs {
u32 user_con;
diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c
index 5252232..9364ecf 100644
--- a/src/soc/rockchip/rk3399/clock.c
+++ b/src/soc/rockchip/rk3399/clock.c
@@ -23,7 +23,6 @@
#include <soc/i2c.h>
#include <soc/soc.h>
#include <stdint.h>
-#include <stdlib.h>
#include <string.h>
struct pll_div {
diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c
index e2e9f7d..9cd4053 100644
--- a/src/soc/rockchip/rk3399/display.c
+++ b/src/soc/rockchip/rk3399/display.c
@@ -21,7 +21,6 @@
#include <delay.h>
#include <edid.h>
#include <gpio.h>
-#include <stdlib.h>
#include <stddef.h>
#include <soc/addressmap.h>
#include <soc/clock.h>
diff --git a/src/soc/rockchip/rk3399/gpio.c b/src/soc/rockchip/rk3399/gpio.c
index 7fe2c19..9a01abc 100644
--- a/src/soc/rockchip/rk3399/gpio.c
+++ b/src/soc/rockchip/rk3399/gpio.c
@@ -18,7 +18,6 @@
#include <soc/gpio.h>
#include <soc/grf.h>
#include <soc/soc.h>
-#include <stdlib.h>
struct rockchip_gpio_regs *gpio_port[] = {
(struct rockchip_gpio_regs *)GPIO0_BASE,
diff --git a/src/soc/rockchip/rk3399/include/soc/mipi.h b/src/soc/rockchip/rk3399/include/soc/mipi.h
index f304d8f..300630b 100644
--- a/src/soc/rockchip/rk3399/include/soc/mipi.h
+++ b/src/soc/rockchip/rk3399/include/soc/mipi.h
@@ -16,7 +16,6 @@
#ifndef __RK_MIPI_H
#define __RK_MIPI_H
-#include <stdlib.h>
struct rk_mipi_regs {
u32 dsi_version;
diff --git a/src/soc/rockchip/rk3399/mipi.c b/src/soc/rockchip/rk3399/mipi.c
index ee8cc2e..1231a1e 100644
--- a/src/soc/rockchip/rk3399/mipi.c
+++ b/src/soc/rockchip/rk3399/mipi.c
@@ -20,7 +20,6 @@
#include <device/device.h>
#include <edid.h>
#include <gpio.h>
-#include <stdlib.h>
#include <stdint.h>
#include <string.h>
#include <soc/addressmap.h>
diff --git a/src/soc/rockchip/rk3399/saradc.c b/src/soc/rockchip/rk3399/saradc.c
index 3c6cbe6..8dd3cb4 100644
--- a/src/soc/rockchip/rk3399/saradc.c
+++ b/src/soc/rockchip/rk3399/saradc.c
@@ -20,7 +20,6 @@
#include <soc/clock.h>
#include <soc/saradc.h>
#include <stdint.h>
-#include <stdlib.h>
#include <timer.h>
struct rk3399_saradc_regs {
diff --git a/src/soc/rockchip/rk3399/soc.c b/src/soc/rockchip/rk3399/soc.c
index 3f3ff97..807a7bc 100644
--- a/src/soc/rockchip/rk3399/soc.c
+++ b/src/soc/rockchip/rk3399/soc.c
@@ -23,7 +23,6 @@
#include <soc/sdram.h>
#include <soc/symbols.h>
#include <stddef.h>
-#include <stdlib.h>
#include <symbols.h>
void bootmem_platform_add_ranges(void)
diff --git a/src/soc/rockchip/rk3399/tsadc.c b/src/soc/rockchip/rk3399/tsadc.c
index d5aeccd..fd73218 100644
--- a/src/soc/rockchip/rk3399/tsadc.c
+++ b/src/soc/rockchip/rk3399/tsadc.c
@@ -20,7 +20,6 @@
#include <soc/grf.h>
#include <soc/tsadc.h>
#include <stdint.h>
-#include <stdlib.h>
struct rk3399_tsadc_regs {
u32 user_con;
diff --git a/src/soc/samsung/exynos5250/alternate_cbfs.c b/src/soc/samsung/exynos5250/alternate_cbfs.c
index 9fef9ae..aa319d6 100644
--- a/src/soc/samsung/exynos5250/alternate_cbfs.c
+++ b/src/soc/samsung/exynos5250/alternate_cbfs.c
@@ -19,7 +19,6 @@
#include <soc/alternate_cbfs.h>
#include <soc/power.h>
#include <soc/spi.h>
-#include <stdlib.h>
#include <symbols.h>
/* This allows USB A-A firmware upload from a compatible host in four parts:
diff --git a/src/soc/samsung/exynos5250/clock.c b/src/soc/samsung/exynos5250/clock.c
index 7e7fe97..1006a98 100644
--- a/src/soc/samsung/exynos5250/clock.c
+++ b/src/soc/samsung/exynos5250/clock.c
@@ -18,7 +18,6 @@
#include <console/console.h>
#include <soc/clk.h>
#include <soc/periph.h>
-#include <stdlib.h>
#include <timer.h>
/* input clock of PLL: SMDK5250 has 24MHz input clock */
diff --git a/src/soc/samsung/exynos5250/cpu.c b/src/soc/samsung/exynos5250/cpu.c
index f00351e..5f99899 100644
--- a/src/soc/samsung/exynos5250/cpu.c
+++ b/src/soc/samsung/exynos5250/cpu.c
@@ -23,7 +23,6 @@
#include <soc/dp-core.h>
#include <soc/fimd.h>
#include <stddef.h>
-#include <stdlib.h>
#include <string.h>
#include "chip.h"
diff --git a/src/soc/samsung/exynos5250/fb.c b/src/soc/samsung/exynos5250/fb.c
index 64980a1..8181c29 100644
--- a/src/soc/samsung/exynos5250/fb.c
+++ b/src/soc/samsung/exynos5250/fb.c
@@ -25,7 +25,6 @@
#include <soc/i2c.h>
#include <soc/power.h>
#include <soc/sysreg.h>
-#include <stdlib.h>
#include <timer.h>
/*
diff --git a/src/soc/samsung/exynos5250/spi.c b/src/soc/samsung/exynos5250/spi.c
index e35f888..cb15f46 100644
--- a/src/soc/samsung/exynos5250/spi.c
+++ b/src/soc/samsung/exynos5250/spi.c
@@ -21,7 +21,6 @@
#include <soc/clk.h>
#include <soc/gpio.h>
#include <soc/spi.h>
-#include <stdlib.h>
#include <symbols.h>
#if defined(CONFIG_DEBUG_SPI) && CONFIG_DEBUG_SPI
diff --git a/src/soc/samsung/exynos5420/alternate_cbfs.c b/src/soc/samsung/exynos5420/alternate_cbfs.c
index a1e92a0..74901ea 100644
--- a/src/soc/samsung/exynos5420/alternate_cbfs.c
+++ b/src/soc/samsung/exynos5420/alternate_cbfs.c
@@ -20,7 +20,6 @@
#include <soc/alternate_cbfs.h>
#include <soc/power.h>
#include <soc/spi.h>
-#include <stdlib.h>
#include <symbols.h>
/* This allows USB A-A firmware upload from a compatible host in four parts:
diff --git a/src/soc/samsung/exynos5420/clock.c b/src/soc/samsung/exynos5420/clock.c
index 720506c..5a7467c 100644
--- a/src/soc/samsung/exynos5420/clock.c
+++ b/src/soc/samsung/exynos5420/clock.c
@@ -18,7 +18,6 @@
#include <console/console.h>
#include <soc/clk.h>
#include <soc/periph.h>
-#include <stdlib.h>
#include <timer.h>
/* input clock of PLL: SMDK5420 has 24MHz input clock */
diff --git a/src/soc/samsung/exynos5420/cpu.c b/src/soc/samsung/exynos5420/cpu.c
index 55b0512..375b370 100644
--- a/src/soc/samsung/exynos5420/cpu.c
+++ b/src/soc/samsung/exynos5420/cpu.c
@@ -24,7 +24,6 @@
#include <soc/cpu.h>
#include <soc/clk.h>
#include <stddef.h>
-#include <stdlib.h>
#include <string.h>
#include "chip.h"
diff --git a/src/soc/samsung/exynos5420/dp.c b/src/soc/samsung/exynos5420/dp.c
index 5ad3dd3..c48ea8c 100644
--- a/src/soc/samsung/exynos5420/dp.c
+++ b/src/soc/samsung/exynos5420/dp.c
@@ -21,7 +21,6 @@
#include <soc/i2c.h>
#include <soc/power.h>
#include <soc/sysreg.h>
-#include <stdlib.h>
#include <string.h>
/*
diff --git a/src/soc/samsung/exynos5420/dp_lowlevel.c b/src/soc/samsung/exynos5420/dp_lowlevel.c
index 164704b..df579b0 100644
--- a/src/soc/samsung/exynos5420/dp_lowlevel.c
+++ b/src/soc/samsung/exynos5420/dp_lowlevel.c
@@ -22,7 +22,6 @@
#include <soc/i2c.h>
#include <soc/power.h>
#include <soc/sysreg.h>
-#include <stdlib.h>
/* FIXME: I think the DP controller shouldn't be hardcoded here... */
static struct exynos_dp * const dp_regs = (void *)EXYNOS5_DP1_BASE;
diff --git a/src/soc/samsung/exynos5420/pinmux.c b/src/soc/samsung/exynos5420/pinmux.c
index d8c1378..eb804c1 100644
--- a/src/soc/samsung/exynos5420/pinmux.c
+++ b/src/soc/samsung/exynos5420/pinmux.c
@@ -16,7 +16,6 @@
#include <assert.h>
#include <soc/gpio.h>
#include <soc/pinmux.h>
-#include <stdlib.h>
static void exynos_pinmux_uart(int start, int count)
{
diff --git a/src/soc/samsung/exynos5420/smp.c b/src/soc/samsung/exynos5420/smp.c
index 5e16063..27c0fa6 100644
--- a/src/soc/samsung/exynos5420/smp.c
+++ b/src/soc/samsung/exynos5420/smp.c
@@ -18,7 +18,6 @@
#include <device/mmio.h>
#include <soc/cpu.h>
#include <soc/power.h>
-#include <stdlib.h>
#include <string.h>
#include <types.h>
diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c
index 753a24b..72761d5 100644
--- a/src/soc/samsung/exynos5420/spi.c
+++ b/src/soc/samsung/exynos5420/spi.c
@@ -20,7 +20,6 @@
#include <soc/cpu.h>
#include <soc/spi.h>
#include <spi-generic.h>
-#include <stdlib.h>
#include <string.h>
#include <symbols.h>
diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c
index 60a8a13..fc472fb 100644
--- a/src/soc/sifive/fu540/clock.c
+++ b/src/soc/sifive/fu540/clock.c
@@ -17,7 +17,6 @@
#include <console/console.h>
#include <soc/clock.h>
#include <soc/addressmap.h>
-#include <stdlib.h>
#include <stdint.h>
// 33.33 Mhz after reset
diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c
index 46eca33..64dc5f5 100644
--- a/src/southbridge/amd/agesa/hudson/sm.c
+++ b/src/southbridge/amd/agesa/hudson/sm.c
@@ -20,7 +20,6 @@
#include <device/smbus.h>
#include <cpu/x86/lapic.h>
#include <arch/ioapic.h>
-#include <stdlib.h>
#include "hudson.h"
#include "smbus.c"
diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c
index 9c546c5..9656027 100644
--- a/src/southbridge/amd/agesa/hudson/spi.c
+++ b/src/southbridge/amd/agesa/hudson/spi.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
#include <stdint.h>
-#include <stdlib.h>
#include <device/mmio.h>
#include <console/console.h>
#include <spi_flash.h>
diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c
index c4a7896..11e852a 100644
--- a/src/southbridge/amd/amd8111/lpc.c
+++ b/src/southbridge/amd/amd8111/lpc.c
@@ -28,7 +28,6 @@
#include <arch/acpigen.h>
#include <cpu/amd/powernow.h>
#endif
-#include <stdlib.h>
#include "amd8111.h"
diff --git a/src/southbridge/amd/cimx/sb800/smbus_spd.c b/src/southbridge/amd/cimx/sb800/smbus_spd.c
index a6881bb..7078379 100644
--- a/src/southbridge/amd/cimx/sb800/smbus_spd.c
+++ b/src/southbridge/amd/cimx/sb800/smbus_spd.c
@@ -15,7 +15,6 @@
#include <device/pci_def.h>
#include <device/device.h>
-#include <stdlib.h>
#include <OEM.h> /* SMBUS0_BASE_ADDRESS */
/* warning: Porting.h includes an open #pragma pack(1) */
diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c
index ffda0a8..42393e9 100644
--- a/src/southbridge/amd/cimx/sb800/spi.c
+++ b/src/southbridge/amd/cimx/sb800/spi.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
#include <stdint.h>
-#include <stdlib.h>
#include <device/mmio.h>
#include <console/console.h>
#include <spi_flash.h>
diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c
index 0387567..2d96856 100644
--- a/src/southbridge/amd/pi/hudson/sm.c
+++ b/src/southbridge/amd/pi/hudson/sm.c
@@ -20,7 +20,6 @@
#include <device/smbus.h>
#include <cpu/x86/lapic.h>
#include <arch/ioapic.h>
-#include <stdlib.h>
#include "hudson.h"
#include "smbus.c"
diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c
index 6b7ce68..510ba75 100644
--- a/src/southbridge/amd/sb700/sm.c
+++ b/src/southbridge/amd/sb700/sm.c
@@ -24,7 +24,6 @@
#include <arch/io.h>
#include <cpu/x86/lapic.h>
#include <arch/ioapic.h>
-#include <stdlib.h>
#include "sb700.h"
#include "smbus.h"
diff --git a/src/southbridge/amd/sb700/spi.c b/src/southbridge/amd/sb700/spi.c
index ee031e9..8ecebc5 100644
--- a/src/southbridge/amd/sb700/spi.c
+++ b/src/southbridge/amd/sb700/spi.c
@@ -15,7 +15,6 @@
*/
#include <stdint.h>
-#include <stdlib.h>
#include <device/mmio.h>
#include <console/console.h>
#include <spi-generic.h>
diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c
index 1d2daed8..29e6474 100644
--- a/src/southbridge/amd/sb800/sm.c
+++ b/src/southbridge/amd/sb800/sm.c
@@ -23,7 +23,6 @@
#include <arch/io.h>
#include <cpu/x86/lapic.h>
#include <arch/ioapic.h>
-#include <stdlib.h>
#include "sb800.h"
#include "smbus.c"
diff --git a/src/southbridge/intel/bd82x6x/me_status.c b/src/southbridge/intel/bd82x6x/me_status.c
index b202376..bb708a1 100644
--- a/src/southbridge/intel/bd82x6x/me_status.c
+++ b/src/southbridge/intel/bd82x6x/me_status.c
@@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <console/console.h>
#include "me.h"
diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c
index 4b08c48..26b2c1c 100644
--- a/src/southbridge/intel/common/smbus.c
+++ b/src/southbridge/intel/common/smbus.c
@@ -18,7 +18,6 @@
#include <arch/io.h>
#include <console/console.h>
#include <device/smbus_def.h>
-#include <stdlib.h>
#include "smbus.h"
diff --git a/src/southbridge/intel/fsp_rangeley/early_init.c b/src/southbridge/intel/fsp_rangeley/early_init.c
index 32e3bb5..4eace72 100644
--- a/src/southbridge/intel/fsp_rangeley/early_init.c
+++ b/src/southbridge/intel/fsp_rangeley/early_init.c
@@ -16,7 +16,6 @@
*/
#include <stdint.h>
-#include <stdlib.h>
#include <console/console.h>
#include <arch/io.h>
#include <device/mmio.h>
diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c
index 99078dc..cae7bee 100644
--- a/src/southbridge/intel/i82801ix/i82801ix.c
+++ b/src/southbridge/intel/i82801ix/i82801ix.c
@@ -16,7 +16,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <arch/io.h>
#include <device/pci_ops.h>
#include <device/device.h>
diff --git a/src/southbridge/intel/i82801jx/i82801jx.c b/src/southbridge/intel/i82801jx/i82801jx.c
index ec5576d..e75456c 100644
--- a/src/southbridge/intel/i82801jx/i82801jx.c
+++ b/src/southbridge/intel/i82801jx/i82801jx.c
@@ -16,7 +16,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <arch/io.h>
#include <device/pci_ops.h>
#include <device/device.h>
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index f5f94fe..02ee1ec 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -34,6 +34,7 @@
#include <delay.h>
#include <elog.h>
#include <halt.h>
+#include <stdlib.h>
#include "me.h"
#include "pch.h"
diff --git a/src/southbridge/intel/lynxpoint/me_status.c b/src/southbridge/intel/lynxpoint/me_status.c
index 9ca5552..eca1f17 100644
--- a/src/southbridge/intel/lynxpoint/me_status.c
+++ b/src/southbridge/intel/lynxpoint/me_status.c
@@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <console/console.h>
#include "me.h"
diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c
index f5c52ef..ac230e0 100644
--- a/src/southbridge/intel/lynxpoint/serialio.c
+++ b/src/southbridge/intel/lynxpoint/serialio.c
@@ -21,7 +21,6 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <stdlib.h>
#include "pch.h"
#include "nvs.h"
diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c
index 2123554..2a4ccd1 100644
--- a/src/southbridge/nvidia/ck804/lpc.c
+++ b/src/southbridge/nvidia/ck804/lpc.c
@@ -29,7 +29,6 @@
#include <arch/ioapic.h>
#include <arch/acpi.h>
#include <cpu/x86/lapic.h>
-#include <stdlib.h>
#include <assert.h>
#include <cpu/amd/powernow.h>
#include "chip.h"
diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c
index 1aef631..e7e3218 100644
--- a/src/southbridge/nvidia/mcp55/lpc.c
+++ b/src/southbridge/nvidia/mcp55/lpc.c
@@ -31,7 +31,6 @@
#include <arch/ioapic.h>
#include <cpu/x86/lapic.h>
#include <arch/acpi.h>
-#include <stdlib.h>
#include <cpu/amd/powernow.h>
#include "mcp55.h"
diff --git a/src/superio/fintek/f71805f/superio.c b/src/superio/fintek/f71805f/superio.c
index 4719923..d69b4c5 100644
--- a/src/superio/fintek/f71805f/superio.c
+++ b/src/superio/fintek/f71805f/superio.c
@@ -17,7 +17,6 @@
#include <device/device.h>
#include <device/pnp.h>
#include <superio/conf_mode.h>
-#include <stdlib.h>
#include "f71805f.h"
static void f71805f_init(struct device *dev)
diff --git a/src/superio/fintek/f71808a/superio.c b/src/superio/fintek/f71808a/superio.c
index 200b21e..05132cc 100644
--- a/src/superio/fintek/f71808a/superio.c
+++ b/src/superio/fintek/f71808a/superio.c
@@ -18,7 +18,6 @@
#include <device/device.h>
#include <device/pnp.h>
#include <superio/conf_mode.h>
-#include <stdlib.h>
#include <pc80/keyboard.h>
#include "f71808a.h"
diff --git a/src/superio/fintek/f71859/superio.c b/src/superio/fintek/f71859/superio.c
index da998d0..2cd1bb1 100644
--- a/src/superio/fintek/f71859/superio.c
+++ b/src/superio/fintek/f71859/superio.c
@@ -18,7 +18,6 @@
#include <device/device.h>
#include <device/pnp.h>
#include <superio/conf_mode.h>
-#include <stdlib.h>
#include "f71859.h"
static void f71859_init(struct device *dev)
diff --git a/src/superio/fintek/f71863fg/superio.c b/src/superio/fintek/f71863fg/superio.c
index 634888b..f4ce234 100644
--- a/src/superio/fintek/f71863fg/superio.c
+++ b/src/superio/fintek/f71863fg/superio.c
@@ -17,7 +17,6 @@
#include <device/device.h>
#include <device/pnp.h>
#include <superio/conf_mode.h>
-#include <stdlib.h>
#include <pc80/keyboard.h>
#include "f71863fg.h"
diff --git a/src/superio/fintek/f71869ad/superio.c b/src/superio/fintek/f71869ad/superio.c
index 15fdf3e..67b39ef 100644
--- a/src/superio/fintek/f71869ad/superio.c
+++ b/src/superio/fintek/f71869ad/superio.c
@@ -17,7 +17,6 @@
#include <device/device.h>
#include <device/pnp.h>
#include <superio/conf_mode.h>
-#include <stdlib.h>
#include <pc80/keyboard.h>
#include "fintek_internal.h"
diff --git a/src/superio/fintek/f71872/superio.c b/src/superio/fintek/f71872/superio.c
index 3316ee2..5111b51 100644
--- a/src/superio/fintek/f71872/superio.c
+++ b/src/superio/fintek/f71872/superio.c
@@ -17,7 +17,6 @@
#include <device/device.h>
#include <device/pnp.h>
#include <superio/conf_mode.h>
-#include <stdlib.h>
#include <pc80/keyboard.h>
#include "f71872.h"
diff --git a/src/superio/fintek/f81216h/superio.c b/src/superio/fintek/f81216h/superio.c
index e55ec57..106ab0e 100644
--- a/src/superio/fintek/f81216h/superio.c
+++ b/src/superio/fintek/f81216h/superio.c
@@ -19,7 +19,6 @@
#include <device/pnp.h>
#include <superio/conf_mode.h>
#include <console/console.h>
-#include <stdlib.h>
#include "chip.h"
#include "f81216h.h"
diff --git a/src/superio/fintek/f81865f/superio.c b/src/superio/fintek/f81865f/superio.c
index b6156ee..af48247 100644
--- a/src/superio/fintek/f81865f/superio.c
+++ b/src/superio/fintek/f81865f/superio.c
@@ -17,7 +17,6 @@
#include <device/device.h>
#include <device/pnp.h>
#include <superio/conf_mode.h>
-#include <stdlib.h>
#include <pc80/keyboard.h>
#include "f81865f.h"
diff --git a/src/superio/fintek/f81866d/superio.c b/src/superio/fintek/f81866d/superio.c
index 53a5aac..dd97a1c 100644
--- a/src/superio/fintek/f81866d/superio.c
+++ b/src/superio/fintek/f81866d/superio.c
@@ -19,7 +19,6 @@
#include <device/device.h>
#include <device/pnp.h>
#include <superio/conf_mode.h>
-#include <stdlib.h>
#include <pc80/keyboard.h>
#include "f81866d.h"
#include "fintek_internal.h"
diff --git a/src/superio/intel/i8900/superio.c b/src/superio/intel/i8900/superio.c
index 24805bc..f65ef43 100644
--- a/src/superio/intel/i8900/superio.c
+++ b/src/superio/intel/i8900/superio.c
@@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <device/device.h>
#include <device/pnp.h>
#include <drivers/uart/uart8250reg.h>
diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c
index 57896e0..d0d1a2f 100644
--- a/src/superio/ite/common/env_ctrl.c
+++ b/src/superio/ite/common/env_ctrl.c
@@ -16,7 +16,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <arch/io.h>
#include <console/console.h>
#include <delay.h>
diff --git a/src/superio/ite/it8528e/superio.c b/src/superio/ite/it8528e/superio.c
index 1ed8fe0..d7169e6 100644
--- a/src/superio/ite/it8528e/superio.c
+++ b/src/superio/ite/it8528e/superio.c
@@ -19,7 +19,6 @@
#include <device/device.h>
#include <device/pnp.h>
-#include <stdlib.h>
#include <superio/conf_mode.h>
#include "it8528e.h"
diff --git a/src/superio/ite/it8623e/superio.c b/src/superio/ite/it8623e/superio.c
index 5fdfcef..0448832 100644
--- a/src/superio/ite/it8623e/superio.c
+++ b/src/superio/ite/it8623e/superio.c
@@ -19,7 +19,6 @@
#include <device/device.h>
#include <device/pnp.h>
#include <pc80/keyboard.h>
-#include <stdlib.h>
#include <superio/conf_mode.h>
#include <superio/ite/common/env_ctrl.h>
diff --git a/src/superio/ite/it8671f/superio.c b/src/superio/ite/it8671f/superio.c
index 70da2ab..f62f574 100644
--- a/src/superio/ite/it8671f/superio.c
+++ b/src/superio/ite/it8671f/superio.c
@@ -17,7 +17,6 @@
#include <device/device.h>
#include <device/pnp.h>
#include <pc80/keyboard.h>
-#include <stdlib.h>
#include <superio/conf_mode.h>
#include "it8671f.h"
diff --git a/src/superio/ite/it8712f/superio.c b/src/superio/ite/it8712f/superio.c
index 6f096b0..2004236 100644
--- a/src/superio/ite/it8712f/superio.c
+++ b/src/superio/ite/it8712f/superio.c
@@ -18,7 +18,6 @@
#include <device/device.h>
#include <device/pnp.h>
#include <pc80/keyboard.h>
-#include <stdlib.h>
#include <superio/conf_mode.h>
#include "it8712f.h"
diff --git a/src/superio/ite/it8716f/superio.c b/src/superio/ite/it8716f/superio.c
index de1ef0d..a3b8ec4 100644
--- a/src/superio/ite/it8716f/superio.c
+++ b/src/superio/ite/it8716f/superio.c
@@ -21,7 +21,6 @@
#include <device/pnp.h>
#include <console/console.h>
#include <pc80/keyboard.h>
-#include <stdlib.h>
#include <superio/conf_mode.h>
#include "it8716f.h"
diff --git a/src/superio/ite/it8718f/superio.c b/src/superio/ite/it8718f/superio.c
index ed15955..297aead 100644
--- a/src/superio/ite/it8718f/superio.c
+++ b/src/superio/ite/it8718f/superio.c
@@ -17,7 +17,6 @@
#include <device/device.h>
#include <device/pnp.h>
#include <pc80/keyboard.h>
-#include <stdlib.h>
#include <superio/ite/common/env_ctrl.h>
#include <superio/conf_mode.h>
diff --git a/src/superio/ite/it8721f/superio.c b/src/superio/ite/it8721f/superio.c
index cf3ca3f..e08339c 100644
--- a/src/superio/ite/it8721f/superio.c
+++ b/src/superio/ite/it8721f/superio.c
@@ -18,7 +18,6 @@
#include <device/device.h>
#include <device/pnp.h>
#include <pc80/keyboard.h>
-#include <stdlib.h>
#include <superio/conf_mode.h>
#include "it8721f.h"
diff --git a/src/superio/ite/it8728f/superio.c b/src/superio/ite/it8728f/superio.c
index 7107bb4..58a837e 100644
--- a/src/superio/ite/it8728f/superio.c
+++ b/src/superio/ite/it8728f/superio.c
@@ -18,7 +18,6 @@
#include <device/pnp.h>
#include <superio/conf_mode.h>
#include <pc80/keyboard.h>
-#include <stdlib.h>
#include <superio/ite/common/env_ctrl.h>
#include "chip.h"
diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c
index ed46e73..7c21f10 100644
--- a/src/superio/ite/it8772f/superio.c
+++ b/src/superio/ite/it8772f/superio.c
@@ -20,7 +20,6 @@
#include <pc80/keyboard.h>
#include <arch/io.h>
#include <delay.h>
-#include <stdlib.h>
#include <superio/conf_mode.h>
#include "chip.h" /* FIXME */
diff --git a/src/superio/nsc/pc87309/superio.c b/src/superio/nsc/pc87309/superio.c
index 4f8f967..fac88d1 100644
--- a/src/superio/nsc/pc87309/superio.c
+++ b/src/superio/nsc/pc87309/superio.c
@@ -17,7 +17,6 @@
#include <device/device.h>
#include <device/pnp.h>
#include <pc80/keyboard.h>
-#include <stdlib.h>
#include "pc87309.h"
static void init(struct device *dev)
diff --git a/src/superio/nsc/pc87360/superio.c b/src/superio/nsc/pc87360/superio.c
index 33f27e1..ae96181 100644
--- a/src/superio/nsc/pc87360/superio.c
+++ b/src/superio/nsc/pc87360/superio.c
@@ -18,7 +18,6 @@
#include <device/device.h>
#include <device/pnp.h>
#include <pc80/keyboard.h>
-#include <stdlib.h>
#include "pc87360.h"
static void init(struct device *dev)
diff --git a/src/superio/nsc/pc87366/superio.c b/src/superio/nsc/pc87366/superio.c
index 6d8c66e..c32f55f 100644
--- a/src/superio/nsc/pc87366/superio.c
+++ b/src/superio/nsc/pc87366/superio.c
@@ -18,7 +18,6 @@
#include <device/device.h>
#include <device/pnp.h>
#include <pc80/keyboard.h>
-#include <stdlib.h>
#include "pc87366.h"
static void init(struct device *dev)
diff --git a/src/superio/nsc/pc87382/superio.c b/src/superio/nsc/pc87382/superio.c
index 7c04023..577193e 100644
--- a/src/superio/nsc/pc87382/superio.c
+++ b/src/superio/nsc/pc87382/superio.c
@@ -16,7 +16,6 @@
#include <device/device.h>
#include <device/pnp.h>
-#include <stdlib.h>
#include "pc87382.h"
static void init(struct device *dev)
diff --git a/src/superio/nsc/pc87384/superio.c b/src/superio/nsc/pc87384/superio.c
index cef7ff7..cc76a62 100644
--- a/src/superio/nsc/pc87384/superio.c
+++ b/src/superio/nsc/pc87384/superio.c
@@ -16,7 +16,6 @@
#include <device/device.h>
#include <device/pnp.h>
-#include <stdlib.h>
#include "pc87384.h"
static struct device_operations ops = {
diff --git a/src/superio/nsc/pc87392/superio.c b/src/superio/nsc/pc87392/superio.c
index a15d0a2..7f2df2e 100644
--- a/src/superio/nsc/pc87392/superio.c
+++ b/src/superio/nsc/pc87392/superio.c
@@ -16,7 +16,6 @@
#include <device/device.h>
#include <device/pnp.h>
-#include <stdlib.h>
#include "pc87392.h"
static void init(struct device *dev)
diff --git a/src/superio/nsc/pc87417/superio.c b/src/superio/nsc/pc87417/superio.c
index f867ff3..b1a23d2 100644
--- a/src/superio/nsc/pc87417/superio.c
+++ b/src/superio/nsc/pc87417/superio.c
@@ -19,7 +19,6 @@
#include <device/device.h>
#include <device/pnp.h>
#include <pc80/keyboard.h>
-#include <stdlib.h>
#include "pc87417.h"
static void init(struct device *dev)
diff --git a/src/superio/nsc/pc97317/superio.c b/src/superio/nsc/pc97317/superio.c
index 42f5434..9b5341c 100644
--- a/src/superio/nsc/pc97317/superio.c
+++ b/src/superio/nsc/pc97317/superio.c
@@ -16,7 +16,6 @@
#include <device/device.h>
#include <device/pnp.h>
-#include <stdlib.h>
#include <pc80/keyboard.h>
#include "pc97317.h"
diff --git a/src/superio/nuvoton/nct5104d/superio.c b/src/superio/nuvoton/nct5104d/superio.c
index 40d1200..ded8fcd 100644
--- a/src/superio/nuvoton/nct5104d/superio.c
+++ b/src/superio/nuvoton/nct5104d/superio.c
@@ -16,7 +16,6 @@
#include <device/pnp.h>
#include <superio/conf_mode.h>
-#include <stdlib.h>
#include "nct5104d.h"
#include "chip.h"
diff --git a/src/superio/nuvoton/nct5572d/superio.c b/src/superio/nuvoton/nct5572d/superio.c
index e8249d4..3084687 100644
--- a/src/superio/nuvoton/nct5572d/superio.c
+++ b/src/superio/nuvoton/nct5572d/superio.c
@@ -21,7 +21,6 @@
#include <device/pnp.h>
#include <pc80/keyboard.h>
#include <pc80/mc146818rtc.h>
-#include <stdlib.h>
#include <arch/acpi.h>
#include <superio/conf_mode.h>
diff --git a/src/superio/nuvoton/nct6776/superio.c b/src/superio/nuvoton/nct6776/superio.c
index e399c0a..78e07b6 100644
--- a/src/superio/nuvoton/nct6776/superio.c
+++ b/src/superio/nuvoton/nct6776/superio.c
@@ -19,7 +19,6 @@
#include <device/device.h>
#include <device/pnp.h>
#include <pc80/keyboard.h>
-#include <stdlib.h>
#include <superio/conf_mode.h>
#include "nct6776.h"
diff --git a/src/superio/nuvoton/nct6779d/superio.c b/src/superio/nuvoton/nct6779d/superio.c
index 49e6306..7ef3488 100644
--- a/src/superio/nuvoton/nct6779d/superio.c
+++ b/src/superio/nuvoton/nct6779d/superio.c
@@ -20,7 +20,6 @@
#include <device/device.h>
#include <device/pnp.h>
#include <pc80/keyboard.h>
-#include <stdlib.h>
#include <superio/conf_mode.h>
#include "nct6779d.h"
diff --git a/src/superio/nuvoton/nct6791d/superio.c b/src/superio/nuvoton/nct6791d/superio.c
index 3a6d740..23d5a6f 100644
--- a/src/superio/nuvoton/nct6791d/superio.c
+++ b/src/superio/nuvoton/nct6791d/superio.c
@@ -21,7 +21,6 @@
#include <device/device.h>
#include <device/pnp.h>
#include <pc80/keyboard.h>
-#include <stdlib.h>
#include <superio/conf_mode.h>
#include "nct6791d.h"
diff --git a/src/superio/nuvoton/npcd378/superio.c b/src/superio/nuvoton/npcd378/superio.c
index c1f557e..f11e75a 100644
--- a/src/superio/nuvoton/npcd378/superio.c
+++ b/src/superio/nuvoton/npcd378/superio.c
@@ -23,7 +23,6 @@
#include <device/pnp.h>
#include <option.h>
#include <pc80/keyboard.h>
-#include <stdlib.h>
#include <superio/conf_mode.h>
#include <arch/acpi.h>
#include <arch/acpigen.h>
diff --git a/src/superio/nuvoton/wpcm450/superio.c b/src/superio/nuvoton/wpcm450/superio.c
index c666818..4c5b6d5 100644
--- a/src/superio/nuvoton/wpcm450/superio.c
+++ b/src/superio/nuvoton/wpcm450/superio.c
@@ -17,7 +17,6 @@
#include <device/device.h>
#include <device/pnp.h>
#include <pc80/keyboard.h>
-#include <stdlib.h>
#include "wpcm450.h"
static void init(struct device *dev)
diff --git a/src/superio/renesas/m3885x/superio.c b/src/superio/renesas/m3885x/superio.c
index b200855..043ba0f 100644
--- a/src/superio/renesas/m3885x/superio.c
+++ b/src/superio/renesas/m3885x/superio.c
@@ -18,7 +18,6 @@
#include <console/console.h>
#include <device/smbus.h>
#include <assert.h>
-#include <stdlib.h>
#include <pc80/keyboard.h>
void m3885_configure_multikey(void);
diff --git a/src/superio/smsc/dme1737/superio.c b/src/superio/smsc/dme1737/superio.c
index 0bfd3b8..0723ae2 100644
--- a/src/superio/smsc/dme1737/superio.c
+++ b/src/superio/smsc/dme1737/superio.c
@@ -21,7 +21,6 @@
#include <superio/conf_mode.h>
#include <device/smbus.h>
#include <pc80/keyboard.h>
-#include <stdlib.h>
#include "dme1737.h"
static void dme1737_init(struct device *dev)
diff --git a/src/superio/smsc/fdc37n972/superio.c b/src/superio/smsc/fdc37n972/superio.c
index 0ee9850..3706dec 100644
--- a/src/superio/smsc/fdc37n972/superio.c
+++ b/src/superio/smsc/fdc37n972/superio.c
@@ -17,7 +17,6 @@
#include <device/pnp.h>
#include <superio/conf_mode.h>
#include <pc80/keyboard.h>
-#include <stdlib.h>
#include "fdc37n972.h"
diff --git a/src/superio/smsc/kbc1100/superio.c b/src/superio/smsc/kbc1100/superio.c
index e43e791..16431a7 100644
--- a/src/superio/smsc/kbc1100/superio.c
+++ b/src/superio/smsc/kbc1100/superio.c
@@ -20,7 +20,6 @@
#include <superio/conf_mode.h>
#include <device/smbus.h>
#include <pc80/keyboard.h>
-#include <stdlib.h>
#include "kbc1100.h"
/* Forward declarations */
diff --git a/src/superio/smsc/lpc47b272/superio.c b/src/superio/smsc/lpc47b272/superio.c
index 6ac2d6d..b0582ae 100644
--- a/src/superio/smsc/lpc47b272/superio.c
+++ b/src/superio/smsc/lpc47b272/superio.c
@@ -24,7 +24,6 @@
#include <superio/conf_mode.h>
#include <device/smbus.h>
#include <pc80/keyboard.h>
-#include <stdlib.h>
#include "lpc47b272.h"
/**
diff --git a/src/superio/smsc/lpc47b397/superio.c b/src/superio/smsc/lpc47b397/superio.c
index ad8153f..f7f1c7a 100644
--- a/src/superio/smsc/lpc47b397/superio.c
+++ b/src/superio/smsc/lpc47b397/superio.c
@@ -22,7 +22,6 @@
#include <console/console.h>
#include <device/smbus.h>
#include <pc80/keyboard.h>
-#include <stdlib.h>
#include "lpc47b397.h"
static void enable_hwm_smbus(struct device *dev)
diff --git a/src/superio/smsc/lpc47m10x/superio.c b/src/superio/smsc/lpc47m10x/superio.c
index cd13854..2596ac4 100644
--- a/src/superio/smsc/lpc47m10x/superio.c
+++ b/src/superio/smsc/lpc47m10x/superio.c
@@ -23,7 +23,6 @@
#include <superio/conf_mode.h>
#include <device/smbus.h>
#include <pc80/keyboard.h>
-#include <stdlib.h>
#include "lpc47m10x.h"
/**
diff --git a/src/superio/smsc/lpc47m15x/superio.c b/src/superio/smsc/lpc47m15x/superio.c
index 80ed456..3cb084a 100644
--- a/src/superio/smsc/lpc47m15x/superio.c
+++ b/src/superio/smsc/lpc47m15x/superio.c
@@ -20,7 +20,6 @@
#include <superio/conf_mode.h>
#include <device/smbus.h>
#include <pc80/keyboard.h>
-#include <stdlib.h>
#include "lpc47m15x.h"
/* Forward declarations */
diff --git a/src/superio/smsc/lpc47n207/early_serial.c b/src/superio/smsc/lpc47n207/early_serial.c
index b8e5c0b..f425730 100644
--- a/src/superio/smsc/lpc47n207/early_serial.c
+++ b/src/superio/smsc/lpc47n207/early_serial.c
@@ -16,7 +16,6 @@
#include <arch/io.h>
#include <device/pnp.h>
#include <stdint.h>
-#include <stdlib.h>
#include "lpc47n207.h"
/*
diff --git a/src/superio/smsc/lpc47n217/superio.c b/src/superio/smsc/lpc47n217/superio.c
index b10e8a1..0808cf6 100644
--- a/src/superio/smsc/lpc47n217/superio.c
+++ b/src/superio/smsc/lpc47n217/superio.c
@@ -25,7 +25,6 @@
#include <console/console.h>
#include <device/smbus.h>
#include <assert.h>
-#include <stdlib.h>
#include "lpc47n217.h"
/* Forward declarations */
diff --git a/src/superio/smsc/lpc47n227/superio.c b/src/superio/smsc/lpc47n227/superio.c
index 610f685..c21cdda 100644
--- a/src/superio/smsc/lpc47n227/superio.c
+++ b/src/superio/smsc/lpc47n227/superio.c
@@ -21,7 +21,6 @@
#include <console/console.h>
#include <device/smbus.h>
#include <assert.h>
-#include <stdlib.h>
#include <pc80/keyboard.h>
#include <superio/conf_mode.h>
diff --git a/src/superio/smsc/mec1308/superio.c b/src/superio/smsc/mec1308/superio.c
index 74b8b2e..c3bd150 100644
--- a/src/superio/smsc/mec1308/superio.c
+++ b/src/superio/smsc/mec1308/superio.c
@@ -20,7 +20,6 @@
#include <superio/conf_mode.h>
#include <device/smbus.h>
#include <pc80/keyboard.h>
-#include <stdlib.h>
#include "mec1308.h"
static void mec1308_init(struct device *dev)
diff --git a/src/superio/smsc/sch4037/superio.c b/src/superio/smsc/sch4037/superio.c
index 5e49aa7..0e102e6 100644
--- a/src/superio/smsc/sch4037/superio.c
+++ b/src/superio/smsc/sch4037/superio.c
@@ -19,7 +19,6 @@
#include <device/pnp.h>
#include <superio/conf_mode.h>
#include <pc80/keyboard.h>
-#include <stdlib.h>
#include "sch4037.h"
diff --git a/src/superio/smsc/sio1036/superio.c b/src/superio/smsc/sio1036/superio.c
index a192831..6ed6954 100644
--- a/src/superio/smsc/sio1036/superio.c
+++ b/src/superio/smsc/sio1036/superio.c
@@ -18,7 +18,6 @@
#include <device/device.h>
#include <device/pnp.h>
#include <superio/conf_mode.h>
-#include <stdlib.h>
#include "sio1036.h"
diff --git a/src/superio/smsc/sio10n268/superio.c b/src/superio/smsc/sio10n268/superio.c
index b8243ec..4428b05 100644
--- a/src/superio/smsc/sio10n268/superio.c
+++ b/src/superio/smsc/sio10n268/superio.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <stdlib.h>
#include <device/device.h>
#include <device/pnp.h>
#include <pc80/keyboard.h>
diff --git a/src/superio/smsc/smscsuperio/superio.c b/src/superio/smsc/smscsuperio/superio.c
index 4ce006d..aa5af38 100644
--- a/src/superio/smsc/smscsuperio/superio.c
+++ b/src/superio/smsc/smscsuperio/superio.c
@@ -35,7 +35,6 @@
#include <superio/conf_mode.h>
#include <console/console.h>
#include <pc80/keyboard.h>
-#include <stdlib.h>
/* The following Super I/O chips are currently supported by this driver: */
#define LPC47M172 0x14
diff --git a/src/superio/via/vt1211/superio.c b/src/superio/via/vt1211/superio.c
index 4d7c8de..aa0a464 100644
--- a/src/superio/via/vt1211/superio.c
+++ b/src/superio/via/vt1211/superio.c
@@ -19,7 +19,6 @@
#include <device/device.h>
#include <device/pnp.h>
#include <superio/conf_mode.h>
-#include <stdlib.h>
#include "vt1211.h"
static u8 hwm_io_regs[] = {
diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c
index 9e15037..e1d4c17 100644
--- a/src/superio/winbond/w83627dhg/superio.c
+++ b/src/superio/winbond/w83627dhg/superio.c
@@ -17,7 +17,6 @@
#include <device/pnp.h>
#include <superio/conf_mode.h>
#include <pc80/keyboard.h>
-#include <stdlib.h>
#include "w83627dhg.h"
static void w83627dhg_enable_UR2(struct device *dev)
diff --git a/src/superio/winbond/w83627ehg/superio.c b/src/superio/winbond/w83627ehg/superio.c
index 88fbc31..fdf0a3f 100644
--- a/src/superio/winbond/w83627ehg/superio.c
+++ b/src/superio/winbond/w83627ehg/superio.c
@@ -23,7 +23,6 @@
#include <console/console.h>
#include <pc80/keyboard.h>
#include <pc80/mc146818rtc.h>
-#include <stdlib.h>
#include "w83627ehg.h"
static void enable_hwm_smbus(struct device *dev)
diff --git a/src/superio/winbond/w83627hf/superio.c b/src/superio/winbond/w83627hf/superio.c
index 318eaa4..0a1f4fd 100644
--- a/src/superio/winbond/w83627hf/superio.c
+++ b/src/superio/winbond/w83627hf/superio.c
@@ -23,7 +23,6 @@
#include <console/console.h>
#include <pc80/keyboard.h>
#include <pc80/mc146818rtc.h>
-#include <stdlib.h>
#include "w83627hf.h"
static void enable_hwm_smbus(struct device *dev)
diff --git a/src/superio/winbond/w83627uhg/superio.c b/src/superio/winbond/w83627uhg/superio.c
index 82974ba..3fb4a10 100644
--- a/src/superio/winbond/w83627uhg/superio.c
+++ b/src/superio/winbond/w83627uhg/superio.c
@@ -18,7 +18,6 @@
#include <device/pnp.h>
#include <superio/conf_mode.h>
#include <stdint.h>
-#include <stdlib.h>
#include <pc80/keyboard.h>
#include "w83627uhg.h"
diff --git a/src/superio/winbond/w83667hg-a/superio.c b/src/superio/winbond/w83667hg-a/superio.c
index 0735f04..4a995d6 100644
--- a/src/superio/winbond/w83667hg-a/superio.c
+++ b/src/superio/winbond/w83667hg-a/superio.c
@@ -21,7 +21,6 @@
#include <device/pnp.h>
#include <pc80/keyboard.h>
#include <pc80/mc146818rtc.h>
-#include <stdlib.h>
#include <arch/acpi.h>
#include <superio/conf_mode.h>
diff --git a/src/superio/winbond/w83697hf/superio.c b/src/superio/winbond/w83697hf/superio.c
index a3c132c..aa684a4 100644
--- a/src/superio/winbond/w83697hf/superio.c
+++ b/src/superio/winbond/w83697hf/superio.c
@@ -20,7 +20,6 @@
#include <superio/conf_mode.h>
#include <console/console.h>
#include <lib.h>
-#include <stdlib.h>
#include "chip.h"
#include "w83697hf.h"
diff --git a/src/superio/winbond/w83977tf/superio.c b/src/superio/winbond/w83977tf/superio.c
index b4f316b..c7cd3e8 100644
--- a/src/superio/winbond/w83977tf/superio.c
+++ b/src/superio/winbond/w83977tf/superio.c
@@ -20,7 +20,6 @@
#include <device/pnp.h>
#include <superio/conf_mode.h>
#include <pc80/keyboard.h>
-#include <stdlib.h>
#include "w83977tf.h"
static void w83977tf_init(struct device *dev)
diff --git a/src/superio/winbond/wpcd376i/superio.c b/src/superio/winbond/wpcd376i/superio.c
index ae4fce4..1625fbd 100644
--- a/src/superio/winbond/wpcd376i/superio.c
+++ b/src/superio/winbond/wpcd376i/superio.c
@@ -19,7 +19,6 @@
#include <device/pnp.h>
#include <drivers/uart/uart8250reg.h>
#include <pc80/keyboard.h>
-#include <stdlib.h>
#include "chip.h"
#include "wpcd376i.h"
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id89751c600bad2ddb4b5aa9822adc5c5097787aa
Gerrit-Change-Number: 32023
Gerrit-PatchSet: 1
Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr>
Gerrit-MessageType: newchange
8
52
Change in ...coreboot[master]: arch/x86: Drop Kconfig SIPI_VECTOR_IN_ROM
by Kyösti Mälkki (Code Review) 21 Dec '19
by Kyösti Mälkki (Code Review) 21 Dec '19
21 Dec '19
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30856
Change subject: arch/x86: Drop Kconfig SIPI_VECTOR_IN_ROM
......................................................................
arch/x86: Drop Kconfig SIPI_VECTOR_IN_ROM
This was used to enforce 4kiB alignment of _start16bit in
romcc bootblock. Platforms requiring this moved away to
C_ENVIRONMENT_BOOTBLOCK that globally forces the alignment.
Change-Id: I8ca453bbc56ab2aeb127f3e081c69e1b38bb8396
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/arch/x86/Kconfig
M src/arch/x86/failover.ld
M src/cpu/intel/car/p4-netburst/cache_as_ram.S
M src/cpu/intel/model_106cx/Kconfig
M src/cpu/intel/socket_LGA775/Kconfig
M src/cpu/intel/socket_mPGA604/Kconfig
M src/cpu/x86/16bit/entry16.inc
7 files changed, 5 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/30856/1
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 242a7cf..c2fc914 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -81,13 +81,6 @@
default n
depends on ARCH_X86 && SMP
-# Aligns 16bit entry code in bootblock so that hyper-threading CPUs
-# can boot AP CPUs to enable their shared caches.
-config SIPI_VECTOR_IN_ROM
- bool
- default n
- depends on ARCH_X86
-
# Set the rambase for systems that still need it, only 5 chipsets as of
# Sep 2018. This value was 0x100000, chosen to match the entry point
# of Linux 2.2 in 1999. The new value, 14 MiB, makes a lot more sense
diff --git a/src/arch/x86/failover.ld b/src/arch/x86/failover.ld
index b32aa29..eabc9f7 100644
--- a/src/arch/x86/failover.ld
+++ b/src/arch/x86/failover.ld
@@ -23,12 +23,11 @@
TARGET(binary)
SECTIONS
{
- /* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs
- * with Startup IPI message without RAM. Align .rom to next 4 byte
- * boundary anyway, so no pad byte appears between _rom and _start.
+ /* Align .rom to 4 byte boundary so no pad byte appears
+ * between _rom and _start.
*/
.bogus ROMLOC_MIN : {
- . = CONFIG_SIPI_VECTOR_IN_ROM ? ALIGN(4096) : ALIGN(4);
+ . = ALIGN(4);
ROMLOC = .;
} >rom = 0xff
@@ -49,12 +48,7 @@
* may cause the total size of a section to change when the start
* address gets applied.
*/
- ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) -
- (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0);
-
- /* Post-check proper SIPI vector. */
- _bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || (ap_sipi_vector_in_rom == 0xff),
- "Address mismatch on AP_SIPI_VECTOR");
+ ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16);
/DISCARD/ : {
*(.comment)
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
index fda572d..5c579a1 100644
--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -23,10 +23,6 @@
/* Macro to access Local APIC registers at default base. */
#define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x)
-#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
-/* Fixed location, ASSERTED in failover.ld if it changes. */
-.set ap_sipi_vector_in_rom, 0xff
-#endif
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig
index f365cf1..2a324fb 100644
--- a/src/cpu/intel/model_106cx/Kconfig
+++ b/src/cpu/intel/model_106cx/Kconfig
@@ -7,7 +7,6 @@
select SMP
select SSE2
select UDELAY_LAPIC
- select SIPI_VECTOR_IN_ROM
select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig
index 8b227bd..6c3d837 100644
--- a/src/cpu/intel/socket_LGA775/Kconfig
+++ b/src/cpu/intel/socket_LGA775/Kconfig
@@ -13,7 +13,6 @@
select CPU_INTEL_MODEL_1067X
select MMX
select SSE
- select SIPI_VECTOR_IN_ROM
config DCACHE_RAM_SIZE
hex
diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig
index ca2f7b3..e860ded 100644
--- a/src/cpu/intel/socket_mPGA604/Kconfig
+++ b/src/cpu/intel/socket_mPGA604/Kconfig
@@ -9,7 +9,6 @@
select MMX
select SSE
select UDELAY_TSC
- select SIPI_VECTOR_IN_ROM
select C_ENVIRONMENT_BOOTBLOCK
# mPGA604 are usually Intel Netburst CPUs which should have SSE2
diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc
index 2a9f8c5..f110980 100644
--- a/src/cpu/x86/16bit/entry16.inc
+++ b/src/cpu/x86/16bit/entry16.inc
@@ -29,8 +29,7 @@
#include <arch/rom_segs.h>
-#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) || \
- IS_ENABLED(CONFIG_SIPI_VECTOR_IN_ROM)
+#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
/* Symbol _start16bit must be aligned to 4kB to start AP CPUs with
* Startup IPI message without RAM.
*/
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I8ca453bbc56ab2aeb127f3e081c69e1b38bb8396
Gerrit-Change-Number: 30856
Gerrit-PatchSet: 1
Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-MessageType: newchange
2
10
Change in ...coreboot[master]: [WIP] Move AGESA and apufw higher in CBFS
by Kyösti Mälkki (Code Review) 19 Dec '19
by Kyösti Mälkki (Code Review) 19 Dec '19
19 Dec '19
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31076
Change subject: [WIP] Move AGESA and apufw higher in CBFS
......................................................................
[WIP] Move AGESA and apufw higher in CBFS
Increases continuous free space in CBFS
from 5.8 MiB to 7.1 MiB.
Will not work with released binaryPI build
from 3rdparty/blobs.
Change-Id: I3c166102b8774499a0b21f212b5e8a66fe6c52eb
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/southbridge/amd/pi/hudson/Makefile.inc
M src/vendorcode/amd/pi/Kconfig
2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/31076/1
diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc
index 81fe7ff..57bad38 100644
--- a/src/southbridge/amd/pi/hudson/Makefile.inc
+++ b/src/southbridge/amd/pi/hudson/Makefile.inc
@@ -75,7 +75,7 @@
ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)
HUDSON_FWM_POSITION=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 0x20000 1)
else
-HUDSON_FWM_POSITION=0xfff20000
+HUDSON_FWM_POSITION=0xfffa0000
endif
ifeq ($(CONFIG_HUDSON_PSP), y)
diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig
index f463b7d..3dc7052 100644
--- a/src/vendorcode/amd/pi/Kconfig
+++ b/src/vendorcode/amd/pi/Kconfig
@@ -96,7 +96,7 @@
config AGESA_BINARY_PI_LOCATION
hex "AGESA PI binary address in ROM"
- default 0xFFE00000
+ default 0xFFF00000
depends on !AGESA_BINARY_PI_AS_STAGE
help
Specify the ROM address at which to store the binary Platform
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I3c166102b8774499a0b21f212b5e8a66fe6c52eb
Gerrit-Change-Number: 31076
Gerrit-PatchSet: 1
Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-MessageType: newchange
3
3
Change in ...coreboot[master]: [RFC] Initial commit to support SKL SP and OCP Tiogapass platform
by Name of user not set (Code Review) 03 Dec '19
by Name of user not set (Code Review) 03 Dec '19
03 Dec '19
Name of user not set #1002246 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31205
Change subject: [RFC] Initial commit to support SKL SP and OCP Tiogapass platform
......................................................................
[RFC] Initial commit to support SKL SP and OCP Tiogapass platform
Summary:
This commit adds support for SK SP and OCP Tiogapass platform:
* Added microcode files.
* Added FSP header files.
* Updated skylake soc code to accomodate FSP 2.0.
* Added tiogapass platform code to accomodate FSP 2.0.
With this commit, it is able to build coreboot.rom image.
The 3 FSP binaries are added to the coreboot image. It looks
okay by examining the coreboot.rom file through ifdtool command.
However, when booting with this image, no postcode is
observed on port 80, no UART message shows up. Debugging
is on-going. This commit is submitted as draft to enable
early review feedback.
Change-Id: I389355162eb9515b533a8d7f77cc8f03b8beb019
Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com>
test
Change-Id: I033a52bc3f0b86f0ec1db8325b7435d20d194fda
---
M src/Kconfig
M src/drivers/intel/fsp2_0/include/fsp/api.h
A src/mainboard/ocp/tiogapass/Kconfig
A src/mainboard/ocp/tiogapass/Kconfig.name
A src/mainboard/ocp/tiogapass/Makefile.inc
A src/mainboard/ocp/tiogapass/acpi/mainboard.asl
A src/mainboard/ocp/tiogapass/board_id.c
A src/mainboard/ocp/tiogapass/board_id.h
A src/mainboard/ocp/tiogapass/board_info.txt
A src/mainboard/ocp/tiogapass/bootblock.c
A src/mainboard/ocp/tiogapass/cmos.default
A src/mainboard/ocp/tiogapass/cmos.layout
A src/mainboard/ocp/tiogapass/devicetree.cb
A src/mainboard/ocp/tiogapass/dsdt.asl
A src/mainboard/ocp/tiogapass/gpio.h
A src/mainboard/ocp/tiogapass/pei_data.c
A src/mainboard/ocp/tiogapass/ramstage.c
A src/mainboard/ocp/tiogapass/romstage.c
A src/mainboard/ocp/tiogapass/spd/Makefile.inc
A src/mainboard/ocp/tiogapass/spd/spd.h
A src/mainboard/ocp/tiogapass/spd/spd_util.c
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/Makefile.inc
M src/soc/intel/skylake/chip_fsp20.c
M src/soc/intel/skylake/include/fsp20/soc/ramstage.h
M src/soc/intel/skylake/irq.c
M src/soc/intel/skylake/romstage/romstage_fsp20.c
M src/soc/intel/skylake/vr_config.c
M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DebugSupport.h
A src/vendorcode/intel/fsp/fsp2_0/skykabylake/FirmwareVersionInfoHob.h
A src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h
A src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h
A src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h
A src/vendorcode/intel/fsp/fsp2_0/skykabylake/FsptUpd.h
34 files changed, 1,968 insertions(+), 162 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/31205/1
diff --git a/src/Kconfig b/src/Kconfig
index a069f63..7de3335 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -360,6 +360,7 @@
source "src/ec/*/*/Kconfig"
# FIXME move to vendorcode
source "src/drivers/intel/fsp1_0/Kconfig"
+source "src/drivers/intel/fsp2_0/Kconfig"
source "src/southbridge/intel/common/firmware/Kconfig"
source "src/vendorcode/*/Kconfig"
diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
index 5ed3801..666020a 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/api.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -66,9 +66,9 @@
void platform_fsp_notify_status(enum fsp_notify_phase phase);
/* Initialize memory margin analysis settings. */
-void setup_mma(FSP_M_CONFIG *memory_cfg);
+void setup_mma(FSPM_CONFIG *memory_cfg);
/* Update the SOC specific memory config param for mma. */
-void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg,
+void soc_update_memory_params_for_mma(FSPM_CONFIG *memory_cfg,
struct mma_config_param *mma_cfg);
/*
diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig
new file mode 100644
index 0000000..c411b15
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/Kconfig
@@ -0,0 +1,58 @@
+if BOARD_OCP_TIOGAPASS
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_32768
+ select CONSOLE_SERIAL
+ select DRIVERS_UART
+ select GENERIC_SPD_BIN
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select EC_ACPI
+ select HAVE_OPTION_TABLE
+ select HAVE_SMI_HANDLER
+ select SERIRQ_CONTINUOUS_MODE
+ select SKYLAKE_SOC_PCH_H
+ select SOC_INTEL_SKYLAKE
+ select SUPERIO_NUVOTON_NCT6776
+ select SUPERIO_NUVOTON_NCT6776_COM_A
+ select MAINBOARD_USES_FSP2_0
+ select HAVE_CMOS_DEFAULT
+
+
+config PLATFORM_USES_FSP2_0
+ bool "FSP driver 2.0"
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config MAINBOARD_DIR
+ string
+ default "ocp/tiogapass"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Tioga Pass"
+
+config MAINBOARD_FAMILY
+ string
+ default "OCP_TiogaPass"
+
+config CBFS_SIZE
+ hex
+ default 0x1000000
+
+config VIRTUAL_ROM_SIZE
+ hex
+ default 0x2000000
+
+config MAX_CPUS
+ int
+ default 8
+
+config TPM_PIRQ
+ hex
+ default 0x18 # GPP_E0_IRQ
+
+endif # BOARD_OCP_TIOGAPASS
diff --git a/src/mainboard/ocp/tiogapass/Kconfig.name b/src/mainboard/ocp/tiogapass/Kconfig.name
new file mode 100644
index 0000000..0c57fd3
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_OCP_TIOGAPASS
+ bool "Tioga Pass"
diff --git a/src/mainboard/ocp/tiogapass/Makefile.inc b/src/mainboard/ocp/tiogapass/Makefile.inc
new file mode 100644
index 0000000..77cdb16
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/Makefile.inc
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+## Copyright (C) 2016 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+subdirs-y += spd
+
+bootblock-y += bootblock.c
+romstage-y += pei_data.c
+romstage-y += board_id.c
+
+ramstage-y += ramstage.c
diff --git a/src/mainboard/ocp/tiogapass/acpi/mainboard.asl b/src/mainboard/ocp/tiogapass/acpi/mainboard.asl
new file mode 100644
index 0000000..5174eeb
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/acpi/mainboard.asl
@@ -0,0 +1,17 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/gpio.h>
diff --git a/src/mainboard/ocp/tiogapass/board_id.c b/src/mainboard/ocp/tiogapass/board_id.c
new file mode 100644
index 0000000..a362b08
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/board_id.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include "board_id.h"
+#include <ec/acpi/ec.h>
+#include <stdint.h>
+
+/*
+ * Get Board ID via EC I/O port write/read
+ */
+int get_board_id(void)
+{
+ uint8_t buffer[2];
+ uint8_t index;
+ if (send_ec_command(EC_FAB_ID_CMD) == 0) {
+ for (index = 0; index < sizeof(buffer); index++)
+ buffer[index] = recv_ec_data();
+ return (buffer[1] << 8) | buffer[0];
+ }
+ return -1;
+}
diff --git a/src/mainboard/ocp/tiogapass/board_id.h b/src/mainboard/ocp/tiogapass/board_id.h
new file mode 100644
index 0000000..881866f
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/board_id.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MAINBOARD_BOARD_ID_H_
+#define _MAINBOARD_BOARD_ID_H_
+
+/* Mobile Board Id 0x00 - 0xFF */
+#define BOARD_ID_SKL_A0_RVP3 0x04
+#define BOARD_ID_SKL_RVP7 0x0B
+
+/* 60-6F reserved for KBL RVPs */
+#define BOARD_ID_KBL_LPDDR3_RVP3 0x60
+#define BOARD_ID_KBL_LPDDR3_RVP7 0x64
+
+/* Board/FAB ID Command */
+#define EC_FAB_ID_CMD 0x0D
+
+/*
+ * Returns board information (board id[15:8] and
+ * Fab info[7:0]) on success and < 0 on error
+ */
+int get_board_id(void);
+
+#endif /* _MAINBOARD_BOARD_ID_H_ */
diff --git a/src/mainboard/ocp/tiogapass/board_info.txt b/src/mainboard/ocp/tiogapass/board_info.txt
new file mode 100644
index 0000000..25dac38
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/board_info.txt
@@ -0,0 +1,5 @@
+Board name: Tioga Pass
+Category: server
+ROM protocol: SPI
+ROM socketed: yes
+Release year: 2017
diff --git a/src/mainboard/ocp/tiogapass/bootblock.c b/src/mainboard/ocp/tiogapass/bootblock.c
new file mode 100644
index 0000000..cf9740d
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/bootblock.c
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <soc/gpio.h>
+#include "gpio.h"
+
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6776/nct6776.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
+
+static void early_config_gpio(void)
+{
+ /* This is a hack for FSP because it does things in MemoryInit()
+ * which it shouldn't do. We have to prepare certain gpios here
+ * because of the brokenness in FSP. */
+ gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
+
+void bootblock_mainboard_init(void)
+{
+ early_config_gpio();
+}
+
+void bootblock_mainboard_early_init(void)
+{
+ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
diff --git a/src/mainboard/ocp/tiogapass/cmos.default b/src/mainboard/ocp/tiogapass/cmos.default
new file mode 100644
index 0000000..cd8bd47
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/cmos.default
@@ -0,0 +1,4 @@
+boot_option=Fallback
+debug_level=Spew
+power_on_after_fail=Disable
+nmi=Enable
diff --git a/src/mainboard/ocp/tiogapass/cmos.layout b/src/mainboard/ocp/tiogapass/cmos.layout
new file mode 100644
index 0000000..83a2e05
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/cmos.layout
@@ -0,0 +1,117 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+## Copyright (C) 2016 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+# -----------------------------------------------------------------
+# Status Register A
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 r 0 unused
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: cpu
+#401 7 r 0 unused
+
+# coreboot config options: southbridge
+409 2 e 7 power_on_after_fail
+#411 5 r 0 unused
+
+# coreboot config options: bootloader
+#544 440 r 0 unused
+
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 0 Emergency
+6 1 Alert
+6 2 Critical
+6 3 Error
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb
new file mode 100644
index 0000000..9b23a0e
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/devicetree.cb
@@ -0,0 +1,293 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2017 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+chip soc/intel/skylake
+
+ # Enable deep Sx states
+ register "deep_s5_enable_ac" = "0"
+ register "deep_s5_enable_dc" = "0"
+ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "gpe0_dw0" = "GPP_B"
+ register "gpe0_dw1" = "GPP_D"
+ register "gpe0_dw2" = "GPP_E"
+
+ # Enable "Intel Speed Shift Technology"
+ register "speed_shift_enable" = "1"
+
+ # FSP Configuration
+ register "EnableAzalia" = "1"
+ register "DspEnable" = "1"
+ register "IoBufferOwnership" = "3"
+ register "SmbusEnable" = "1"
+ register "ScsEmmcEnabled" = "0"
+ register "ScsEmmcHs400Enabled" = "0"
+ register "ScsSdCardEnabled" = "0"
+ register "InternalGfx" = "1"
+ register "SkipExtGfxScan" = "1"
+ register "Device4Enable" = "0"
+ register "Heci3Enabled" = "0"
+
+ register "SaGv" = "3"
+ register "PmTimerDisabled" = "0"
+
+ # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
+ # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
+ register "PmConfigSlpS3MinAssert" = "0x02"
+
+ # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s
+ register "PmConfigSlpS4MinAssert" = "0x04"
+
+ # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s
+ register "PmConfigSlpSusMinAssert" = "0x03"
+
+ # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
+ register "PmConfigSlpAMinAssert" = "0x03"
+
+ # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled
+ register "SerialIrqConfigSirqEnable" = "0x01"
+ register "SerialIrqConfigSirqMode" = "0x01"
+
+ # VR Settings Configuration for 5 Domains
+ #+----------------+-------+-------+-------------+-------------+-------+
+ #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT |
+ #+----------------+-------+-------+-------------+-------------+-------+
+ #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A |
+ #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A |
+ #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A |
+ #| Psi3Enable | 1 | 1 | 1 | 1 | 1 |
+ #| Psi4Enable | 1 | 1 | 1 | 1 | 1 |
+ #| ImonSlope | 0 | 0 | 0 | 0 | 0 |
+ #| ImonOffset | 0 | 0 | 0 | 0 | 0 |
+ #| IccMax | 7A | 34A | 34A | 35A | 35A |
+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V |
+ #+----------------+-------+-------+-------------+-------------+-------+
+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
+ .vr_config_enable = 1, \
+ .psi1threshold = 0x50, \
+ .psi2threshold = 0x10, \
+ .psi3threshold = 0x4, \
+ .psi3enable = 1, \
+ .psi4enable = 1, \
+ .imon_slope = 0x0, \
+ .imon_offset = 0x0, \
+ .icc_max = 0x1C, \
+ .voltage_limit = 0x5F0 \
+ }"
+
+ register "domain_vr_config[VR_IA_CORE]" = "{
+ .vr_config_enable = 1, \
+ .psi1threshold = 0x50, \
+ .psi2threshold = 0x14, \
+ .psi3threshold = 0x4, \
+ .psi3enable = 1, \
+ .psi4enable = 1, \
+ .imon_slope = 0x0, \
+ .imon_offset = 0x0, \
+ .icc_max = 0x88, \
+ .voltage_limit = 0x5F0 \
+ }"
+
+ register "domain_vr_config[VR_GT_UNSLICED]" = "{
+ .vr_config_enable = 1, \
+ .psi1threshold = 0x50, \
+ .psi2threshold = 0x14, \
+ .psi3threshold = 0x4, \
+ .psi3enable = 1, \
+ .psi4enable = 1, \
+ .imon_slope = 0x0, \
+ .imon_offset = 0x0, \
+ .icc_max = 0x8C ,\
+ .voltage_limit = 0x5F0 \
+ }"
+
+ register "domain_vr_config[VR_GT_SLICED]" = "{
+ .vr_config_enable = 1, \
+ .psi1threshold = 0x50, \
+ .psi2threshold = 0x14, \
+ .psi3threshold = 0x4, \
+ .psi3enable = 1, \
+ .psi4enable = 1, \
+ .imon_slope = 0x0, \
+ .imon_offset = 0x0, \
+ .icc_max = 0x8C, \
+ .voltage_limit = 0x5F0 \
+ }"
+
+ # Skip coreboot MP Init
+ register "common_soc_config" = "{
+ .use_fsp_mp_init = 1,
+ }"
+
+ # Enable x1 slot
+ register "PcieRpEnable[7]" = "1"
+ register "PcieRpClkReqSupport[7]" = "1"
+ register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3
+
+ # Enable x4 slot
+ register "PcieRpEnable[8]" = "1"
+ register "PcieRpClkReqSupport[8]" = "1"
+ register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4
+
+ # Enable Root port 6 and 13.
+ register "PcieRpEnable[5]" = "1"
+ register "PcieRpEnable[12]" = "1"
+
+ # Enable CLKREQ#
+ register "PcieRpClkReqSupport[5]" = "1"
+ register "PcieRpClkReqSupport[12]" = "1"
+
+ # RP 6 uses SRCCLKREQ1# while RP `3 uses SRCCLKREQ2#
+ register "PcieRpClkReqNumber[5]" = "0"
+ register "PcieRpClkReqNumber[12]" = "1"
+
+ register "EnableLan" = "1"
+
+ # USB related
+ register "SsicPortEnable" = "1"
+
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # OTG
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Touch Pad
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 BT
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Touch Panel
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Front Panel
+ register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # Front Panel
+ register "usb2_ports[7]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb)
+ register "usb2_ports[8]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb)
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK
+ register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK
+ register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" # Finger print sensor
+ register "usb2_ports[12]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn
+ register "usb2_ports[13]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" # OTG
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Flex
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # IVCAM
+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK
+ register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel
+ register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel
+ register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn
+ register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn
+ register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK
+
+ register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
+
+ # Must leave UART0 enabled or SD/eMMC will not work as PCI
+
+ register "pirqa_routing" = "0x0b"
+ register "pirqb_routing" = "0x0a"
+ register "pirqc_routing" = "0x0b"
+ register "pirqd_routing" = "0x0b"
+ register "pirqe_routing" = "0x0b"
+ register "pirqf_routing" = "0x0b"
+ register "pirqg_routing" = "0x0b"
+ register "pirqh_routing" = "0x0b"
+
+ register "PmTimerDisabled" = "0"
+
+ register "EnableSata" = "1"
+ register "SataSalpSupport" = "1"
+ register "SataPortsEnable" = "{ \
+ [0] = 1, \
+ [1] = 1, \
+ [2] = 1, \
+ [3] = 1, \
+ [4] = 1, \
+ [5] = 1, \
+ [6] = 1, \
+ [7] = 1, \
+ }"
+ register "SerialIoDevMode" = "{ \
+ [PchSerialIoIndexI2C0] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C1] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C2] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C3] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C4] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C5] = PchSerialIoPci, \
+ [PchSerialIoIndexSpi0] = PchSerialIoPci, \
+ [PchSerialIoIndexSpi1] = PchSerialIoPci, \
+ [PchSerialIoIndexUart0] = PchSerialIoPci, \
+ [PchSerialIoIndexUart1] = PchSerialIoPci, \
+ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
+ }"
+
+ # PL2 override 25W
+ register "tdp_pl2_override" = "25"
+
+ # Send an extra VR mailbox command for the PS4 exit issue
+ register "SendVrMbxCmd" = "2"
+
+ # Enable/Disable VMX feature
+ register "VmxEnable" = "0"
+ # Use default SD card detect GPIO configuration
+ #register "sdcard_cd_gpio_default" = "GPP_A7"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 14.0 on end # USB xHCI
+ device pci 14.1 off end # USB xDCI (OTG)
+ device pci 14.2 on end # Thermal Subsystem
+ device pci 15.0 on end # I2C #0
+ device pci 15.1 on end # I2C #1
+ device pci 15.2 on end # I2C #2
+ device pci 15.3 on end # I2C #3
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 17.0 on end # SATA
+ device pci 19.0 on end # UART #2
+ device pci 19.1 on end # I2C #5
+ device pci 19.2 on end # I2C #4
+ device pci 1c.0 on end # PCI Express Port 1
+ device pci 1c.1 off end # PCI Express Port 2
+ device pci 1c.2 off end # PCI Express Port 3
+ device pci 1c.3 off end # PCI Express Port 4
+ device pci 1c.4 off end # PCI Express Port 5
+ device pci 1c.5 off end # PCI Express Port 6
+ device pci 1c.6 off end # PCI Express Port 7
+ device pci 1c.7 off end # PCI Express Port 8
+ device pci 1d.0 off end # PCI Express Port 9
+ device pci 1d.1 off end # PCI Express Port 10
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 off end # PCI Express Port 12
+ device pci 1e.0 on end # UART #0
+ device pci 1e.1 on end # UART #1
+ device pci 1e.2 on end # GSPI #0
+ device pci 1e.3 on end # GSPI #1
+ device pci 1e.4 off end # eMMC
+ device pci 1e.5 off end # SDIO
+ device pci 1e.6 off end # SDCard
+ device pci 1f.0 on
+ end # LPC Interface
+ device pci 1f.1 on end # P2SB
+ device pci 1f.2 on end # Power Management Controller
+ device pci 1f.3 on end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 on end # PCH SPI
+ device pci 1f.6 on end # GbE
+ end
+end
diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl
new file mode 100644
index 0000000..45d9a85
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/dsdt.asl
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x05, // DSDT revision: ACPI v5.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20110725 // OEM revision
+)
+{
+ // Some generic macros
+ #include <soc/intel/skylake/acpi/platform.asl>
+
+ // global NVS and variables
+ #include <soc/intel/skylake/acpi/globalnvs.asl>
+
+ // CPU
+ #include <soc/intel/skylake/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <soc/intel/skylake/acpi/systemagent.asl>
+ #include <soc/intel/skylake/acpi/pch.asl>
+ }
+ }
+
+ // Chipset specific sleep states
+ #include <soc/intel/skylake/acpi/sleepstates.asl>
+
+ // Mainboard specific
+ #include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/ocp/tiogapass/gpio.h b/src/mainboard/ocp/tiogapass/gpio.h
new file mode 100644
index 0000000..f8db6cd
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/gpio.h
@@ -0,0 +1,183 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _GPIORVP8_H
+#define _GPIORVP8_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* TCA6424A I/O Expander */
+#define IO_EXPANDER_BUS 4
+#define IO_EXPANDER_0_ADDR 0x22
+#define IO_EXPANDER_P0CONF 0x0C /* Port 0 conf offset */
+#define IO_EXPANDER_P0DOUT 0x04 /* Port 0 data offset */
+#define IO_EXPANDER_P1CONF 0x0D
+#define IO_EXPANDER_P1DOUT 0x05
+#define IO_EXPANDER_P2CONF 0x0E
+#define IO_EXPANDER_P2DOUT 0x06
+#define IO_EXPANDER_1_ADDR 0x23
+
+/* GPE_EC_WAKE */
+#define GPE_EC_WAKE GPE0_LAN_WAK
+#define EC_SMI_GPI GPP_I3
+
+/*
+ * Gpio based irq for touchpad, 18th index in North Bank
+ * MAX_DIRECT_IRQ + GPSW_SIZE + 19
+ */
+#define KBLRVP_TOUCHPAD_IRQ 33
+
+#define KBLRVP_TOUCH_IRQ 31
+
+#define BOARD_TOUCHPAD_NAME "touchpad"
+#define BOARD_TOUCHPAD_IRQ KBLRVP_TOUCHPAD_IRQ
+#define BOARD_TOUCHPAD_I2C_BUS 0
+#define BOARD_TOUCHPAD_I2C_ADDR 0x20
+
+#define BOARD_TOUCHSCREEN_NAME "touchscreen"
+#define BOARD_TOUCHSCREEN_IRQ KBLRVP_TOUCH_IRQ
+#define BOARD_TOUCHSCREEN_I2C_BUS 0
+#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4c
+
+#ifndef __ACPI__
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+/* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF3),
+/* EC_LPC_IO0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF3),
+/* EC_LPC_IO1*/ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF3),
+/* EC_LPC_IO2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF3),
+/* EC_LPC_IO3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF3),
+/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF3),
+/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF3),
+/* PIRQAB */ PAD_CFG_GPI(GPP_A7, NONE, DEEP),
+/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+/* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF3),
+/* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1),
+/* PMEB */ PAD_CFG_GPI(GPP_A11, NONE, DEEP),
+/* SUS_PWR_ACK_R */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
+/* PM_SUS_ESPI_RST */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF3),
+/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1),
+/* BT_RF_KILL */ PAD_CFG_GPO(GPP_B3, 1, DEEP),
+/* EXTTS_SNI_DRV1 */ PAD_CFG_NF(GPP_B4, NONE, DEEP, NF1),
+/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES),
+/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+/* GPP_B_14_SPKR */ PAD_CFG_NF(GPP_B14, 20K_PD, DEEP, NF1),
+/* GSPI0_MISO */ PAD_CFG_GPO(GPP_B17, 1, DEEP),
+/* PCHHOTB */ PAD_CFG_NF(GPP_B23, 20K_PD, DEEP, NF2),
+/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 1, DEEP),
+/* SML0_CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
+/* SML0_DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
+/* SML1_CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
+/* SML1_DATA */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
+/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
+/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
+/* UART0_RTS_N */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
+/* UART0_CTS_N */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
+/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+/* UART2_RTS_N */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
+/* UART2_CTS_N */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
+/* SSP0_SFRM */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+/* SSP0_TXD */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+/* SSP0_RXD */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
+/* SSP0_SCLK */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
+/* SATAE_IFDET */ PAD_CFG_NF(GPP_E0, 20K_PU, DEEP, NF1),
+/* SATAE_IFDET */ PAD_CFG_NF(GPP_E1, 20K_PU, DEEP, NF1),
+/* CPU_GP0 */ PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1),
+/* SSD_SATA_DEVSLP */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1),
+/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
+/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
+/* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
+/* SATAXPCIE_4 */ PAD_CFG_NF(GPP_F1, 20K_PU, DEEP,NF1),
+/* SATA_DEVSLP_3 */ PAD_CFG_GPI_ACPI_SCI(GPP_F5, NONE, DEEP, YES),
+/* SATA_DEVSLP_4 */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
+/* SATA_SCLOCK */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP),
+/* SATA_SLOAD */ PAD_CFG_GPI(GPP_F11, NONE, DEEP),
+/* SATA_SDATAOUT1 */ PAD_CFG_GPI_APIC(GPP_F12, NONE, DEEP),
+/* SATA_SDATAOUT0 */ PAD_CFG_GPI_APIC(GPP_F13, NONE, DEEP),
+/* H_SKTOCC_N */ PAD_CFG_GPI_APIC(GPP_F14, NONE, DEEP),
+/* USB_OC4_R_N */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
+/* USB_OC5_R_N */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
+/* USB_OC6_R_N */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
+/* USB_OC7_R_N */ PAD_CFG_GPO(GPP_F18, 1, DEEP),
+/* GPIO_PEG_RESET */ PAD_CFG_GPO(GPP_F22, 1, DEEP),
+/* VCORE_VBOOST_CTRL */ PAD_CFG_GPO(GPP_F23, 0, DEEP),
+/* FAN_TACH_0 */ PAD_CFG_GPO(GPP_G0, 1, DEEP),
+/* FAN_TACH_1 */ PAD_CFG_GPO(GPP_G1, 1, DEEP),
+/* FAN_TACH_2 */ PAD_CFG_GPI_ACPI_SCI(GPP_G2, NONE, DEEP, YES),
+/* FAN_TACH_3 */ PAD_CFG_GPI_ACPI_SCI(GPP_G3, NONE, DEEP, YES),
+/* FAN_TACH_4 */ PAD_CFG_GPO(GPP_G4, 1, DEEP),
+/* FAN_TACH_5 */ PAD_CFG_GPI_APIC(GPP_G5, NONE, DEEP),
+/* FAN_TACH_6 */ PAD_CFG_GPI_ACPI_SCI(GPP_G6, NONE, DEEP, YES),
+/* FAN_TACH_7 */ PAD_CFG_GPO(GPP_G7, 1, DEEP),
+/* GSXDOUT */ PAD_CFG_GPI_ACPI_SCI(GPP_G12, 20K_PD, DEEP, YES),
+/* GSXSLOAD */ PAD_CFG_GPO(GPP_G13, 1, DEEP),
+/* GSXDIN */ PAD_CFG_GPI_ACPI_SCI(GPP_G14, NONE, DEEP, YES),
+/* GSXSRESETB */ PAD_CFG_GPO(GPP_G15, 0, DEEP),
+/* GSXCLK */ PAD_CFG_GPO(GPP_G16, 0, DEEP),
+/* NMIB */ PAD_CFG_GPI_APIC(GPP_G18, NONE, DEEP),
+/* SMIB */ PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1),
+/* TEST_SETUP_MENU */ PAD_CFG_GPI_APIC(GPP_G20, NONE, DEEP),
+/* P_INTF_N */ PAD_CFG_GPI_ACPI_SCI(GPP_G21, NONE, DEEP, YES),
+/* PCH_PEGSLOT1 */ PAD_CFG_GPO(GPP_G22, 1, DEEP),
+/* IVCAM_DFU_R */ PAD_CFG_GPO(GPP_G23, 1, DEEP),
+/* SRCCLKREQB_8 */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
+/* SML2CLK */ PAD_CFG_GPI(GPP_H10, NONE, DEEP),
+/* SML2DATA */ PAD_CFG_GPI(GPP_H11, NONE, DEEP),
+/* SML3CLK */ PAD_CFG_GPI_APIC(GPP_H13, NONE, DEEP),
+/* SML3DATA */ PAD_CFG_GPI_APIC(GPP_H14, NONE, DEEP),
+/* SML3ALERTB */ PAD_CFG_GPI_APIC(GPP_H15, NONE, DEEP),
+/* SML4DATA */ PAD_CFG_GPO(GPP_H17, 1, DEEP),
+/* LED_DRIVE */ PAD_CFG_GPO(GPP_H23, 0, DEEP),
+/* DDSP_HPD_0 */ PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1),
+/* DDSP_HPD_1 */ PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1),
+/* DDSP_HPD_2 */ PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1),
+/* DDSP_HPD_1 */ PAD_CFG_GPI_ACPI_SMI(GPP_I3, NONE, DEEP, YES),
+/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1),
+/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_I6, 20K_PD, DEEP, NF1),
+/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),
+/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_I8, 20K_PD, DEEP, NF1),
+/* DDPD_CTRLCLK */ PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1),
+/* DDPD_CTRLDATA */ PAD_CFG_NF(GPP_I10, 20K_PD, DEEP, NF1),
+/* EC_PCH_ACPRESENT */ PAD_CFG_GPO(GPD1, 0, DEEP),
+/* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
+/* PM_PWRBTN_R_N */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1),
+/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
+/* USB_WAKEOUT_N */ PAD_CFG_NF(GPD7, NONE, DEEP, NF1),
+/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+/* PCH_SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
+/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
+/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
+
+};
+
+/* Early pad configuration in romstage. */
+static const struct pad_config early_gpio_table[] = {
+/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
+/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
+};
+
+
+#endif
+#endif
diff --git a/src/mainboard/ocp/tiogapass/pei_data.c b/src/mainboard/ocp/tiogapass/pei_data.c
new file mode 100644
index 0000000..ac4ce95
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/pei_data.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+#include "spd/spd.h"
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+ mainboard_fill_dq_map_data(&pei_data->dq_map);
+ mainboard_fill_dqs_map_data(&pei_data->dqs_map);
+ mainboard_fill_rcomp_res_data(&pei_data->RcompResistor);
+ mainboard_fill_rcomp_strength_data(&pei_data->RcompTarget);
+}
diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c
new file mode 100644
index 0000000..6fef017
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/ramstage.c
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootstate.h>
+#include <console/console.h>
+#include <device/i2c_simple.h>
+#include <soc/ramstage.h>
+#include "gpio.h"
+
+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
+{
+ /* Configure pads prior to SiliconInit() in case there's any
+ * dependencies during hardware initialization. */
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+// params->CdClock = 3;
+
+ /* Enable Virtual Channel 1 */
+// params->PchHdaVcType = 0x1;
+}
+
+static void ioexpander_init(void *unused)
+{
+ printk(BIOS_DEBUG, "Programming TCA6424A I/O expander\n");
+
+ /* I/O Expander 1, Port 0 Data */
+ i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_0_ADDR, IO_EXPANDER_P0DOUT,
+ 0xF7);
+ /* Port 0 Configuration */
+ i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_0_ADDR, IO_EXPANDER_P0CONF,
+ 0xE0);
+
+ /* Port 1 Data */
+ i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_0_ADDR, IO_EXPANDER_P1DOUT,
+ 0x9E);
+ /* Port 1 Configuration */
+ i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_0_ADDR, IO_EXPANDER_P1CONF,
+ 0x8C);
+
+ /* Port 2 Data */
+ i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_0_ADDR, IO_EXPANDER_P2DOUT,
+ 0xDA);
+ /* Port 2 Configuration */
+ i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_0_ADDR, IO_EXPANDER_P2CONF,
+ 0x08);
+
+ /* I/O Expander 2, Port 0 Data */
+ i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_1_ADDR, IO_EXPANDER_P0DOUT,
+ 0xFF);
+ /* Port 0 Configuration */
+ i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_1_ADDR, IO_EXPANDER_P0CONF,
+ 0x00);
+
+}
+
+BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, ioexpander_init, NULL);
diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c
new file mode 100644
index 0000000..230cc50
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/romstage.c
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/byteorder.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <fsp/api.h>
+#include <gpio.h>
+#include "gpio.h"
+#include <soc/romstage.h>
+#include <soc/gpio.h>
+#include "spd/spd.h"
+#include <string.h>
+#include <spd_bin.h>
+#include "board_id.h"
+
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ FSPM_CONFIG *mem_cfg;
+ mem_cfg = &mupd->FspmConfig;
+ u8 spd_index = (get_board_id() >> 5) & 0x7;
+
+ printk(BIOS_INFO, "SPD index %d\n", spd_index);
+/*
+ mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0);
+ mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0);
+ mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
+ mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
+*/
+ if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP3)) {
+ struct region_device spd_rdev;
+
+// mem_cfg->DqPinsInterleaved = 0;
+ if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0)
+ die("spd.bin not found\n");
+// mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev);
+ /* Memory leak is ok since we have memory mapped boot media */
+// mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev);
+ } else { /* CONFIG_BOARD_INTEL_KBLRVP7 and CONFIG_BOARD_INTEL_KBLRVP8 */
+ struct spd_block blk = {
+ .addr_map = { 0x50, 0x51, 0x52, 0x53, },
+ };
+
+// mem_cfg->DqPinsInterleaved = 1;
+ get_spd_smbus(&blk);
+// mem_cfg->MemorySpdDataLen = blk.len;
+// mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
+// mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2];
+ if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8)) {
+// mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1];
+// mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3];
+ }
+
+ }
+// mupd->FspmTestConfig.DmiVc1 = 1;
+// if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8))
+// mem_cfg->UserBd = BOARD_TYPE_DESKTOP;
+}
diff --git a/src/mainboard/ocp/tiogapass/spd/Makefile.inc b/src/mainboard/ocp/tiogapass/spd/Makefile.inc
new file mode 100644
index 0000000..721736d
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/spd/Makefile.inc
@@ -0,0 +1,17 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google Inc.
+## Copyright (C) 2015 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+romstage-y += spd_util.c
diff --git a/src/mainboard/ocp/tiogapass/spd/spd.h b/src/mainboard/ocp/tiogapass/spd/spd.h
new file mode 100644
index 0000000..a5f1af3
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/spd/spd.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_SPD_H
+#define MAINBOARD_SPD_H
+
+#define RCOMP_TARGET_PARAMS 0x5
+
+void mainboard_fill_dq_map_data(void *dq_map_ptr);
+void mainboard_fill_dqs_map_data(void *dqs_map_ptr);
+void mainboard_fill_rcomp_res_data(void *rcomp_ptr);
+void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr);
+
+#endif
diff --git a/src/mainboard/ocp/tiogapass/spd/spd_util.c b/src/mainboard/ocp/tiogapass/spd/spd_util.c
new file mode 100644
index 0000000..2c26d78
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/spd/spd_util.c
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+#include "spd.h"
+
+void mainboard_fill_dq_map_data(void *dq_map_ptr)
+{
+ /* DQ byte map */
+ const u8 dq_map[2][12] = {
+ { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
+ 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
+ { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
+ 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
+ memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
+}
+
+void mainboard_fill_dqs_map_data(void *dqs_map_ptr)
+{
+ /* DQS CPU<>DRAM map */
+ const u8 dqs_map[2][8] = {
+ { 0, 1, 3, 2, 4, 5, 6, 7 },
+ { 1, 0, 4, 5, 2, 3, 6, 7 } };
+ memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map));
+}
+
+void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
+{
+ /* Rcomp resistor */
+ const u16 RcompResistor[3] = { 121, 81, 100 };
+ memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor));
+}
+
+void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
+{
+ /* Rcomp target */
+ static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = {
+ 100, 40, 20, 20, 26 };
+ memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
+}
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 506a041..f1f03d7 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -20,6 +20,7 @@
select ARCH_RAMSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_VERSTAGE_X86_32
+ select BOOTBLOCK_CONSOLE
select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
select BOOT_DEVICE_SUPPORTS_WRITES
select CACHE_MRC_SETTINGS
@@ -28,43 +29,40 @@
select COMMON_FADT
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select C_ENVIRONMENT_BOOTBLOCK
- select FSP_M_XIP if MAINBOARD_USES_FSP2_0
- select FSP_T_XIP if FSP_CAR
select GENERIC_GPIO_LIB
select HAVE_FSP_GOP
- select INTEL_DESCRIPTOR_MODE_CAPABLE
+ select HAVE_INTEL_FIRMWARE
select HAVE_MONOTONIC_TIMER
select HAVE_SMI_HANDLER
- select INTEL_CAR_NEM_ENHANCED
select INTEL_GMA_ACPI
select IOAPIC
select MRC_SETTINGS_PROTECT
select NO_FIXED_XIP_ROM_SIZE
select PARALLEL_MP
select PARALLEL_MP_AP_WORK
+ select PCIEXP_ASPM
+ select PCIEXP_CLK_PM
+ select PCIEXP_COMMON_CLOCK
+ select PCIEXP_L1_SUB_STATE
select PCIEX_LENGTH_64MB
select REG_SCRIPT
+ select RTC
select SA_ENABLE_DPR
select SMM_TSEG
select SMP
- select PMC_GLOBAL_RESET_ENABLE_LOCK
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
- select SOC_INTEL_COMMON_BLOCK_CAR
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
select SOC_INTEL_COMMON_BLOCK_CPU
select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
- select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS
select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
select SOC_INTEL_COMMON_BLOCK_GSPI
- select SOC_INTEL_COMMON_BLOCK_HDA
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_SGX
select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
- select SOC_INTEL_COMMON_BLOCK_UART
select SOC_INTEL_COMMON_BLOCK_VMX
select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_NHLT
@@ -76,10 +74,6 @@
select TSC_SYNC_MFENCE
select UDELAY_TSC
-config CPU_INTEL_NUM_FIT_ENTRIES
- int
- default 10
-
config MAINBOARD_USES_FSP2_0
bool
default n
@@ -88,7 +82,7 @@
def_bool y
depends on MAINBOARD_USES_FSP2_0
select PLATFORM_USES_FSP2_0
- select UDK_2015_BINDING
+ select UDK_2017_BINDING
select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
select POSTCAR_CONSOLE
select POSTCAR_STAGE
@@ -98,7 +92,6 @@
depends on !MAINBOARD_USES_FSP2_0
select PLATFORM_USES_FSP1_1
select DISPLAY_FSP_ENTRY_POINTS
- select SKIP_FSP_CAR
config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC
@@ -112,6 +105,10 @@
select VBOOT_VBNV_CMOS
select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
+config BOOTBLOCK_RESETS
+ string
+ default "soc/intel/common/reset.c"
+
config CBFS_SIZE
hex
default 0x200000
@@ -124,6 +121,10 @@
hex
default 0xfef00000
+config BOOTBLOCK_CPU_INIT
+ string
+ default "soc/intel/skylake/bootblock/bootblock.c"
+
config DCACHE_RAM_SIZE
hex
default 0x40000
@@ -162,6 +163,10 @@
help
This option allows you to select MMIO Base Address of sideband bus.
+config SERIAL_CPU_INIT
+ bool
+ default n
+
config SERIRQ_CONTINUOUS_MODE
bool
default n
@@ -181,12 +186,31 @@
string
default "8086,0406"
+config UART_DEBUG
+ bool "Enable UART debug port."
+ default y
+ select CONSOLE_SERIAL
+ select DRIVERS_UART_8250MEM_32
+ select NO_UART_ON_SUPERIO
+
+config UART_FOR_CONSOLE
+ int "Index for LPSS UART port to use for console"
+ default 2 if DRIVERS_UART_8250MEM
+ default 0
+ help
+ Index for LPSS UART port to use for console:
+ 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2
+
config SKYLAKE_SOC_PCH_H
bool
default n
help
Choose this option if you have a PCH-H chipset.
+config CHIPSET_BOOTBLOCK_INCLUDE
+ string
+ default "soc/intel/skylake/bootblock/timestamp.inc"
+
config NHLT_DMIC_2CH
bool
default n
@@ -247,19 +271,37 @@
help
Include DSP firmware settings for DA7219 headset codec.
-config FSP_HEADER_PATH
- string "Location of FSP headers"
- depends on MAINBOARD_USES_FSP2_0
- # Use KabylakeFsp for both Skylake and Kabylake as it supports both.
- # SkylakeFsp is FSP 1.1 and therefore incompatible.
- default "3rdparty/fsp/KabylakeFspBinPkg/Include/" if SOC_INTEL_SKYLAKE
- default "3rdparty/fsp/KabylakeFspBinPkg/Include/" if SOC_INTEL_KABYLAKE
+choice
+ prompt "Cache-as-ram implementation"
+ default USE_SKYLAKE_CAR_NEM_ENHANCED
+ help
+ This option allows you to select how cache-as-ram (CAR) is set up.
-config FSP_FD_PATH
- string
- depends on FSP_USE_REPO
- default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" if SOC_INTEL_SKYLAKE
- default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" if SOC_INTEL_KABYLAKE
+config USE_SKYLAKE_CAR_NEM_ENHANCED
+ bool "Enhanced Non-evict mode"
+ select SOC_INTEL_COMMON_BLOCK_CAR
+ select INTEL_CAR_NEM_ENHANCED
+ help
+ A current limitation of NEM (Non-Evict mode) is that code and data
+ sizes are derived from the requirement to not write out any modified
+ cache line. With NEM, if there is no physical memory behind the
+ cached area, the modified data will be lost and NEM results will be
+ inconsistent. ENHANCED NEM guarantees that modified data is always
+ kept in cache while clean data is replaced.
+
+config USE_SKYLAKE_FSP_CAR
+ bool "Use FSP CAR"
+ select FSP_CAR
+ help
+ Use FSP APIs to initialize and tear down the Cache-As-Ram.
+
+endchoice
+
+config SKIP_FSP_CAR
+ bool "Skip cache as RAM setup in FSP"
+ default y
+ help
+ Skip Cache as RAM setup in FSP.
config SPI_FLASH_INCLUDE_ALL_DRIVERS
bool
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index ee2c928..c5451e6 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -2,7 +2,6 @@
subdirs-y += nhlt
subdirs-y += romstage
-subdirs-y += ../../../cpu/intel/common
subdirs-y += ../../../cpu/intel/microcode
subdirs-y += ../../../cpu/intel/turbo
subdirs-y += ../../../cpu/x86/lapic
@@ -11,7 +10,6 @@
subdirs-y += ../../../cpu/x86/tsc
bootblock-y += bootblock/bootblock.c
-bootblock-$(CONFIG_FSP_CAR) += fspcar.c
bootblock-y += bootblock/cpu.c
bootblock-y += i2c.c
bootblock-y += bootblock/pch.c
@@ -22,13 +20,13 @@
bootblock-y += pmutil.c
bootblock-y += spi.c
bootblock-y += lpc.c
-bootblock-y += uart.c
+bootblock-$(CONFIG_UART_DEBUG) += uart.c
verstage-y += gspi.c
verstage-y += pmutil.c
verstage-y += i2c.c
verstage-y += spi.c
-verstage-y += uart.c
+verstage-$(CONFIG_UART_DEBUG) += uart.c
romstage-y += gpio.c
romstage-y += gspi.c
@@ -40,7 +38,7 @@
romstage-y += pmutil.c
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
romstage-y += spi.c
-romstage-y += uart.c
+romstage-$(CONFIG_UART_DEBUG) += uart.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += chip.c
@@ -67,33 +65,22 @@
ramstage-y += spi.c
ramstage-y += systemagent.c
ramstage-y += thermal.c
-ramstage-y += uart.c
-ramstage-y += vr_config.c
+ramstage-$(CONFIG_UART_DEBUG) += uart.c
+//ramstage-y += vr_config.c
smm-y += elog.c
smm-y += gpio.c
smm-y += p2sb.c
smm-y += pmutil.c
smm-y += smihandler.c
-smm-y += uart.c
+smm-$(CONFIG_UART_DEBUG) += uart.c
postcar-y += memmap.c
postcar-y += gspi.c
postcar-y += spi.c
-postcar-y += i2c.c
-postcar-y += uart.c
+postcar-$(CONFIG_UART_DEBUG) += uart.c
-
-# Skylake D0
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_406ex/microcode.bin
-# Skylake H Q0
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_506ex/microcode.bin
-# Kabylake H0, Y0
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_806ex/microcode.bin
-# Kabylake HB0
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_906ex/microcode.bin
-# Missing for Skylake C0 (0x406e2), Kabylake G0 (0x406e8), Kabylake HA0 (0x506e8)
-# since those are probably pre-release samples.
+# cpu_microcode_bins += ???
CPPFLAGS_common += -I$(src)/soc/intel/skylake
CPPFLAGS_common += -I$(src)/soc/intel/skylake/include
@@ -103,6 +90,7 @@
CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/skylake
else
CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp20
+CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/skykabylake
endif
# Currently used for microcode path.
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 3ade8d7..020dea3 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -20,12 +20,16 @@
#include <fsp/api.h>
#include <arch/acpi.h>
#include <arch/io.h>
+#include <chip.h>
+#include <compiler.h>
+#include <bootstate.h>
#include <console/console.h>
#include <device/device.h>
+#include <device/pci.h>
#include <device/pci_ids.h>
+#include <fsp/api.h>
#include <fsp/util.h>
#include <intelblocks/chip.h>
-#include <intelblocks/itss.h>
#include <intelblocks/xdci.h>
#include <intelpch/lockdown.h>
#include <romstage_handoff.h>
@@ -34,7 +38,6 @@
#include <soc/interrupt.h>
#include <soc/iomap.h>
#include <soc/irq.h>
-#include <soc/itss.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include <soc/systemagent.h>
@@ -165,16 +168,8 @@
void soc_init_pre_device(void *chip_info)
{
- /* Snapshot the current GPIO IRQ polarities. FSP is setting a
- * default policy that doesn't honor boards' requirements. */
- itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
-
/* Perform silicon specific init. */
fsp_silicon_init(romstage_handoff_is_resume());
-
- /* Restore GPIO IRQ polarities back to previous settings. */
- itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
-
/* swap enabled PCI ports in device tree if needed */
pcie_override_devicetree_after_silicon_init();
}
@@ -227,8 +222,9 @@
/* UPD parameters to be initialized before SiliconInit */
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
{
- FSP_S_CONFIG *params = &supd->FspsConfig;
- FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig;
+ FSPS_CONFIG *params = &supd->FspsConfig;
+#if 0
+// FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig;
static struct soc_intel_skylake_config *config;
uintptr_t vbt_data = (uintptr_t)vbt_get();
int i;
@@ -244,14 +240,14 @@
/* Set PsysPmax if it is available from DT */
if (config->psys_pmax) {
/* PsysPmax is in unit of 1/8 Watt */
- tconfig->PsysPmax = config->psys_pmax * 8;
- printk(BIOS_DEBUG, "psys_pmax = %d\n", tconfig->PsysPmax);
+// tconfig->PsysPmax = config->psys_pmax * 8;
+// printk(BIOS_DEBUG, "psys_pmax = %d\n", tconfig->PsysPmax);
}
- params->GraphicsConfigPtr = (u32) vbt_data;
+// params->GraphicsConfigPtr = (u32) vbt_data;
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
- params->PortUsb20Enable[i] =
+/* params->PortUsb20Enable[i] =
config->usb2_ports[i].enable;
params->Usb2OverCurrentPin[i] =
config->usb2_ports[i].ocpin;
@@ -295,6 +291,7 @@
sizeof(params->PcieRpLtrEnable));
memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug,
sizeof(params->PcieRpHotPlug));
+*/
/*
* PcieRpClkSrcNumber UPD is set to clock source number(0-6) for
@@ -341,15 +338,6 @@
params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
params->ScsSdCardEnabled = config->ScsSdCardEnabled;
- if (!!params->ScsEmmcHs400Enabled && !!config->EmmcHs400DllNeed) {
- params->PchScsEmmcHs400DllDataValid =
- !!config->EmmcHs400DllNeed;
- params->PchScsEmmcHs400RxStrobeDll1 =
- config->ScsEmmcHs400RxStrobeDll1;
- params->PchScsEmmcHs400TxDataDll =
- config->ScsEmmcHs400TxDataDll;
- }
-
/* If ISH is enabled, enable ISH elements */
dev = dev_find_slot(0, PCH_DEVFN_ISH);
if (dev)
@@ -365,20 +353,18 @@
params->SataMode = config->SataMode;
params->SataSpeedLimit = config->SataSpeedLimit;
params->SataPwrOptEnable = config->SataPwrOptEnable;
- params->EnableTcoTimer = !config->PmTimerDisabled;
- tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi;
- tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock;
- tconfig->PowerLimit4 = config->PowerLimit4;
+// tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi;
+// tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock;
/*
* To disable HECI, the Psf needs to be left unlocked
* by FSP till end of post sequence. Based on the devicetree
* setting, we set the appropriate PsfUnlock policy in FSP,
* do the changes and then lock it back in coreboot during finalize.
*/
- tconfig->PchSbAccessUnlock = (config->HeciEnabled == 0) ? 1 : 0;
+// tconfig->PchSbAccessUnlock = (config->HeciEnabled == 0) ? 1 : 0;
if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) {
- tconfig->PchLockDownBiosInterface = 0;
+// tconfig->PchLockDownBiosInterface = 0;
params->PchLockDownBiosLock = 0;
params->PchLockDownSpiEiss = 0;
/*
@@ -390,17 +376,8 @@
*/
params->SpiFlashCfgLockDown = 0;
}
- /* only replacing preexisting subsys ID defaults when non-zero */
- if (CONFIG_SUBSYSTEM_VENDOR_ID != 0) {
- params->DefaultSvid = CONFIG_SUBSYSTEM_VENDOR_ID;
- params->PchSubSystemVendorId = CONFIG_SUBSYSTEM_VENDOR_ID;
- }
-
- if (CONFIG_SUBSYSTEM_DEVICE_ID != 0) {
- params->DefaultSid = CONFIG_SUBSYSTEM_DEVICE_ID;
- params->PchSubSystemId = CONFIG_SUBSYSTEM_DEVICE_ID;
- }
-
+ params->PchSubSystemVendorId = config->PchConfigSubSystemVendorId;
+ params->PchSubSystemId = config->PchConfigSubSystemId;
params->PchPmWolEnableOverride = config->WakeConfigWolEnableOverride;
params->PchPmPcieWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx;
params->PchPmDeepSxPol = config->PmConfigDeepSxPol;
@@ -467,13 +444,13 @@
params->FastPkgCRampDisableSa = config->FastPkgCRampDisableSa;
/* Enable PMC XRAM read */
- tconfig->PchPmPmcReadDisable = config->PchPmPmcReadDisable;
+// tconfig->PchPmPmcReadDisable = config->PchPmPmcReadDisable;
/* Enable/Disable EIST */
- tconfig->Eist = config->eist_enable;
+// tconfig->Eist = config->eist_enable;
/* Set TccActivationOffset */
- tconfig->TccActivationOffset = config->tcc_offset;
+// tconfig->TccActivationOffset = config->tcc_offset;
/* Enable VT-d and X2APIC */
if (!config->ignore_vtd && soc_is_vtd_capable()) {
@@ -487,12 +464,13 @@
params->PchIoApicDeviceNumber = 31;
params->PchIoApicFunctionNumber = 0;
}
+#endif
soc_irq_settings(params);
}
/* Mainboard GPIO Configuration */
-__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+__weak void mainboard_silicon_init_params(FSPS_CONFIG *params)
{
printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
}
diff --git a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h
index e75b350..820e517 100644
--- a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h
+++ b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h
@@ -22,10 +22,10 @@
#include <fsp/api.h>
#include <fsp/util.h>
-#define FSP_SIL_UPD FSP_S_CONFIG
-#define FSP_MEM_UPD FSP_M_CONFIG
+#define FSP_SIL_UPD FSPS_CONFIG
+#define FSP_MEM_UPD FSPM_CONFIG
-void mainboard_silicon_init_params(FSP_S_CONFIG *params);
+void mainboard_silicon_init_params(FSPS_CONFIG *params);
void soc_fsp_load(void);
void soc_init_pre_device(void *chip_info);
void soc_irq_settings(FSP_SIL_UPD *params);
diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c
index 7b3e1bd..d26bd84 100644
--- a/src/soc/intel/skylake/irq.c
+++ b/src/soc/intel/skylake/irq.c
@@ -22,6 +22,7 @@
#include <soc/irq.h>
#include <string.h>
+#if 0
static const SI_PCH_DEVICE_INTERRUPT_CONFIG devintconfig[] = {
/*
* cAVS(Audio, Voice, Speech), INTA is default, programmed in
@@ -216,23 +217,26 @@
DEVICE_INT_CONFIG(PCH_DEV_SLOT_ISH,
PCI_FUNC(PCH_DEVFN_ISH), int_A, ISH_IRQ)
};
+#endif
void soc_irq_settings(FSP_SIL_UPD *params)
{
- uint32_t i, intdeventry;
+ uint32_t i;
+// uint32_t i, intdeventry;
u8 irq_config[PCH_MAX_IRQ_CONFIG];
- const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
- const struct soc_intel_skylake_config *config = dev->chip_info;
+// const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+// const struct soc_intel_skylake_config *config = dev->chip_info;
/* Get Device Int Count */
- intdeventry = ARRAY_SIZE(devintconfig);
+// intdeventry = ARRAY_SIZE(devintconfig);
/* update irq table */
- memcpy((SI_PCH_DEVICE_INTERRUPT_CONFIG *)
+/* memcpy((SI_PCH_DEVICE_INTERRUPT_CONFIG *)
(params->DevIntConfigPtr), devintconfig, intdeventry *
sizeof(SI_PCH_DEVICE_INTERRUPT_CONFIG));
params->NumOfDevIntConfig = intdeventry;
+*/
/* PxRC to IRQ programming */
for (i = 0; i < PCH_MAX_IRQ_CONFIG; i++) {
switch (i) {
@@ -250,13 +254,15 @@
break;
}
}
- memcpy(params->PxRcConfig, irq_config, PCH_MAX_IRQ_CONFIG);
+// memcpy(params->PxRcConfig, irq_config, PCH_MAX_IRQ_CONFIG);
/* GPIO IRQ Route The valid values is 14 or 15 */
- if (config->GpioIrqSelect == 0)
+/* if (config->GpioIrqSelect == 0)
params->GpioIrqRoute = GPIO_IRQ14;
else
params->GpioIrqRoute = config->GpioIrqSelect;
+*/
/* SCI IRQ Select The valid values is 9, 10, 11 and 20 21, 22, 23 */
+#if 0
if (config->SciIrqSelect == 0)
params->SciIrqSelect = SCI_IRQ9;
else
@@ -268,6 +274,7 @@
params->TcoIrqSelect = config->TcoIrqSelect;
/* TCO Irq enable/disable */
params->TcoIrqEnable = config->TcoIrqEnable;
+#endif
}
/*
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index 2a60158..48f3429 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -18,6 +18,7 @@
#include <arch/io.h>
#include <arch/symbols.h>
#include <assert.h>
+#include <compiler.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
#include <cbmem.h>
@@ -37,6 +38,7 @@
#include <string.h>
#include <timestamp.h>
#include <security/vboot/vboot_common.h>
+#include <MemInfoHob.h>
#define FSP_SMBIOS_MEMORY_INFO_GUID \
{ \
@@ -101,18 +103,18 @@
if (src_dimm->Status != DIMM_PRESENT)
continue;
- switch (memory_info_hob->MemoryType) {
+ switch(memory_info_hob->MemoryType) {
case MRC_DDR_TYPE_DDR4:
- ddr_type = MEMORY_TYPE_DDR4;
+ ddr_type = MEMORY_DEVICE_DDR4;
break;
case MRC_DDR_TYPE_DDR3:
- ddr_type = MEMORY_TYPE_DDR3;
+ ddr_type = MEMORY_DEVICE_DDR3;
break;
case MRC_DDR_TYPE_LPDDR3:
- ddr_type = MEMORY_TYPE_LPDDR3;
+ ddr_type = MEMORY_DEVICE_LPDDR3;
break;
default:
- ddr_type = MEMORY_TYPE_UNKNOWN;
+ ddr_type = MEMORY_DEVICE_UNKNOWN;
break;
}
@@ -190,19 +192,19 @@
run_postcar_phase(&pcf);
}
-static void cpu_flex_override(FSP_M_CONFIG *m_cfg)
+static void cpu_flex_override(FSPM_CONFIG *m_cfg)
{
msr_t flex_ratio;
- m_cfg->CpuRatioOverride = 1;
+// m_cfg->CpuRatioOverride = 1;
/*
* Set cpuratio to that value set in bootblock, This will ensure FSPM
* knows the intended flex ratio.
*/
flex_ratio = rdmsr(MSR_FLEX_RATIO);
- m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff;
+// m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff;
}
-static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
+static void soc_memory_init_params(FSPM_CONFIG *m_cfg,
const struct soc_intel_skylake_config *config)
{
int i;
@@ -215,31 +217,30 @@
* With the default stolen size of 32MB(-8MB) there is not enough space
* for FBC to work with a high resolution panel.
*/
- m_cfg->IgdDvmt50PreAlloc = 2;
- m_cfg->MmioSize = 0x800; /* 2GB in MB */
- m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
- m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
- m_cfg->ProbelessTrace = config->ProbelessTrace;
- m_cfg->SaGv = config->SaGv;
- m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
- m_cfg->RMT = config->Rmt;
- m_cfg->CmdTriStateDis = config->CmdTriStateDis;
- m_cfg->DdrFreqLimit = config->DdrFreqLimit;
- m_cfg->VmxEnable = config->VmxEnable;
- m_cfg->PrmrrSize = config->PrmrrSize;
+// m_cfg->IgdDvmt50PreAlloc = 2;
+// m_cfg->MmioSize = 0x800; /* 2GB in MB */
+// m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
+// m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
+// m_cfg->ProbelessTrace = config->ProbelessTrace;
+// m_cfg->SaGv = config->SaGv;
+// m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
+// m_cfg->RMT = config->Rmt;
+// m_cfg->DdrFreqLimit = config->DdrFreqLimit;
+// m_cfg->VmxEnable = config->VmxEnable;
+// m_cfg->PrmrrSize = config->PrmrrSize;
for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
if (config->PcieRpEnable[i])
mask |= (1<<i);
}
- m_cfg->PcieRpEnableMask = mask;
+// m_cfg->PcieRpEnableMask = mask;
cpu_flex_override(m_cfg);
if (!config->ignore_vtd) {
- m_cfg->PchHpetBdfValid = 1;
- m_cfg->PchHpetBusNumber = 250;
- m_cfg->PchHpetDeviceNumber = 15;
- m_cfg->PchHpetFunctionNumber = 0;
+// m_cfg->PchHpetBdfValid = 1;
+// m_cfg->PchHpetBusNumber = 250;
+// m_cfg->PchHpetDeviceNumber = 15;
+// m_cfg->PchHpetFunctionNumber = 0;
}
}
@@ -247,8 +248,8 @@
{
const struct device *dev;
const struct soc_intel_skylake_config *config;
- FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
- FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig;
+ FSPM_CONFIG *m_cfg = &mupd->FspmConfig;
+// FSPM_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig;
dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
config = dev->chip_info;
@@ -256,43 +257,43 @@
soc_memory_init_params(m_cfg, config);
/* Skip creating Management Engine MBP HOB */
- m_t_cfg->SkipMbpHob = 0x01;
+// m_t_cfg->SkipMbpHob = 0x01;
/* Enable DMI Virtual Channel for ME */
- m_t_cfg->DmiVcm = 0x01;
+// m_t_cfg->DmiVcm = 0x01;
/* Enable Sending DID to ME */
- m_t_cfg->SendDidMsg = 0x01;
- m_t_cfg->DidInitStat = 0x01;
+// m_t_cfg->SendDidMsg = 0x01;
+// m_t_cfg->DidInitStat = 0x01;
/* DCI and TraceHub configs */
- m_t_cfg->PchDciEn = config->PchDciEn;
- m_cfg->EnableTraceHub = config->EnableTraceHub;
- m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size;
- m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size;
+// m_t_cfg->PchDciEn = config->PchDciEn;
+// m_cfg->EnableTraceHub = config->EnableTraceHub;
+// m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size;
+// m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size;
/* Enable SMBus controller based on config */
- m_cfg->SmbusEnable = config->SmbusEnable;
+// m_cfg->SmbusEnable = config->SmbusEnable;
mainboard_memory_init_params(mupd);
}
-void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg,
+void soc_update_memory_params_for_mma(FSPM_CONFIG *memory_cfg,
struct mma_config_param *mma_cfg)
{
/* Boot media is memory mapped for Skylake and Kabylake (SPI). */
assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED));
- memory_cfg->MmaTestContentPtr =
- (uintptr_t) rdev_mmap_full(&mma_cfg->test_content);
- memory_cfg->MmaTestContentSize =
- region_device_sz(&mma_cfg->test_content);
- memory_cfg->MmaTestConfigPtr =
- (uintptr_t) rdev_mmap_full(&mma_cfg->test_param);
- memory_cfg->MmaTestConfigSize =
- region_device_sz(&mma_cfg->test_param);
- memory_cfg->MrcFastBoot = 0x00;
- memory_cfg->SaGv = 0x02;
+// memory_cfg->MmaTestContentPtr =
+// (uintptr_t) rdev_mmap_full(&mma_cfg->test_content);
+// memory_cfg->MmaTestContentSize =
+// region_device_sz(&mma_cfg->test_content);
+// memory_cfg->MmaTestConfigPtr =
+// (uintptr_t) rdev_mmap_full(&mma_cfg->test_param);
+// memory_cfg->MmaTestConfigSize =
+// region_device_sz(&mma_cfg->test_param);
+// memory_cfg->MrcFastBoot = 0x00;
+// memory_cfg->SaGv = 0x02;
}
__weak void mainboard_memory_init_params(FSPM_UPD *mupd)
diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c
index 4508fda..9266330 100644
--- a/src/soc/intel/skylake/vr_config.c
+++ b/src/soc/intel/skylake/vr_config.c
@@ -56,7 +56,7 @@
* | IccMax(AML-Y) | 4.1A | 28A | 24A | 24A |
* +----------------+-------------+---------------+------+-----+
*/
-
+#if 0
static const struct {
uint16_t icc_max[NUM_VR_DOMAINS];
}sku_icc_max_mapping[] = {
@@ -167,12 +167,13 @@
.voltage_limit = 1520,
},
};
+#endif
static uint16_t get_dev_id(struct device *dev)
{
return pci_read_config16(dev, PCI_DEVICE_ID);
}
-
+#if 0
static int get_kbl_sku(void)
{
static int sku = -1;
@@ -201,7 +202,6 @@
sku = -2;
return sku;
}
-
static uint16_t get_sku_icc_max(int domain, uint16_t board_icc_max)
{
/* If board provided non-zero value, use it. */
@@ -229,7 +229,7 @@
cfg = chip_cfg;
else
cfg = &default_configs[domain];
-
+/*
vr_params->VrConfigEnable[domain] = cfg->vr_config_enable;
vr_params->Psi1Threshold[domain] = cfg->psi1threshold;
vr_params->Psi2Threshold[domain] = cfg->psi2threshold;
@@ -240,9 +240,10 @@
vr_params->ImonOffset[domain] = cfg->imon_offset;
vr_params->IccMax[domain] = get_sku_icc_max(domain, cfg->icc_max);
vr_params->VrVoltageLimit[domain] = cfg->voltage_limit;
-
+*/
#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP2_0)
- vr_params->AcLoadline[domain] = cfg->ac_loadline;
- vr_params->DcLoadline[domain] = cfg->dc_loadline;
+// vr_params->AcLoadline[domain] = cfg->ac_loadline;
+// vr_params->DcLoadline[domain] = cfg->dc_loadline;
#endif
}
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DebugSupport.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DebugSupport.h
index 6983469..af0950f 100644
--- a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DebugSupport.h
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DebugSupport.h
@@ -605,7 +605,7 @@
UINT64 ELR; // Exception Link Register
UINT64 SPSR; // Saved Processor Status Register
UINT64 FPSR; // Floating Point Status Register
- UINT64 ESR; // Exception syndrome register
+// UINT64 ESR; // Exception syndrome register
UINT64 FAR; // Fault Address Register
} EFI_SYSTEM_CONTEXT_AARCH64;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FirmwareVersionInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FirmwareVersionInfoHob.h
new file mode 100644
index 0000000..fca01e9
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FirmwareVersionInfoHob.h
@@ -0,0 +1,67 @@
+/** @file
+ Header file for Firmware Version Information
+
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License which accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _FIRMWARE_VERSION_INFO_HOB_H_
+#define _FIRMWARE_VERSION_INFO_HOB_H_
+
+#include <Uefi/UefiMultiPhase.h>
+#include <Pi/PiBootMode.h>
+#include <Pi/PiHob.h>
+
+#pragma pack(1)
+///
+/// Firmware Version Structure
+///
+typedef struct {
+ UINT8 MajorVersion;
+ UINT8 MinorVersion;
+ UINT8 Revision;
+ UINT16 BuildNumber;
+} FIRMWARE_VERSION;
+
+///
+/// Firmware Version Information Structure
+///
+typedef struct {
+ UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name
+ UINT8 VersionStringIndex; ///< Offset 1 Index of Version String
+ FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version
+} FIRMWARE_VERSION_INFO;
+
+#ifndef __SMBIOS_STANDARD_H__
+///
+/// The Smbios structure header.
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Handle;
+} SMBIOS_STRUCTURE;
+#endif
+
+///
+/// Firmware Version Information HOB Structure
+///
+typedef struct {
+ EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB
+ SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB
+ UINT8 Count; ///< Offset 28 Number of FVI elements included.
+///
+/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
+///
+} FIRMWARE_VERSION_INFO_HOB;
+#pragma pack()
+
+#endif // _FIRMWARE_VERSION_INFO_HOB_H_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h
new file mode 100644
index 0000000..cf543fe
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h
@@ -0,0 +1,48 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPUPD_H__
+#define __FSPUPD_H__
+
+#include <FspEas.h>
+
+#pragma pack(1)
+
+#define FSPT_UPD_SIGNATURE 0x545F445055434F53 /* 'SOCUPD_T' */
+
+#define FSPM_UPD_SIGNATURE 0x4D5F445055434F53 /* 'SOCUPD_M' */
+
+#define FSPS_UPD_SIGNATURE 0x535F445055434F53 /* 'SOCUPD_S' */
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h
new file mode 100644
index 0000000..a66b3306
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h
@@ -0,0 +1,248 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPMUPD_H__
+#define __FSPMUPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+
+/** FSP-M Configuration
+**/
+typedef struct {
+
+/** Offset 0x0040 - Tseg Size
+ Size of SMRAM memory reserved.
+ 2:2 MB, 4:4 MB, 8:8 MB, 16:16 MB
+**/
+ UINT8 PcdSmmTsegSize;
+
+/** Offset 0x0041 - FSP Debug Print Level
+ Select the FSP debug message print level.
+ 0:NO DEBUG, 1:MIN DEBUG, 2:MED DEBUG, 3:VERBOSE DEBUG
+**/
+ UINT8 PcdFspDebugPrintErrorLevel;
+
+/** Offset 0x0042 - Channel 0 DIMM 0 SPD SMBus Address
+ SPD SMBus Address of each DIMM slot.
+**/
+ UINT8 PcdSpdSmbusAddress_0_0;
+
+/** Offset 0x0043 - Channel 0 DIMM 1 SPD SMBus Address
+ SPD SMBus Address of each DIMM slot.
+**/
+ UINT8 PcdSpdSmbusAddress_0_1;
+
+/** Offset 0x0044 - Channel 1 DIMM 0 SPD SMBus Address
+ SPD SMBus Address of each DIMM slot.
+**/
+ UINT8 PcdSpdSmbusAddress_1_0;
+
+/** Offset 0x0045 - Channel 1 DIMM 1 SPD SMBus Address
+ SPD SMBus Address of each DIMM slot.
+**/
+ UINT8 PcdSpdSmbusAddress_1_1;
+
+/** Offset 0x0046 - Enable Rank Margin Tool
+ Enable/disable Rank Margin Tool.
+ $EN_DIS
+**/
+ UINT8 PcdMrcRmtSupport;
+
+/** Offset 0x0047 - RMT CPGC exp_loop_cnt
+ Set the CPGC exp_loop_cnt field for RMT execution 2^(exp_loop_cnt -1).
+ 1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15
+**/
+ UINT8 PcdMrcRmtCpgcExpLoopCntValue;
+
+/** Offset 0x0048 - RMT CPGC num_bursts
+ Set the CPGC num_bursts field for RMT execution 2^(num_bursts -1).
+ 1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15
+**/
+ UINT8 PcdMrcRmtCpgcNumBursts;
+
+/** Offset 0x0049 - Preserve Memory Across Reset
+ Enable/disable memory preservation across reset.
+ $EN_DIS
+**/
+ UINT8 PcdMemoryPreservation;
+
+/** Offset 0x004A - Fast Boot
+ Enable/disable Fast Boot function. Once enabled, all following boots will use the
+ presaved MRC data to improve the boot performance.
+ $EN_DIS
+**/
+ UINT8 PcdFastBoot;
+
+/** Offset 0x004B - ECC Support
+ Enable/disable ECC Support.
+ $EN_DIS
+**/
+ UINT8 PcdEccSupport;
+
+/** Offset 0x004C - HSUART Device
+ Select the PCI High Speed UART Device for Serial Port.
+ 0:HSUART0, 1:HSUART1, 2:HSUART2
+**/
+ UINT8 PcdHsuartDevice;
+
+/** Offset 0x004D - Memory Down
+ Enable/disable Memory Down function.
+ $EN_DIS
+**/
+ UINT8 PcdMemoryDown;
+
+/** Offset 0x004E
+**/
+ UINT32 PcdMemoryDownConfigPtr;
+
+/** Offset 0x0052 - SATA Controller 0
+ Enable/disable SATA Controller 0.
+ $EN_DIS
+**/
+ UINT8 PcdEnableSATA0;
+
+/** Offset 0x0053 - SATA Controller 1
+ Enable/disable SATA Controller 1.
+ $EN_DIS
+**/
+ UINT8 PcdEnableSATA1;
+
+/** Offset 0x0054 - Intel Quick Assist Technology
+ Enable/disable Intel Quick Assist Technology.
+ $EN_DIS
+**/
+ UINT8 PcdEnableIQAT;
+
+/** Offset 0x0055 - SPD Write Disable
+ Select SMBus SPD Write Enable State (Default: 0 = [FORCE_ENABLE], 1 = [FORCE_DISABLE])
+ 0:Force Enable, 1:Force Disable
+**/
+ UINT8 PcdSmbusSpdWriteDisable;
+
+/** Offset 0x0056 - ME_SHUTDOWN Message
+ Enable/Disable sending ME_SHUTDOWN message to ME, refer to FSP Integration Guide
+ for details.
+ $EN_DIS
+**/
+ UINT8 PcdEnableMeShutdown;
+
+/** Offset 0x0057 - XHCI Controller
+ Enable / Disable XHCI controller
+ $EN_DIS
+**/
+ UINT8 PcdEnableXhci;
+
+/** Offset 0x0058 - Memory Frequency
+ Set DDR Memory Frequency, refer to FSP Integration Guide for details..
+ 15:Auto, 3:1600, 4:1866, 5:2133, 6:2400
+**/
+ UINT8 PcdDdrFreq;
+
+/** Offset 0x0059 - MMIO Size
+ Set memory mapped IO space size
+ 0:2048M, 1:1024M, 2:3072M
+**/
+ UINT8 PcdMmioSize;
+
+/** Offset 0x005A
+**/
+ UINT8 UnusedUpdSpace0[6];
+
+/** Offset 0x0060 - Customer Revision
+ The Customer can set this revision string for their own purpose.
+**/
+ UINT8 PcdCustomerRevision[32];
+
+/** Offset 0x0080 - 32-Bit bus mode
+ Enable/Disable 32-Bit bus memory mode.
+ $EN_DIS
+**/
+ UINT8 PcdHalfWidthEnable;
+
+/** Offset 0x0081 - TCL Performance
+ Enable/Disable Tcl timing for performance.
+ $EN_DIS
+**/
+ UINT8 PcdTclIdle;
+
+/** Offset 0x0082 - Interleave Mode
+ Select Interleave Mode
+ 0:DISABLED, 1:MODE0, 2:MODE1, 3:MODE2
+**/
+ UINT8 PcdInterleaveMode;
+
+/** Offset 0x0083 - Memory Thermal Throttling
+ Enable/disable Memory Thermal Throttling management mode
+ $EN_DIS
+**/
+ UINT8 PcdMemoryThermalThrottling;
+
+/** Offset 0x0084
+**/
+ UINT8 UnusedUpdSpace1[348];
+
+/** Offset 0x01E0
+**/
+ UINT8 ReservedMemoryInitUpd[16];
+} FSPM_CONFIG;
+
+/** Fsp M UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+ FSP_UPD_HEADER FspUpdHeader;
+
+/** Offset 0x0020
+**/
+ FSPM_ARCH_UPD FspmArchUpd;
+
+/** Offset 0x0040
+**/
+ FSPM_CONFIG FspmConfig;
+
+/** Offset 0x01F0
+**/
+ UINT8 UnusedUpdSpace2[14];
+
+/** Offset 0x01FE
+**/
+ UINT16 UpdTerminator;
+} FSPM_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h
new file mode 100644
index 0000000..5d0b793
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h
@@ -0,0 +1,192 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPSUPD_H__
+#define __FSPSUPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+
+/** FSP-S Configuration
+**/
+typedef struct {
+
+/** Offset 0x0020 - PCIe Controller 0 Bifurcation
+ Configure PCI Express controller 0 bifurcation.
+ 0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8
+**/
+ UINT8 PcdBifurcationPcie0;
+
+/** Offset 0x0021 - PCIe Controller 1 Bifurcation
+ Configure PCI Express controller 1 bifurcation.
+ 0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8
+**/
+ UINT8 PcdBifurcationPcie1;
+
+/** Offset 0x0022 - Active Core Count
+ Select # of Active Cores (Default: 0, 0:ALL, 1..15 = 1..15 Cores)
+ 0:ALL, 1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13,
+ 14:14, 15:15
+**/
+ UINT8 PcdActiveCoreCount;
+
+/** Offset 0x0023
+**/
+ UINT32 PcdCpuMicrocodePatchBase;
+
+/** Offset 0x0027
+**/
+ UINT32 PcdCpuMicrocodePatchSize;
+
+/** Offset 0x002B - PCIe Controller 0
+ Enable / Disable PCI Express controller 0
+ $EN_DIS
+**/
+ UINT8 PcdEnablePcie0;
+
+/** Offset 0x002C - PCIe Controller 1
+ Enable / Disable PCI Express controller 1
+ $EN_DIS
+**/
+ UINT8 PcdEnablePcie1;
+
+/** Offset 0x002D - Embedded Multi-Media Controller (eMMC)
+ Enable / Disable Embedded Multi-Media controller
+ $EN_DIS
+**/
+ UINT8 PcdEnableEmmc;
+
+/** Offset 0x002E - LAN Controllers
+ Enable / Disable LAN controllers, refer to FSP Integration Guide for details.
+ 0:Disable LAN 0 & LAN 1, 1:Enable LAN 0 & LAN 1, 2:Disable LAN 1 only
+**/
+ UINT8 PcdEnableGbE;
+
+/** Offset 0x002F
+**/
+ UINT32 PcdFiaMuxConfigRequestPtr;
+
+/** Offset 0x0033
+**/
+ UINT8 UnusedUpdSpace0[4];
+
+/** Offset 0x0037 - PCIe Root Port 0 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 PcdPcieRootPort0DeEmphasis;
+
+/** Offset 0x0038 - PCIe Root Port 1 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 PcdPcieRootPort1DeEmphasis;
+
+/** Offset 0x0039 - PCIe Root Port 2 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 PcdPcieRootPort2DeEmphasis;
+
+/** Offset 0x003A - PCIe Root Port 3 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 PcdPcieRootPort3DeEmphasis;
+
+/** Offset 0x003B - PCIe Root Port 4 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 PcdPcieRootPort4DeEmphasis;
+
+/** Offset 0x003C - PCIe Root Port 5 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 PcdPcieRootPort5DeEmphasis;
+
+/** Offset 0x003D - PCIe Root Port 6 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 PcdPcieRootPort6DeEmphasis;
+
+/** Offset 0x003E - PCIe Root Port 7 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 PcdPcieRootPort7DeEmphasis;
+
+/** Offset 0x003F
+**/
+ UINT8 UnusedUpdSpace1;
+
+/** Offset 0x0040
+**/
+ UINT32 PcdEMMCDLLConfigPtr;
+
+/** Offset 0x0044
+**/
+ UINT8 UnusedUpdSpace2[156];
+
+/** Offset 0x00E0
+**/
+ UINT8 ReservedSiliconInitUpd[16];
+} FSPS_CONFIG;
+
+/** Fsp S UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+ FSP_UPD_HEADER FspUpdHeader;
+
+/** Offset 0x0020
+**/
+ FSPS_CONFIG FspsConfig;
+
+/** Offset 0x00F0
+**/
+ UINT8 UnusedUpdSpace3[14];
+
+/** Offset 0x00FE
+**/
+ UINT16 UpdTerminator;
+} FSPS_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FsptUpd.h
new file mode 100644
index 0000000..340f144
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FsptUpd.h
@@ -0,0 +1,109 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPTUPD_H__
+#define __FSPTUPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+
+/** FSP-T Core UPD
+**/
+typedef struct {
+
+/** Offset 0x0020
+**/
+ UINT32 MicrocodeRegionBase;
+
+/** Offset 0x0024
+**/
+ UINT32 MicrocodeRegionLength;
+
+/** Offset 0x0028
+**/
+ UINT32 CodeRegionBase;
+
+/** Offset 0x002C
+**/
+ UINT32 CodeRegionLength;
+
+/** Offset 0x0030
+**/
+ UINT8 Reserved1[16];
+} FSPT_CORE_UPD;
+
+/** FSP-T Configuration
+**/
+typedef struct {
+
+/** Offset 0x0040 - Disable Port80 output in FSP-T
+ Select Port80 Control in FSP-T (0:VPD-Style, 1:Enable Port80 Output, 2:Disable Port80
+ Output, refer to FSP Integration Guide for details
+ 0:VPD-Style, 1:Enable Port80 Output[Default], 2:Disable Port80 Output
+**/
+ UINT8 PcdFsptPort80RouteDisable;
+
+/** Offset 0x0041
+**/
+ UINT8 ReservedTempRamInitUpd[31];
+} FSPT_CONFIG;
+
+/** Fsp T UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+ FSP_UPD_HEADER FspUpdHeader;
+
+/** Offset 0x0020
+**/
+ FSPT_CORE_UPD FsptCoreUpd;
+
+/** Offset 0x0040
+**/
+ FSPT_CONFIG FsptConfig;
+
+/** Offset 0x0060
+**/
+ UINT8 UnusedUpdSpace0[30];
+
+/** Offset 0x007E
+**/
+ UINT16 UpdTerminator;
+} FSPT_UPD;
+
+#pragma pack()
+
+#endif
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I033a52bc3f0b86f0ec1db8325b7435d20d194fda
Gerrit-Change-Number: 31205
Gerrit-PatchSet: 1
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3
2
Change in ...coreboot[master]: drivers/smmstore: Fix some issues
by Arthur Heymans (Code Review) 29 Nov '19
by Arthur Heymans (Code Review) 29 Nov '19
29 Nov '19
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30432
Change subject: drivers/smmstore: Fix some issues
......................................................................
drivers/smmstore: Fix some issues
This fixes the following:
- Make the API ARCH independent (no dependency on size_t)
- clean up the code a little
Change-Id: I629be25d2a9b65796ae8f7a700b6bdab57b91b22
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/drivers/smmstore/store.c
M src/include/smmstore.h
M src/soc/intel/common/block/smm/smihandler.c
3 files changed, 86 insertions(+), 67 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/30432/1
diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c
index 409949a..0a62b3c 100644
--- a/src/drivers/smmstore/store.c
+++ b/src/drivers/smmstore/store.c
@@ -62,8 +62,8 @@
if (cbfs_locate_file_in_region(&file,
CONFIG_SMMSTORE_REGION,
CONFIG_SMMSTORE_FILENAME, NULL) < 0) {
- printk(BIOS_WARNING, "smm store: "
- "Unable to find SMM store file in region '%s'\n",
+ printk(BIOS_WARNING,
+ "smm store: Unable to find SMM store file in region '%s'\n",
CONFIG_SMMSTORE_REGION);
return -1;
}
@@ -87,14 +87,13 @@
* returns 0 on success, -1 on failure
* writes up to `*bufsize` bytes into `buf` and updates `*bufsize`
*/
-int smmstore_read_region(void *buf, ssize_t *bufsize)
+int smmstore_read_region(void *buf, uint32_t *bufsize)
{
struct region_device store;
if (bufsize == NULL)
return -1;
- *bufsize = 0;
if (lookup_store(&store) < 0) {
printk(BIOS_WARNING, "reading region failed\n");
return -1;
@@ -109,6 +108,66 @@
return 0;
}
+static enum cb_err scan_end(ssize_t *end)
+{
+ struct region_device store;
+
+ if (lookup_store(&store) < 0) {
+ printk(BIOS_WARNING, "reading region failed\n");
+ return CB_ERR;
+ }
+ ssize_t data_sz = region_device_sz(&store);
+
+ /* scan for end */
+ *end = 0;
+ uint32_t k_sz, v_sz;
+ while (*end < data_sz) {
+ /* make odd corner cases identifiable, eg. invalid v_sz */
+ k_sz = 0;
+
+ if (rdev_readat(&store, &k_sz, *end, sizeof(k_sz)) < 0) {
+ printk(BIOS_WARNING, "failed reading key size\n");
+ return CB_ERR;
+ }
+
+ /* found the end */
+ if (k_sz == 0xffffffff)
+ break;
+
+ /* something is fishy here:
+ * Avoid wrapping (since data_size < MAX_UINT32_T / 2) while
+ * other problems are covered by the loop condition
+ */
+ if (k_sz > data_sz) {
+ printk(BIOS_WARNING, "key size out of bounds\n");
+ return CB_ERR;
+ }
+
+ if (rdev_readat(&store, &v_sz, *end + 4, sizeof(v_sz)) < 0) {
+ printk(BIOS_WARNING, "failed reading value size\n");
+ return CB_ERR;
+ }
+
+ if (v_sz > data_sz) {
+ printk(BIOS_WARNING, "value size out of bounds\n");
+ return CB_ERR;
+ }
+
+ *end += sizeof(k_sz) + sizeof(v_sz) + k_sz + v_sz + 1;
+ *end = ALIGN_UP(*end, sizeof(uint32_t));
+ }
+
+ printk(BIOS_WARNING, "used smm store size might be 0x%zx bytes\n", *end);
+
+ if (k_sz != 0xffffffff) {
+ printk(BIOS_WARNING,
+ "eof of data marker looks invalid: 0x%x\n", k_sz);
+ return CB_ERR;
+ }
+
+ return CB_SUCCESS;
+
+}
/*
* Append data to region
*
@@ -124,78 +183,38 @@
return -1;
}
- ssize_t data_sz = region_device_sz(&store);
-
- /* scan for end */
- ssize_t end = 0;
- uint32_t k_sz, v_sz;
- while (end < data_sz) {
- /* make odd corner cases identifiable, eg. invalid v_sz */
- k_sz = 0;
-
- if (rdev_readat(&store, &k_sz, end, sizeof(k_sz)) < 0) {
- printk(BIOS_WARNING, "failed reading key size\n");
- return -1;
- }
-
- /* found the end */
- if (k_sz == 0xffffffff)
- break;
-
- /* something is fishy here:
- * Avoid wrapping (since data_size < MAX_UINT32_T / 2) while
- * other problems are covered by the loop condition
- */
- if (k_sz > data_sz) {
- printk(BIOS_WARNING, "key size out of bounds\n");
- return -1;
- }
-
- if (rdev_readat(&store, &v_sz, end + 4, sizeof(v_sz)) < 0) {
- printk(BIOS_WARNING, "failed reading value size\n");
- return -1;
- }
-
- if (v_sz > data_sz) {
- printk(BIOS_WARNING, "value size out of bounds\n");
- return -1;
- }
-
- end += 8 + k_sz + v_sz + 1;
- end = ALIGN_UP(end, sizeof(uint32_t));
- }
-
- printk(BIOS_WARNING, "used smm store size might be 0x%zx bytes\n", end);
-
- if (k_sz != 0xffffffff) {
- printk(BIOS_WARNING,
- "eof of data marker looks invalid: 0x%x\n", k_sz);
+ ssize_t end;
+ if (scan_end(&end) == CB_ERR)
return -1;
- }
printk(BIOS_WARNING, "used size looks legit\n");
printk(BIOS_WARNING, "open (%zx, %zx) for writing\n",
region_device_offset(&store), region_device_sz(&store));
- if (boot_device_rw_subregion(&store.region, &store) < 0) {
+ if (boot_device_rw_subregion(region_device_region(&store), &store) < 0) {
printk(BIOS_WARNING, "couldn't open store for writing\n");
return -1;
}
- uint32_t record_sz = 8 + key_sz + value_sz + 1;
- if (end + record_sz >= data_sz) {
+ struct region subregion =
+ {
+ .offset = end,
+ .size = sizeof(key_sz) + sizeof(value_sz) + key_sz + value_sz + 1,
+ };
+
+ if (region_is_subregion(region_device_region(&store), &subregion)) {
printk(BIOS_WARNING, "not enough space for new data\n");
return -1;
}
- if (rdev_writeat(&store, &key_sz, end, 4) != 4) {
+ if (rdev_writeat(&store, &key_sz, end, sizeof(key_sz) != sizeof(key_sz))) {
printk(BIOS_WARNING, "failed writing key size\n");
}
- end += 4;
- if (rdev_writeat(&store, &value_sz, end, 4) != 4) {
+ end += sizeof(key_sz);
+ if (rdev_writeat(&store, &value_sz, end, sizeof(value_sz) != sizeof(key_sz))) {
printk(BIOS_WARNING, "failed writing value size\n");
}
- end += 4;
+ end += sizeof(value_sz);
if (rdev_writeat(&store, key, end, key_sz) != key_sz) {
printk(BIOS_WARNING, "failed writing key data\n");
}
@@ -205,7 +224,7 @@
}
end += value_sz;
uint8_t nul = 0;
- if (rdev_writeat(&store, &nul, end, 1) != 1) {
+ if (rdev_writeat(&store, &nul, end, sizeof(nul)) != sizeof(nul)) {
printk(BIOS_WARNING, "failed writing termination\n");
}
diff --git a/src/include/smmstore.h b/src/include/smmstore.h
index a535c5b..30a8191 100644
--- a/src/include/smmstore.h
+++ b/src/include/smmstore.h
@@ -28,22 +28,22 @@
#define SMMSTORE_CMD_APPEND 3
struct smmstore_params_read {
- void *buf;
- ssize_t bufsize;
+ uint32_t *buf;
+ uint32_t bufsize;
};
struct smmstore_params_append {
- void *key;
- size_t keysize;
- void *val;
- size_t valsize;
+ uint32_t *key;
+ uint32_t keysize;
+ uint32_t *val;
+ uint32_t valsize;
};
/* SMM responder */
uint32_t smmstore_exec(uint8_t command, void *param);
/* implementation */
-int smmstore_read_region(void *buf, ssize_t *bufsize);
+int smmstore_read_region(void *buf, uint32_t *bufsize);
int smmstore_append_data(void *key, uint32_t key_sz,
void *value, uint32_t value_sz);
int smmstore_clear_region(void);
diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c
index 2ffc00f..c125c0c 100644
--- a/src/soc/intel/common/block/smm/smihandler.c
+++ b/src/soc/intel/common/block/smm/smihandler.c
@@ -311,7 +311,7 @@
reg_ebx = save_state_ops->get_reg(io_smi, RBX);
/* drivers/smmstore/smi.c */
- ret = smmstore_exec(sub_command, (void *)reg_ebx);
+ ret = smmstore_exec(sub_command, (uintptr_t *)reg_ebx);
save_state_ops->set_reg(io_smi, RAX, ret);
}
--
To view, visit https://review.coreboot.org/c/coreboot/+/30432
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I629be25d2a9b65796ae8f7a700b6bdab57b91b22
Gerrit-Change-Number: 30432
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-MessageType: newchange
6
35
Change in ...coreboot[master]: /mainboard/pcengines/apu2: implement POSTCAR_STAGE
by Krystian Hebel (Code Review) 27 Nov '19
by Krystian Hebel (Code Review) 27 Nov '19
27 Nov '19
Krystian Hebel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32363
Change subject: /mainboard/pcengines/apu2: implement POSTCAR_STAGE
......................................................................
/mainboard/pcengines/apu2: implement POSTCAR_STAGE
As in [1], POSTCAR_STAGE will be required since October 2019.
[1]https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/HN…
Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com>
Change-Id: Iff3dbe68ac17eb2947ff40b9769c6650255656cf
---
M src/mainboard/pcengines/apu2/BiosCallOuts.c
M src/mainboard/pcengines/apu2/Kconfig
M src/mainboard/pcengines/apu2/Makefile.inc
M src/mainboard/pcengines/apu2/OemCustomize.c
A src/mainboard/pcengines/apu2/postcar.c
M src/mainboard/pcengines/apu2/romstage.c
A src/mainboard/pcengines/apu2/state_machine.c
7 files changed, 213 insertions(+), 136 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/32363/1
diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c
index 535024a..0178018 100644
--- a/src/mainboard/pcengines/apu2/BiosCallOuts.c
+++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c
@@ -16,6 +16,7 @@
#include <AGESA.h>
#include <spd_bin.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
+#include <northbridge/amd/agesa/state_machine.h>
#include <FchPlatform.h>
#include <stdlib.h>
@@ -23,7 +24,6 @@
#include "imc.h"
#include "hudson.h"
-static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr);
static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr);
const BIOS_CALLOUT_STRUCT BiosCallouts[] =
@@ -34,8 +34,7 @@
{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
{AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
- {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
- {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }
+ {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }
};
const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
@@ -56,75 +55,66 @@
FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 1 enable, 0 disable TSI Auto Polling */
}
-/**
- * Fch Oem setting callback
- *
- * Configure platform specific Hudson device,
- * such Azalia, SATA, IMC etc.
- */
-static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
+void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams)
{
- AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr;
- if (StdHeader->Func == AMD_INIT_RESET) {
- FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData;
- printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
- //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
- FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
- FchParams->FchReset.SataEnable = hudson_sata_enable();
- FchParams->FchReset.IdeEnable = hudson_ide_enable();
- FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
- FchParams->FchReset.Xhci1Enable = FALSE;
- } else if (StdHeader->Func == AMD_INIT_ENV) {
- FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData;
- printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
+ printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
+ //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
+ FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
+ FchParams->FchReset.SataEnable = hudson_sata_enable();
+ FchParams->FchReset.IdeEnable = hudson_ide_enable();
+ FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
+ FchParams->FchReset.Xhci1Enable = FALSE;
+ printk(BIOS_DEBUG, "Done\n");
+}
+
+void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams)
+{
+ printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
- FchParams->Azalia.AzaliaEnable = AzDisable;
+ FchParams->Azalia.AzaliaEnable = AzDisable;
- /* Fan Control */
- oem_fan_control(FchParams);
+ /* Fan Control */
+ oem_fan_control(FchParams);
- /* XHCI configuration */
- FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
- FchParams->Usb.Xhci1Enable = FALSE;
+ /* XHCI configuration */
+ FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
+ FchParams->Usb.Xhci1Enable = FALSE;
- /* EHCI configuration */
- FchParams->Usb.Ehci3Enable = !CONFIG(HUDSON_XHCI_ENABLE);
+ /* EHCI configuration */
+ FchParams->Usb.Ehci3Enable = !CONFIG(HUDSON_XHCI_ENABLE);
- if (CONFIG(BOARD_PCENGINES_APU2)) {
- // Disable EHCI 0 (port 0 to 3)
- FchParams->Usb.Ehci1Enable = FALSE;
- } else {
- // Enable EHCI 0 (port 0 to 3)
- FchParams->Usb.Ehci1Enable = TRUE;
- }
+ if (CONFIG(BOARD_PCENGINES_APU2)) {
+ // Disable EHCI 0 (port 0 to 3)
+ FchParams->Usb.Ehci1Enable = FALSE;
+ } else {
+ // Enable EHCI 0 (port 0 to 3)
+ FchParams->Usb.Ehci1Enable = TRUE;
+ }
- // Enable EHCI 1 (port 4 to 7)
- // port 4 and 5 to EHCI header port 6 and 7 to PCIe slot.
- FchParams->Usb.Ehci2Enable = TRUE;
+ // Enable EHCI 1 (port 4 to 7)
+ // port 4 and 5 to EHCI header port 6 and 7 to PCIe slot.
+ FchParams->Usb.Ehci2Enable = TRUE;
- /* sata configuration */
- FchParams->Sata.SataDevSlpPort0 = 0; // Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP
- FchParams->Sata.SataDevSlpPort1 = 0;
+ /* sata configuration */
+ FchParams->Sata.SataDevSlpPort0 = 0; // Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP
+ FchParams->Sata.SataDevSlpPort1 = 0;
- FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE;
- switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) {
- case SataRaid:
- case SataAhci:
- case SataAhci7804:
- case SataLegacyIde:
- FchParams->Sata.SataIdeMode = FALSE;
- break;
- case SataIde2Ahci:
- case SataIde2Ahci7804:
- default: /* SataNativeIde */
- FchParams->Sata.SataIdeMode = TRUE;
- break;
- }
+ FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE;
+ switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) {
+ case SataRaid:
+ case SataAhci:
+ case SataAhci7804:
+ case SataLegacyIde:
+ FchParams->Sata.SataIdeMode = FALSE;
+ break;
+ case SataIde2Ahci:
+ case SataIde2Ahci7804:
+ default: /* SataNativeIde */
+ FchParams->Sata.SataIdeMode = TRUE;
+ break;
}
printk(BIOS_DEBUG, "Done\n");
-
- return AGESA_SUCCESS;
}
static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr)
diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig
index 6c3958b..28f9eb8 100644
--- a/src/mainboard/pcengines/apu2/Kconfig
+++ b/src/mainboard/pcengines/apu2/Kconfig
@@ -20,7 +20,6 @@
config BOARD_SPECIFIC_OPTIONS
def_bool y
- select BINARYPI_LEGACY_WRAPPER
select CPU_AMD_PI_00730F01
select NORTHBRIDGE_AMD_PI_00730F01
select SOUTHBRIDGE_AMD_PI_AVALON
diff --git a/src/mainboard/pcengines/apu2/Makefile.inc b/src/mainboard/pcengines/apu2/Makefile.inc
index 4e6364e..7824996 100644
--- a/src/mainboard/pcengines/apu2/Makefile.inc
+++ b/src/mainboard/pcengines/apu2/Makefile.inc
@@ -14,10 +14,14 @@
# GNU General Public License for more details.
#
+romstage-y += state_machine.c
romstage-y += BiosCallOuts.c
romstage-y += OemCustomize.c
romstage-y += gpio_ftns.c
+postcar-y += postcar.c
+
+ramstage-y += state_machine.c
ramstage-y += BiosCallOuts.c
ramstage-y += OemCustomize.c
ramstage-y += gpio_ftns.c
diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c
index 700f4c7..7ef7e00 100644
--- a/src/mainboard/pcengines/apu2/OemCustomize.c
+++ b/src/mainboard/pcengines/apu2/OemCustomize.c
@@ -14,7 +14,7 @@
*/
#include <AGESA.h>
-#include <northbridge/amd/pi/agesawrapper.h>
+#include <northbridge/amd/agesa/state_machine.h>
static const PCIe_PORT_DESCRIPTOR PortList[] = {
@@ -76,25 +76,7 @@
.DdiLinkList = NULL,
};
-/*---------------------------------------------------------------------------------------*/
-/**
- * OemCustomizeInitEarly
- *
- * Description:
- * This stub function will call the host environment through the binary block
- * interface (call-out port) to provide a user hook opportunity
- *
- * Parameters:
- * @param[in] *InitEarly
- *
- * @retval VOID
- *
- **/
-/*---------------------------------------------------------------------------------------*/
-VOID
-OemCustomizeInitEarly (
- IN OUT AMD_EARLY_PARAMS *InitEarly
- )
+void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{
InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
InitEarly->PlatformConfig.CStateMode = CStateModeC6;
diff --git a/src/mainboard/pcengines/apu2/postcar.c b/src/mainboard/pcengines/apu2/postcar.c
new file mode 100644
index 0000000..b57ea94
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/postcar.c
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/cpu.h>
+#include <arch/io.h>
+
+void late_car_teardown(void)
+{
+ /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
+ outb(0xEA, 0xCD6);
+ outb(0x1, 0xcd7);
+}
diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c
index bd3c421..a6fe713 100644
--- a/src/mainboard/pcengines/apu2/romstage.c
+++ b/src/mainboard/pcengines/apu2/romstage.c
@@ -40,9 +40,11 @@
static void early_lpc_init(void);
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void board_BeforeAgesa(struct sysinfo *cb)
{
u32 val;
+ pci_devfn_t dev;
+ u32 data;
/*
* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
@@ -57,51 +59,32 @@
hudson_lpc_port80();
- if (!cpu_init_detectedx && boot_cpu()) {
- pci_devfn_t dev;
- u32 data;
+ timestamp_init(timestamp_get());
+ timestamp_add_now(TS_START_ROMSTAGE);
- timestamp_init(timestamp_get());
- timestamp_add_now(TS_START_ROMSTAGE);
+ post_code(0x30);
+ early_lpc_init();
- post_code(0x30);
- early_lpc_init();
+ hudson_clk_output_48Mhz();
+ post_code(0x31);
- hudson_clk_output_48Mhz();
- post_code(0x31);
+ dev = PCI_DEV(0, 0x14, 3);
+ data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
+ /* enable 0x2e/0x4e IO decoding before configuring SuperIO */
+ pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3);
- dev = PCI_DEV(0, 0x14, 3);
- data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
- /* enable 0x2e/0x4e IO decoding before configuring SuperIO */
- pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3);
+ /* COM2 on apu5 is reserved so only COM1 should be supported */
+ if ((CONFIG_UART_FOR_CONSOLE == 1) &&
+ !CONFIG(BOARD_PCENGINES_APU5))
+ nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE);
+ else if (CONFIG_UART_FOR_CONSOLE == 0)
+ nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE);
- /* COM2 on apu5 is reserved so only COM1 should be supported */
- if ((CONFIG_UART_FOR_CONSOLE == 1) &&
- !CONFIG(BOARD_PCENGINES_APU5))
- nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE);
- else if (CONFIG_UART_FOR_CONSOLE == 0)
- nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE);
-
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
+ console_init();
/* Load MPB */
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- post_code(0x37);
- AGESAWRAPPER(amdinitreset);
-
- post_code(0x38);
- printk(BIOS_DEBUG, "Got past avalon_early_setup\n");
-
- post_code(0x39);
- AGESAWRAPPER(amdinitearly);
/* Disable SVI2 controller to wait for command completion */
val = pci_read_config32(PCI_DEV(0, 0x18, 5), 0x12C);
@@ -112,27 +95,17 @@
val |= (1 << 30);
pci_write_config32(PCI_DEV(0, 0x18, 5), 0x12C, val);
}
-
- timestamp_add_now(TS_BEFORE_INITRAM);
-
- post_code(0x40);
- AGESAWRAPPER(amdinitpost);
-
- /* FIXME: Detect if TSC frequency changed during raminit? */
- timestamp_rescale_table(1, 4);
-
- timestamp_add_now(TS_AFTER_INITRAM);
}
-void agesa_postcar(struct sysinfo *cb)
-{
- //PspMboxBiosCmdDramInfo();
- post_code(0x41);
- AGESAWRAPPER(amdinitenv);
+//~ void agesa_postcar(struct sysinfo *cb)
+//~ {
+ //~ //PspMboxBiosCmdDramInfo();
+ //~ post_code(0x41);
+ //~ AGESAWRAPPER(amdinitenv);
- outb(0xEA, 0xCD6);
- outb(0x1, 0xcd7);
-}
+ //~ outb(0xEA, 0xCD6);
+ //~ outb(0x1, 0xcd7);
+//~ }
static void early_lpc_init(void)
{
diff --git a/src/mainboard/pcengines/apu2/state_machine.c b/src/mainboard/pcengines/apu2/state_machine.c
new file mode 100644
index 0000000..4a10df9
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/state_machine.c
@@ -0,0 +1,105 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Kyösti Mälkki
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <Porting.h>
+#include <AGESA.h>
+#include <binaryPI/FieldAccessors.h>
+
+#include <cbmem.h>
+#include <northbridge/amd/agesa/state_machine.h>
+#include <northbridge/amd/agesa/agesa_helper.h>
+
+void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
+{
+}
+
+void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early)
+{
+}
+
+void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)
+{
+}
+
+void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)
+{
+ backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop);
+}
+
+void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume)
+{
+}
+
+void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume)
+{
+}
+
+void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env)
+{
+ EmptyHeap();
+}
+
+void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env)
+{
+}
+
+void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late)
+{
+}
+
+void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late)
+{
+ amd_initcpuio();
+}
+
+void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid)
+{
+ amd_initcpuio();
+}
+
+void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late)
+{
+}
+
+void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save)
+{
+}
+
+AGESA_STATUS
+AmdGetValue (
+ IN CONST AGESA_FIELD_NAME name,
+ IN OUT VOID** value,
+ IN UINT32 size
+ )
+{
+ AGESA_STATUS status;
+ struct sysinfo cb;
+ AMD_ACCESSOR_PARAMS Params = {};
+
+ agesa_set_interface(&cb);
+ Params.StdHeader.ImageBasePtr = cb.StdHeader.ImageBasePtr;
+
+ Params.AllocationMethod = ByHost;
+ Params.FieldName = name;
+ Params.FieldValue = *value;
+ Params.FieldSize = size;
+
+ status = module_dispatch(AMD_GET_VALUE, (AMD_CONFIG_PARAMS*) &Params);
+
+ *value = Params.FieldValue;
+ size = Params.FieldSize;
+
+ return status;
+}
--
To view, visit https://review.coreboot.org/c/coreboot/+/32363
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iff3dbe68ac17eb2947ff40b9769c6650255656cf
Gerrit-Change-Number: 32363
Gerrit-PatchSet: 1
Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com>
Gerrit-MessageType: newchange
8
21
Change in ...coreboot[master]: nb/amd/pi: support for boards without BINARYPI_LEGACY_WRAPPER
by Krystian Hebel (Code Review) 26 Nov '19
by Krystian Hebel (Code Review) 26 Nov '19
26 Nov '19
Krystian Hebel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32421
Change subject: nb/amd/pi: support for boards without BINARYPI_LEGACY_WRAPPER
......................................................................
nb/amd/pi: support for boards without BINARYPI_LEGACY_WRAPPER
A stripped down version (without S3) of ../agesa/family*/state_machine.c
is used to provide platform-specific hooks.
AmdGetValue() is required by cpu_bus_scan(), it is adapted from binaryPI
wrapper to use new interface for dispatcher.
Tested only on 00730F01 (apu2) - no other platforms available.
Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com>
Change-Id: I700a7d8d3c77ee0525b2c764c720ab5bf39925f8
Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com>
---
M src/northbridge/amd/pi/00630F01/northbridge.c
M src/northbridge/amd/pi/00660F01/northbridge.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/amd/pi/Makefile.inc
A src/northbridge/amd/pi/state_machine.c
5 files changed, 164 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/32421/1
diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c
index eca2f0c..c64a7ba 100644
--- a/src/northbridge/amd/pi/00630F01/northbridge.c
+++ b/src/northbridge/amd/pi/00630F01/northbridge.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2019 3mdeb Embedded Systems Consulting
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -38,6 +39,8 @@
#if CONFIG(BINARYPI_LEGACY_WRAPPER)
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
+#else
+#include <northbridge/amd/agesa/state_machine.h>
#endif
#define MAX_NODE_NUMS MAX_NODES
@@ -1006,3 +1009,28 @@
return new_vendev;
}
+
+#if !CONFIG_BINARYPI_LEGACY_WRAPPER
+AGESA_STATUS
+AmdGetValue(IN CONST AGESA_FIELD_NAME name, IN OUT VOID **value, IN UINT32 size)
+{
+ AGESA_STATUS status;
+ struct sysinfo cb;
+ AMD_ACCESSOR_PARAMS Params = {};
+
+ agesa_set_interface(&cb);
+ Params.StdHeader.ImageBasePtr = cb.StdHeader.ImageBasePtr;
+
+ Params.AllocationMethod = ByHost;
+ Params.FieldName = name;
+ Params.FieldValue = *value;
+ Params.FieldSize = size;
+
+ status = module_dispatch(AMD_GET_VALUE, (AMD_CONFIG_PARAMS*) &Params);
+
+ *value = Params.FieldValue;
+ size = Params.FieldSize;
+
+ return status;
+}
+#endif
diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c
index 43df725..08dfd84 100644
--- a/src/northbridge/amd/pi/00660F01/northbridge.c
+++ b/src/northbridge/amd/pi/00660F01/northbridge.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Advanced Micro Devices, Inc.
+ * Copyright (C) 2019 3mdeb Embedded Systems Consulting
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -38,6 +39,8 @@
#if CONFIG(BINARYPI_LEGACY_WRAPPER)
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
+#else
+#include <northbridge/amd/agesa/state_machine.h>
#endif
#define MAX_NODE_NUMS MAX_NODES
@@ -991,3 +994,28 @@
return new_vendev;
}
+
+#if !CONFIG_BINARYPI_LEGACY_WRAPPER
+AGESA_STATUS
+AmdGetValue(IN CONST AGESA_FIELD_NAME name, IN OUT VOID **value, IN UINT32 size)
+{
+ AGESA_STATUS status;
+ struct sysinfo cb;
+ AMD_ACCESSOR_PARAMS Params = {};
+
+ agesa_set_interface(&cb);
+ Params.StdHeader.ImageBasePtr = cb.StdHeader.ImageBasePtr;
+
+ Params.AllocationMethod = ByHost;
+ Params.FieldName = name;
+ Params.FieldValue = *value;
+ Params.FieldSize = size;
+
+ status = module_dispatch(AMD_GET_VALUE, (AMD_CONFIG_PARAMS*) &Params);
+
+ *value = Params.FieldValue;
+ size = Params.FieldSize;
+
+ return status;
+}
+#endif
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index 926208c..f69f226 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -40,6 +40,8 @@
#if CONFIG(BINARYPI_LEGACY_WRAPPER)
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
+#else
+#include <northbridge/amd/agesa/state_machine.h>
#endif
#define MAX_NODE_NUMS MAX_NODES
@@ -1242,3 +1244,28 @@
return new_vendev;
}
+
+#if !CONFIG_BINARYPI_LEGACY_WRAPPER
+AGESA_STATUS
+AmdGetValue(IN CONST AGESA_FIELD_NAME name, IN OUT VOID **value, IN UINT32 size)
+{
+ AGESA_STATUS status;
+ struct sysinfo cb;
+ AMD_ACCESSOR_PARAMS Params = {};
+
+ agesa_set_interface(&cb);
+ Params.StdHeader.ImageBasePtr = cb.StdHeader.ImageBasePtr;
+
+ Params.AllocationMethod = ByHost;
+ Params.FieldName = name;
+ Params.FieldValue = *value;
+ Params.FieldSize = size;
+
+ status = module_dispatch(AMD_GET_VALUE, (AMD_CONFIG_PARAMS*) &Params);
+
+ *value = Params.FieldValue;
+ size = Params.FieldSize;
+
+ return status;
+}
+#endif
diff --git a/src/northbridge/amd/pi/Makefile.inc b/src/northbridge/amd/pi/Makefile.inc
index c2c8d88..349761b 100644
--- a/src/northbridge/amd/pi/Makefile.inc
+++ b/src/northbridge/amd/pi/Makefile.inc
@@ -22,6 +22,9 @@
ifeq ($(CONFIG_BINARYPI_LEGACY_WRAPPER), y)
romstage-y += agesawrapper.c
ramstage-y += agesawrapper.c
+else
+romstage-y += state_machine.c
+ramstage-y += state_machine.c
endif
romstage-y += ramtop.c
diff --git a/src/northbridge/amd/pi/state_machine.c b/src/northbridge/amd/pi/state_machine.c
new file mode 100644
index 0000000..f42e97f
--- /dev/null
+++ b/src/northbridge/amd/pi/state_machine.c
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Kyösti Mälkki
+ * Copyright (C) 2019 3mdeb Embedded Systems Consulting
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <Porting.h>
+#include <AGESA.h>
+
+#include <cbmem.h>
+#include <northbridge/amd/agesa/state_machine.h>
+#include <northbridge/amd/agesa/agesa_helper.h>
+
+void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
+{
+}
+
+void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early)
+{
+}
+
+void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)
+{
+}
+
+void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)
+{
+ backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop);
+}
+
+void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume)
+{
+}
+
+void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume)
+{
+}
+
+void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env)
+{
+ EmptyHeap();
+}
+
+void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env)
+{
+}
+
+void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late)
+{
+}
+
+void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late)
+{
+ amd_initcpuio();
+}
+
+void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid)
+{
+ amd_initcpuio();
+}
+
+void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late)
+{
+}
+
+void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save)
+{
+}
--
To view, visit https://review.coreboot.org/c/coreboot/+/32421
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I700a7d8d3c77ee0525b2c764c720ab5bf39925f8
Gerrit-Change-Number: 32421
Gerrit-PatchSet: 1
Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com>
Gerrit-MessageType: newchange
6
24