coreboot-gerrit February 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: soc/intel/denverton + mb: Change UART IRQ line in conflict with ME
by Julien Viard de Galbert (Code Review) 21 Feb '19

21 Feb '19

Julien Viard de Galbert has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25444 ) Change subject: soc/intel/denverton + mb: Change UART IRQ line in conflict with ME ...................................................................... Patch Set 10: Thanks Vanessa for testing this. I discarded the patch -- To view, visit https://review.coreboot.org/c/coreboot/+/25444 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c59ff80ef19b54c2de1a6a8205afe6482adfdff Gerrit-Change-Number: 25444 Gerrit-PatchSet: 10 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Comment-Date: Thu, 21 Feb 2019 21:34:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/denverton + mb: Change UART IRQ line in conflict with ME
by Julien Viard de Galbert (Code Review) 21 Feb '19

21 Feb '19

Julien Viard de Galbert has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/25444 ) Change subject: soc/intel/denverton + mb: Change UART IRQ line in conflict with ME ...................................................................... Abandoned This patch is no longer necessary -- To view, visit https://review.coreboot.org/c/coreboot/+/25444 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c59ff80ef19b54c2de1a6a8205afe6482adfdff Gerrit-Change-Number: 25444 Gerrit-PatchSet: 10 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: soc/amd/common: Fix AmdLateRunApTask()
by Richard Spiegel (Code Review) 21 Feb '19

21 Feb '19

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27277 ) Change subject: soc/amd/common: Fix AmdLateRunApTask() ...................................................................... Patch Set 5: Code-Review+2 (1 comment) Been a little busy myself... I'll give you a +2 assuming your answer to my question being a yes. https://review.coreboot.org/#/c/27277/5/src/soc/amd/common/block/pi/agesawr… File src/soc/amd/common/block/pi/agesawrapper.c: https://review.coreboot.org/#/c/27277/5/src/soc/amd/common/block/pi/agesawr… PS5, Line 356: amd_late_run_ap_task > That prefix agesawrapper_ was stupid in the first place and followups shall remove the rest. […] I would tend to agree. Are you planning on doing the followups that you mentioned? -- To view, visit https://review.coreboot.org/c/coreboot/+/27277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1dad64b955b53bd19363737665235f95aa3d451e Gerrit-Change-Number: 27277 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 21 Feb 2019 20:47:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Comment-In-Reply-To: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: cpu/intel/common: Add newline to set_feature_ctrl_lock() output
by Matt DeVillier (Code Review) 21 Feb '19

21 Feb '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31532 Change subject: cpu/intel/common: Add newline to set_feature_ctrl_lock() output ...................................................................... cpu/intel/common: Add newline to set_feature_ctrl_lock() output Without newline, if IA32_FEATURE_CONTROL already locked, next console line will be concatenated. If run on a multiple CPUs, you get multiple lines concatenated. Change-Id: I5b73ae4cb045973fa3ce07f4d93fda0caadf78eb Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/cpu/intel/common/common_init.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/31532/1 diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index 0aef3e8..321c56c 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -83,7 +83,7 @@ msr = rdmsr(IA32_FEATURE_CONTROL); if (msr.lo & (1 << 0)) { - printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked; "); + printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n"); /* IA32_FEATURE_CONTROL locked. If we set it again we get an * illegal instruction */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b73ae4cb045973fa3ce07f4d93fda0caadf78eb Gerrit-Change-Number: 31532 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mediatek/mt8183: Support gpio eh and rsel setting for I2C
by wang qii (Code Review) 21 Feb '19

21 Feb '19

wang qii has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30974 Change subject: mediatek/mt8183: Support gpio eh and rsel setting for I2C ...................................................................... mediatek/mt8183: Support gpio eh and rsel setting for I2C The setting of these registers are only for i2c pin. BUG=b:80501386 BRANCH=none TEST=Boot correctly on Kukui Change-Id: I518ca07645fe55aa55e94e4f98178baa0b74a882 Signed-off-by: jg_poxu <jg_poxu(a)mediatek.com> --- M src/soc/mediatek/mt8183/gpio.c M src/soc/mediatek/mt8183/include/soc/gpio.h 2 files changed, 67 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/30974/1 diff --git a/src/soc/mediatek/mt8183/gpio.c b/src/soc/mediatek/mt8183/gpio.c index d555c33..c87509a 100644 --- a/src/soc/mediatek/mt8183/gpio.c +++ b/src/soc/mediatek/mt8183/gpio.c @@ -15,10 +15,12 @@ #include <arch/io.h> #include <gpio.h> +#include <assert.h> enum { EN_OFFSET = 0x60, SEL_OFFSET = 0x80, + EH_RSEL_OFFSET = 0xF0, }; static void gpio_set_pull_pupd(gpio_t gpio, enum pull_enable enable, @@ -67,3 +69,66 @@ else gpio_set_pull_en_sel(gpio, enable, select); } + +struct i2c_pin_spec { + uint16_t id; + uint8_t eh_bit; + uint8_t rsel_bit; +}; + +#define MTK_I2C_PIN_SPEC(pad_id, eh, rsel) \ + { \ + .id = pad_id, \ + .eh_bit = eh, \ + .rsel_bit = rsel, \ + } + +static const struct i2c_pin_spec i2c_pin_spec_list[] = { + MTK_I2C_PIN_SPEC(PAD_SCL5_ID, 20, 18), + MTK_I2C_PIN_SPEC(PAD_SDA5_ID, 15, 13), + MTK_I2C_PIN_SPEC(PAD_SCL3_ID, 12, 10), + MTK_I2C_PIN_SPEC(PAD_SDA3_ID, 7, 5), + MTK_I2C_PIN_SPEC(PAD_SDA1_ID, 12, 7), + MTK_I2C_PIN_SPEC(PAD_SDA0_ID, 9, 5), + MTK_I2C_PIN_SPEC(PAD_SCL0_ID, 19, 15), + MTK_I2C_PIN_SPEC(PAD_SCL1_ID, 22, 17), + MTK_I2C_PIN_SPEC(PAD_SCL2_ID, 24, 20), + MTK_I2C_PIN_SPEC(PAD_SDA2_ID, 14, 10), + MTK_I2C_PIN_SPEC(PAD_SCL4_ID, 27, 22), + MTK_I2C_PIN_SPEC(PAD_SDA4_ID, 17, 12), +}; + +static const struct i2c_pin_spec *get_i2c_pin_spec(gpio_t gpio) +{ + size_t i; + + for (i = 0; i < ARRAY_SIZE(i2c_pin_spec_list); i++) + if (gpio.id == i2c_pin_spec_list[i].id) + return &i2c_pin_spec_list[i]; + + return NULL; +} + +void gpio_set_i2c_eh(gpio_t gpio, uint32_t select) +{ + void *reg = GPIO_TO_IOCFG_BASE(gpio.base) + EH_RSEL_OFFSET; + uint8_t bit; + const struct i2c_pin_spec *pin = get_i2c_pin_spec(gpio); + + assert(pin); + assert(select < 8); + bit = pin->eh_bit; + clrsetbits_le32(reg, 7 << bit, select << bit); +} + +void gpio_set_i2c_rsel(gpio_t gpio, uint32_t select) +{ + void *reg = GPIO_TO_IOCFG_BASE(gpio.base) + EH_RSEL_OFFSET; + uint8_t bit; + const struct i2c_pin_spec *pin = get_i2c_pin_spec(gpio); + + assert(pin); + assert(select < 4); + bit = pin->rsel_bit; + clrsetbits_le32(reg, 3 << bit, select << bit); +} diff --git a/src/soc/mediatek/mt8183/include/soc/gpio.h b/src/soc/mediatek/mt8183/include/soc/gpio.h index c3c8dda..a3a972b 100644 --- a/src/soc/mediatek/mt8183/include/soc/gpio.h +++ b/src/soc/mediatek/mt8183/include/soc/gpio.h @@ -616,5 +616,6 @@ check_member(gpio_regs, mode[22].val, 0x460); static struct gpio_regs *const mtk_gpio = (void *)(GPIO_BASE); - +void gpio_set_i2c_eh(gpio_t gpio, uint32_t select); +void gpio_set_i2c_rsel(gpio_t gpio, uint32_t select); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/30974 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I518ca07645fe55aa55e94e4f98178baa0b74a882 Gerrit-Change-Number: 30974 Gerrit-PatchSet: 1 Gerrit-Owner: wang qii <Qii.Wang(a)mediatek.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: timestamp: Move timestamp_should_run() call
by Kyösti Mälkki (Code Review) 21 Feb '19

21 Feb '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31524 Change subject: timestamp: Move timestamp_should_run() call ...................................................................... timestamp: Move timestamp_should_run() call Old location caused spurious error messages when called from APs, where timestamp_add_now() should do nothing. Moving the test also makes usecs_from_boot() usable from APs (assuming cache coherency). Change-Id: Ice9ece11b15bbe1a58a038cda3d299862e6f822b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/lib/timestamp.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/31524/1 diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 6885e7b..f84b9d5 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -125,9 +125,6 @@ MAYBE_STATIC struct timestamp_table *ts_table = NULL; struct timestamp_cache *ts_cache; - if (!timestamp_should_run()) - return NULL; - if (ts_table != NULL) return ts_table; @@ -188,6 +185,9 @@ { struct timestamp_table *ts_table; + if (!timestamp_should_run()) + return; + ts_table = timestamp_table_get(); if (!ts_table) { -- To view, visit https://review.coreboot.org/c/coreboot/+/31524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice9ece11b15bbe1a58a038cda3d299862e6f822b Gerrit-Change-Number: 31524 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: SoC specific microcode update check
by Patrick Georgi (Code Review) 21 Feb '19

21 Feb '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31492 ) Change subject: soc/intel/cannonlake: SoC specific microcode update check ...................................................................... soc/intel/cannonlake: SoC specific microcode update check For CFL and WHL, Microcode is being loaded from FIT. Both supports the PRMRR/SGX feature. If This is supported the FIT microcode load will set the msr (0x08b) with the Patch id one less than the id in the microcode binary. This results in Microcode getting reloaded again in bootblock and ramstage. Avoid the microcode reload by checking for PRMRR support. CFL and WHL CPU die are based on KBL CPU so we need to have this check, where CNL CPU die is not based on KBL CPU so skip this check for CNL. BUG=b:124126405 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Change-Id: I3311a7413d27044f9c819179e5b0cb9a67b46955 Reviewed-on: https://review.coreboot.org/c/31492 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/soc/intel/cannonlake/cpu.c 1 file changed, 33 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Rizwan Qureshi: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index f987f8b..19ff171 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -31,6 +31,8 @@ #include <soc/pm.h> #include <soc/smm.h> #include <soc/systemagent.h> +#include <cpu/x86/mtrr.h> +#include <cpu/intel/microcode.h> /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ static const u8 power_limit_time_sec_to_msr[] = { @@ -484,3 +486,34 @@ /* Thermal throttle activation offset */ configure_thermal_target(); } + +int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) +{ + msr_t msr1; + msr_t msr2; + + /* + * CFL and WHL CPU die are based on KBL CPU so we need to + * have this check, where CNL CPU die is not based on KBL CPU + * so skip this check for CNL. + */ + if (!IS_ENABLED(CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE)) + return 0; + + /* + * If PRMRR/SGX is supported the FIT microcode load will set the msr + * 0x08b with the Patch revision id one less than the id in the + * microcode binary. The PRMRR support is indicated in the MSR + * MTRRCAP[12]. If SGX is not enabled, check and avoid reloading the + * same microcode during CPU initialization. If SGX is enabled, as + * part of SGX BIOS initialization steps, the same microcode needs to + * be reloaded after the core PRMRR MSRs are programmed. + */ + msr1 = rdmsr(MTRR_CAP_MSR); + msr2 = rdmsr(MSR_PRMRR_PHYS_BASE); + if (msr2.lo && (current_patch_id == new_patch_id - 1)) + return 0; + + return (msr1.lo & PRMRR_SUPPORTED) && + (current_patch_id == new_patch_id - 1); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3311a7413d27044f9c819179e5b0cb9a67b46955 Gerrit-Change-Number: 31492 Gerrit-PatchSet: 5 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: RONAK KANABAR <ronak199323(a)gmail.com> Gerrit-MessageType: merged

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Change in ...coreboot[master]: sb/intel/bd82x6x: Fix default IRQ mapping
by Nico Huber (Code Review) 21 Feb '19

21 Feb '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31498 Change subject: sb/intel/bd82x6x: Fix default IRQ mapping ...................................................................... sb/intel/bd82x6x: Fix default IRQ mapping The default mapping was probably copy-pasted from a random board and disabled some interrupts (by implicitly clearing some register bits). We provide a new default mapping with some reasoning, that tries to be most compatible (i.e. avoids to use PIRQ E-H that are not shareable on some boards). Change-Id: I33f82702ea9c1b9c22ce14f01ee630dbf6203362 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/southbridge/intel/bd82x6x/early_rcba.c 1 file changed, 60 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/31498/1 diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c index 443b6c2..0dd7a56 100644 --- a/src/southbridge/intel/bd82x6x/early_rcba.c +++ b/src/southbridge/intel/bd82x6x/early_rcba.c @@ -23,40 +23,73 @@ southbridge_configure_default_intmap(void) { /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP SLOT1 INTA -> PIRQB - * D28IP_P2IP SLOT2 INTB -> PIRQF - * D28IP_P3IP SLOT3 INTC -> PIRQD - * D28IP_P5IP SLOT5 INTC -> PIRQD - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQF - * D31IP_SIP SATA INTA -> PIRQB (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQH - * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQA (MSI) - * - + * For the PCH internal PCI functions, provide a reasonable + * default IRQ mapping that utilizes only PIRQ A to D. Higher + * PIRQs are sometimes used for other on-board chips that + * require an edge triggered interrupt which is not shareable. */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + /* + * We use a linear mapping for the pin numbers. They are not + * physical pins, and thus, have no relation between the dif- + * ferent devices. Only rule we must obey is that a single- + * function device has to use pin A. + */ + RCBA32(D31IP) = (INTD << D31IP_TTIP) | (INTC << D31IP_SIP2) | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D30IP) = (NOINT << D30IP_PIP); RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | - (INTC << D28IP_P3IP) | (INTC << D28IP_P5IP); + RCBA32(D28IP) = (INTD << D28IP_P8IP) | (INTC << D28IP_P7IP) | + (INTB << D28IP_P6IP) | (INTA << D28IP_P5IP) | + (INTD << D28IP_P4IP) | (INTC << D28IP_P3IP) | + (INTB << D28IP_P2IP) | (INTA << D28IP_P1IP); RCBA32(D27IP) = (INTA << D27IP_ZIP); RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + RCBA32(D25IP) = (INTA << D25IP_LIP); + RCBA32(D22IP) = (INTA << D22IP_MEI1IP); + RCBA32(D20IP) = (INTA << D20IP_XHCIIP); - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + /* + * For the PIRQ allocation the following was taken into + * account: + * o Interrupts of the PCIe root ports are only about + * events at the ports, not downstream devices. So we + * don't expect many interrupts there and ignore them. + * o We don't expect to talk constantly to the ME either + * so ignore that, too. Same for SMBus and the thermal + * device. + * o Second SATA interface is only used in non-AHCI mode + * so unlikely to coexist with modern interfaces (e.g. + * xHCI). + * o An OS that knows USB3 will likely also know how to + * use MSI. + * + * The functions that might matter first: + * + * D31IP_SIP SATA 1 -> PIRQ A (MSI capable in AHCI mode) + * D31IP_SIP2 SATA 2 -> PIRQ B + * D29IP_E1P EHCI 1 -> PIRQ C + * D27IP_ZIP HDA -> PIRQ D (MSI capable) + * D26IP_E2P EHCI 2 -> PIRQ D + * D25IP_LIP GbE -> PIRQ B (MSI capable) + * D20IP_XHCIIP xHCI -> PIRQ B (MSI capable) + * + * D31IP_TTIP Thermal -> PIRQ B + * D31IP_SMIP SMBUS -> PIRQ A + * D28IP_* PCIe RP -> PIRQ A-D (MSI capable) + * D22IP_MEI1IP ME -> PIRQ A (MSI capable) + * + * Note, CPU-integrated functions seem to always use PIRQ A. + */ +#define _none 0 + DIR_ROUTE(D31IR, PIRQA, PIRQA, PIRQB, PIRQB); + DIR_ROUTE(D29IR, PIRQC, _none, _none, _none); + DIR_ROUTE(D28IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D27IR, PIRQD, _none, _none, _none); + DIR_ROUTE(D26IR, PIRQD, _none, _none, _none); + DIR_ROUTE(D25IR, PIRQB, _none, _none, _none); + DIR_ROUTE(D22IR, PIRQA, _none, _none, _none); + DIR_ROUTE(D20IR, PIRQB, _none, _none, _none); +#undef _none /* Enable IOAPIC (generic) */ RCBA16(OIC) = 0x0100; -- To view, visit https://review.coreboot.org/c/coreboot/+/31498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33f82702ea9c1b9c22ce14f01ee630dbf6203362 Gerrit-Change-Number: 31498 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: SMBIOS: Fix bios version
by HAOUAS Elyes (Code Review) 21 Feb '19

21 Feb '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31437 Change subject: SMBIOS: Fix bios version ...................................................................... SMBIOS: Fix bios version Change-Id: I142f08ed3c2704b8fde6d176f23772f5d6b33e85 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/smbios.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/31437/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index f816647..345e737 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -382,7 +382,9 @@ t->extended_bios_rom_size = DIV_ROUND_UP(CONFIG_ROM_SIZE, MiB); } - t->system_bios_major_release = 4; + t->system_bios_major_release = coreboot_version; + t->system_bios_minor_release = coreboot_extra_version; + t->bios_characteristics = BIOS_CHARACTERISTICS_PCI_SUPPORTED | BIOS_CHARACTERISTICS_SELECTABLE_BOOT | -- To view, visit https://review.coreboot.org/c/coreboot/+/31437 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I142f08ed3c2704b8fde6d176f23772f5d6b33e85 Gerrit-Change-Number: 31437 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: vendorcode/intel/fsp/fsp2_0/cml: Add FSP header files for Cometlake
by Subrata Banik (Code Review) 21 Feb '19

21 Feb '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31529 ) Change subject: vendorcode/intel/fsp/fsp2_0/cml: Add FSP header files for Cometlake ...................................................................... Patch Set 2: > Please use the 3rdparty FSP repo instead. product is not PRQ'ed hence those headers can't be uploaded into FSP repo for now. After FSI we should . -- To view, visit https://review.coreboot.org/c/coreboot/+/31529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I734316445dda5b1feb4098ce3c58b6dd8ce2d272 Gerrit-Change-Number: 31529 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Thu, 21 Feb 2019 19:04:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2019