coreboot-gerrit February 2019

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Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by Philipp Deppenwiese (Code Review) 22 Feb '19

22 Feb '19

Hello Werner Zeh, Aaron Durbin, Julius Werner, Patrick Rudolph, Paul Menzel, David Hendricks, build bot (Jenkins), Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29563 to look at the new patch set (#42). Change subject: security/tpm: Fix TCPA log feature ...................................................................... security/tpm: Fix TCPA log feature Until now the TCPA log wasn't working correctly. * Refactor TCPA log code. * Add TCPA log dump fucntion. * Make TCPA log available in bootblock. * Fix TCPA log formatting. * Add x86 and Cavium memory for early log. Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/arch/x86/car.ld M src/commonlib/include/commonlib/tcpa_log_serialized.h M src/include/memlayout.h M src/security/tpm/tspi.h M src/security/tpm/tspi/log.c M src/security/tpm/tspi/tspi.c M src/security/vboot/Kconfig M src/security/vboot/secdata_tpm.c M src/security/vboot/symbols.h M src/soc/cavium/cn81xx/include/soc/memlayout.ld M src/soc/imgtec/pistachio/include/soc/memlayout.ld M src/soc/mediatek/mt8173/include/soc/memlayout.ld M src/soc/mediatek/mt8183/include/soc/memlayout.ld M src/soc/nvidia/tegra124/include/soc/memlayout.ld M src/soc/nvidia/tegra210/include/soc/memlayout.ld M src/soc/samsung/exynos5250/include/soc/memlayout.ld M util/cbmem/cbmem.c 17 files changed, 172 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/29563/42 -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 42 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by build bot (Jenkins) (Code Review) 22 Feb '19

22 Feb '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29563 ) Change subject: security/tpm: Fix TCPA log feature ...................................................................... Patch Set 41: (10 comments) https://review.coreboot.org/#/c/29563/41/src/include/memlayout.h File src/include/memlayout.h: https://review.coreboot.org/#/c/29563/41/src/include/memlayout.h@167 PS41, Line 167: #define VBOOT2_TPM_LOG(addr, size) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/29563/41/src/include/memlayout.h@167 PS41, Line 167: #define VBOOT2_TPM_LOG(addr, size) \ macros should not use a trailing semicolon https://review.coreboot.org/#/c/29563/41/src/security/tpm/tspi.h File src/security/tpm/tspi.h: https://review.coreboot.org/#/c/29563/41/src/security/tpm/tspi.h@50 PS41, Line 50: uint32_t tpm_extend_pcr(int pcr, const char *digest_type, uint8_t *digest, size_t digest_len, line over 80 characters https://review.coreboot.org/#/c/29563/41/src/security/tpm/tspi/log.c File src/security/tpm/tspi/log.c: https://review.coreboot.org/#/c/29563/41/src/security/tpm/tspi/log.c@37 PS41, Line 37: size_t tcpa_log_len = sizeof(struct tcpa_table) + MAX_TCPA_LOG_ENTRIES * sizeof(struct tcpa_entry); line over 80 characters https://review.coreboot.org/#/c/29563/41/src/security/tpm/tspi/log.c@44 PS41, Line 44: strncpy((char *)tclt->header, TCPA_LOG_HEADER, sizeof(tclt->header)); line over 80 characters https://review.coreboot.org/#/c/29563/41/src/security/tpm/tspi/log.c@50 PS41, Line 50: if (!cbmem_possibly_online() && IS_ENABLED(CONFIG_VBOOT_TCPA_LOG_RECOVERY)) { line over 80 characters https://review.coreboot.org/#/c/29563/41/src/security/tpm/tspi/log.c@53 PS41, Line 53: if (strncmp(TCPA_LOG_HEADER, (const char *)tclt->header, sizeof(tclt->header))) { line over 80 characters https://review.coreboot.org/#/c/29563/41/src/security/tpm/tspi/log.c@56 PS41, Line 56: strncpy((char *)tclt->header, TCPA_LOG_HEADER, sizeof(tclt->header)); line over 80 characters https://review.coreboot.org/#/c/29563/41/src/security/tpm/tspi/log.c@91 PS41, Line 91: void tcpa_log_add_table_entry(const char *name, const uint32_t pcr, const char *digest_type, line over 80 characters https://review.coreboot.org/#/c/29563/41/src/security/vboot/secdata_tpm.c File src/security/vboot/secdata_tpm.c: https://review.coreboot.org/#/c/29563/41/src/security/vboot/secdata_tpm.c@86 PS41, Line 86: return tpm_extend_pcr(pcr, "SHA256", buffer, size, TPM_PCR_GBB_HWID_NAME); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 41 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 22 Feb 2019 11:36:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by Philipp Deppenwiese (Code Review) 22 Feb '19

22 Feb '19

Hello Werner Zeh, Aaron Durbin, Julius Werner, Patrick Rudolph, Paul Menzel, David Hendricks, build bot (Jenkins), Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29563 to look at the new patch set (#41). Change subject: security/tpm: Fix TCPA log feature ...................................................................... security/tpm: Fix TCPA log feature Until now the TCPA log wasn't working correctly. * Refactor TCPA log code. * Add TCPA log dump fucntion. * Make TCPA log available in bootblock. * Fix TCPA log formatting. * Add x86 and Cavium memory for early log. Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/arch/x86/car.ld M src/commonlib/include/commonlib/tcpa_log_serialized.h M src/include/memlayout.h M src/security/tpm/tspi.h M src/security/tpm/tspi/log.c M src/security/tpm/tspi/tspi.c M src/security/vboot/Kconfig M src/security/vboot/secdata_tpm.c M src/security/vboot/symbols.h M src/soc/cavium/cn81xx/include/soc/memlayout.ld M src/soc/imgtec/pistachio/include/soc/memlayout.ld M src/soc/mediatek/mt8173/include/soc/memlayout.ld M src/soc/mediatek/mt8183/include/soc/memlayout.ld M src/soc/nvidia/tegra124/include/soc/memlayout.ld M src/soc/nvidia/tegra210/include/soc/memlayout.ld M src/soc/samsung/exynos5250/include/soc/memlayout.ld M util/cbmem/cbmem.c 17 files changed, 175 insertions(+), 65 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/29563/41 -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 41 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: arch/arm64: Add PCI config support in romstage
by Patrick Rudolph (Code Review) 22 Feb '19

22 Feb '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31307 ) Change subject: arch/arm64: Add PCI config support in romstage ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cc3dc51764f24b986434080f480932dceb8d133 Gerrit-Change-Number: 31307 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 22 Feb 2019 11:14:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/arm64: Add PCI config support in romstage
by Patrick Rudolph (Code Review) 22 Feb '19

22 Feb '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31307 ) Change subject: arch/arm64: Add PCI config support in romstage ...................................................................... Patch Set 2: Tested on OpenCellular Elgon using I886f920e9941793fb76b56cc5a24a42e23b082e0 I18b1ede56795bf8c1f9476592291b8ea610eccd4 Works fine. -- To view, visit https://review.coreboot.org/c/coreboot/+/31307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cc3dc51764f24b986434080f480932dceb8d133 Gerrit-Change-Number: 31307 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 22 Feb 2019 11:13:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: vboot: fix STARTS_IN_BOOTBLOCK/_ROMSTAGE logic
by Joel Kitching (Code Review) 22 Feb '19

22 Feb '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31541 Change subject: vboot: fix STARTS_IN_BOOTBLOCK/_ROMSTAGE logic ...................................................................... vboot: fix STARTS_IN_BOOTBLOCK/_ROMSTAGE logic Fix up the logic of when to include VBOOT2_WORK symbols on x86, which are only needed when VBOOT_STARTS_IN_BOOTBLOCK is enabled. Also correct the value of the __PRE_RAM__ macro in the case that VBOOT_STARTS_IN_ROMSTAGE is selected. In this case, DRAM is already up and verstage should not be considered pre-ram. BUG=b:124141368, b:124192753 TEST=Build locally for eve TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x TEST=make clean && make test-abuild BRANCH=none Change-Id: Ie51e8f93b99ab230f3caeede2a33ec8b443e3d7a Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/arch/x86/car.ld M src/security/vboot/Makefile.inc 2 files changed, 10 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/31541/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 6fe8f14..2d835a3 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -26,9 +26,9 @@ . += 4096 * CONFIG_NUM_CAR_PAGE_TABLE_PAGES; _epagetables = . ; #endif - /* Vboot work buffer is completely volatile outside of verstage and - * romstage. Appropriate code needs to handle the transition. */ -#if IS_ENABLED(CONFIG_VBOOT_SEPARATE_VERSTAGE) + /* Vboot work buffer only needs to be available when verified boot + * starts in bootblock. */ +#if IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK) VBOOT2_WORK(., 16K) #endif /* Stack for CAR stages. Since it persists across all stages that diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 6c63f7b..0c32d94 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -22,7 +22,13 @@ verstage-y += bootmode.c postcar-y += bootmode.c -verstage-generic-ccopts += -D__PRE_RAM__ -D__VERSTAGE__ +# When VBOOT_STARTS_IN_ROMSTAGE is selected, DRAM is already up by +# the time verstage runs. +ifneq ($(CONFIG_VBOOT_STARTS_IN_ROMSTAGE),y) +verstage-generic-ccopts += -D__PRE_RAM__ +endif + +verstage-generic-ccopts += -D__VERSTAGE__ ramstage-y += gbb.c -- To view, visit https://review.coreboot.org/c/coreboot/+/31541 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie51e8f93b99ab230f3caeede2a33ec8b443e3d7a Gerrit-Change-Number: 31541 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: intelvbttool: Added support for reading vbt from sysfs
by Alex Feinman (Code Review) 22 Feb '19

22 Feb '19

Alex Feinman has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31531 Change subject: intelvbttool: Added support for reading vbt from sysfs ...................................................................... intelvbttool: Added support for reading vbt from sysfs VBT on intel systems is available via sysfs as /sys/kernel/debug/dri/0/i915_vbt However the size of this file reads as 0 causing intelvbttool to fail. This patch implements incremental reads with realloc for such cases. After this patch is applied, intelvbttool can be used as follows: sudo intelvbttool -f /sys/kernel/debug/dri/0/i915_vbt -d Change-Id: I5d17095a5747550b7115a54a7619b7294a846196 Signed-off-by: Alex Feinman <alexfeinman(a)hotmail.com> --- M util/intelvbttool/intelvbttool.c 1 file changed, 21 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/31531/1 diff --git a/util/intelvbttool/intelvbttool.c b/util/intelvbttool/intelvbttool.c index 1444129..2941b42 100644 --- a/util/intelvbttool/intelvbttool.c +++ b/util/intelvbttool/intelvbttool.c @@ -29,6 +29,7 @@ typedef uint16_t u16; typedef uint32_t u32; +#define DEF_ALLOC 1024 typedef struct { u16 signature; @@ -392,8 +393,8 @@ return NULL; } - const off_t size = ftell(fd); - if (size < 0 || size > SIZE_MAX) { + off_t read_size = ftell(fd); + if (read_size < 0 || read_size > SIZE_MAX) { printerr("%s tell failed: %s\n", filename, strerror(errno)); fclose(fd); return NULL; @@ -405,14 +406,29 @@ return NULL; } - struct fileobject *fo = malloc_fo(size); + if ( read_size == 0 ) + read_size = DEF_ALLOC; + + struct fileobject *fo = malloc_fo(read_size); if (!fo) { printerr("malloc failed\n"); fclose(fd); return NULL; } - if (fread(fo->data, 1, size, fd) != size) { + off_t bytes_read = 0, cb; + while((cb = fread(fo->data + bytes_read, 1, read_size, fd)) > 0) { + bytes_read += cb; + struct fileobject* newfo = remalloc_fo(fo, fo->size + read_size); + if (!newfo) { + fclose(fd); + free_fo(fo); + return NULL; + } + fo = newfo; + } + + if (!bytes_read) { fclose(fd); free_fo(fo); return NULL; @@ -424,7 +440,7 @@ return NULL; } - fo->size = size; + fo->size = bytes_read; return fo; } -- To view, visit https://review.coreboot.org/c/coreboot/+/31531 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d17095a5747550b7115a54a7619b7294a846196 Gerrit-Change-Number: 31531 Gerrit-PatchSet: 1 Gerrit-Owner: Alex Feinman <alexfeinman(a)hotmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/ocp/monolake: fix for booting issues + tmp and ipmi support
by Łukasz Siudut (Code Review) 22 Feb '19

22 Feb '19

Łukasz Siudut has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31435 Change subject: mb/ocp/monolake: fix for booting issues + tmp and ipmi support ...................................................................... mb/ocp/monolake: fix for booting issues + tmp and ipmi support This change brings monolake platform to sane state when it actually boots. First of all - we experienced booting issues during FSP-M phase. Applying fix that was introduced for wedge100s - 817994c1bec - helped and systems started to boot properly. Secondly, changes includes: - enabled TPM1 + added entry in devicetree - configured LPC IO to make IPMI work + added entry in devicetree - introduced DSDT and SMBIOS entries for IPMI to make it detectable Also I changed the length of SMBIOS type 38 entry. Subtracting 2 of it was effectively cutting information about register spacing, don't know why was it there on the first place. Signed-off-by: Lukasz Siudut <lsiudut(a)fb.com> Change-Id: Ibfbe9d19c7413098c56d1b6131640097fdf731ab --- M src/arch/x86/smbios.c M src/mainboard/ocp/monolake/Kconfig M src/mainboard/ocp/monolake/devicetree.cb M src/mainboard/ocp/monolake/dsdt.asl M src/mainboard/ocp/monolake/mainboard.c M src/mainboard/ocp/monolake/romstage.c 6 files changed, 172 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/31435/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index c0545ce..69be77d 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -642,7 +642,7 @@ memset(t, 0, sizeof(struct smbios_type38)); t->type = SMBIOS_IPMI_DEVICE_INFORMATION; t->handle = *handle; - t->length = len - 2; + t->length = len; t->interface_type = interface_type; t->ipmi_rev = ipmi_rev; t->i2c_slave_addr = i2c_addr; diff --git a/src/mainboard/ocp/monolake/Kconfig b/src/mainboard/ocp/monolake/Kconfig index 76ecb48..70b01c3 100644 --- a/src/mainboard/ocp/monolake/Kconfig +++ b/src/mainboard/ocp/monolake/Kconfig @@ -11,6 +11,8 @@ select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select SERIRQ_CONTINUOUS_MODE select MAINBOARD_USES_IFD_GBE_REGION + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 config MAINBOARD_DIR string diff --git a/src/mainboard/ocp/monolake/devicetree.cb b/src/mainboard/ocp/monolake/devicetree.cb index 30d99c2..2d91b73 100644 --- a/src/mainboard/ocp/monolake/devicetree.cb +++ b/src/mainboard/ocp/monolake/devicetree.cb @@ -7,7 +7,14 @@ device pci 14.0 on end # xHCI Controller device pci 19.0 on end # Gigabit LAN Controller device pci 1d.0 on end # EHCI Controller - device pci 1f.0 on end # LPC Bridge + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip drivers/generic/generic # BMC KCS + device pnp ca2.0 on end + end + end # LPC Bridge device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus Controller device pci 1f.5 on end # SATA Controller diff --git a/src/mainboard/ocp/monolake/dsdt.asl b/src/mainboard/ocp/monolake/dsdt.asl index 1248703..e59bb32 100644 --- a/src/mainboard/ocp/monolake/dsdt.asl +++ b/src/mainboard/ocp/monolake/dsdt.asl @@ -27,6 +27,9 @@ { #include "acpi/platform.asl" + Name (IDTP, 0x0CA2) + Name (ICDP, 0x0CA6) + Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 }) Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 }) @@ -290,5 +293,97 @@ } } + Scope (_SB.PCI0.LPC0) + { + Device(SPMI) + { + Name (_HID, EisaId ("IPI0001")) + Name (_STR, Unicode ("IPMI_KCS")) + Name (_UID, 0x00) + OperationRegion (IPST, SystemIO, ICDP, 0x01) + Field (IPST, ByteAcc, NoLock, Preserve) + { + STAS, 8 + } + Method (_STA, 0, NotSerialized) { + Return (0x0f) + } + Name (ICRS, ResourceTemplate () + { + IO (Decode16, + 0x0000, + 0x0000, + 0x00, + 0x00, + _Y01) + IO (Decode16, + 0x0000, + 0x0000, + 0x00, + 0x00, + _Y02) + + }) + Method (_CRS, 0, NotSerialized) + { + CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._MIN, IPDB) + CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._MAX, IPDH) + CreateByteField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._LEN, IPDL) + CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._MIN, IPCB) + CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._MAX, IPCH) + CreateByteField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._LEN, IPCL) + + IPDB = IDTP + IPDH = IDTP + IPDL = 0x01 + + IPCB = ICDP + IPCH = ICDP + IPCL = 0x01 + + Return (ICRS) + } + Method (_IFT, 0, NotSerialized) { + Return (0x01) + } + Method(_SRV, 0, NotSerialized) { + Return (0x0200) + } + } + + Device(SYSR) + { + Name (_HID, EisaId ("PNP0C02")) + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0CA2, + 0x0CA2, + 0x01, + 0x01, + ) + IO (Decode16, + 0x0CA6, + 0x0CA6, + 0x01, + 0x01, + ) + IO (Decode16, + 0x0CA8, + 0x0CA8, + 0x01, + 0x01, + ) + IO (Decode16, + 0x0CAC, + 0x0CAC, + 0x01, + 0x01, + ) + }) + } + } + #include "acpi/mainboard.asl" } diff --git a/src/mainboard/ocp/monolake/mainboard.c b/src/mainboard/ocp/monolake/mainboard.c index f1a3a20..eacb577 100644 --- a/src/mainboard/ocp/monolake/mainboard.c +++ b/src/mainboard/ocp/monolake/mainboard.c @@ -14,18 +14,56 @@ * GNU General Public License for more details. */ +#include <console/console.h> #include <device/device.h> +#include <smbios.h> + #if IS_ENABLED(CONFIG_VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif +#define BMC_KCS_BASE 0xca2 +#define INTERFACE_IS_IO 0x1 + +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) +static int mainboard_smbios_data(struct device *dev, int *handle, + unsigned long *current) +{ + int len = 0; + + // add IPMI Device Information + len += smbios_write_type38( + current, handle, + SMBIOS_BMC_INTERFACE_KCS, + 0x20, // IPMI Version + 0x20, // I2C address + 0xff, // no NV storage + BMC_KCS_BASE | INTERFACE_IS_IO, // IO port interface address + 0x40, + 0); // no IRQ + + return len; +} +#endif + +// static const unsigned char ipmi_command[] = {}; /* * mainboard_enable is executed as first thing after enumerate_buses(). * This is the earliest point to add customization. */ static void mainboard_enable(struct device *dev) { +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) + dev->ops->get_smbios_data = mainboard_smbios_data; +#endif + printk(BIOS_INFO, "mainboard_enable() called\n"); + /* Enable access to the BMC IPMI via KCS */ + struct device *lpc_sio_dev = dev_find_slot_pnp(BMC_KCS_BASE, 0); + struct resource *res = new_resource(lpc_sio_dev, BMC_KCS_BASE); + res->base = BMC_KCS_BASE; + res->size = 1; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/ocp/monolake/romstage.c b/src/mainboard/ocp/monolake/romstage.c index cf52c01..4784dff 100644 --- a/src/mainboard/ocp/monolake/romstage.c +++ b/src/mainboard/ocp/monolake/romstage.c @@ -17,6 +17,11 @@ #include <stddef.h> #include <soc/romstage.h> #include <drivers/intel/fsp1_0/fsp_util.h> +#include <cpu/x86/msr.h> +#include <cf9_reset.h> +#include <console/console.h> +#include <soc/pci_devs.h> +#include <soc/lpc.h> /** * /brief mainboard call for setup that needs to be done before fsp init @@ -24,7 +29,30 @@ */ void early_mainboard_romstage_entry(void) { + /* + * Sometimes the system boots in an invalid state, where random values + * have been written to MSRs and then the MSRs are locked. + * Seems to always happen on warm reset. + * + * Power cycling or a board_reset() isn't sufficient in this case, so + * issue a full_reset() to "fix" this issue. + */ + msr_t msr = rdmsr(IA32_FEATURE_CONTROL); + if (msr.lo & 1) { + console_init(); + printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n"); + full_reset(); + } + pci_write_config16(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_IO_DEC, 0x0010); + pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN1_DEC, + 0x0c0681); + pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN2_DEC, + 0x0c0ca1); + pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN3_DEC, + 0xfc0201); + pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN4_DEC, + 0xfc0601); } /** @@ -33,7 +61,6 @@ */ void late_mainboard_romstage_entry(void) { - } /** @@ -41,5 +68,4 @@ */ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) { - } -- To view, visit https://review.coreboot.org/c/coreboot/+/31435 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibfbe9d19c7413098c56d1b6131640097fdf731ab Gerrit-Change-Number: 31435 Gerrit-PatchSet: 1 Gerrit-Owner: Łukasz Siudut Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Add support for setting FSP-S PcieRpHotPlug fro...
by Jeremy Soller (Code Review) 22 Feb '19

22 Feb '19

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31535 Change subject: soc/intel/cannonlake: Add support for setting FSP-S PcieRpHotPlug from devicetree ...................................................................... soc/intel/cannonlake: Add support for setting FSP-S PcieRpHotPlug from devicetree Change-Id: I3aa8990a335e413628c016007ebabf7142aef80d --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/31535/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index cb9ad38..71e6f52 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -162,6 +162,8 @@ uint8_t PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS]; /* PCIe LTR(Latency Tolerance Reporting) mechanism */ uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; + /* Enable/Disable HotPlug support for Root Port */ + uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]; /* eMMC and SD */ uint8_t ScsEmmcHs400Enabled; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index c276c86..2107610 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -181,6 +181,8 @@ sizeof(config->PcieClkSrcClkReq)); memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, sizeof(config->PcieRpLtrEnable)); + memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, + sizeof(config->PcieRpHotPlug)); /* eMMC and SD */ dev = dev_find_slot(0, PCH_DEVFN_EMMC); -- To view, visit https://review.coreboot.org/c/coreboot/+/31535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3aa8990a335e413628c016007ebabf7142aef80d Gerrit-Change-Number: 31535 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Soller <jackpot51(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Add ASL function for setting pad mode
by Rizwan Qureshi (Code Review) 22 Feb '19

22 Feb '19

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31444 Change subject: soc/intel/cannonlake: Add ASL function for setting pad mode ...................................................................... soc/intel/cannonlake: Add ASL function for setting pad mode Add a funtion in gpio ASL library to set pad mode. BUG=b:123350329 Change-Id: I6c683f27ddffc3132001706d1694c71bb5664577 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/soc/intel/cannonlake/acpi/gpio_op.asl 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/31444/1 diff --git a/src/soc/intel/cannonlake/acpi/gpio_op.asl b/src/soc/intel/cannonlake/acpi/gpio_op.asl index 0618601..b051685 100644 --- a/src/soc/intel/cannonlake/acpi/gpio_op.asl +++ b/src/soc/intel/cannonlake/acpi/gpio_op.asl @@ -72,3 +72,24 @@ } And (Not (GPIOTXSTATE_MASK), VAL0, VAL0) } + +/* + * Set Pad mode + * Arg0 - GPIO Number + * Arg1 - Pad mode + * 0 = GPIO control pad + * 1 = Native Funtion 1 + * 2 = Native Funtion 2 + * 3 = Native Funtion 3 + */ +Method (GPMO, 2, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + TMP1, 10, + PADM, 2, + TMP2, 20, + } + Store(Arg1, PADM) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31444 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c683f27ddffc3132001706d1694c71bb5664577 Gerrit-Change-Number: 31444 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2019