coreboot-gerrit February 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: flapjack: get sku_id from ec (cbi)
by YH Lin (Code Review) 23 Feb '19

23 Feb '19

YH Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31586 ) Change subject: flapjack: get sku_id from ec (cbi) ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/31586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad7a52df38e2045abbdded8ba0a1f1544de961fc Gerrit-Change-Number: 31586 Gerrit-PatchSet: 1 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Comment-Date: Sat, 23 Feb 2019 03:28:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: ec/google/chromeec: fix the error status passing for cbi
by YH Lin (Code Review) 23 Feb '19

23 Feb '19

YH Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31585 ) Change subject: ec/google/chromeec: fix the error status passing for cbi ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/31585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f0a8a61d01d942cba57036a17dd527fdbbf940c Gerrit-Change-Number: 31585 Gerrit-PatchSet: 1 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Comment-Date: Sat, 23 Feb 2019 03:27:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: Revert "src/soc/intel/cannonlake: Add _DSM methods for LPIT table"
by Shaunak Saha (Code Review) 22 Feb '19

22 Feb '19

Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31584 ) Change subject: Revert "src/soc/intel/cannonlake: Add _DSM methods for LPIT table" ...................................................................... Patch Set 2: Code-Review-1 -- To view, visit https://review.coreboot.org/c/coreboot/+/31584 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I090e69e0a20a1cc209c82bae914e1640f7fce90e Gerrit-Change-Number: 31584 Gerrit-PatchSet: 2 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Comment-Date: Fri, 22 Feb 2019 22:57:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/arm64: Add PCI config support in romstage
by Kyösti Mälkki (Code Review) 22 Feb '19

22 Feb '19

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31307 ) Change subject: arch/arm64: Add PCI config support in romstage ...................................................................... arch/arm64: Add PCI config support in romstage Change-Id: I9cc3dc51764f24b986434080f480932dceb8d133 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/31307 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M src/arch/arm64/include/arch/pci_ops.h M src/include/rules.h 2 files changed, 2 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Patrick Rudolph: Looks good to me, approved diff --git a/src/arch/arm64/include/arch/pci_ops.h b/src/arch/arm64/include/arch/pci_ops.h index 0e6f52d..7a62d4a 100644 --- a/src/arch/arm64/include/arch/pci_ops.h +++ b/src/arch/arm64/include/arch/pci_ops.h @@ -16,16 +16,6 @@ #ifndef ARCH_ARM64_PCI_OPS_H #define ARCH_ARM64_PCI_OPS_H -#include <stdint.h> -#include <device/pci_type.h> - -#ifdef __SIMPLE_DEVICE__ -u8 pci_read_config8(pci_devfn_t dev, unsigned int where); -u16 pci_read_config16(pci_devfn_t dev, unsigned int where); -u32 pci_read_config32(pci_devfn_t dev, unsigned int where); -void pci_write_config8(pci_devfn_t dev, unsigned int where, u8 val); -void pci_write_config16(pci_devfn_t dev, unsigned int where, u16 val); -void pci_write_config32(pci_devfn_t dev, unsigned int where, u32 val); -#endif +#include <device/pci_mmio_cfg.h> #endif diff --git a/src/include/rules.h b/src/include/rules.h index deea50b..8fef534 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -266,11 +266,9 @@ * For ramstage individual source file may define __SIMPLE_DEVICE__ * before including any header files to force that particular source * be built with simple device model. - * - * For now only x86 is supported. */ -#if ENV_X86 && (defined(__PRE_RAM__) || ENV_SMM || ENV_POSTCAR) +#if (defined(__PRE_RAM__) || ENV_SMM || ENV_POSTCAR) #define __SIMPLE_DEVICE__ #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cc3dc51764f24b986434080f480932dceb8d133 Gerrit-Change-Number: 31307 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/google/hatch: Enable wake from trackpad
by Shelley Chen (Code Review) 22 Feb '19

22 Feb '19

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31533 Change subject: mb/google/hatch: Enable wake from trackpad ...................................................................... mb/google/hatch: Enable wake from trackpad For some reason, wake does not currently work from GPP_D21, but IRQs are working fine from that gpio. Thus, we have to switch IRQ to GPP_D21 and wake to GPP_A21, which was previously used for IRQs from the trackpad. Additionally, we need to use two gpios for irqs and wake source at the moment because of b:123967687, where FSP is locking down PCR and configuring ITSS. We need to configure the wake source gpio as inverted and the IRQ gpio as non-inverted until the bug is resolved. BUG=b:121212459 BRANCH=None TEST=run evtest with trackpad Use trackpad with ChromeOS UI and make sure it reacts as expected. Run powerd_dbus_suspend and press trackpad and make sure DUT wakes. Change-Id: I7b236136befc05c6586d9ba69185ed4b5d385273 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/gpio.c 2 files changed, 14 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/31533/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index eb528f2..690ce76 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -195,7 +195,8 @@ chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A21_IRQ)" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D21_IRQ)" + register "wake" = "GPE0_DW0_21" device i2c 15 on end end end # I2C #0 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index b87cfa8..b459560 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -27,8 +27,12 @@ PAD_CFG_GPO(GPP_A18, 1, DEEP), /* WWAN_RADIO_DISABLE_1V8_ODL */ PAD_CFG_GPO(GPP_A19, 1, DEEP), - /* TRACKPAD_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A21, NONE, PLTRST, LEVEL, INVERT), + /* + * TRACKPAD_INT_ODL (wake) + * TODO Combine into single gpio, when ITSS IPCx configuration + * is fixed in FSP. + */ + PAD_CFG_GPI_SCI(GPP_A21, NONE, DEEP, EDGE_SINGLE, INVERT), /* SRCCLKREQ1 */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* PCIE_14_WLAN_CLKREQ_ODL */ @@ -85,6 +89,12 @@ PAD_CFG_GPO(GPP_D15, 0, DEEP), /* TOUCHSCREEN_INT_L */ PAD_CFG_GPI_APIC(GPP_D16, NONE, DEEP, LEVEL, INVERT), + /* + * TRACKPAD_INT_ODL + * TODO Combine into single gpio with invert mode, when ITSS + * IPCx configuration is fixed in FSP. + */ + PAD_CFG_GPI_APIC(GPP_D21, NONE, PLTRST, LEVEL, NONE), /* SATAGP1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2), /* M2_SSD_PE_WAKE_ODL */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b236136befc05c6586d9ba69185ed4b5d385273 Gerrit-Change-Number: 31533 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/common: Include cometlake PCH IDs
by Furquan Shaikh (Code Review) 22 Feb '19

22 Feb '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31234 ) Change subject: soc/intel/common: Include cometlake PCH IDs ...................................................................... Patch Set 5: (2 comments) https://review.coreboot.org/#/c/31234/5/src/soc/intel/cannonlake/bootblock/… File src/soc/intel/cannonlake/bootblock/report_platform.c: https://review.coreboot.org/#/c/31234/5/src/soc/intel/cannonlake/bootblock/… PS5, Line 79: Premim Premium https://review.coreboot.org/#/c/31234/5/src/soc/intel/cannonlake/bootblock/… PS5, Line 80: Premim Premium -- To view, visit https://review.coreboot.org/c/coreboot/+/31234 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18dda48cee29213aa66c0ccddf3da31f0f489d2f Gerrit-Change-Number: 31234 Gerrit-PatchSet: 5 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 22 Feb 2019 18:23:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/common: Include cometlake SA IDs
by Furquan Shaikh (Code Review) 22 Feb '19

22 Feb '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31226 ) Change subject: soc/intel/common: Include cometlake SA IDs ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31226 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fbbab8a7797b36a9eacbd1c6a0644466f2fe6b1 Gerrit-Change-Number: 31226 Gerrit-PatchSet: 5 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 22 Feb 2019 18:21:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/common: Include cometlake CPU IDs
by Furquan Shaikh (Code Review) 22 Feb '19

22 Feb '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31143 ) Change subject: soc/intel/common: Include cometlake CPU IDs ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75d5b82524c9df1402abf6659d62dbc716c28c30 Gerrit-Change-Number: 31143 Gerrit-PatchSet: 6 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 22 Feb 2019 18:19:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: drivers/intel/fsp2_0: Update dependency of USE_FSP_REPO
by Furquan Shaikh (Code Review) 22 Feb '19

22 Feb '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31530 ) Change subject: drivers/intel/fsp2_0: Update dependency of USE_FSP_REPO ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31530 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e5d5a9fdf3f5d3e79922e97719e8491aa514cef Gerrit-Change-Number: 31530 Gerrit-PatchSet: 3 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 22 Feb 2019 18:14:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/x86/smbios(type4): Write processor_upgrade field
by HAOUAS Elyes (Code Review) 22 Feb '19

22 Feb '19

HAOUAS Elyes has restored this change. ( https://review.coreboot.org/c/coreboot/+/29529 ) Change subject: arch/x86/smbios(type4): Write processor_upgrade field ...................................................................... Restored socket information needed for SMBIOS type4 -- To view, visit https://review.coreboot.org/c/coreboot/+/29529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1bf5ac6c411720d349df8fd706015c6835758cd0 Gerrit-Change-Number: 29529 Gerrit-PatchSet: 12 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: restore

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coreboot-gerrit February 2019