coreboot-gerrit February 2019

coreboot-gerrit@coreboot.org

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1249 discussions

Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by Philipp Deppenwiese (Code Review) 23 Feb '19

23 Feb '19

Hello Werner Zeh, Aaron Durbin, Julius Werner, Patrick Rudolph, Paul Menzel, David Hendricks, build bot (Jenkins), Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29563 to look at the new patch set (#44). Change subject: security/tpm: Fix TCPA log feature ...................................................................... security/tpm: Fix TCPA log feature Until now the TCPA log wasn't working correctly. * Refactor TCPA log code. * Add TCPA log dump fucntion. * Make TCPA log available in bootblock. * Fix TCPA log formatting. * Add x86 and Cavium memory for early log. Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/arch/x86/car.ld M src/commonlib/include/commonlib/tcpa_log_serialized.h M src/include/memlayout.h M src/security/tpm/tspi.h M src/security/tpm/tspi/log.c M src/security/tpm/tspi/tspi.c M src/security/vboot/Kconfig M src/security/vboot/secdata_tpm.c M src/security/vboot/symbols.h M src/security/vboot/vboot_crtm.c M src/soc/cavium/cn81xx/include/soc/memlayout.ld M src/soc/imgtec/pistachio/include/soc/memlayout.ld M src/soc/mediatek/mt8173/include/soc/memlayout.ld M src/soc/mediatek/mt8183/include/soc/memlayout.ld M src/soc/nvidia/tegra124/include/soc/memlayout.ld M src/soc/nvidia/tegra210/include/soc/memlayout.ld M src/soc/samsung/exynos5250/include/soc/memlayout.ld M util/cbmem/cbmem.c 18 files changed, 210 insertions(+), 70 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/29563/44 -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 44 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: flapjack: get sku_id from ec (cbi)
by Nick Sanders (Code Review) 23 Feb '19

23 Feb '19

Nick Sanders has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31586 ) Change subject: flapjack: get sku_id from ec (cbi) ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/31586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad7a52df38e2045abbdded8ba0a1f1544de961fc Gerrit-Change-Number: 31586 Gerrit-PatchSet: 1 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Nick Sanders <nsanders(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 23 Feb 2019 18:41:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/x86/smbios.c: Remove duplicated 'processor_upgrade'
by Elyes HAOUAS (Code Review) 23 Feb '19

23 Feb '19

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31555 Change subject: arch/x86/smbios.c: Remove duplicated 'processor_upgrade' ...................................................................... arch/x86/smbios.c: Remove duplicated 'processor_upgrade' Change-Id: I3500a648631c91f3a0812c7e661440743ed6a1e1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/smbios.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/31555/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 1f03bc9..d23b5a0 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -560,7 +560,6 @@ t->processor_version = smbios_processor_name(t->eos); t->processor_family = (res.eax > 0) ? 0x0c : 0x6; t->processor_type = 3; /* System Processor */ - t->processor_upgrade = 0x06; t->core_count2 = (res.ebx >> 16) & 0xffff; if (core_count2 >= 0xff) t->core_count = 0xff; -- To view, visit https://review.coreboot.org/c/coreboot/+/31555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3500a648631c91f3a0812c7e661440743ed6a1e1 Gerrit-Change-Number: 31555 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/intel/fsp2_0: Update dependency of USE_FSP_REPO
by Philipp Deppenwiese (Code Review) 23 Feb '19

23 Feb '19

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31530 ) Change subject: drivers/intel/fsp2_0: Update dependency of USE_FSP_REPO ...................................................................... drivers/intel/fsp2_0: Update dependency of USE_FSP_REPO USE_FSP_REPO used to rely on SOC_INTEL_COMMON_CANNONLAKE_BASE which was getting selected for cometlake soc also. Since FSP is not yet upstreamed for cometlake, compilation was failing due to FSP was not found. So limiting USE_FSP_REPO option to coffeelake and whiskeylake soc only and excluding for cometlake. Change-Id: I5e5d5a9fdf3f5d3e79922e97719e8491aa514cef Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Reviewed-on: https://review.coreboot.org/c/31530 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/drivers/intel/fsp2_0/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Furquan Shaikh: Looks good to me, approved Subrata Banik: Looks good to me, approved Aamir Bohra: Looks good to me, approved diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 60fed37..8e64c6b 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -85,7 +85,8 @@ bool "Use the IntelFSP based binaries" depends on ADD_FSP_BINARIES depends on SOC_INTEL_APOLLOLAKE || SOC_INTEL_SKYLAKE || \ - SOC_INTEL_KABYLAKE || SOC_INTEL_COMMON_CANNONLAKE_BASE + SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE || \ + SOC_INTEL_WHISKEYLAKE help When selecting this option, the SoC must set FSP_HEADER_PATH and FSP_FD_PATH correctly so FSP splitting works. -- To view, visit https://review.coreboot.org/c/coreboot/+/31530 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e5d5a9fdf3f5d3e79922e97719e8491aa514cef Gerrit-Change-Number: 31530 Gerrit-PatchSet: 4 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: northbridge/intel/pineview: Add remaining boilerplate code for northb...
by HAOUAS Elyes (Code Review) 23 Feb '19

23 Feb '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/12430 ) Change subject: northbridge/intel/pineview: Add remaining boilerplate code for northbridge ...................................................................... Patch Set 18: (8 comments) https://review.coreboot.org/#/c/12430/18/src/northbridge/intel/pineview/ear… File src/northbridge/intel/pineview/early_init.c: https://review.coreboot.org/#/c/12430/18/src/northbridge/intel/pineview/ear… PS18, Line 66: reg32 = MCHBAR32(0x30); : MCHBAR32(0x30) = 0x21800; Do we need to read this register before writing on it ? https://review.coreboot.org/#/c/12430/18/src/northbridge/intel/pineview/ear… PS18, Line 73: reg16 not used? do we need to read it? https://review.coreboot.org/#/c/12430/18/src/northbridge/intel/pineview/ear… PS18, Line 75: reg16 not used. maybe we need to read this ? https://review.coreboot.org/#/c/12430/18/src/northbridge/intel/pineview/ear… PS18, Line 77: reg16 not used https://review.coreboot.org/#/c/12430/18/src/northbridge/intel/pineview/ear… PS18, Line 80: reg8 not used? https://review.coreboot.org/#/c/12430/18/src/northbridge/intel/pineview/ear… PS18, Line 81: reg16 = MCHBAR16(0xc8c); : MCHBAR16(0xc8c) = reg16 | 0x0200; why don't we use MCHBAR16(0xc8c) |= 0x0200 ? https://review.coreboot.org/#/c/12430/18/src/northbridge/intel/pineview/ear… PS18, Line 83: reg8 = MCHBAR8(0xc8c); : MCHBAR8(0xc8c) = reg8; : MCHBAR8(0xc8c) = 0x12; why please ? https://review.coreboot.org/#/c/12430/18/src/northbridge/intel/pineview/ear… PS18, Line 98: eg32 = MCHBAR32(0x40); : MCHBAR32(0x40) = 0x0; : reg32 = MCHBAR32(0x40); : MCHBAR32(0x40) = 0x8; do we need to read before write some thing ? -- To view, visit https://review.coreboot.org/c/coreboot/+/12430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3fb8146ef7fe2ad27c167ecd2fb0fd629f051cc1 Gerrit-Change-Number: 12430 Gerrit-PatchSet: 18 Gerrit-Owner: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sat, 23 Feb 2019 11:05:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: drivers/intel/fsp2_0: Update dependency of USE_FSP_REPO
by Nico Huber (Code Review) 23 Feb '19

23 Feb '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31530 ) Change subject: drivers/intel/fsp2_0: Update dependency of USE_FSP_REPO ...................................................................... Patch Set 3: Code-Review+1 I agree to the change, but just realized that the description of SOC_INTEL_COMMON_CANNONLAKE_BASE doesn't make much sense any more, does it? -- To view, visit https://review.coreboot.org/c/coreboot/+/31530 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e5d5a9fdf3f5d3e79922e97719e8491aa514cef Gerrit-Change-Number: 31530 Gerrit-PatchSet: 3 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 23 Feb 2019 10:46:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: vendorcode/intel/fsp/fsp2_0/cml: Add FSP header files for Cometlake
by Nico Huber (Code Review) 23 Feb '19

23 Feb '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31529 ) Change subject: vendorcode/intel/fsp/fsp2_0/cml: Add FSP header files for Cometlake ...................................................................... Patch Set 3: Code-Review-1 (2 comments) I somehow doubt that this was really reviewed. https://review.coreboot.org/#/c/31529/3/src/vendorcode/intel/fsp/fsp2_0/com… File src/vendorcode/intel/fsp/fsp2_0/cometlake/FspUpd.h: https://review.coreboot.org/#/c/31529/3/src/vendorcode/intel/fsp/fsp2_0/com… PS3, Line 3: Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> The date is wrong. It should reflect the date when the contents were written. Obviously not in 2019 as we had this file already last year. If the date is wrong the whole copyright line is void, AFAIK. (not that I'd assume that copyright applies to this file anyway) https://review.coreboot.org/#/c/31529/3/src/vendorcode/intel/fsp/fsp2_0/com… PS3, Line 40: #define FSPT_UPD_SIGNATURE 0x545F4450554C4643 /* 'CFLUPD_T' */ Same signatures as for Coffee Lake? I was told by somebody @intel that the UPD structs should stay backwards compatible... these are really not. -- To view, visit https://review.coreboot.org/c/coreboot/+/31529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I734316445dda5b1feb4098ce3c58b6dd8ce2d272 Gerrit-Change-Number: 31529 Gerrit-PatchSet: 3 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 23 Feb 2019 10:43:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: ec/google/chromeec: fix the error status passing for cbi
by Paul Menzel (Code Review) 23 Feb '19

23 Feb '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31585 ) Change subject: ec/google/chromeec: fix the error status passing for cbi ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/31585/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/31585/1//COMMIT_MSG@8 PS1, Line 8: : google_chromeec_command() can return non-zero number (both positive : and negative) to indicate error. That should be fixed instead, shouldn’t it? The convention is, that errors are negative? -- To view, visit https://review.coreboot.org/c/coreboot/+/31585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f0a8a61d01d942cba57036a17dd527fdbbf940c Gerrit-Change-Number: 31585 Gerrit-PatchSet: 1 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 23 Feb 2019 09:23:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: Revert "src/soc/intel/cannonlake: Add _DSM methods for LPIT table"
by Paul Menzel (Code Review) 23 Feb '19

23 Feb '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31584 ) Change subject: Revert "src/soc/intel/cannonlake: Add _DSM methods for LPIT table" ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/#/c/31584/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/31584/2//COMMIT_MSG@9 PS2, Line 9: This reverts commit 5620b105461cc18cf1439f02013153237f372b4b. Please add a blank line below. https://review.coreboot.org/#/c/31584/2//COMMIT_MSG@11 PS2, Line 11: One space. -- To view, visit https://review.coreboot.org/c/coreboot/+/31584 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I090e69e0a20a1cc209c82bae914e1640f7fce90e Gerrit-Change-Number: 31584 Gerrit-PatchSet: 2 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 23 Feb 2019 09:07:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Make few more whitespace proper in MCH name
by Subrata Banik (Code Review) 23 Feb '19

23 Feb '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31563 Change subject: soc/intel/cannonlake: Make few more whitespace proper in MCH name ...................................................................... soc/intel/cannonlake: Make few more whitespace proper in MCH name CB:31547 fixes few whitespace error. Here is few more whitespace clean up. Change-Id: I69c12a5da4feb48b2bc23874332ab341a559f6e6 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/bootblock/report_platform.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/31563/1 diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index b8b467f..0b87615 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -48,7 +48,7 @@ } mch_table[] = { { PCI_DEVICE_ID_INTEL_CNL_ID_U, "Cannonlake-U" }, { PCI_DEVICE_ID_INTEL_CNL_ID_Y, "Cannonlake-Y" }, - { PCI_DEVICE_ID_INTEL_CFL_ID_U, "Coffeelake U (4+3e)"}, + { PCI_DEVICE_ID_INTEL_CFL_ID_U, "Coffeelake U (4+3e)" }, { PCI_DEVICE_ID_INTEL_WHL_ID_Wx4, "Whiskeylake W (4+2)" }, { PCI_DEVICE_ID_INTEL_WHL_ID_Wx2, "Whiskeylake W (2+2)" }, { PCI_DEVICE_ID_INTEL_CFL_ID_H, "Coffeelake-H" }, -- To view, visit https://review.coreboot.org/c/coreboot/+/31563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69c12a5da4feb48b2bc23874332ab341a559f6e6 Gerrit-Change-Number: 31563 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2019