coreboot-gerrit February 2019

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Change in ...coreboot[master]: soc/cavium/common: Make ecam0_get_bar_val common
by Patrick Rudolph (Code Review) 25 Feb '19

25 Feb '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31566 Change subject: soc/cavium/common: Make ecam0_get_bar_val common ...................................................................... soc/cavium/common: Make ecam0_get_bar_val common Move ecam0_get_bar_val into the common folder and make it public. Compile it for romstage and ramstage. To be used by romstage PCI code. Tested on OpenCellular Elgon. Change-Id: I18b1ede56795bf8c1f9476592291b8ea610eccd4 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/cavium/cn81xx/ecam0.c M src/soc/cavium/common/Makefile.inc A src/soc/cavium/common/ecam.c A src/soc/cavium/common/include/soc/ecam.h 4 files changed, 108 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/31566/1 diff --git a/src/soc/cavium/cn81xx/ecam0.c b/src/soc/cavium/cn81xx/ecam0.c index 6747fa6..0ce0c8f 100644 --- a/src/soc/cavium/cn81xx/ecam0.c +++ b/src/soc/cavium/cn81xx/ecam0.c @@ -22,6 +22,7 @@ #include <device/pci_ops.h> #include <soc/addressmap.h> #include <soc/cavium/common/pci/chip.h> +#include <soc/ecam.h> #include <assert.h> #define CAVM_PCCPF_XXX_VSEC_CTL 0x108 @@ -137,50 +138,6 @@ } /** - * Get PCI BAR address from cavium specific extended capability. - * Use regular BAR if not found in extended capability space. - * - * @return The pyhsical address of the BAR, zero on error - */ -static uint64_t get_bar_val(struct device *dev, u8 bar) -{ - size_t cap_offset = pci_find_capability(dev, 0x14); - uint64_t h, l, ret = 0; - if (cap_offset) { - /* Found EA */ - u8 es, bei; - u8 ne = pci_read_config8(dev, cap_offset + 2) & 0x3f; - - cap_offset += 4; - while (ne) { - uint32_t dw0 = pci_read_config32(dev, cap_offset); - - es = dw0 & 7; - bei = (dw0 >> 4) & 0xf; - if (bei == bar) { - h = 0; - l = pci_read_config32(dev, cap_offset + 4); - if (l & 2) - h = pci_read_config32(dev, - cap_offset + 12); - ret = (h << 32) | (l & ~0xfull); - break; - } - cap_offset += (es + 1) * 4; - ne--; - } - } else { - h = 0; - l = pci_read_config32(dev, bar * 4 + PCI_BASE_ADDRESS_0); - if (l & 4) - h = pci_read_config32(dev, bar * 4 + PCI_BASE_ADDRESS_0 - + 4); - ret = (h << 32) | (l & ~0xfull); - } - return ret; -} - -/** * pci_enable_msix - configure device's MSI-X capability structure * @dev: pointer to the pci_dev data structure of MSI-X device function * @entries: pointer to an array of MSI-X entries @@ -237,7 +194,7 @@ dev_path(dev)); return -1; } - bar = get_bar_val(dev, bar_idx); + bar = ecam0_get_bar_val(dev, bar_idx); if (!bar) { printk(BIOS_ERR, "ERROR: %s: Failed to find MSI-X bar\n", dev_path(dev)); diff --git a/src/soc/cavium/common/Makefile.inc b/src/soc/cavium/common/Makefile.inc index ecde220..96e38c3 100644 --- a/src/soc/cavium/common/Makefile.inc +++ b/src/soc/cavium/common/Makefile.inc @@ -25,11 +25,13 @@ # romstage romstage-y += bdk-coreboot.c +romstage-y += ecam.c ################################################################################ # ramstage ramstage-y += bdk-coreboot.c +ramstage-y += ecam.c CPPFLAGS_common += -Isrc/soc/cavium/common/include diff --git a/src/soc/cavium/common/ecam.c b/src/soc/cavium/common/ecam.c new file mode 100644 index 0000000..af93a8a --- /dev/null +++ b/src/soc/cavium/common/ecam.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Facebook, Inc. + * Copyright 2003-2017 Cavium Inc. <support(a)cavium.com> + * Copyright 2019 9elements Agency GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0. + */ + +#include <arch/io.h> +#include <device/pci_ops.h> +#include <device/pci_def.h> +#include <device/pci.h> +#include <soc/addressmap.h> +#include <soc/ecam.h> +#include <assert.h> + +/** + * Get PCI BAR address from cavium specific extended capability. + * Use regular BAR if not found in extended capability space. + * + * @return The pyhsical address of the BAR, zero on error + */ +#ifdef __SIMPLE_DEVICE__ +uint64_t ecam0_get_bar_val(pci_devfn_t dev, u8 bar) +#else +uint64_t ecam0_get_bar_val(struct device *dev, u8 bar) +#endif +{ + size_t cap_offset = pci_find_capability(dev, 0x14); + uint64_t h, l, ret = 0; + if (cap_offset) { + /* Found EA */ + u8 es, bei; + u8 ne = pci_read_config8(dev, cap_offset + 2) & 0x3f; + + cap_offset += 4; + while (ne) { + uint32_t dw0 = pci_read_config32(dev, cap_offset); + + es = dw0 & 7; + bei = (dw0 >> 4) & 0xf; + if (bei == bar) { + h = 0; + l = pci_read_config32(dev, cap_offset + 4); + if (l & 2) + h = pci_read_config32(dev, + cap_offset + 12); + ret = (h << 32) | (l & ~0xfull); + break; + } + cap_offset += (es + 1) * 4; + ne--; + } + } else { + h = 0; + l = pci_read_config32(dev, bar * 4 + PCI_BASE_ADDRESS_0); + if (l & 4) + h = pci_read_config32(dev, bar * 4 + PCI_BASE_ADDRESS_0 + + 4); + ret = (h << 32) | (l & ~0xfull); + } + return ret; +} diff --git a/src/soc/cavium/common/include/soc/ecam.h b/src/soc/cavium/common/include/soc/ecam.h new file mode 100644 index 0000000..16e3d27 --- /dev/null +++ b/src/soc/cavium/common/include/soc/ecam.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018-present Facebook, Inc. + * Copyright 2019 9elements Agency GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __COREBOOT_SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_ECAM_H +#define __COREBOOT_SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_ECAM_H + +#ifdef __SIMPLE_DEVICE__ +#include <device/pci_type.h> + +uint64_t ecam0_get_bar_val(pci_devfn_t dev, u8 bar); +#else +#include <device/device.h> + +uint64_t ecam0_get_bar_val(struct device *dev, u8 bar); +#endif + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18b1ede56795bf8c1f9476592291b8ea610eccd4 Gerrit-Change-Number: 31566 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: gizmosphere/gizmo2:(faile test)
by HAOUAS Elyes (Code Review) 25 Feb '19

25 Feb '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31554 Change subject: gizmosphere/gizmo2:(faile test) ...................................................................... gizmosphere/gizmo2:(faile test) why gizmo2 failed when using IASL v 20190215? https://qa.coreboot.org/job/coreboot-toolchain/532/testReport/(root)/board/… Change-Id: I1e4ca2c765083db3a27e415d3a69bef0912a606b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/gizmosphere/gizmo2/acpi/superio.asl 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/31554/1 diff --git a/src/mainboard/gizmosphere/gizmo2/acpi/superio.asl b/src/mainboard/gizmosphere/gizmo2/acpi/superio.asl index e69de29..0043c3b 100644 --- a/src/mainboard/gizmosphere/gizmo2/acpi/superio.asl +++ b/src/mainboard/gizmosphere/gizmo2/acpi/superio.asl @@ -0,0 +1 @@ +/* test */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e4ca2c765083db3a27e415d3a69bef0912a606b Gerrit-Change-Number: 31554 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 12

Change in ...coreboot[master]: ec/google/wilco: Fix ACPI power status events
by Duncan Laurie (Code Review) 25 Feb '19

25 Feb '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31560 Change subject: ec/google/wilco: Fix ACPI power status events ...................................................................... ec/google/wilco: Fix ACPI power status events This change fixes the power status events for AC and battery events from the EC. The register that was being used is not returning the expected information. BUG=b:125472740 TEST=enable ACPI debug in the kernel and verify that AC and battery insert/remove are detected properly. Change-Id: I15f71fcf0ca6aa9438e951865787c9fc273792d8 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/ec/google/wilco/acpi/ec.asl M src/ec/google/wilco/acpi/ec_ram.asl M src/ec/google/wilco/acpi/event.asl 3 files changed, 7 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/31560/1 diff --git a/src/ec/google/wilco/acpi/ec.asl b/src/ec/google/wilco/acpi/ec.asl index 5aca187..675ee37 100644 --- a/src/ec/google/wilco/acpi/ec.asl +++ b/src/ec/google/wilco/acpi/ec.asl @@ -42,7 +42,7 @@ EREG = Arg1 /* Store initial value for power status */ - ECPR = R (APWR) + ECPR = R (PWSR) /* Indicate to EC that OS is ready for queries */ W (ERDY, Arg1) diff --git a/src/ec/google/wilco/acpi/ec_ram.asl b/src/ec/google/wilco/acpi/ec_ram.asl index 1c030af..b7cfefa 100644 --- a/src/ec/google/wilco/acpi/ec_ram.asl +++ b/src/ec/google/wilco/acpi/ec_ram.asl @@ -53,6 +53,7 @@ Name (P6ST, Package () { 0x05, 0xff, RD }) /* PmSt6 */ Name (P6AC, Package () { 0x05, 0x08, RD }) /* PmSt6_AC_UPDATE */ +Name (PWSR, Package () { 0x06, 0xff, RD }) /* POWER_SOURCE */ Name (ACEX, Package () { 0x06, 0x01, RD }) /* AC Present */ Name (BTEX, Package () { 0x06, 0x02, RD }) /* Battery Present */ Name (BTSC, Package () { 0x06, 0x04, RD }) /* Battery Status Changed */ @@ -122,11 +123,6 @@ Name (BCCY, Package () { 0x3e, 0xffff, RD }) /* BCACHE: Cycle Count */ -Name (APWR, Package () { 0x47, 0xff, RD }) /* POWER: Full Status */ -Name (APAC, Package () { 0x47, 0x01, RD }) /* POWER: AC */ -Name (APB1, Package () { 0x47, 0x02, RD }) /* POWER: Main Battery */ -Name (APC1, Package () { 0x47, 0x04, RD }) /* POWER: Main Batt Status */ - /* * EC RAM WRITE */ diff --git a/src/ec/google/wilco/acpi/event.asl b/src/ec/google/wilco/acpi/event.asl index 24cf268..fab4fc4 100644 --- a/src/ec/google/wilco/acpi/event.asl +++ b/src/ec/google/wilco/acpi/event.asl @@ -19,17 +19,17 @@ Method (ECQP, 0, Serialized) { - Local0 = R (APWR) + Local0 = R (PWSR) Local1 = Local0 ^ ECPR ECPR = Local0 - If (EBIT (APAC, Local1)) { + If (EBIT (ACEX, Local1)) { Printf ("AC Power Status Changed") Notify (AC, 0x80) } - If (EBIT (APB1, Local1)) { - If (EBIT (APB1, Local0)) { + If (EBIT (BTEX, Local1)) { + If (EBIT (BTEX, Local0)) { Printf ("BAT0 Inserted") Notify (BAT0, 0x81) } Else { @@ -39,7 +39,7 @@ } } - If (EBIT (APC1, Local1)) { + If (EBIT (BTSC, Local1)) { Printf ("BAT0 Status Change") Notify (BAT0, 0x80) } -- To view, visit https://review.coreboot.org/c/coreboot/+/31560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15f71fcf0ca6aa9438e951865787c9fc273792d8 Gerrit-Change-Number: 31560 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: AGESA vendorcode: Define libagesa rule just once
by Kyösti Mälkki (Code Review) 25 Feb '19

25 Feb '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31509 Change subject: AGESA vendorcode: Define libagesa rule just once ...................................................................... AGESA vendorcode: Define libagesa rule just once No reason to keep this rule in per-family directory. Change-Id: I6bfc9a277674077774c4cb398f8add5e4fa99c69 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/vendorcode/amd/agesa/Makefile.inc M src/vendorcode/amd/agesa/f12/Makefile.inc M src/vendorcode/amd/agesa/f14/Makefile.inc M src/vendorcode/amd/agesa/f15tn/Makefile.inc M src/vendorcode/amd/agesa/f16kb/Makefile.inc 5 files changed, 7 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/31509/1 diff --git a/src/vendorcode/amd/agesa/Makefile.inc b/src/vendorcode/amd/agesa/Makefile.inc index 24110a7..df34330 100644 --- a/src/vendorcode/amd/agesa/Makefile.inc +++ b/src/vendorcode/amd/agesa/Makefile.inc @@ -18,6 +18,13 @@ $(eval $(call create_class_compiler,libagesa,x86_64)) endif +$(obj)/libagesa.a: $$(libagesa-objs) + @printf " AGESA $(subst $(obj)/,,$(@))\n" + $(AR_libagesa) rcsDT $@ $+ + +romstage-libs += $(obj)/libagesa.a +ramstage-libs += $(obj)/libagesa.a + # buildOpts should be in libagesa $(obj)/romstage/mainboard/$(MAINBOARDDIR)/buildOpts.o: CPPFLAGS_x86_32 += $(BUILDOPTS_INCLUDES) $(obj)/ramstage/mainboard/$(MAINBOARDDIR)/buildOpts.o: CPPFLAGS_x86_32 += $(BUILDOPTS_INCLUDES) diff --git a/src/vendorcode/amd/agesa/f12/Makefile.inc b/src/vendorcode/amd/agesa/f12/Makefile.inc index 8cc73a8..f925ccb 100644 --- a/src/vendorcode/amd/agesa/f12/Makefile.inc +++ b/src/vendorcode/amd/agesa/f12/Makefile.inc @@ -55,10 +55,3 @@ subdirs-y += Legacy/Proc subdirs-y += $(dir $(shell cd $(dir); find Proc -name Makefile.inc)) - -$(obj)/libagesa.fam12.a: $$(libagesa-objs) - @printf " AGESA $(subst $(obj)/,,$(@))\n" - $(AR_libagesa) rcsDT $@ $+ - -romstage-libs += $(obj)/libagesa.fam12.a -ramstage-libs += $(obj)/libagesa.fam12.a diff --git a/src/vendorcode/amd/agesa/f14/Makefile.inc b/src/vendorcode/amd/agesa/f14/Makefile.inc index bfe5d74..ad2d2dc 100644 --- a/src/vendorcode/amd/agesa/f14/Makefile.inc +++ b/src/vendorcode/amd/agesa/f14/Makefile.inc @@ -56,10 +56,3 @@ subdirs-y += Legacy/Proc subdirs-y += $(dir $(shell cd $(dir); find Proc -name Makefile.inc)) - -$(obj)/libagesa.fam14.a: $$(libagesa-objs) - @printf " AGESA $(subst $(obj)/,,$(@))\n" - $(AR_libagesa) rcsDT $@ $+ - -romstage-libs += $(obj)/libagesa.fam14.a -ramstage-libs += $(obj)/libagesa.fam14.a diff --git a/src/vendorcode/amd/agesa/f15tn/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Makefile.inc index f33c7b8..57350d9 100644 --- a/src/vendorcode/amd/agesa/f15tn/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15tn/Makefile.inc @@ -60,10 +60,3 @@ subdirs-y += Legacy/Proc subdirs-y += $(dir $(shell cd $(dir); find Proc -name Makefile.inc)) - -$(obj)/libagesa.fam15tn.a: $$(libagesa-objs) - @printf " AGESA $(subst $(obj)/,,$(@))\n" - $(AR_libagesa) rcsDT $@ $+ - -romstage-libs += $(obj)/libagesa.fam15tn.a -ramstage-libs += $(obj)/libagesa.fam15tn.a diff --git a/src/vendorcode/amd/agesa/f16kb/Makefile.inc b/src/vendorcode/amd/agesa/f16kb/Makefile.inc index 11b67ed..3115c4d 100644 --- a/src/vendorcode/amd/agesa/f16kb/Makefile.inc +++ b/src/vendorcode/amd/agesa/f16kb/Makefile.inc @@ -60,10 +60,3 @@ subdirs-y += Legacy/Proc subdirs-y += $(dir $(shell cd $(dir); find Proc -name Makefile.inc)) - -$(obj)/libagesa.fam16kb.a: $$(libagesa-objs) - @printf " AGESA $(subst $(obj)/,,$(@))\n" - $(AR_libagesa) rcsDT $@ $+ - -romstage-libs += $(obj)/libagesa.fam16kb.a -ramstage-libs += $(obj)/libagesa.fam16kb.a -- To view, visit https://review.coreboot.org/c/coreboot/+/31509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6bfc9a277674077774c4cb398f8add5e4fa99c69 Gerrit-Change-Number: 31509 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: soc/amd/common: Fix AmdLateRunApTask()
by Patrick Georgi (Code Review) 25 Feb '19

25 Feb '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/27277 ) Change subject: soc/amd/common: Fix AmdLateRunApTask() ...................................................................... soc/amd/common: Fix AmdLateRunApTask() Third parameter ConfigPtr of the callout is of type AP_EXE_PARAMS and needs to be passed back to AGESA with AmdLateRunApTask() call. Change-Id: I1dad64b955b53bd19363737665235f95aa3d451e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/27277 Reviewed-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/include/amdblocks/agesawrapper.h M src/soc/amd/common/block/pi/agesawrapper.c M src/soc/amd/common/block/pi/def_callouts.c 3 files changed, 6 insertions(+), 26 deletions(-) Approvals: build bot (Jenkins): Verified Richard Spiegel: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h index 43bd8de..2f3b8a6 100644 --- a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h +++ b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h @@ -34,6 +34,8 @@ /* Return current dispatcher or NULL on error. */ MODULE_ENTRY agesa_get_dispatcher(void); +AGESA_STATUS amd_late_run_ap_task(AP_EXE_PARAMS *ApExeParams); + AGESA_STATUS agesawrapper_amdinitreset(void); AGESA_STATUS agesawrapper_amdinitearly(void); AGESA_STATUS agesawrapper_amdinitenv(void); @@ -41,8 +43,6 @@ AGESA_STATUS agesawrapper_amdinitpost(void); AGESA_STATUS agesawrapper_amdinitmid(void); void *agesawrapper_getlateinitptr(int pick); -AGESA_STATUS agesawrapper_amdlaterunaptask(uint32_t Func, uintptr_t Data, - void *ConfigPtr); AGESA_STATUS agesawrapper_amdinitrtb(void); AGESA_STATUS agesawrapper_amdinitresume(void); AGESA_STATUS agesawrapper_amds3laterestore(void); diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 92153ee..fc69b46 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -353,28 +353,9 @@ return Status; } -AGESA_STATUS agesawrapper_amdlaterunaptask(uint32_t Func, uintptr_t Data, - void *ConfigPtr) +AGESA_STATUS amd_late_run_ap_task(AP_EXE_PARAMS *ApExeParams) { - AGESA_STATUS Status; - AP_EXE_PARAMS ApExeParams; - - memset(&ApExeParams, 0, sizeof(ApExeParams)); - - ApExeParams.StdHeader.AltImageBasePtr = 0; - ApExeParams.StdHeader.CalloutPtr = &GetBiosCallout; - ApExeParams.StdHeader.Func = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; - ApExeParams.FunctionNumber = Func; - ApExeParams.RelatedDataBlock = ConfigPtr; - - Status = AmdLateRunApTask(&ApExeParams); - if (Status != AGESA_SUCCESS) { - /* agesawrapper_readeventlog(); */ - ASSERT(Status == AGESA_SUCCESS); - } - - return Status; + return AmdLateRunApTask(ApExeParams); } AGESA_STATUS agesawrapper_amdinitrtb(void) diff --git a/src/soc/amd/common/block/pi/def_callouts.c b/src/soc/amd/common/block/pi/def_callouts.c index 693c7c5..0b119b7 100644 --- a/src/soc/amd/common/block/pi/def_callouts.c +++ b/src/soc/amd/common/block/pi/def_callouts.c @@ -186,7 +186,7 @@ static struct agesa_data { uint32_t Func; uintptr_t Data; - void *ConfigPtr; + AP_EXE_PARAMS *ConfigPtr; } agesadata; /* @@ -205,8 +205,7 @@ (agesadata.Data == lapicid()))) return; - Status = agesawrapper_amdlaterunaptask(agesadata.Func, agesadata.Data, - agesadata.ConfigPtr); + Status = amd_late_run_ap_task(agesadata.ConfigPtr); if (Status) printk(BIOS_DEBUG, "There was a problem with %lx returned %s\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/27277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1dad64b955b53bd19363737665235f95aa3d451e Gerrit-Change-Number: 27277 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: soc/intel/common: Include cometlake PCH IDs
by Ronak Kanabar (Code Review) 25 Feb '19

25 Feb '19

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31234 ) Change subject: soc/intel/common: Include cometlake PCH IDs ...................................................................... Patch Set 8: (2 comments) https://review.coreboot.org/#/c/31234/5/src/soc/intel/cannonlake/bootblock/… File src/soc/intel/cannonlake/bootblock/report_platform.c: https://review.coreboot.org/#/c/31234/5/src/soc/intel/cannonlake/bootblock/… PS5, Line 79: Premim > Premium done https://review.coreboot.org/#/c/31234/5/src/soc/intel/cannonlake/bootblock/… PS5, Line 80: Premim > Premium done -- To view, visit https://review.coreboot.org/c/coreboot/+/31234 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18dda48cee29213aa66c0ccddf3da31f0f489d2f Gerrit-Change-Number: 31234 Gerrit-PatchSet: 8 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Feb 2019 08:03:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/common: Include cometlake PCH IDs
by Ronak Kanabar (Code Review) 25 Feb '19

25 Feb '19

Hello Patrick Rudolph, Aaron Durbin, Subrata Banik, Krishna P Bhat D, Balaji Manigandan, Wonkyu Kim, Maulik V Vaghela, Duncan Laurie, Rizwan Qureshi, Shelley Chen, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31234 to look at the new patch set (#8). Change subject: soc/intel/common: Include cometlake PCH IDs ...................................................................... soc/intel/common: Include cometlake PCH IDs Add cometlake specific PCH IDs Change-Id: I18dda48cee29213aa66c0ccddf3da31f0f489d2f Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/hda/hda.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/scs/sd.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c 17 files changed, 100 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/31234/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/31234 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18dda48cee29213aa66c0ccddf3da31f0f489d2f Gerrit-Change-Number: 31234 Gerrit-PatchSet: 8 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: flapjack: get sku_id from ec (cbi)
by You-Cheng Syu (Code Review) 25 Feb '19

25 Feb '19

You-Cheng Syu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31586 ) Change subject: flapjack: get sku_id from ec (cbi) ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/31586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad7a52df38e2045abbdded8ba0a1f1544de961fc Gerrit-Change-Number: 31586 Gerrit-PatchSet: 1 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Nick Sanders <nsanders(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 25 Feb 2019 07:00:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: vendorcode/siemens: Save currently open hwi file name
by Werner Zeh (Code Review) 25 Feb '19

25 Feb '19

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31518 Change subject: vendorcode/siemens: Save currently open hwi file name ...................................................................... vendorcode/siemens: Save currently open hwi file name On every call of hwilib_find_blocks() the CBFS file will be mapped and the contents are parsed to get the offsets for every single block. This is not needed if the CBFS file name is the same for the different calls. This patch adds a storage for the currently open CBFS file name in CAR_GLOBAL and checks on each call if the file to open is already open. If yes, the file will not be mapped again which saves execution time. Test=Booted mc_tcu3, mc_bdx1 and mc_apl1 and verified that hwinfo.hex is only mapped once across several following hwilib_find_blocks() calls. In addition a test was done to ensure that files with different names get mapped correctly. Change-Id: Id69e0f6c914c2b8e4551fd8a4fb7d452d176afb3 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/vendorcode/siemens/hwilib/hwilib.c 1 file changed, 19 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/31518/1 diff --git a/src/vendorcode/siemens/hwilib/hwilib.c b/src/vendorcode/siemens/hwilib/hwilib.c index f15937b..b618304 100644 --- a/src/vendorcode/siemens/hwilib/hwilib.c +++ b/src/vendorcode/siemens/hwilib/hwilib.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Siemens AG + * Copyright (C) 2014-2019 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -39,6 +39,7 @@ #define EIB_FEATRUE_OFFSET 0x00e #define LEN_MAGIC_NUM 0x007 #define BLOCK_MAGIC "H1W2M3I" +#define HWI_MAX_NAME_LEN 32 /* Define all supported block types. */ enum { @@ -79,6 +80,9 @@ */ static uint16_t all_blk_size[MAX_BLOCK_NUM] CAR_GLOBAL; +/* Storage for the cbfs file name of the currently open hwi file. */ +static char current_hwi[HWI_MAX_NAME_LEN] CAR_GLOBAL; + static uint32_t hwilib_read_bytes (const struct param_info *param, uint8_t *dst, uint32_t maxlen); @@ -469,11 +473,21 @@ uint32_t next_offset = 1; uint8_t **blk_ptr = car_get_var_ptr(&all_blocks[0]); uint16_t *all_blk_size_ptr = car_get_var_ptr(&all_blk_size[0]); + char *curr_hwi_name_ptr = car_get_var_ptr(&current_hwi); size_t filesize = 0; /* Check for a valid parameter */ if (!hwi_filename) return CB_ERR_ARG; + /* Check if this file is already open. If yes, just leave as there is + * nothing left to do here. */ + if (curr_hwi_name_ptr && + !strncmp(curr_hwi_name_ptr, hwi_filename, HWI_MAX_NAME_LEN)) { + printk(BIOS_SPEW, "HWILIB: File \"%s\" already open.\n", + hwi_filename); + return CB_SUCCESS; + } + ptr = cbfs_boot_map_with_leak(hwi_filename, CBFS_TYPE_RAW, &filesize); if (!ptr) { printk(BIOS_ERR,"HWILIB: Missing file \"%s\" in cbfs.\n", @@ -533,8 +547,11 @@ } /* We should have found at least one valid block */ if (blk_ptr[BLK_HIB] || blk_ptr[BLK_SIB] || blk_ptr[BLK_EIB] || - blk_ptr[BLK_XIB]) + blk_ptr[BLK_XIB]) { + /* Save currently opened hwi filename. */ + strncpy(curr_hwi_name_ptr, hwi_filename, HWI_MAX_NAME_LEN); return CB_SUCCESS; + } else return CB_ERR; } -- To view, visit https://review.coreboot.org/c/coreboot/+/31518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id69e0f6c914c2b8e4551fd8a4fb7d452d176afb3 Gerrit-Change-Number: 31518 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: ec/google/chromeec: fix the error status passing for cbi
by YH Lin (Code Review) 25 Feb '19

25 Feb '19

YH Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31585 ) Change subject: ec/google/chromeec: fix the error status passing for cbi ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/31585/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/31585/1//COMMIT_MSG@8 PS1, Line 8: : google_chromeec_command() can return non-zero number (both positive : and negative) to indicate error. > That should be fixed instead, shouldn’t it? The convention is, that errors are negative? Hmmm. Other than the places being modified, all seem to be checking for non-zero as error. So I'm assuming non-zero indicates error (either positive or negative)? -- To view, visit https://review.coreboot.org/c/coreboot/+/31585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f0a8a61d01d942cba57036a17dd527fdbbf940c Gerrit-Change-Number: 31585 Gerrit-PatchSet: 1 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 25 Feb 2019 03:02:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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coreboot-gerrit February 2019