coreboot-gerrit February 2019

coreboot-gerrit@coreboot.org

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1249 discussions

Change in ...coreboot[master]: drivers/intel/fsp2_0: Update dependency of USE_FSP_REPO
by Nico Huber (Code Review) 24 Feb '19

24 Feb '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31530 ) Change subject: drivers/intel/fsp2_0: Update dependency of USE_FSP_REPO ...................................................................... Patch Set 4: >> I agree to the change, but just realized that the description >> of SOC_INTEL_COMMON_CANNONLAKE_BASE doesn't make much sense >> any more, does it? > > Still some context SOC_INTEL_COMMON_CANNONLAKE_BASE is applicable. may be you can check CNL code base for that. Yes, sure. It's just the help text of that Kconfig option; it seems outdated with the addition of CML. It talks about FSP header differences of SOC_INTEL_COMMON_CANNONLAKE_BASE and SOC_INTEL_CANNONLAKE. But with CML, FSP headers differ even within the group of SOC_INTEL_COMMON_CANNONLAKE_BASE. -- To view, visit https://review.coreboot.org/c/coreboot/+/31530 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e5d5a9fdf3f5d3e79922e97719e8491aa514cef Gerrit-Change-Number: 31530 Gerrit-PatchSet: 4 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 24 Feb 2019 22:33:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: Revert "vboot: Fix linking error with USE_OPTION_TABLE enabled"
by Angel Pons (Code Review) 24 Feb '19

24 Feb '19

Hello Aaron Durbin, Patrick Rudolph, Arthur Heymans, Patrick Rudolph, Paul Menzel, Philipp Deppenwiese, build bot (Jenkins), Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30904 to review the following change. Change subject: Revert "vboot: Fix linking error with USE_OPTION_TABLE enabled" ...................................................................... Revert "vboot: Fix linking error with USE_OPTION_TABLE enabled" This reverts commit 9554b26f9fd608cc613fc3ad869db33ef0edfe5c. Reason for revert: This breaks USB Always On, and no one cared to investigate the issue further. Change-Id: I5a13be56d47dc8373d9c6d556505bb2e3674d4a8 --- M src/drivers/pc80/rtc/mc146818rtc.c M src/lib/cbfs.c M src/security/vboot/Makefile.inc 3 files changed, 18 insertions(+), 71 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/30904/1 diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 34db4c3..928b403 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -240,34 +240,9 @@ return CB_SUCCESS; } -static enum cb_err locate_cmos_layout(struct region_device *rdev) -{ - uint32_t cbfs_type = CBFS_COMPONENT_CMOS_LAYOUT; - struct cbfsf fh; - - /* - * In case VBOOT is enabled and this function is called from SMM, - * we have multiple CMOS layout files and to locate them we'd need to - * include VBOOT into SMM... - * - * Support only one CMOS layout in the 'COREBOOT' region for now. - */ - if (cbfs_locate_file_in_region(&fh, "COREBOOT", "cmos_layout.bin", - &cbfs_type)) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " - "Options are disabled\n"); - return CB_CMOS_LAYOUT_NOT_FOUND; - } - - cbfs_file_data(rdev, &fh); - - return CB_SUCCESS; -} - enum cb_err get_option(void *dest, const char *name) { struct cmos_option_table *ct; - struct region_device rdev; struct cmos_entries *ce; size_t namelen; int found = 0; @@ -280,20 +255,16 @@ /* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - if (locate_cmos_layout(&rdev) != CB_SUCCESS) { - UNLOCK_NVRAM_CBFS_SPINLOCK(); - return CB_CMOS_LAYOUT_NOT_FOUND; - } - ct = rdev_mmap_full(&rdev); - if (!ct) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be mapped. " - "Options are disabled\n"); - - UNLOCK_NVRAM_CBFS_SPINLOCK(); - return CB_CMOS_LAYOUT_NOT_FOUND; - } - /* find the requested entry record */ + ct = cbfs_boot_map_with_leak("cmos_layout.bin", + CBFS_COMPONENT_CMOS_LAYOUT, NULL); + if (!ct) { + printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " + "Options are disabled\n"); + + UNLOCK_NVRAM_CBFS_SPINLOCK(); + return CB_CMOS_LAYOUT_NOT_FOUND; + } ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length); for (; ce->tag == LB_TAG_OPTION; ce = (struct cmos_entries *)((unsigned char *)ce + ce->size)) { @@ -304,22 +275,18 @@ } if (!found) { printk(BIOS_DEBUG, "WARNING: No CMOS option '%s'.\n", name); - rdev_munmap(&rdev, ct); UNLOCK_NVRAM_CBFS_SPINLOCK(); return CB_CMOS_OPTION_NOT_FOUND; } if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC)) { - rdev_munmap(&rdev, ct); UNLOCK_NVRAM_CBFS_SPINLOCK(); return CB_CMOS_CHECKSUM_INVALID; } if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS) { - rdev_munmap(&rdev, ct); UNLOCK_NVRAM_CBFS_SPINLOCK(); return CB_CMOS_ACCESS_ERROR; } - rdev_munmap(&rdev, ct); UNLOCK_NVRAM_CBFS_SPINLOCK(); return CB_SUCCESS; } @@ -380,7 +347,6 @@ enum cb_err set_option(const char *name, void *value) { struct cmos_option_table *ct; - struct region_device rdev; struct cmos_entries *ce; unsigned long length; size_t namelen; @@ -392,20 +358,14 @@ /* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - if (locate_cmos_layout(&rdev) != CB_SUCCESS) { - UNLOCK_NVRAM_CBFS_SPINLOCK(); - return CB_CMOS_LAYOUT_NOT_FOUND; - } - ct = rdev_mmap_full(&rdev); - if (!ct) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be mapped. " - "Options are disabled\n"); - - UNLOCK_NVRAM_CBFS_SPINLOCK(); - return CB_CMOS_LAYOUT_NOT_FOUND; - } - /* find the requested entry record */ + ct = cbfs_boot_map_with_leak("cmos_layout.bin", + CBFS_COMPONENT_CMOS_LAYOUT, NULL); + if (!ct) { + printk(BIOS_ERR, "cmos_layout.bin could not be found. " + "Options are disabled\n"); + return CB_CMOS_LAYOUT_NOT_FOUND; + } ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length); for (; ce->tag == LB_TAG_OPTION; ce = (struct cmos_entries *)((unsigned char *)ce + ce->size)) { @@ -416,7 +376,6 @@ } if (!found) { printk(BIOS_DEBUG, "WARNING: No CMOS option '%s'.\n", name); - rdev_munmap(&rdev, ct); return CB_CMOS_OPTION_NOT_FOUND; } @@ -425,18 +384,13 @@ length = MAX(strlen((const char *)value) * 8, ce->length - 8); /* make sure the string is null terminated */ if (set_cmos_value(ce->bit + ce->length - 8, 8, &(u8[]){0}) - != CB_SUCCESS) { - rdev_munmap(&rdev, ct); + != CB_SUCCESS) return CB_CMOS_ACCESS_ERROR; - } } - if (set_cmos_value(ce->bit, length, value) != CB_SUCCESS) { - rdev_munmap(&rdev, ct); + if (set_cmos_value(ce->bit, length, value) != CB_SUCCESS) return CB_CMOS_ACCESS_ERROR; - } - rdev_munmap(&rdev, ct); return CB_SUCCESS; } diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index ca1fc84..9938e6a 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -321,11 +321,6 @@ static const struct cbfs_locator *locators[] = { #if IS_ENABLED(CONFIG_VBOOT) - /* - * NOTE: Does not link in SMM, as the vboot_locator isn't compiled. - * ATM there's no need for VBOOT functionality in SMM and it's not - * a problem. - */ &vboot_locator, #endif &cbfs_master_header_locator, diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 75c2a9e..6f18a35 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -154,8 +154,6 @@ font.bin \ vbgfx.bin \ rmu.bin \ - cmos_layout.bin \ - cmos.default \ $(call strip_quotes,$(CONFIG_RO_REGION_ONLY)) \ ,$(1)),COREBOOT,COREBOOT FW_MAIN_A FW_MAIN_B))) -- To view, visit https://review.coreboot.org/c/coreboot/+/30904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a13be56d47dc8373d9c6d556505bb2e3674d4a8 Gerrit-Change-Number: 30904 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP] src/mb/fujitsu/esprimo_q510: add new mainboard
by Angel Pons (Code Review) 24 Feb '19

24 Feb '19

Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30650 ) Change subject: [WIP] src/mb/fujitsu/esprimo_q510: add new mainboard ...................................................................... Abandoned Mainboard fails to power up -- To view, visit https://review.coreboot.org/c/coreboot/+/30650 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I812d7680765b1adb001029e43ce7f5df48b2da2d Gerrit-Change-Number: 30650 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: src/mb/gigabyte/ga-h61m-s2pv: fix random things
by Angel Pons (Code Review) 24 Feb '19

24 Feb '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31558 ) Change subject: src/mb/gigabyte/ga-h61m-s2pv: fix random things ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/31558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice0eff7b9829816aff4d334f4ac4a2fb435a2fb0 Gerrit-Change-Number: 31558 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 24 Feb 2019 18:56:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/emulation/qemu: Fix fw_cfg regression
by Patrick Rudolph (Code Review) 24 Feb '19

24 Feb '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31593 Change subject: mb/emulation/qemu: Fix fw_cfg regression ...................................................................... mb/emulation/qemu: Fix fw_cfg regression The change I48cc943aaa999e4323e9d7e5dd666c5316533dcc "mb/emulation/qemu-i440fx: change file handling" introduced a regression where it loads only 4 bytes of the ACPI table, instead of the whole table. Load the whole ACPI table. Tested on Qemu using GNU/Linux. Change-Id: Ibacbf7caab9be5f181c12e9dd39a2893b13cf6c9 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/emulation/qemu-i440fx/fw_cfg.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/31593/1 diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index 6a9ef03..a029b38 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -251,7 +251,7 @@ printk(BIOS_DEBUG, "QEMU: loading \"%s\" to 0x%lx (len %d)\n", s[i].alloc.file, current, f.size); - fw_cfg_get(f.select, (void *)current, sizeof(current)); + fw_cfg_get(f.select, (void *)current, f.size); addrs[i] = current; current += f.size; break; -- To view, visit https://review.coreboot.org/c/coreboot/+/31593 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibacbf7caab9be5f181c12e9dd39a2893b13cf6c9 Gerrit-Change-Number: 31593 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: security/vboot: Add measured boot mode
by Paul Menzel (Code Review) 24 Feb '19

24 Feb '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29547 ) Change subject: security/vboot: Add measured boot mode ...................................................................... Patch Set 70: (3 comments) I see that maintaining this change-set is cumbersome. But I agree with Julius regarding the coding style issues. There are too long lines introduced. Werner, can you point to an announcement on the mailing list for the clang-format requirement? It looks to me, that clang-format is still not configured properly to be used by default and blindly. How the clang-format transition should be conducted, should be discussed on the mailing list. https://review.coreboot.org/#/c/29547/70//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29547/70//COMMIT_MSG@12 PS70, Line 12: Could you please add on what platforms this was tested? https://review.coreboot.org/#/c/29547/70/Documentation/security/index.md File Documentation/security/index.md: PS70: Could be split out. https://review.coreboot.org/#/c/29547/70/src/security/vboot/vboot_logic.c File src/security/vboot/vboot_logic.c: https://review.coreboot.org/#/c/29547/70/src/security/vboot/vboot_logic.c@2… PS70, Line 281: return vboot_extend_pcr(ctx, 0, BOOT_MODE_PCR) || vboot_extend_pcr(ctx, 1, HWID_DIGEST_PCR); > line over 80 characters So clang-format seems to be incorrect here, and should not have touched these lines. -- To view, visit https://review.coreboot.org/c/coreboot/+/29547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e Gerrit-Change-Number: 29547 Gerrit-PatchSet: 70 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 24 Feb 2019 11:03:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/common: Include cometlake SA IDs
by Subrata Banik (Code Review) 24 Feb '19

24 Feb '19

Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31226 ) Change subject: soc/intel/common: Include cometlake SA IDs ...................................................................... soc/intel/common: Include cometlake SA IDs Add cometlake specific SA IDs Change-Id: I1fbbab8a7797b36a9eacbd1c6a0644466f2fe6b1 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/31226 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/systemagent/systemagent.c 4 files changed, 75 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Subrata Banik: Looks good to me, approved Wonkyu Kim: Looks good to me, but someone else must approve diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 9be9759..81654bc 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3001,6 +3001,24 @@ #define PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_5 0x8A56 #define PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_6 0x8A57 #define PCI_DEVICE_ID_INTEL_ICL_GT3_ULT 0x8A62 +#define PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1 0x9B21 +#define PCI_DEVICE_ID_INTEL_CML_GT1_ULT_2 0x9B2A +#define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_1 0x9B41 +#define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_2 0x9B4A +#define PCI_DEVICE_ID_INTEL_CML_GT1_ULT_3 0x9B2B +#define PCI_DEVICE_ID_INTEL_CML_GT1_ULT_4 0x9B2C +#define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_3 0x9B4B +#define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_4 0x9B4C +#define PCI_DEVICE_ID_INTEL_CML_GT1_ULX_1 0x9B20 +#define PCI_DEVICE_ID_INTEL_CML_GT2_ULX_1 0x9B40 +#define PCI_DEVICE_ID_INTEL_CML_GT1_S_1 0x9B25 +#define PCI_DEVICE_ID_INTEL_CML_GT1_S_2 0x9B28 +#define PCI_DEVICE_ID_INTEL_CML_GT2_S_1 0x9B45 +#define PCI_DEVICE_ID_INTEL_CML_GT2_S_2 0x9B48 +#define PCI_DEVICE_ID_INTEL_CML_GT1_H_1 0x9B24 +#define PCI_DEVICE_ID_INTEL_CML_GT1_H_2 0x9B22 +#define PCI_DEVICE_ID_INTEL_CML_GT2_H_1 0x9B44 +#define PCI_DEVICE_ID_INTEL_CML_GT2_H_2 0x9B42 /* Intel Northbridge Ids */ #define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 @@ -3027,6 +3045,13 @@ #define PCI_DEVICE_ID_INTEL_ICL_ID_U_2_2 0x8A02 #define PCI_DEVICE_ID_INTEL_ICL_ID_Y 0x8A10 #define PCI_DEVICE_ID_INTEL_ICL_ID_Y_2 0x8A00 +#define PCI_DEVICE_ID_INTEL_CML_ULT 0x9B61 +#define PCI_DEVICE_ID_INTEL_CML_ULT_6_2 0x9B51 +#define PCI_DEVICE_ID_INTEL_CML_ULX 0x9B60 +#define PCI_DEVICE_ID_INTEL_CML_S 0x9B55 +#define PCI_DEVICE_ID_INTEL_CML_S_10_2 0x9B35 +#define PCI_DEVICE_ID_INTEL_CML_H 0x9B54 +#define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44 /* Intel SMBUS device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23 diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index a4328cb..faa4924 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -57,6 +57,13 @@ { PCI_DEVICE_ID_INTEL_WHL_ID_Wx2, "Whiskeylake W (2+2)" }, { PCI_DEVICE_ID_INTEL_CFL_ID_H, "Coffeelake-H" }, { PCI_DEVICE_ID_INTEL_CFL_ID_S, "Coffeelake-S" }, + { PCI_DEVICE_ID_INTEL_CML_ULT, "CometLake-U (4+2)" }, + { PCI_DEVICE_ID_INTEL_CML_ULT_6_2, "CometLake-U (6+2)" }, + { PCI_DEVICE_ID_INTEL_CML_ULX, "CometLake-ULX (4+2)" }, + { PCI_DEVICE_ID_INTEL_CML_S, "CometLake-S (6+2)" }, + { PCI_DEVICE_ID_INTEL_CML_S_10_2, "CometLake-S (10+2)" }, + { PCI_DEVICE_ID_INTEL_CML_H, "CometLake-H (6+2)" }, + { PCI_DEVICE_ID_INTEL_CML_H_8_2, "CometLake-H (8+2)" }, }; static struct { @@ -86,6 +93,24 @@ { PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1, "Whiskeylake ULT GT1" }, { PCI_DEVICE_ID_INTEL_CFL_H_GT2, "Coffeelake-H GT2" }, { PCI_DEVICE_ID_INTEL_CFL_S_GT2, "Coffeelake-S GT2" }, + { PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1, "CometLake ULT GT1" }, + { PCI_DEVICE_ID_INTEL_CML_GT1_ULT_2, "CometLake ULT GT1" }, + { PCI_DEVICE_ID_INTEL_CML_GT2_ULT_1, "CometLake ULT GT2" }, + { PCI_DEVICE_ID_INTEL_CML_GT2_ULT_2, "CometLake ULT GT2" }, + { PCI_DEVICE_ID_INTEL_CML_GT1_ULT_3, "CometLake ULT GT1" }, + { PCI_DEVICE_ID_INTEL_CML_GT1_ULT_4, "CometLake ULT GT1" }, + { PCI_DEVICE_ID_INTEL_CML_GT2_ULT_3, "CometLake ULT GT2" }, + { PCI_DEVICE_ID_INTEL_CML_GT2_ULT_4, "CometLake ULT GT2" }, + { PCI_DEVICE_ID_INTEL_CML_GT1_ULX_1, "CometLake ULX GT1" }, + { PCI_DEVICE_ID_INTEL_CML_GT2_ULX_1, "CometLake ULX GT2" }, + { PCI_DEVICE_ID_INTEL_CML_GT1_S_1, "CometLake S GT1" }, + { PCI_DEVICE_ID_INTEL_CML_GT1_S_2, "CometLake S GT1" }, + { PCI_DEVICE_ID_INTEL_CML_GT2_S_1, "CometLake S GT2" }, + { PCI_DEVICE_ID_INTEL_CML_GT2_S_2, "CometLake S GT2" }, + { PCI_DEVICE_ID_INTEL_CML_GT1_H_1, "CometLake H GT1" }, + { PCI_DEVICE_ID_INTEL_CML_GT1_H_2, "CometLake H GT1" }, + { PCI_DEVICE_ID_INTEL_CML_GT2_H_1, "CometLake H GT2" }, + { PCI_DEVICE_ID_INTEL_CML_GT2_H_2, "CometLake H GT2" }, }; static uint8_t get_dev_revision(pci_devfn_t dev) diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 8eebd12..da2b25f 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -151,6 +151,24 @@ PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_5, PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_6, PCI_DEVICE_ID_INTEL_ICL_GT3_ULT, + PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1, + PCI_DEVICE_ID_INTEL_CML_GT1_ULT_2, + PCI_DEVICE_ID_INTEL_CML_GT2_ULT_1, + PCI_DEVICE_ID_INTEL_CML_GT2_ULT_2, + PCI_DEVICE_ID_INTEL_CML_GT1_ULT_3, + PCI_DEVICE_ID_INTEL_CML_GT1_ULT_4, + PCI_DEVICE_ID_INTEL_CML_GT2_ULT_3, + PCI_DEVICE_ID_INTEL_CML_GT2_ULT_4, + PCI_DEVICE_ID_INTEL_CML_GT1_ULX_1, + PCI_DEVICE_ID_INTEL_CML_GT2_ULX_1, + PCI_DEVICE_ID_INTEL_CML_GT1_S_1, + PCI_DEVICE_ID_INTEL_CML_GT1_S_2, + PCI_DEVICE_ID_INTEL_CML_GT2_S_1, + PCI_DEVICE_ID_INTEL_CML_GT2_S_2, + PCI_DEVICE_ID_INTEL_CML_GT1_H_1, + PCI_DEVICE_ID_INTEL_CML_GT1_H_2, + PCI_DEVICE_ID_INTEL_CML_GT2_H_1, + PCI_DEVICE_ID_INTEL_CML_GT2_H_2, 0, }; diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 299cc5f..69c1232 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -322,6 +322,13 @@ PCI_DEVICE_ID_INTEL_ICL_ID_U_2_2, PCI_DEVICE_ID_INTEL_ICL_ID_Y, PCI_DEVICE_ID_INTEL_ICL_ID_Y_2, + PCI_DEVICE_ID_INTEL_CML_ULT, + PCI_DEVICE_ID_INTEL_CML_ULT_6_2, + PCI_DEVICE_ID_INTEL_CML_ULX, + PCI_DEVICE_ID_INTEL_CML_S, + PCI_DEVICE_ID_INTEL_CML_S_10_2, + PCI_DEVICE_ID_INTEL_CML_H, + PCI_DEVICE_ID_INTEL_CML_H_8_2, 0 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/31226 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fbbab8a7797b36a9eacbd1c6a0644466f2fe6b1 Gerrit-Change-Number: 31226 Gerrit-PatchSet: 8 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: soc/intel/common: Include cometlake CPU IDs
by Subrata Banik (Code Review) 24 Feb '19

24 Feb '19

Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31143 ) Change subject: soc/intel/common: Include cometlake CPU IDs ...................................................................... soc/intel/common: Include cometlake CPU IDs Add cometlake specific CPU IDs Change-Id: I75d5b82524c9df1402abf6659d62dbc716c28c30 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/31143 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim(a)intel.com> --- M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/include/intelblocks/mp_init.h 3 files changed, 13 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Subrata Banik: Looks good to me, approved Wonkyu Kim: Looks good to me, but someone else must approve diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 0b87615..a4328cb 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -40,6 +40,10 @@ { CPUID_WHISKEYLAKE_V0, "Whiskeylake V0" }, { CPUID_WHISKEYLAKE_W0, "Whiskeylake W0" }, { CPUID_COFFEELAKE_U0, "Coffeelake U0 (6+2)" }, + { CPUID_COMETLAKE_U_A0, "Cometlake-U A0 (6+2)" }, + { CPUID_COMETLAKE_U_K0_S0, "Cometlake-U K0/S0 (6+2)/(4+2)" }, + { CPUID_COMETLAKE_H_S_6_2_P0, "Cometlake-H/S P0 (6+2)" }, + { CPUID_COMETLAKE_H_S_10_2_P0, "Cometlake-H/S P0 (10+2)" }, }; static struct { diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 7deaaa8..4aecf84 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -76,6 +76,10 @@ { X86_VENDOR_INTEL, CPUID_COFFEELAKE_D0 }, { X86_VENDOR_INTEL, CPUID_ICELAKE_A0 }, { X86_VENDOR_INTEL, CPUID_ICELAKE_B0 }, + { X86_VENDOR_INTEL, CPUID_COMETLAKE_U_A0 }, + { X86_VENDOR_INTEL, CPUID_COMETLAKE_U_K0_S0 }, + { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_6_2_P0 }, + { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_P0 }, { 0, 0 }, }; diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index fca6ca5..3c7467d 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -44,6 +44,11 @@ #define CPUID_ICELAKE_A0 0x706e0 #define CPUID_ICELAKE_B0 0x706e1 +#define CPUID_COMETLAKE_U_A0 0xa0660 +#define CPUID_COMETLAKE_U_K0_S0 0xa0661 +#define CPUID_COMETLAKE_H_S_6_2_P0 0xa0650 +#define CPUID_COMETLAKE_H_S_10_2_P0 0xa0651 + /* * MP Init callback function to Find CPU Topology. This function is common * among all SOCs and thus its in Common CPU block. -- To view, visit https://review.coreboot.org/c/coreboot/+/31143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75d5b82524c9df1402abf6659d62dbc716c28c30 Gerrit-Change-Number: 31143 Gerrit-PatchSet: 9 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...coreboot[master]: drivers/intel/fsp2_0: Update dependency of USE_FSP_REPO
by Subrata Banik (Code Review) 24 Feb '19

24 Feb '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31530 ) Change subject: drivers/intel/fsp2_0: Update dependency of USE_FSP_REPO ...................................................................... Patch Set 4: > I agree to the change, but just realized that the description > of SOC_INTEL_COMMON_CANNONLAKE_BASE doesn't make much sense > any more, does it? Still some context SOC_INTEL_COMMON_CANNONLAKE_BASE is applicable. may be you can check CNL code base for that. -- To view, visit https://review.coreboot.org/c/coreboot/+/31530 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e5d5a9fdf3f5d3e79922e97719e8491aa514cef Gerrit-Change-Number: 31530 Gerrit-PatchSet: 4 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 24 Feb 2019 04:47:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: vendorcode/intel/fsp/fsp2_0/cml: Add FSP header files for Cometlake
by Subrata Banik (Code Review) 24 Feb '19

24 Feb '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31529 ) Change subject: vendorcode/intel/fsp/fsp2_0/cml: Add FSP header files for Cometlake ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/#/c/31529/3/src/vendorcode/intel/fsp/fsp2_0/com… File src/vendorcode/intel/fsp/fsp2_0/cometlake/FspUpd.h: https://review.coreboot.org/#/c/31529/3/src/vendorcode/intel/fsp/fsp2_0/com… PS3, Line 3: Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> > The date is wrong. It should reflect the date when the contents […] i don't understand the point of this argument. CML FSP code base is newly created in FSP stream in 2019. https://review.coreboot.org/#/c/31529/3/src/vendorcode/intel/fsp/fsp2_0/com… PS3, Line 40: #define FSPT_UPD_SIGNATURE 0x545F4450554C4643 /* 'CFLUPD_T' */ > Same signatures as for Coffee Lake? I was told by somebody @intel […] this is a bug, we have already raised hence nothing much to worry. once fix it will available for next RC release. -- To view, visit https://review.coreboot.org/c/coreboot/+/31529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I734316445dda5b1feb4098ce3c58b6dd8ce2d272 Gerrit-Change-Number: 31529 Gerrit-PatchSet: 3 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 24 Feb 2019 04:46:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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coreboot-gerrit February 2019