February 2019 - coreboot-gerrit

Change in ...coreboot[master]: google/mistral: Enable additional GBB flags in vboot.

by SANTHOSH JANARDHANA HASSAN (Code Review)

SANTHOSH JANARDHANA HASSAN has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31171 Change subject: google/mistral: Enable additional GBB flags in vboot. ...................................................................... google/mistral: Enable additional GBB flags in vboot. Enable GBB_FLAG_FORCE_MANUAL_RECOVERY and GBB_FLAG_DEV_SCREEN_SHORT_DELAY as additional default flags. Change-Id: If1e7effb2d74b861f196ce861a3c8779ce89b3b2 Signed-off-by: Santhosh Hassan <sahassan(a)google.com> Change-Id: Ic0a00c6a7bfa5090461c2c9da0bc6ee73118ca74 --- M src/mainboard/google/mistral/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/31171/1 diff --git a/src/mainboard/google/mistral/Kconfig b/src/mainboard/google/mistral/Kconfig index c369472..5e97bb6 100644 --- a/src/mainboard/google/mistral/Kconfig +++ b/src/mainboard/google/mistral/Kconfig @@ -20,7 +20,9 @@ config VBOOT select VBOOT_VBNV_FLASH select VBOOT_NO_BOARD_SUPPORT + select GBB_FLAG_DEV_SCREEN_SHORT_DELAY select GBB_FLAG_FORCE_DEV_SWITCH_ON + select GBB_FLAG_FORCE_MANUAL_RECOVERY config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/31171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0a00c6a7bfa5090461c2c9da0bc6ee73118ca74 Gerrit-Change-Number: 31171 Gerrit-PatchSet: 1 Gerrit-Owner: SANTHOSH JANARDHANA HASSAN <sahassan(a)google.com> Gerrit-MessageType: newchange

1 year, 6 months

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Change in ...coreboot[master]: qclib: Differentiate between ES_1.0 and ES1.1 silicon

by Name of user not set (Code Review)

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30903 Change subject: qclib: Differentiate between ES_1.0 and ES1.1 silicon ...................................................................... qclib: Differentiate between ES_1.0 and ES1.1 silicon The PBL data ptr gets passed at a different location for 1.0 vs 1.1. So let us read the revision from TCSR and pass the right value. Change-Id: Id23493c8cfc64f62964a453cd32a0ddc4bff9e84 Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/qclib_execute.c 1 file changed, 14 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/30903/1 diff --git a/src/soc/qualcomm/qcs405/qclib_execute.c b/src/soc/qualcomm/qcs405/qclib_execute.c index 917a04c..214128f 100644 --- a/src/soc/qualcomm/qcs405/qclib_execute.c +++ b/src/soc/qualcomm/qcs405/qclib_execute.c @@ -14,6 +14,7 @@ */ #include <string.h> +#include <arch/io.h> #include <arch/cache.h> #include <arch/mmu.h> #include <cbfs.h> @@ -28,7 +29,12 @@ #define DCB_NAME "/dcb" #define QCLIB_NAME "/qclib" -#define PBL_DATA_PTR 0x8c101a0 //0x14810188 +#define TCSR_SOC_HW_VERSION 0x0194D000 +#define ES_1_0 0x20140100 +#define ES_1_1 0x20140101 + +#define PBL_DATA_PTR_ES_1_0 0x8c101a0 +#define PBL_DATA_PTR_ES_1_1 0x8c111a0 void qclib_load_and_run(void) { @@ -36,6 +42,7 @@ void *arg; int ret_code; struct mmu_context pre_qclib_mmu_context; + void *pbl_data_ptr; struct prog qclib = PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX QCLIB_NAME); @@ -67,7 +74,12 @@ if (cbfs_prog_stage_load(&qclib)) goto fail; - prog_set_entry(&qclib, qclib.entry, (void *)PBL_DATA_PTR); + if (read32((void *) TCSR_SOC_HW_VERSION) == ES_1_1) + pbl_data_ptr = (void *) 0x8c111a0; + else + pbl_data_ptr = (void *) 0x8c101a0; + + prog_set_entry(&qclib, qclib.entry, (void *)pbl_data_ptr); printk(BIOS_DEBUG, "\n\n\nQCLib is about to Initialize PMIC and DDR\n"); printk(BIOS_DEBUG, "Jumping to QCLib code at %p(%p)\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/30903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id23493c8cfc64f62964a453cd32a0ddc4bff9e84 Gerrit-Change-Number: 30903 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 year, 6 months

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Change in ...coreboot[master]: google/mistral: move bootblock and fmap to their previous location

by Patrick Georgi (Code Review)

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30965 Change subject: google/mistral: move bootblock and fmap to their previous location ...................................................................... google/mistral: move bootblock and fmap to their previous location Helps with the current boot hack that requires them to be at certain locations. Also make GBB smaller. We don't store graphics in there anymore. Change-Id: I09c3a6d4221990cd51d4793693a7c7ae2df85105 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/google/mistral/chromeos.fmd 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/30965/1 diff --git a/src/mainboard/google/mistral/chromeos.fmd b/src/mainboard/google/mistral/chromeos.fmd index a9bdd7b..ffeec16 100644 --- a/src/mainboard/google/mistral/chromeos.fmd +++ b/src/mainboard/google/mistral/chromeos.fmd @@ -2,9 +2,9 @@ WP_RO@0x0 0x400000 { RO_SECTION@0x0 0x3e0000 { BOOTBLOCK@0 128K - COREBOOT(CBFS)@0x20000 0x2e0000 - FMAP@0x300000 0x1000 - GBB@0x301000 0xdef00 + COREBOOT(CBFS)@0x3e000 0x1e0000 + FMAP@0x21e000 0x1000 + GBB@0x3dd000 0x2f00 RO_FRID@0x3dff00 0x100 } RO_VPD@0x3e0000 0x20000 -- To view, visit https://review.coreboot.org/c/coreboot/+/30965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09c3a6d4221990cd51d4793693a7c7ae2df85105 Gerrit-Change-Number: 30965 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

1 year, 6 months

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Change in ...coreboot[master]: soc/intel/common: Add more GPIO definition macros

by Thomas Heijligen (Code Review)

Hello Nico Huber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31350 to review the following change. Change subject: soc/intel/common: Add more GPIO definition macros ...................................................................... soc/intel/common: Add more GPIO definition macros Change-Id: Id1a3c00aa8a857afa08e745b0b6a578b01fa6d47 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/31350/1 diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 35f89c9..4d9f2be 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -236,6 +236,16 @@ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)) +#define PAD_CFG_GPI_IOSSTATE(pad, pull, rst, iosstate) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ + PAD_PULL(pull) | PAD_IOSSTATE(iosstate)) + +#define PAD_CFG_GPI_IOSSTATE_IOSTERM(pad, pull, rst, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ + PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + /* General purpose input. The following macro sets the * Host Software Pad Ownership to GPIO Driver mode. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1a3c00aa8a857afa08e745b0b6a578b01fa6d47 Gerrit-Change-Number: 31350 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

1 year, 6 months

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Change in ...coreboot[master]: soc/intel/denverton_ns: Allow using FSP repo

by Felix Singer (Code Review)

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30931 Change subject: soc/intel/denverton_ns: Allow using FSP repo ...................................................................... soc/intel/denverton_ns: Allow using FSP repo Change-Id: I615305da5865bef305f560f5c90482cf0937b25a Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/denverton_ns/Kconfig 2 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/30931/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 8156d18..6f5ed2a 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -85,7 +85,8 @@ bool "Use the IntelFSP based binaries" depends on ADD_FSP_BINARIES depends on SOC_INTEL_APOLLOLAKE || SOC_INTEL_SKYLAKE || \ - SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE + SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE || \ + SOC_INTEL_DENVERTON_NS help When selecting this option, the SoC must set FSP_HEADER_PATH and FSP_FD_PATH correctly so FSP splitting works. diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 1096549..dfb5c37 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -78,6 +78,16 @@ help The memory location of the Intel FSP-S binary for this platform. +config FSP_HEADER_PATH + string "Location of FSP headers" + depends on MAINBOARD_USES_FSP2_0 + default "3rdparty/fsp/DenvertonNSFspBinPkg/Include/" + +config FSP_FD_PATH + string + depends on FSP_USE_REPO + default "3rdparty/fsp/DenvertonNSFspBinPkg/FspBin/DenvertonNSFsp.fd" + # CAR memory layout on DENVERTON_NS hardware: ## CAR base address - 0xfef00000 ## CAR size 1MB - 0x100 (0xfff00) -- To view, visit https://review.coreboot.org/c/coreboot/+/30931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I615305da5865bef305f560f5c90482cf0937b25a Gerrit-Change-Number: 30931 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

1 year, 6 months

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Change in ...coreboot[master]: README: Spell Web site with one space

by Paul Menzel (Code Review)

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31384 Change subject: README: Spell Web site with one space ...................................................................... README: Spell Web site with one space Change-Id: I4119ae6df01dbafb60b2a132c887844739839de6 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M payloads/libpayload/README 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/31384/1 diff --git a/payloads/libpayload/README b/payloads/libpayload/README index fdf9b18..7348934 100644 --- a/payloads/libpayload/README +++ b/payloads/libpayload/README @@ -49,10 +49,10 @@ Please see the sample/ directory for details. -Website and Mailing List +Web site and Mailing List ------------------------ -The main website is https://www.coreboot.org/Libpayload. +The main web site is https://www.coreboot.org/Libpayload. For additional information, patches, and discussions, please join the coreboot mailing list at https://www.coreboot.org/Mailinglist, where most -- To view, visit https://review.coreboot.org/c/coreboot/+/31384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4119ae6df01dbafb60b2a132c887844739839de6 Gerrit-Change-Number: 31384 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

1 year, 6 months

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Change in ...coreboot[master]: x86/acpi_s3: Remove trailing dots from debug message

by Paul Menzel (Code Review)

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30806 Change subject: x86/acpi_s3: Remove trailing dots from debug message ...................................................................... x86/acpi_s3: Remove trailing dots from debug message The dot is not needed, as it is no sentence and followed by a line break. Change-Id: I3905853eb7039f9c6d2486a77da47a4460276624 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/arch/x86/acpi_s3.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/30806/1 diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index ad9fe00..07c0332 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -34,10 +34,10 @@ { if (acpi_slp_type < 0) { if (romstage_handoff_is_resume()) { - printk(BIOS_DEBUG, "S3 Resume.\n"); + printk(BIOS_DEBUG, "S3 Resume\n"); acpi_slp_type = ACPI_S3; } else { - printk(BIOS_DEBUG, "Normal boot.\n"); + printk(BIOS_DEBUG, "Normal boot\n"); acpi_slp_type = ACPI_S0; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/30806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3905853eb7039f9c6d2486a77da47a4460276624 Gerrit-Change-Number: 30806 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

1 year, 6 months

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Change in ...coreboot[master]: mb/lenovo/x1_carbon_gen1: Swap Fn-F2 and Fn-F3

by Nicola Corna (Code Review)

Nicola Corna has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31470 Change subject: mb/lenovo/x1_carbon_gen1: Swap Fn-F2 and Fn-F3 ...................................................................... mb/lenovo/x1_carbon_gen1: Swap Fn-F2 and Fn-F3 thinkpad_acpi expects the battery hotkey (KEY_BATTERY) on scancode 0x01 (Fn-F2) and the lock hotkey (KEY_COFFEE) on scancode 0x02 (Fn-F3). This is true for most of the Thinkpads, however on the X1 Carbon Gen1 (and possibly others), the battery hotkey is not present and the lock one is instead on Fn-F3. Swap the RHK calls in _Q11 (Fn-F2) and _Q12 (Fn-F3) to fix the issue, so that the lock hotkey is on F3 and the battery one is on F2 (even if it's not marked so). Change-Id: Ib2d96be1a7815d7d03e6e8c6d300fd671c8598ca Signed-off-by: Nicola Corna <nicola(a)corna.info> --- M src/ec/lenovo/h8/acpi/ec.asl M src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/31470/1 diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index 327a2cf..6ffba5e 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -197,12 +197,20 @@ Method (_Q11, 0, NotSerialized) { +#if IS_ENABLED(EC_LENOVO_H8_SWAP_FNF2_FNF3) + ^HKEY.RHK (0x03) +#else ^HKEY.RHK (0x02) +#endif } Method (_Q12, 0, NotSerialized) { +#if IS_ENABLED(EC_LENOVO_H8_SWAP_FNF2_FNF3) + ^HKEY.RHK (0x02) +#else ^HKEY.RHK (0x03) +#endif } Method (_Q64, 0, NotSerialized) diff --git a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl index 8c9bd5a..2696607 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl +++ b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl @@ -20,6 +20,7 @@ #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 +#define EC_LENOVO_H8_SWAP_FNF2_FNF3 1 #include <arch/acpi.h> DefinitionBlock( -- To view, visit https://review.coreboot.org/c/coreboot/+/31470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2d96be1a7815d7d03e6e8c6d300fd671c8598ca Gerrit-Change-Number: 31470 Gerrit-PatchSet: 1 Gerrit-Owner: Nicola Corna <nicola(a)corna.info> Gerrit-MessageType: newchange

1 year, 7 months

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Change in ...libgfxinit[master]: [WIP] gma: Add Gemini Lake support

by Nico Huber (Code Review)

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/31611 Change subject: [WIP] gma: Add Gemini Lake support ...................................................................... [WIP] gma: Add Gemini Lake support Change-Id: I84347130fc3fcaf33d9f3d84fab47c67899c792d Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M common/Makefile.inc M common/broxton/hw-gfx-gma-ddi_phy.ads M common/broxton/hw-gfx-gma-plls.adb M common/broxton/hw-gfx-gma-power_and_clocks.adb M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma-registers.ads M common/hw-gfx-gma.ads R configs/apollolake C configs/geminilake 9 files changed, 109 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/11/31611/1 diff --git a/common/Makefile.inc b/common/Makefile.inc index 61955eb..cfb2dfa 100644 --- a/common/Makefile.inc +++ b/common/Makefile.inc @@ -68,7 +68,7 @@ subdirs-y += ironlake else ifneq ($(filter Haswell Broadwell,$(CONFIG_GFX_GMA_CPU)),) subdirs-y += haswell_shared haswell -else ifneq ($(filter Broxton,$(CONFIG_GFX_GMA_CPU)),) +else ifneq ($(filter Apollolake Geminilake,$(CONFIG_GFX_GMA_CPU)),) subdirs-y += haswell_shared broxton else ifneq ($(filter Skylake Kabylake,$(CONFIG_GFX_GMA_CPU)),) subdirs-y += haswell_shared skylake diff --git a/common/broxton/hw-gfx-gma-ddi_phy.ads b/common/broxton/hw-gfx-gma-ddi_phy.ads index fc6cacf..e6301bf 100644 --- a/common/broxton/hw-gfx-gma-ddi_phy.ads +++ b/common/broxton/hw-gfx-gma-ddi_phy.ads @@ -16,7 +16,7 @@ private package HW.GFX.GMA.DDI_Phy is - type T is (BC, A); + type T is (BC, A, C); procedure Power_On (Phy : T); procedure Power_Off (Phy : T); diff --git a/common/broxton/hw-gfx-gma-plls.adb b/common/broxton/hw-gfx-gma-plls.adb index 087ff12..f7ecc05 100644 --- a/common/broxton/hw-gfx-gma-plls.adb +++ b/common/broxton/hw-gfx-gma-plls.adb @@ -170,6 +170,8 @@ PLL_10 : Registers_Index; PCS_DW12_LN01 : Registers_Index; PCS_DW12_GRP : Registers_Index; + TX_DW5_LN0 : Registers_Index; + TX_DW5_GRP : Registers_Index; end record; type Port_PLL_Array is array (Valid_PLLs) of Port_PLL_Regs; @@ -187,7 +189,9 @@ PLL_9 => BXT_PORT_PLL_9_A, PLL_10 => BXT_PORT_PLL_10_A, PCS_DW12_LN01 => BXT_PORT_PCS_DW12_01_A, - PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_A), + PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_A, + TX_DW5_LN0 => BXT_PORT_TX_DW5_LN0_A, + TX_DW5_GRP => BXT_PORT_TX_DW5_GRP_A), DPLL_B => (PLL_ENABLE => BXT_PORT_PLL_ENABLE_B, PLL_EBB_0 => BXT_PORT_PLL_EBB_0_B, @@ -201,7 +205,9 @@ PLL_9 => BXT_PORT_PLL_9_B, PLL_10 => BXT_PORT_PLL_10_B, PCS_DW12_LN01 => BXT_PORT_PCS_DW12_01_B, - PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_B), + PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_B, + TX_DW5_LN0 => BXT_PORT_TX_DW5_LN0_B, + TX_DW5_GRP => BXT_PORT_TX_DW5_GRP_B), DPLL_C => (PLL_ENABLE => BXT_PORT_PLL_ENABLE_C, PLL_EBB_0 => BXT_PORT_PLL_EBB_0_C, @@ -215,11 +221,15 @@ PLL_9 => BXT_PORT_PLL_9_C, PLL_10 => BXT_PORT_PLL_10_C, PCS_DW12_LN01 => BXT_PORT_PCS_DW12_01_C, - PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_C)); + PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_C, + TX_DW5_LN0 => BXT_PORT_TX_DW5_LN0_C, + TX_DW5_GRP => BXT_PORT_TX_DW5_GRP_C)); PORT_PLL_ENABLE : constant := 1 * 2 ** 31; PORT_PLL_ENABLE_LOCK : constant := 1 * 2 ** 30; PORT_PLL_ENABLE_REF_SEL : constant := 1 * 2 ** 27; + PORT_PLL_POWER_ENABLE : constant := 1 * 2 ** 26; + PORT_PLL_POWER_STATE : constant := 1 * 2 ** 25; PORT_PLL_EBB0_P1_SHIFT : constant := 13; PORT_PLL_EBB0_P1_MASK : constant := 16#07# * 2 ** 13; @@ -336,8 +346,17 @@ begin pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); - Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_ENABLE_REF_SEL); -- non-SSC ref - Unset_Mask (PORT (P).PLL_EBB_4, PORT_PLL_EBB4_10BIT_CLK_ENABLE); + Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_ENABLE_REF_SEL); -- non-SSC ref + + if Config.Has_Port_PLL_Pwr_En then + Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_POWER_ENABLE); + Wait_Set_Mask + (Register => PORT (P).PLL_ENABLE, + Mask => PORT_PLL_POWER_STATE, + TOut_MS => 1); -- 200us + end if; + + Unset_Mask (PORT (P).PLL_EBB_4, PORT_PLL_EBB4_10BIT_CLK_ENABLE); Unset_And_Set_Mask (Register => PORT (P).PLL_EBB_0, @@ -388,7 +407,16 @@ Wait_Set_Mask (Register => PORT (P).PLL_ENABLE, Mask => PORT_PLL_ENABLE_LOCK, - TOut_MS => 1); -- 100us + TOut_MS => 1); -- 200us + + if (Config.Has_DCC_Delay_Range) then + declare + Delay_Range : Word32; + begin + Read (PORT (P).DW5_LN0, Delay_Range); + Delay_Range := Delay_Range or PORT_TX_DW5_DCC_DELAY_RANGE_2; + Write (PORT (P).DW5_GRP, Delay_Range); + end if; Read (PORT (P).PCS_DW12_LN01, PCS); PCS := PCS and not PORT_PCS_LANE_STAGGER_MASK; @@ -471,6 +499,13 @@ begin if PLL in Valid_PLLs then Unset_Mask (PORT (PLL).PLL_ENABLE, PORT_PLL_ENABLE); + if Config.Has_Port_PLL_Pwr_En then + Unset_Mask (PORT (P).PLL_ENABLE, PORT_PLL_POWER_ENABLE); + Wait_Unset_Mask + (Register => PORT (P).PLL_ENABLE, + Mask => PORT_PLL_POWER_STATE, + TOut_MS => 1); -- 200us + end if; end if; end Free; diff --git a/common/broxton/hw-gfx-gma-power_and_clocks.adb b/common/broxton/hw-gfx-gma-power_and_clocks.adb index 8aa9a21..4e3fbc3 100644 --- a/common/broxton/hw-gfx-gma-power_and_clocks.adb +++ b/common/broxton/hw-gfx-gma-power_and_clocks.adb @@ -214,22 +214,12 @@ ---------------------------------------------------------------------------- - CDClk_Ref : constant := 19_200_000; - procedure Set_CDClk (Freq : Frequency_Type) with - Pre => - Freq = CDClk_Ref or Freq = 144_000_000 or Freq = 288_000_000 or - Freq = 384_000_000 or Freq = 576_000_000 or Freq = 624_000_000 + Pre => Config.Valid_CDClk (Freq) is VCO : constant Int64 := - CDClk_Ref * - (if Freq = CDClk_Ref then - 0 - elsif Freq = 624_000_000 then - 65 - else - 60); + Config.Broxton_CDClk_Ref * Config.CDClk_Ratio (Freq); CDCLK_CD2X_Div_Sel : constant Word32 := (case VCO / Freq is -- CDClk = VCO / 2 / Div when 2 => CDCLK_CD2X_DIV_SEL_1, @@ -255,7 +245,8 @@ Unset_And_Set_Mask (Register => BXT_DE_PLL_CTL, Mask_Unset => BXT_DE_PLL_RATIO_MASK, - Mask_Set => Word32 (VCO / CDClk_Ref)); + Mask_Set => (if Freq = Config.Broxton_CDClk_Ref then 0 else + Word32 (VCO / Config.Broxton_CDClk_Ref))); Write (Register => BXT_DE_PLL_ENABLE, Value => BXT_DE_PLL_PLL_ENABLE); @@ -297,7 +288,7 @@ -- Linux' i915 never keeps the PLL disabled but runs it -- at a "ratio" of 0 with CDClk at its reference clock. - Set_CDClk (CDClk_Ref); + Set_CDClk (Config.Broxton_CDClk_Ref); PW_Off (PW1); end Post_All_Off; diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index 4653ae9..972cfa8 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -40,7 +40,8 @@ Has_Internal_Display : constant Boolean := Internal_Display /= None; Internal_Is_EDP : constant Boolean := Internal_Display = DP; Have_DVI_I : constant Boolean := Analog_I2C_Port /= PCH_DAC; - Has_Presence_Straps : constant Boolean := CPU /= Broxton; + Is_Broxton : constant Boolean := CPU in Apollolake..Geminilake; + Has_Presence_Straps : constant Boolean := not Is_Broxton; Is_ULT : constant Boolean := CPU_Var = ULT; Is_ULX : constant Boolean := CPU_Var = ULX; Is_LP : constant Boolean := Is_ULT or Is_ULX; @@ -57,7 +58,7 @@ Has_Pipe_MSA_Misc : constant Boolean := CPU >= Haswell; Has_Pipeconf_Misc : constant Boolean := CPU >= Broadwell; Has_Pipeconf_BPC : constant Boolean := CPU /= Haswell; - Has_Plane_Control : constant Boolean := CPU >= Broxton; + Has_Plane_Control : constant Boolean := CPU >= Apollolake; Has_DSP_Linoff : constant Boolean := CPU <= Ivybridge; Has_PF_Pipe_Select : constant Boolean := CPU in Ivybridge .. Haswell; Has_Cursor_FBC_Control : constant Boolean := CPU >= Ivybridge; @@ -73,7 +74,7 @@ Has_PCH_Panel_Power : constant Boolean := CPU >= Ironlake; ----- PCH/FDI: --------- - Has_PCH : constant Boolean := CPU /= Broxton and CPU /= G45; + Has_PCH : constant Boolean := not Is_Broxton and CPU /= G45; Has_PCH_DAC : constant Boolean := CPU in Ironlake .. Ivybridge or (CPU in Haswell .. Broadwell and not Is_LP); @@ -103,7 +104,9 @@ and Is_LP) or CPU >= Skylake; - Has_DDI_PHYs : constant Boolean := CPU = Broxton; + Has_DDI_PHYs : constant Boolean := Is_Broxton; + Has_Dual_DDI_Phy_BC : constant Boolean := CPU = Apollolake; + Has_Port_PLL_Pwr_En : constant Boolean := CPU = Geminilake; Has_DDI_D : constant Boolean := CPU >= Haswell and not Is_LP and @@ -112,8 +115,8 @@ Has_DDI_D; Has_DDI_Buffer_Trans : constant Boolean := CPU >= Haswell and - CPU /= Broxton; - Has_Low_Voltage_Swing : constant Boolean := CPU >= Broxton; + not Is_Broxton; + Has_Low_Voltage_Swing : constant Boolean := CPU >= Apollolake; Has_Iboost_Config : constant Boolean := CPU >= Skylake; Use_KBL_DDI_Buf_Trans : constant Boolean := CPU = Kabylake; @@ -126,7 +129,7 @@ ----- GMBUS: ----------- Ungate_GMBUS_Unit_Level : constant Boolean := CPU >= Skylake; - GMBUS_Alternative_Pins : constant Boolean := CPU = Broxton; + GMBUS_Alternative_Pins : constant Boolean := Is_Broxton; Has_PCH_GMBUS : constant Boolean := CPU >= Ironlake; ----- Power: ----------- @@ -178,7 +181,8 @@ DP3 => CPU_Var = Normal, Analog => CPU_Var = Normal, others => True), - Broxton => + Apollolake | + Geminilake => (Internal => Config.Internal_Display = DP, DP1 => True, DP2 => True, @@ -234,11 +238,12 @@ Default_DDI_HDMI_Buffer_Translation : constant DDI_HDMI_Buf_Trans_Range := (case CPU is - when Haswell => 6, - when Broadwell => 7, - when Broxton => 8, - when Skylake => 8, - when others => 0); + when Haswell => 6, + when Broadwell => 7, + when Apollolake | + Geminilake => 8, + when Skylake => 8, + when others => 0); ---------------------------------------------------------------------------- @@ -250,7 +255,8 @@ Ivybridge => 400_000_000, when Haswell | Broadwell => (if Is_ULX then 337_500_000 else 450_000_000), - when Broxton => 288_000_000, + when Apollolake => 288_000_000, + when Geminilake => 158_400_000, when Skylake | Kabylake => 337_500_000); @@ -262,13 +268,34 @@ Ivybridge => 125_000_000, when Haswell | Broadwell => (if Is_LP then 24_000_000 else 125_000_000), - when Broxton => Frequency_Type'First, -- none needed + when Apollolake | + Geminilake => Frequency_Type'First, -- none needed when Skylake | Kabylake => 24_000_000); Raw_Clock : Frequency_Type := Default_RawClk_Freq with Part_Of => GMA.Config_State; + Broxton_CDClk_Ref : constant := 19_200_000; + + function Valid_CDClk (Freq : Frequency_Type) return Boolean is + (case CPU is + when Geminilake => + Freq = Broxton_CDClk_Ref or Freq = 79_200_000 or + Freq = 158_400_000 or Freq = 316_800_000, + when Apollolake => + Freq = Broxton_CDClk_Ref or Freq = 144_000_000 or + Freq = 288_000_000 or Freq = 384_000_000 or + Freq = 576_000_000 or Freq = 624_000_000, + when others => + True); + + function CDClk_Ratio (Freq : Frequency_Type) return Int64 is + (case CPU is + when Geminilake => 33, + when Apollolake => if Freq = 624_000_000 then 65 else 60, + when others => 1); + ---------------------------------------------------------------------------- -- Maximum source width with enabled scaler. This only accounts @@ -414,7 +441,8 @@ when Normal => Is_Broadwell (Device_Id), when ULT => Is_Broadwell_U (Device_Id), when ULX => Is_Broadwell_Y (Device_Id)), - when Broxton => (Device_Id and 16#fffe#) = 16#5a84#, + when Apollolake => (Device_Id and 16#fffe#) = 16#5a84#, + when Geminilake => (Device_Id and 16#fffe#) = 16#3184#, when Skylake => (case CPU_Var is when Normal => Is_Skylake (Device_Id), when ULT => Is_Skylake_U (Device_Id), diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads index 1220d1a..b14194b 100644 --- a/common/hw-gfx-gma-registers.ads +++ b/common/hw-gfx-gma-registers.ads @@ -413,6 +413,7 @@ BXT_PORT_TX_DW2_LN0_B, BXT_PORT_TX_DW3_LN0_B, BXT_PORT_TX_DW4_LN0_B, + BXT_PORT_TX_DW5_LN0_B, BXT_PORT_TX_DW14_LN0_B, BXT_PORT_TX_DW14_LN1_B, BXT_PORT_TX_DW14_LN2_B, @@ -422,6 +423,7 @@ BXT_PORT_TX_DW2_LN0_C, BXT_PORT_TX_DW3_LN0_C, BXT_PORT_TX_DW4_LN0_C, + BXT_PORT_TX_DW5_LN0_C, BXT_PORT_TX_DW14_LN0_C, BXT_PORT_TX_DW14_LN1_C, BXT_PORT_TX_DW14_LN2_C, @@ -431,11 +433,13 @@ BXT_PORT_TX_DW2_GRP_B, BXT_PORT_TX_DW3_GRP_B, BXT_PORT_TX_DW4_GRP_B, + BXT_PORT_TX_DW5_GRP_B, BXT_PORT_PCS_DW10_GRP_C, BXT_PORT_PCS_DW12_GRP_C, BXT_PORT_TX_DW2_GRP_C, BXT_PORT_TX_DW3_GRP_C, BXT_PORT_TX_DW4_GRP_C, + BXT_PORT_TX_DW5_GRP_C, BXT_DE_PLL_CTL, HTOTAL_EDP, HBLANK_EDP, @@ -722,6 +726,7 @@ BXT_PORT_TX_DW2_LN0_A, BXT_PORT_TX_DW3_LN0_A, BXT_PORT_TX_DW4_LN0_A, + BXT_PORT_TX_DW5_LN0_A, BXT_PORT_TX_DW14_LN0_A, BXT_PORT_TX_DW14_LN1_A, BXT_PORT_TX_DW14_LN2_A, @@ -730,7 +735,8 @@ BXT_PORT_PCS_DW12_GRP_A, BXT_PORT_TX_DW2_GRP_A, BXT_PORT_TX_DW3_GRP_A, - BXT_PORT_TX_DW4_GRP_A); + BXT_PORT_TX_DW4_GRP_A, + BXT_PORT_TX_DW5_GRP_A); pragma Warnings (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)", @@ -1351,6 +1357,7 @@ BXT_PORT_TX_DW2_LN0_A => 16#16_2508# / Register_Width, BXT_PORT_TX_DW3_LN0_A => 16#16_250c# / Register_Width, BXT_PORT_TX_DW4_LN0_A => 16#16_2510# / Register_Width, + BXT_PORT_TX_DW5_LN0_A => 16#16_2514# / Register_Width, BXT_PORT_TX_DW14_LN0_A => 16#16_2538# / Register_Width, BXT_PORT_TX_DW14_LN1_A => 16#16_25b8# / Register_Width, BXT_PORT_TX_DW14_LN2_A => 16#16_2738# / Register_Width, @@ -1358,9 +1365,11 @@ BXT_PORT_TX_DW2_GRP_A => 16#16_2d08# / Register_Width, BXT_PORT_TX_DW3_GRP_A => 16#16_2d0c# / Register_Width, BXT_PORT_TX_DW4_GRP_A => 16#16_2d10# / Register_Width, + BXT_PORT_TX_DW5_GRP_A => 16#16_2d14# / Register_Width, BXT_PORT_TX_DW2_LN0_B => 16#06_c508# / Register_Width, BXT_PORT_TX_DW3_LN0_B => 16#06_c50c# / Register_Width, BXT_PORT_TX_DW4_LN0_B => 16#06_c510# / Register_Width, + BXT_PORT_TX_DW5_LN0_B => 16#06_c514# / Register_Width, BXT_PORT_TX_DW14_LN0_B => 16#06_c538# / Register_Width, BXT_PORT_TX_DW14_LN1_B => 16#06_c5b8# / Register_Width, BXT_PORT_TX_DW14_LN2_B => 16#06_c738# / Register_Width, @@ -1368,9 +1377,11 @@ BXT_PORT_TX_DW2_GRP_B => 16#06_cd08# / Register_Width, BXT_PORT_TX_DW3_GRP_B => 16#06_cd0c# / Register_Width, BXT_PORT_TX_DW4_GRP_B => 16#06_cd10# / Register_Width, + BXT_PORT_TX_DW5_GRP_B => 16#06_cd14# / Register_Width, BXT_PORT_TX_DW2_LN0_C => 16#06_c908# / Register_Width, BXT_PORT_TX_DW3_LN0_C => 16#06_c90c# / Register_Width, BXT_PORT_TX_DW4_LN0_C => 16#06_c910# / Register_Width, + BXT_PORT_TX_DW5_LN0_C => 16#06_c914# / Register_Width, BXT_PORT_TX_DW14_LN0_C => 16#06_c938# / Register_Width, BXT_PORT_TX_DW14_LN1_C => 16#06_c9b8# / Register_Width, BXT_PORT_TX_DW14_LN2_C => 16#06_cb38# / Register_Width, @@ -1378,6 +1389,7 @@ BXT_PORT_TX_DW2_GRP_C => 16#06_cf08# / Register_Width, BXT_PORT_TX_DW3_GRP_C => 16#06_cf0c# / Register_Width, BXT_PORT_TX_DW4_GRP_C => 16#06_cf10# / Register_Width, + BXT_PORT_TX_DW5_GRP_C => 16#06_cf14# / Register_Width, -- Broxton DDI PHY ref registers BXT_PORT_REF_DW3_A => 16#16_218c# / Register_Width, diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads index 7ca0ca1..c282935 100644 --- a/common/hw-gfx-gma.ads +++ b/common/hw-gfx-gma.ads @@ -41,7 +41,8 @@ Ivybridge, Haswell, Broadwell, - Broxton, + Apollolake, + Geminilake, Skylake, Kabylake); diff --git a/configs/broxton b/configs/apollolake similarity index 83% rename from configs/broxton rename to configs/apollolake index b5f1f9a..24e0847 100644 --- a/configs/broxton +++ b/configs/apollolake @@ -1,4 +1,4 @@ -CONFIG_GFX_GMA_CPU = Broxton +CONFIG_GFX_GMA_CPU = Apollolake CONFIG_GFX_GMA_CPU_VARIANT = Normal # N/A CONFIG_GFX_GMA_INTERNAL_PORT = DP CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC # N/A diff --git a/configs/broxton b/configs/geminilake similarity index 83% copy from configs/broxton copy to configs/geminilake index b5f1f9a..be34de7 100644 --- a/configs/broxton +++ b/configs/geminilake @@ -1,4 +1,4 @@ -CONFIG_GFX_GMA_CPU = Broxton +CONFIG_GFX_GMA_CPU = Geminilake CONFIG_GFX_GMA_CPU_VARIANT = Normal # N/A CONFIG_GFX_GMA_INTERNAL_PORT = DP CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC # N/A -- To view, visit https://review.coreboot.org/c/libgfxinit/+/31611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I84347130fc3fcaf33d9f3d84fab47c67899c792d Gerrit-Change-Number: 31611 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: for review d945gclf/Kconig and devicetree.cb . these files are modif...

by junaid (Code Review)

junaid has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30798 Change subject: for review d945gclf/Kconig and devicetree.cb . these files are modified according to the superIO chip Winbond w83627DHG ...................................................................... for review d945gclf/Kconig and devicetree.cb . these files are modified according to the superIO chip Winbond w83627DHG Change-Id: I1449d9351bd1b76ecad16e6d81c501c1d4dd80f5 Signed-off-by: junaid <junaidimpex(a)gmail.com> --- M src/mainboard/intel/d945gclf/Kconfig M src/mainboard/intel/d945gclf/devicetree.cb 2 files changed, 37 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/30798/1 diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig index 70fa848..906dd01 100644 --- a/src/mainboard/intel/d945gclf/Kconfig +++ b/src/mainboard/intel/d945gclf/Kconfig @@ -20,7 +20,8 @@ select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GC select SOUTHBRIDGE_INTEL_I82801GX - select SUPERIO_SMSC_LPC47M15X +## changed as per Advantech SOM 4461 + select SUPERIO_WINBOND_W83627DHG select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index 90c517f..864775a 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -65,44 +65,42 @@ device pci 1d.1 on end # USB UHCI device pci 1d.2 on end # USB UHCI device pci 1d.3 off end # USB UHCI - device pci 1d.7 on end # USB2 EHCI - device pci 1e.0 on end # PCI bridge - device pci 1e.2 off end # AC'97 Audio + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on end # PCI bridge + device pci 1e.2 off end # AC'97 Audio device pci 1e.3 off end # AC'97 Modem device pci 1f.0 on # LPC bridge - chip superio/smsc/lpc47m15x - device pnp 2e.0 off # Floppy - end - device pnp 2e.3 off # Parport - end - device pnp 2e.4 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 on - io 0x60 = 0x2f8 - irq 0x70 = 3 - irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq - end - device pnp 2e.7 on # Keyboard+Mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - irq 0xf0 = 0x82 # HW accel A20. - end - device pnp 2e.8 on # GAME - # all default - end - device pnp 2e.a on # PME - end - device pnp 2e.b on # MPU - end - end - end + chip superio/winbond/w83627dhg + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel Port + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard,Mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + #device pnp 2e.6 off end # SPI + device pnp 2e.307 off end # GPIO6 + device pnp 2e.8 off end # WDTO, PLED + device pnp 2e.009 off end # GPIO2 + device pnp 2e.109 off end # GPIO3 + device pnp 2e.209 off end # GPIO4 + device pnp 2e.309 off end # GPIO5 + device pnp 2e.A off end # ACPI + device pnp 2e.B off end # HW Monitor + end # w83627dhg + end device pci 1f.1 off end # IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - end - end + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus + end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/30798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1449d9351bd1b76ecad16e6d81c501c1d4dd80f5 Gerrit-Change-Number: 30798 Gerrit-PatchSet: 1 Gerrit-Owner: junaid <junaidimpex(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2019