February 2019 - coreboot-gerrit

Change in ...coreboot[master]: x86/acpi_s3: Remove trailing dots from debug message

by Paul Menzel (Code Review)

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30806 Change subject: x86/acpi_s3: Remove trailing dots from debug message ...................................................................... x86/acpi_s3: Remove trailing dots from debug message The dot is not needed, as it is no sentence and followed by a line break. Change-Id: I3905853eb7039f9c6d2486a77da47a4460276624 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/arch/x86/acpi_s3.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/30806/1 diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index ad9fe00..07c0332 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -34,10 +34,10 @@ { if (acpi_slp_type < 0) { if (romstage_handoff_is_resume()) { - printk(BIOS_DEBUG, "S3 Resume.\n"); + printk(BIOS_DEBUG, "S3 Resume\n"); acpi_slp_type = ACPI_S3; } else { - printk(BIOS_DEBUG, "Normal boot.\n"); + printk(BIOS_DEBUG, "Normal boot\n"); acpi_slp_type = ACPI_S0; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/30806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3905853eb7039f9c6d2486a77da47a4460276624 Gerrit-Change-Number: 30806 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

4 months, 1 week

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Change in ...coreboot[master]: mb/lenovo/x1_carbon_gen1: Swap Fn-F2 and Fn-F3

by Nicola Corna (Code Review)

Nicola Corna has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31470 Change subject: mb/lenovo/x1_carbon_gen1: Swap Fn-F2 and Fn-F3 ...................................................................... mb/lenovo/x1_carbon_gen1: Swap Fn-F2 and Fn-F3 thinkpad_acpi expects the battery hotkey (KEY_BATTERY) on scancode 0x01 (Fn-F2) and the lock hotkey (KEY_COFFEE) on scancode 0x02 (Fn-F3). This is true for most of the Thinkpads, however on the X1 Carbon Gen1 (and possibly others), the battery hotkey is not present and the lock one is instead on Fn-F3. Swap the RHK calls in _Q11 (Fn-F2) and _Q12 (Fn-F3) to fix the issue, so that the lock hotkey is on F3 and the battery one is on F2 (even if it's not marked so). Change-Id: Ib2d96be1a7815d7d03e6e8c6d300fd671c8598ca Signed-off-by: Nicola Corna <nicola(a)corna.info> --- M src/ec/lenovo/h8/acpi/ec.asl M src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/31470/1 diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index 327a2cf..6ffba5e 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -197,12 +197,20 @@ Method (_Q11, 0, NotSerialized) { +#if IS_ENABLED(EC_LENOVO_H8_SWAP_FNF2_FNF3) + ^HKEY.RHK (0x03) +#else ^HKEY.RHK (0x02) +#endif } Method (_Q12, 0, NotSerialized) { +#if IS_ENABLED(EC_LENOVO_H8_SWAP_FNF2_FNF3) + ^HKEY.RHK (0x02) +#else ^HKEY.RHK (0x03) +#endif } Method (_Q64, 0, NotSerialized) diff --git a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl index 8c9bd5a..2696607 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl +++ b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl @@ -20,6 +20,7 @@ #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 +#define EC_LENOVO_H8_SWAP_FNF2_FNF3 1 #include <arch/acpi.h> DefinitionBlock( -- To view, visit https://review.coreboot.org/c/coreboot/+/31470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2d96be1a7815d7d03e6e8c6d300fd671c8598ca Gerrit-Change-Number: 31470 Gerrit-PatchSet: 1 Gerrit-Owner: Nicola Corna <nicola(a)corna.info> Gerrit-MessageType: newchange

4 months, 3 weeks

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Change in ...libgfxinit[master]: [WIP] gma: Add Gemini Lake support

by Nico Huber (Code Review)

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/31611 Change subject: [WIP] gma: Add Gemini Lake support ...................................................................... [WIP] gma: Add Gemini Lake support Change-Id: I84347130fc3fcaf33d9f3d84fab47c67899c792d Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M common/Makefile.inc M common/broxton/hw-gfx-gma-ddi_phy.ads M common/broxton/hw-gfx-gma-plls.adb M common/broxton/hw-gfx-gma-power_and_clocks.adb M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma-registers.ads M common/hw-gfx-gma.ads R configs/apollolake C configs/geminilake 9 files changed, 109 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/11/31611/1 diff --git a/common/Makefile.inc b/common/Makefile.inc index 61955eb..cfb2dfa 100644 --- a/common/Makefile.inc +++ b/common/Makefile.inc @@ -68,7 +68,7 @@ subdirs-y += ironlake else ifneq ($(filter Haswell Broadwell,$(CONFIG_GFX_GMA_CPU)),) subdirs-y += haswell_shared haswell -else ifneq ($(filter Broxton,$(CONFIG_GFX_GMA_CPU)),) +else ifneq ($(filter Apollolake Geminilake,$(CONFIG_GFX_GMA_CPU)),) subdirs-y += haswell_shared broxton else ifneq ($(filter Skylake Kabylake,$(CONFIG_GFX_GMA_CPU)),) subdirs-y += haswell_shared skylake diff --git a/common/broxton/hw-gfx-gma-ddi_phy.ads b/common/broxton/hw-gfx-gma-ddi_phy.ads index fc6cacf..e6301bf 100644 --- a/common/broxton/hw-gfx-gma-ddi_phy.ads +++ b/common/broxton/hw-gfx-gma-ddi_phy.ads @@ -16,7 +16,7 @@ private package HW.GFX.GMA.DDI_Phy is - type T is (BC, A); + type T is (BC, A, C); procedure Power_On (Phy : T); procedure Power_Off (Phy : T); diff --git a/common/broxton/hw-gfx-gma-plls.adb b/common/broxton/hw-gfx-gma-plls.adb index 087ff12..f7ecc05 100644 --- a/common/broxton/hw-gfx-gma-plls.adb +++ b/common/broxton/hw-gfx-gma-plls.adb @@ -170,6 +170,8 @@ PLL_10 : Registers_Index; PCS_DW12_LN01 : Registers_Index; PCS_DW12_GRP : Registers_Index; + TX_DW5_LN0 : Registers_Index; + TX_DW5_GRP : Registers_Index; end record; type Port_PLL_Array is array (Valid_PLLs) of Port_PLL_Regs; @@ -187,7 +189,9 @@ PLL_9 => BXT_PORT_PLL_9_A, PLL_10 => BXT_PORT_PLL_10_A, PCS_DW12_LN01 => BXT_PORT_PCS_DW12_01_A, - PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_A), + PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_A, + TX_DW5_LN0 => BXT_PORT_TX_DW5_LN0_A, + TX_DW5_GRP => BXT_PORT_TX_DW5_GRP_A), DPLL_B => (PLL_ENABLE => BXT_PORT_PLL_ENABLE_B, PLL_EBB_0 => BXT_PORT_PLL_EBB_0_B, @@ -201,7 +205,9 @@ PLL_9 => BXT_PORT_PLL_9_B, PLL_10 => BXT_PORT_PLL_10_B, PCS_DW12_LN01 => BXT_PORT_PCS_DW12_01_B, - PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_B), + PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_B, + TX_DW5_LN0 => BXT_PORT_TX_DW5_LN0_B, + TX_DW5_GRP => BXT_PORT_TX_DW5_GRP_B), DPLL_C => (PLL_ENABLE => BXT_PORT_PLL_ENABLE_C, PLL_EBB_0 => BXT_PORT_PLL_EBB_0_C, @@ -215,11 +221,15 @@ PLL_9 => BXT_PORT_PLL_9_C, PLL_10 => BXT_PORT_PLL_10_C, PCS_DW12_LN01 => BXT_PORT_PCS_DW12_01_C, - PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_C)); + PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_C, + TX_DW5_LN0 => BXT_PORT_TX_DW5_LN0_C, + TX_DW5_GRP => BXT_PORT_TX_DW5_GRP_C)); PORT_PLL_ENABLE : constant := 1 * 2 ** 31; PORT_PLL_ENABLE_LOCK : constant := 1 * 2 ** 30; PORT_PLL_ENABLE_REF_SEL : constant := 1 * 2 ** 27; + PORT_PLL_POWER_ENABLE : constant := 1 * 2 ** 26; + PORT_PLL_POWER_STATE : constant := 1 * 2 ** 25; PORT_PLL_EBB0_P1_SHIFT : constant := 13; PORT_PLL_EBB0_P1_MASK : constant := 16#07# * 2 ** 13; @@ -336,8 +346,17 @@ begin pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); - Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_ENABLE_REF_SEL); -- non-SSC ref - Unset_Mask (PORT (P).PLL_EBB_4, PORT_PLL_EBB4_10BIT_CLK_ENABLE); + Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_ENABLE_REF_SEL); -- non-SSC ref + + if Config.Has_Port_PLL_Pwr_En then + Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_POWER_ENABLE); + Wait_Set_Mask + (Register => PORT (P).PLL_ENABLE, + Mask => PORT_PLL_POWER_STATE, + TOut_MS => 1); -- 200us + end if; + + Unset_Mask (PORT (P).PLL_EBB_4, PORT_PLL_EBB4_10BIT_CLK_ENABLE); Unset_And_Set_Mask (Register => PORT (P).PLL_EBB_0, @@ -388,7 +407,16 @@ Wait_Set_Mask (Register => PORT (P).PLL_ENABLE, Mask => PORT_PLL_ENABLE_LOCK, - TOut_MS => 1); -- 100us + TOut_MS => 1); -- 200us + + if (Config.Has_DCC_Delay_Range) then + declare + Delay_Range : Word32; + begin + Read (PORT (P).DW5_LN0, Delay_Range); + Delay_Range := Delay_Range or PORT_TX_DW5_DCC_DELAY_RANGE_2; + Write (PORT (P).DW5_GRP, Delay_Range); + end if; Read (PORT (P).PCS_DW12_LN01, PCS); PCS := PCS and not PORT_PCS_LANE_STAGGER_MASK; @@ -471,6 +499,13 @@ begin if PLL in Valid_PLLs then Unset_Mask (PORT (PLL).PLL_ENABLE, PORT_PLL_ENABLE); + if Config.Has_Port_PLL_Pwr_En then + Unset_Mask (PORT (P).PLL_ENABLE, PORT_PLL_POWER_ENABLE); + Wait_Unset_Mask + (Register => PORT (P).PLL_ENABLE, + Mask => PORT_PLL_POWER_STATE, + TOut_MS => 1); -- 200us + end if; end if; end Free; diff --git a/common/broxton/hw-gfx-gma-power_and_clocks.adb b/common/broxton/hw-gfx-gma-power_and_clocks.adb index 8aa9a21..4e3fbc3 100644 --- a/common/broxton/hw-gfx-gma-power_and_clocks.adb +++ b/common/broxton/hw-gfx-gma-power_and_clocks.adb @@ -214,22 +214,12 @@ ---------------------------------------------------------------------------- - CDClk_Ref : constant := 19_200_000; - procedure Set_CDClk (Freq : Frequency_Type) with - Pre => - Freq = CDClk_Ref or Freq = 144_000_000 or Freq = 288_000_000 or - Freq = 384_000_000 or Freq = 576_000_000 or Freq = 624_000_000 + Pre => Config.Valid_CDClk (Freq) is VCO : constant Int64 := - CDClk_Ref * - (if Freq = CDClk_Ref then - 0 - elsif Freq = 624_000_000 then - 65 - else - 60); + Config.Broxton_CDClk_Ref * Config.CDClk_Ratio (Freq); CDCLK_CD2X_Div_Sel : constant Word32 := (case VCO / Freq is -- CDClk = VCO / 2 / Div when 2 => CDCLK_CD2X_DIV_SEL_1, @@ -255,7 +245,8 @@ Unset_And_Set_Mask (Register => BXT_DE_PLL_CTL, Mask_Unset => BXT_DE_PLL_RATIO_MASK, - Mask_Set => Word32 (VCO / CDClk_Ref)); + Mask_Set => (if Freq = Config.Broxton_CDClk_Ref then 0 else + Word32 (VCO / Config.Broxton_CDClk_Ref))); Write (Register => BXT_DE_PLL_ENABLE, Value => BXT_DE_PLL_PLL_ENABLE); @@ -297,7 +288,7 @@ -- Linux' i915 never keeps the PLL disabled but runs it -- at a "ratio" of 0 with CDClk at its reference clock. - Set_CDClk (CDClk_Ref); + Set_CDClk (Config.Broxton_CDClk_Ref); PW_Off (PW1); end Post_All_Off; diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index 4653ae9..972cfa8 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -40,7 +40,8 @@ Has_Internal_Display : constant Boolean := Internal_Display /= None; Internal_Is_EDP : constant Boolean := Internal_Display = DP; Have_DVI_I : constant Boolean := Analog_I2C_Port /= PCH_DAC; - Has_Presence_Straps : constant Boolean := CPU /= Broxton; + Is_Broxton : constant Boolean := CPU in Apollolake..Geminilake; + Has_Presence_Straps : constant Boolean := not Is_Broxton; Is_ULT : constant Boolean := CPU_Var = ULT; Is_ULX : constant Boolean := CPU_Var = ULX; Is_LP : constant Boolean := Is_ULT or Is_ULX; @@ -57,7 +58,7 @@ Has_Pipe_MSA_Misc : constant Boolean := CPU >= Haswell; Has_Pipeconf_Misc : constant Boolean := CPU >= Broadwell; Has_Pipeconf_BPC : constant Boolean := CPU /= Haswell; - Has_Plane_Control : constant Boolean := CPU >= Broxton; + Has_Plane_Control : constant Boolean := CPU >= Apollolake; Has_DSP_Linoff : constant Boolean := CPU <= Ivybridge; Has_PF_Pipe_Select : constant Boolean := CPU in Ivybridge .. Haswell; Has_Cursor_FBC_Control : constant Boolean := CPU >= Ivybridge; @@ -73,7 +74,7 @@ Has_PCH_Panel_Power : constant Boolean := CPU >= Ironlake; ----- PCH/FDI: --------- - Has_PCH : constant Boolean := CPU /= Broxton and CPU /= G45; + Has_PCH : constant Boolean := not Is_Broxton and CPU /= G45; Has_PCH_DAC : constant Boolean := CPU in Ironlake .. Ivybridge or (CPU in Haswell .. Broadwell and not Is_LP); @@ -103,7 +104,9 @@ and Is_LP) or CPU >= Skylake; - Has_DDI_PHYs : constant Boolean := CPU = Broxton; + Has_DDI_PHYs : constant Boolean := Is_Broxton; + Has_Dual_DDI_Phy_BC : constant Boolean := CPU = Apollolake; + Has_Port_PLL_Pwr_En : constant Boolean := CPU = Geminilake; Has_DDI_D : constant Boolean := CPU >= Haswell and not Is_LP and @@ -112,8 +115,8 @@ Has_DDI_D; Has_DDI_Buffer_Trans : constant Boolean := CPU >= Haswell and - CPU /= Broxton; - Has_Low_Voltage_Swing : constant Boolean := CPU >= Broxton; + not Is_Broxton; + Has_Low_Voltage_Swing : constant Boolean := CPU >= Apollolake; Has_Iboost_Config : constant Boolean := CPU >= Skylake; Use_KBL_DDI_Buf_Trans : constant Boolean := CPU = Kabylake; @@ -126,7 +129,7 @@ ----- GMBUS: ----------- Ungate_GMBUS_Unit_Level : constant Boolean := CPU >= Skylake; - GMBUS_Alternative_Pins : constant Boolean := CPU = Broxton; + GMBUS_Alternative_Pins : constant Boolean := Is_Broxton; Has_PCH_GMBUS : constant Boolean := CPU >= Ironlake; ----- Power: ----------- @@ -178,7 +181,8 @@ DP3 => CPU_Var = Normal, Analog => CPU_Var = Normal, others => True), - Broxton => + Apollolake | + Geminilake => (Internal => Config.Internal_Display = DP, DP1 => True, DP2 => True, @@ -234,11 +238,12 @@ Default_DDI_HDMI_Buffer_Translation : constant DDI_HDMI_Buf_Trans_Range := (case CPU is - when Haswell => 6, - when Broadwell => 7, - when Broxton => 8, - when Skylake => 8, - when others => 0); + when Haswell => 6, + when Broadwell => 7, + when Apollolake | + Geminilake => 8, + when Skylake => 8, + when others => 0); ---------------------------------------------------------------------------- @@ -250,7 +255,8 @@ Ivybridge => 400_000_000, when Haswell | Broadwell => (if Is_ULX then 337_500_000 else 450_000_000), - when Broxton => 288_000_000, + when Apollolake => 288_000_000, + when Geminilake => 158_400_000, when Skylake | Kabylake => 337_500_000); @@ -262,13 +268,34 @@ Ivybridge => 125_000_000, when Haswell | Broadwell => (if Is_LP then 24_000_000 else 125_000_000), - when Broxton => Frequency_Type'First, -- none needed + when Apollolake | + Geminilake => Frequency_Type'First, -- none needed when Skylake | Kabylake => 24_000_000); Raw_Clock : Frequency_Type := Default_RawClk_Freq with Part_Of => GMA.Config_State; + Broxton_CDClk_Ref : constant := 19_200_000; + + function Valid_CDClk (Freq : Frequency_Type) return Boolean is + (case CPU is + when Geminilake => + Freq = Broxton_CDClk_Ref or Freq = 79_200_000 or + Freq = 158_400_000 or Freq = 316_800_000, + when Apollolake => + Freq = Broxton_CDClk_Ref or Freq = 144_000_000 or + Freq = 288_000_000 or Freq = 384_000_000 or + Freq = 576_000_000 or Freq = 624_000_000, + when others => + True); + + function CDClk_Ratio (Freq : Frequency_Type) return Int64 is + (case CPU is + when Geminilake => 33, + when Apollolake => if Freq = 624_000_000 then 65 else 60, + when others => 1); + ---------------------------------------------------------------------------- -- Maximum source width with enabled scaler. This only accounts @@ -414,7 +441,8 @@ when Normal => Is_Broadwell (Device_Id), when ULT => Is_Broadwell_U (Device_Id), when ULX => Is_Broadwell_Y (Device_Id)), - when Broxton => (Device_Id and 16#fffe#) = 16#5a84#, + when Apollolake => (Device_Id and 16#fffe#) = 16#5a84#, + when Geminilake => (Device_Id and 16#fffe#) = 16#3184#, when Skylake => (case CPU_Var is when Normal => Is_Skylake (Device_Id), when ULT => Is_Skylake_U (Device_Id), diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads index 1220d1a..b14194b 100644 --- a/common/hw-gfx-gma-registers.ads +++ b/common/hw-gfx-gma-registers.ads @@ -413,6 +413,7 @@ BXT_PORT_TX_DW2_LN0_B, BXT_PORT_TX_DW3_LN0_B, BXT_PORT_TX_DW4_LN0_B, + BXT_PORT_TX_DW5_LN0_B, BXT_PORT_TX_DW14_LN0_B, BXT_PORT_TX_DW14_LN1_B, BXT_PORT_TX_DW14_LN2_B, @@ -422,6 +423,7 @@ BXT_PORT_TX_DW2_LN0_C, BXT_PORT_TX_DW3_LN0_C, BXT_PORT_TX_DW4_LN0_C, + BXT_PORT_TX_DW5_LN0_C, BXT_PORT_TX_DW14_LN0_C, BXT_PORT_TX_DW14_LN1_C, BXT_PORT_TX_DW14_LN2_C, @@ -431,11 +433,13 @@ BXT_PORT_TX_DW2_GRP_B, BXT_PORT_TX_DW3_GRP_B, BXT_PORT_TX_DW4_GRP_B, + BXT_PORT_TX_DW5_GRP_B, BXT_PORT_PCS_DW10_GRP_C, BXT_PORT_PCS_DW12_GRP_C, BXT_PORT_TX_DW2_GRP_C, BXT_PORT_TX_DW3_GRP_C, BXT_PORT_TX_DW4_GRP_C, + BXT_PORT_TX_DW5_GRP_C, BXT_DE_PLL_CTL, HTOTAL_EDP, HBLANK_EDP, @@ -722,6 +726,7 @@ BXT_PORT_TX_DW2_LN0_A, BXT_PORT_TX_DW3_LN0_A, BXT_PORT_TX_DW4_LN0_A, + BXT_PORT_TX_DW5_LN0_A, BXT_PORT_TX_DW14_LN0_A, BXT_PORT_TX_DW14_LN1_A, BXT_PORT_TX_DW14_LN2_A, @@ -730,7 +735,8 @@ BXT_PORT_PCS_DW12_GRP_A, BXT_PORT_TX_DW2_GRP_A, BXT_PORT_TX_DW3_GRP_A, - BXT_PORT_TX_DW4_GRP_A); + BXT_PORT_TX_DW4_GRP_A, + BXT_PORT_TX_DW5_GRP_A); pragma Warnings (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)", @@ -1351,6 +1357,7 @@ BXT_PORT_TX_DW2_LN0_A => 16#16_2508# / Register_Width, BXT_PORT_TX_DW3_LN0_A => 16#16_250c# / Register_Width, BXT_PORT_TX_DW4_LN0_A => 16#16_2510# / Register_Width, + BXT_PORT_TX_DW5_LN0_A => 16#16_2514# / Register_Width, BXT_PORT_TX_DW14_LN0_A => 16#16_2538# / Register_Width, BXT_PORT_TX_DW14_LN1_A => 16#16_25b8# / Register_Width, BXT_PORT_TX_DW14_LN2_A => 16#16_2738# / Register_Width, @@ -1358,9 +1365,11 @@ BXT_PORT_TX_DW2_GRP_A => 16#16_2d08# / Register_Width, BXT_PORT_TX_DW3_GRP_A => 16#16_2d0c# / Register_Width, BXT_PORT_TX_DW4_GRP_A => 16#16_2d10# / Register_Width, + BXT_PORT_TX_DW5_GRP_A => 16#16_2d14# / Register_Width, BXT_PORT_TX_DW2_LN0_B => 16#06_c508# / Register_Width, BXT_PORT_TX_DW3_LN0_B => 16#06_c50c# / Register_Width, BXT_PORT_TX_DW4_LN0_B => 16#06_c510# / Register_Width, + BXT_PORT_TX_DW5_LN0_B => 16#06_c514# / Register_Width, BXT_PORT_TX_DW14_LN0_B => 16#06_c538# / Register_Width, BXT_PORT_TX_DW14_LN1_B => 16#06_c5b8# / Register_Width, BXT_PORT_TX_DW14_LN2_B => 16#06_c738# / Register_Width, @@ -1368,9 +1377,11 @@ BXT_PORT_TX_DW2_GRP_B => 16#06_cd08# / Register_Width, BXT_PORT_TX_DW3_GRP_B => 16#06_cd0c# / Register_Width, BXT_PORT_TX_DW4_GRP_B => 16#06_cd10# / Register_Width, + BXT_PORT_TX_DW5_GRP_B => 16#06_cd14# / Register_Width, BXT_PORT_TX_DW2_LN0_C => 16#06_c908# / Register_Width, BXT_PORT_TX_DW3_LN0_C => 16#06_c90c# / Register_Width, BXT_PORT_TX_DW4_LN0_C => 16#06_c910# / Register_Width, + BXT_PORT_TX_DW5_LN0_C => 16#06_c914# / Register_Width, BXT_PORT_TX_DW14_LN0_C => 16#06_c938# / Register_Width, BXT_PORT_TX_DW14_LN1_C => 16#06_c9b8# / Register_Width, BXT_PORT_TX_DW14_LN2_C => 16#06_cb38# / Register_Width, @@ -1378,6 +1389,7 @@ BXT_PORT_TX_DW2_GRP_C => 16#06_cf08# / Register_Width, BXT_PORT_TX_DW3_GRP_C => 16#06_cf0c# / Register_Width, BXT_PORT_TX_DW4_GRP_C => 16#06_cf10# / Register_Width, + BXT_PORT_TX_DW5_GRP_C => 16#06_cf14# / Register_Width, -- Broxton DDI PHY ref registers BXT_PORT_REF_DW3_A => 16#16_218c# / Register_Width, diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads index 7ca0ca1..c282935 100644 --- a/common/hw-gfx-gma.ads +++ b/common/hw-gfx-gma.ads @@ -41,7 +41,8 @@ Ivybridge, Haswell, Broadwell, - Broxton, + Apollolake, + Geminilake, Skylake, Kabylake); diff --git a/configs/broxton b/configs/apollolake similarity index 83% rename from configs/broxton rename to configs/apollolake index b5f1f9a..24e0847 100644 --- a/configs/broxton +++ b/configs/apollolake @@ -1,4 +1,4 @@ -CONFIG_GFX_GMA_CPU = Broxton +CONFIG_GFX_GMA_CPU = Apollolake CONFIG_GFX_GMA_CPU_VARIANT = Normal # N/A CONFIG_GFX_GMA_INTERNAL_PORT = DP CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC # N/A diff --git a/configs/broxton b/configs/geminilake similarity index 83% copy from configs/broxton copy to configs/geminilake index b5f1f9a..be34de7 100644 --- a/configs/broxton +++ b/configs/geminilake @@ -1,4 +1,4 @@ -CONFIG_GFX_GMA_CPU = Broxton +CONFIG_GFX_GMA_CPU = Geminilake CONFIG_GFX_GMA_CPU_VARIANT = Normal # N/A CONFIG_GFX_GMA_INTERNAL_PORT = DP CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC # N/A -- To view, visit https://review.coreboot.org/c/libgfxinit/+/31611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I84347130fc3fcaf33d9f3d84fab47c67899c792d Gerrit-Change-Number: 31611 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: for review d945gclf/Kconig and devicetree.cb . these files are modif...

by junaid (Code Review)

junaid has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30798 Change subject: for review d945gclf/Kconig and devicetree.cb . these files are modified according to the superIO chip Winbond w83627DHG ...................................................................... for review d945gclf/Kconig and devicetree.cb . these files are modified according to the superIO chip Winbond w83627DHG Change-Id: I1449d9351bd1b76ecad16e6d81c501c1d4dd80f5 Signed-off-by: junaid <junaidimpex(a)gmail.com> --- M src/mainboard/intel/d945gclf/Kconfig M src/mainboard/intel/d945gclf/devicetree.cb 2 files changed, 37 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/30798/1 diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig index 70fa848..906dd01 100644 --- a/src/mainboard/intel/d945gclf/Kconfig +++ b/src/mainboard/intel/d945gclf/Kconfig @@ -20,7 +20,8 @@ select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GC select SOUTHBRIDGE_INTEL_I82801GX - select SUPERIO_SMSC_LPC47M15X +## changed as per Advantech SOM 4461 + select SUPERIO_WINBOND_W83627DHG select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index 90c517f..864775a 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -65,44 +65,42 @@ device pci 1d.1 on end # USB UHCI device pci 1d.2 on end # USB UHCI device pci 1d.3 off end # USB UHCI - device pci 1d.7 on end # USB2 EHCI - device pci 1e.0 on end # PCI bridge - device pci 1e.2 off end # AC'97 Audio + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on end # PCI bridge + device pci 1e.2 off end # AC'97 Audio device pci 1e.3 off end # AC'97 Modem device pci 1f.0 on # LPC bridge - chip superio/smsc/lpc47m15x - device pnp 2e.0 off # Floppy - end - device pnp 2e.3 off # Parport - end - device pnp 2e.4 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 on - io 0x60 = 0x2f8 - irq 0x70 = 3 - irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq - end - device pnp 2e.7 on # Keyboard+Mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - irq 0xf0 = 0x82 # HW accel A20. - end - device pnp 2e.8 on # GAME - # all default - end - device pnp 2e.a on # PME - end - device pnp 2e.b on # MPU - end - end - end + chip superio/winbond/w83627dhg + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel Port + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard,Mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + #device pnp 2e.6 off end # SPI + device pnp 2e.307 off end # GPIO6 + device pnp 2e.8 off end # WDTO, PLED + device pnp 2e.009 off end # GPIO2 + device pnp 2e.109 off end # GPIO3 + device pnp 2e.209 off end # GPIO4 + device pnp 2e.309 off end # GPIO5 + device pnp 2e.A off end # ACPI + device pnp 2e.B off end # HW Monitor + end # w83627dhg + end device pci 1f.1 off end # IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - end - end + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus + end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/30798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1449d9351bd1b76ecad16e6d81c501c1d4dd80f5 Gerrit-Change-Number: 30798 Gerrit-PatchSet: 1 Gerrit-Owner: junaid <junaidimpex(a)gmail.com> Gerrit-MessageType: newchange

5 months

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Change in ...coreboot[master]: intel/apollolake: Add early smbus support

by Christian Gmeiner (Code Review)

Christian Gmeiner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31461 Change subject: intel/apollolake: Add early smbus support ...................................................................... intel/apollolake: Add early smbus support Change-Id: Ic472c71998064d09c9caddc5c80c01e85a381c69 Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/apollolake/include/soc/smbus.h 3 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/31461/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 19cd296..f7ddc6f 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -85,6 +85,7 @@ select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_P2SB select SOC_INTEL_COMMON_BLOCK_PMC + select SOC_INTEL_COMMON_BLOCK_SMBUS select SOC_INTEL_COMMON_BLOCK_SRAM select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_SA diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index cf3e839..99a9467 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -23,6 +23,7 @@ #include <intelblocks/p2sb.h> #include <intelblocks/pcr.h> #include <intelblocks/rtc.h> +#include <intelblocks/smbus.h> #include <intelblocks/systemagent.h> #include <intelblocks/pmclib.h> #include <intelblocks/tco.h> @@ -112,6 +113,9 @@ /* Program TCO Timer Halt */ tco_configure(); + /* Program SMBUS_BASE_ADDRESS and Enable it */ + smbus_common_init(); + /* Use Nx and paging to prevent the frontend from writing back dirty * cache-as-ram lines to backing store that doesn't exist when the L1I * speculatively fetches a line that is sitting in the L1D. */ diff --git a/src/soc/intel/apollolake/include/soc/smbus.h b/src/soc/intel/apollolake/include/soc/smbus.h index 4b252d6..a4ff451 100644 --- a/src/soc/intel/apollolake/include/soc/smbus.h +++ b/src/soc/intel/apollolake/include/soc/smbus.h @@ -16,6 +16,9 @@ #ifndef _SOC_APOLLOLAKE_SMBUS_H_ #define _SOC_APOLLOLAKE_SMBUS_H_ +/* PCI Configuration Space (D31:F3): SMBus */ +#define SMB_RCV_SLVA 0x09 + /* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ #define TCO1_STS 0x04 #define TCO_TIMEOUT (1 << 3) @@ -25,4 +28,7 @@ #define TCO_LOCK (1 << 12) #define TCO_TMR_HLT (1 << 11) +/* SMBus I/O bits. */ +#define SMBUS_SLAVE_ADDR 0x24 + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic472c71998064d09c9caddc5c80c01e85a381c69 Gerrit-Change-Number: 31461 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Gmeiner <christian.gmeiner(a)gmail.com> Gerrit-MessageType: newchange

5 months

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Change in ...coreboot[master]: superio/nsc: Use common defines for NSC PC8xxxx chips

by Peter Lemenkov (Code Review)

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31427 Change subject: superio/nsc: Use common defines for NSC PC8xxxx chips ...................................................................... superio/nsc: Use common defines for NSC PC8xxxx chips * Some common NSC defines moved to superio/nsc/common * All NSC's pc8xxxx chips uses these common definitions * Lenovo T60/X60/Z61t/T400 docking updated to use these common defines * HP ProLiant DL165 G6 Fam10 updated to use this common code Build tested - Lenovo T60/X60/Z61t/T400, HP ProLiant DL165 G6 Fam10 builds fine. Change-Id: Iffdb4752f3075b1a1b391d4cf8d4416748bfe485 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/hp/dl165_g6_fam10/romstage.c M src/mainboard/lenovo/t400/dock.c M src/mainboard/lenovo/t60/dock.c M src/mainboard/lenovo/x60/dock.c M src/mainboard/lenovo/z61t/dock.c A src/superio/nsc/common/superio_defs.h D src/superio/nsc/pc87309/pc87309.h M src/superio/nsc/pc87309/superio.c D src/superio/nsc/pc87360/pc87360.h M src/superio/nsc/pc87360/superio.c D src/superio/nsc/pc87366/pc87366.h M src/superio/nsc/pc87366/superio.c D src/superio/nsc/pc87382/pc87382.h M src/superio/nsc/pc87382/superio.c D src/superio/nsc/pc87384/pc87384.h M src/superio/nsc/pc87384/superio.c D src/superio/nsc/pc87392/pc87392.h M src/superio/nsc/pc87392/superio.c M src/superio/nsc/pc87417/pc87417.h M src/superio/nsc/pc87417/superio.c 20 files changed, 219 insertions(+), 369 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/31427/1 diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 6d2eed4..7f5411e 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -34,6 +34,7 @@ #include <spd.h> #include <delay.h> #include <superio/serverengines/pilot/pilot.h> +#include <superio/nsc/common/superio_defs.h> #include <superio/nsc/pc87417/pc87417.h> #include <cpu/x86/bist.h> #include <cpu/amd/car.h> @@ -50,7 +51,7 @@ #include "cpu/amd/quadcore/quadcore.c" #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) -#define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) +#define RTC_DEV PNP_DEV(0x4e, PC8XXXX_RTC) void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); diff --git a/src/mainboard/lenovo/t400/dock.c b/src/mainboard/lenovo/t400/dock.c index 6d1a80c..58788e7 100644 --- a/src/mainboard/lenovo/t400/dock.c +++ b/src/mainboard/lenovo/t400/dock.c @@ -23,7 +23,7 @@ #include <device/pnp.h> #include <delay.h> #include "dock.h" -#include <superio/nsc/pc87382/pc87382.h> +#include <superio/nsc/common/superio_defs.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <ec/lenovo/h8/h8.h> @@ -64,8 +64,8 @@ return 0; } -static const pnp_devfn_t l_dlpc = PNP_DEV(0x164e, PC87382_DOCK); -static const pnp_devfn_t l_gpio = PNP_DEV(0x164e, PC87382_GPIO); +static const pnp_devfn_t l_dlpc = PNP_DEV(0x164e, PC8XXXX_DOCK); +static const pnp_devfn_t l_gpio = PNP_DEV(0x164e, PC8XXXX_GPIO); static int pc87382_init(pnp_devfn_t dlpc, u16 dlpc_base) { @@ -170,20 +170,18 @@ /* Docking station side. */ -#include <superio/nsc/pc87384/pc87384.h> - -static const pnp_devfn_t r_gpio = PNP_DEV(SUPERIO_DEV, PC87384_GPIO); -static const pnp_devfn_t r_serial = PNP_DEV(SUPERIO_DEV, PC87384_SP1); +static const pnp_devfn_t r_gpio = PNP_DEV(SUPERIO_DEV, PC8XXXX_GPIO); +static const pnp_devfn_t r_serial = PNP_DEV(SUPERIO_DEV, PC8XXXX_SP1); static const struct pin_config remote_gpio[] = { - {0x00, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP}, - {0x01, PC87384_GPIO_PIN_TYPE_PUSH_PULL | PC87384_GPIO_PIN_OE}, - {0x02, PC87384_GPIO_PIN_TYPE_PUSH_PULL | PC87384_GPIO_PIN_OE}, - {0x03, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP}, - {0x04, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP}, - {0x05, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP}, - {0x06, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP}, - {0x07, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP}, + {0x00, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP}, + {0x01, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | PC8XXXX_GPIO_PIN_OE}, + {0x02, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | PC8XXXX_GPIO_PIN_OE}, + {0x03, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP}, + {0x04, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP}, + {0x05, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP}, + {0x06, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP}, + {0x07, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP}, }; static int pc87384_init(void) diff --git a/src/mainboard/lenovo/t60/dock.c b/src/mainboard/lenovo/t60/dock.c index 05dd65e..57a5a00 100644 --- a/src/mainboard/lenovo/t60/dock.c +++ b/src/mainboard/lenovo/t60/dock.c @@ -18,7 +18,7 @@ #include <arch/io.h> #include <delay.h> #include "dock.h" -#include <superio/nsc/pc87384/pc87384.h> +#include <superio/nsc/common/superio_defs.h> #include "ec/acpi/ec.h" #include "ec/lenovo/pmh7/pmh7.h" #include <southbridge/intel/i82801gx/i82801gx.h> @@ -128,38 +128,38 @@ dock_write_register(0x22, 0xa9); /* enable serial port */ - dock_write_register(0x07, PC87384_SP1); + dock_write_register(0x07, PC8XXXX_SP1); dock_write_register(0x30, 0x01); - dock_write_register(0x07, PC87384_GPIO); + dock_write_register(0x07, PC8XXXX_GPIO); dock_write_register(0x60, 0x16); dock_write_register(0x61, 0x20); /* enable GPIO */ dock_write_register(0x30, 0x01); - dock_gpio_set_mode(0x00, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x00, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x01, PC87384_GPIO_PIN_TYPE_PUSH_PULL | - PC87384_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x01, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x02, PC87384_GPIO_PIN_TYPE_PUSH_PULL | - PC87384_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x02, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x03, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x03, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x04, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x04, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x05, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x05, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x06, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x06, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x07, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x07, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); /* no GPIO events enabled for PORT0 */ diff --git a/src/mainboard/lenovo/x60/dock.c b/src/mainboard/lenovo/x60/dock.c index b94d818..cf5e71d 100644 --- a/src/mainboard/lenovo/x60/dock.c +++ b/src/mainboard/lenovo/x60/dock.c @@ -20,7 +20,7 @@ #include <delay.h> #include "dock.h" #include <southbridge/intel/i82801gx/i82801gx.h> -#include <superio/nsc/pc87392/pc87392.h> +#include <superio/nsc/common/superio_defs.h> static void dlpc_write_register(int reg, int value) { @@ -165,58 +165,58 @@ dock_write_register(0x61, 0x20); /* init GPIO pins */ - dock_gpio_set_mode(0x00, PC87392_GPIO_PIN_DEBOUNCE | - PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x00, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x01, PC87392_GPIO_PIN_DEBOUNCE | - PC87392_GPIO_PIN_PULLUP, - PC87392_GPIO_PIN_TRIGGERS_SMI); + dock_gpio_set_mode(0x01, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, + PC8XXXX_GPIO_PIN_TRIGGERS_SMI); - dock_gpio_set_mode(0x02, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x03, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x04, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x05, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x06, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x07, PC87392_GPIO_PIN_PULLUP, 0x02); + dock_gpio_set_mode(0x02, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x03, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x04, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x05, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x06, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x07, PC8XXXX_GPIO_PIN_PULLUP, 0x02); - dock_gpio_set_mode(0x10, PC87392_GPIO_PIN_DEBOUNCE | - PC87392_GPIO_PIN_PULLUP, - PC87392_GPIO_PIN_TRIGGERS_SMI); + dock_gpio_set_mode(0x10, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, + PC8XXXX_GPIO_PIN_TRIGGERS_SMI); - dock_gpio_set_mode(0x11, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x12, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x13, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x14, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x15, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x16, PC87392_GPIO_PIN_PULLUP | - PC87392_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x11, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x12, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x13, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x14, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x15, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x16, PC8XXXX_GPIO_PIN_PULLUP | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x17, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x17, PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x20, PC87392_GPIO_PIN_TYPE_PUSH_PULL | - PC87392_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x20, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x21, PC87392_GPIO_PIN_TYPE_PUSH_PULL | - PC87392_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x21, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x22, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x23, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x24, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x25, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x26, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x27, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x22, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x23, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x24, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x25, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x26, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x27, PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x30, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x31, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x32, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x33, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x34, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x30, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x31, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x32, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x33, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x34, PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x35, PC87392_GPIO_PIN_PULLUP | - PC87392_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x35, PC8XXXX_GPIO_PIN_PULLUP | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x36, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x37, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x36, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x37, PC8XXXX_GPIO_PIN_PULLUP, 0x00); /* enable GPIO */ dock_write_register(0x30, 0x01); diff --git a/src/mainboard/lenovo/z61t/dock.c b/src/mainboard/lenovo/z61t/dock.c index 05dd65e..57a5a00 100644 --- a/src/mainboard/lenovo/z61t/dock.c +++ b/src/mainboard/lenovo/z61t/dock.c @@ -18,7 +18,7 @@ #include <arch/io.h> #include <delay.h> #include "dock.h" -#include <superio/nsc/pc87384/pc87384.h> +#include <superio/nsc/common/superio_defs.h> #include "ec/acpi/ec.h" #include "ec/lenovo/pmh7/pmh7.h" #include <southbridge/intel/i82801gx/i82801gx.h> @@ -128,38 +128,38 @@ dock_write_register(0x22, 0xa9); /* enable serial port */ - dock_write_register(0x07, PC87384_SP1); + dock_write_register(0x07, PC8XXXX_SP1); dock_write_register(0x30, 0x01); - dock_write_register(0x07, PC87384_GPIO); + dock_write_register(0x07, PC8XXXX_GPIO); dock_write_register(0x60, 0x16); dock_write_register(0x61, 0x20); /* enable GPIO */ dock_write_register(0x30, 0x01); - dock_gpio_set_mode(0x00, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x00, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x01, PC87384_GPIO_PIN_TYPE_PUSH_PULL | - PC87384_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x01, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x02, PC87384_GPIO_PIN_TYPE_PUSH_PULL | - PC87384_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x02, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x03, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x03, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x04, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x04, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x05, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x05, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x06, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x06, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x07, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x07, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); /* no GPIO events enabled for PORT0 */ diff --git a/src/superio/nsc/common/superio_defs.h b/src/superio/nsc/common/superio_defs.h new file mode 100644 index 0000000..cc35508 --- /dev/null +++ b/src/superio/nsc/common/superio_defs.h @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_NSC_COMMON_SUPERIO_DEFS_H +#define SUPERIO_NSC_COMMON_SUPERIO_DEFS_H + +#define PC8XXXX_FDC 0x00 /* Floppy */ +#define PC8XXXX_PP 0x01 /* Parallel port */ +#define PC8XXXX_SP2 0x02 /* COM 2 / IR */ +#define PC8XXXX_SP1 0x03 /* COM 1 */ +#define PC8XXXX_SWC 0x04 /* System wakeup control */ +//#define PC8XXXX_PM 0x04 /* Power management */ +#define PC8XXXX_KBCM 0x05 /* Mouse */ +#define PC8XXXX_KBCK 0x06 /* Keyboard */ +#define PC8XXXX_GPIO 0x07 /* General purpose IO */ +//#define PC8XXXX_HM 0x08 +#define PC8XXXX_FSD 0x08 /* Fan speed device */ +#define PC8XXXX_ACB 0x08 +#define PC8XXXX_FSCM 0x09 +#define PC8XXXX_FMC 0x09 +#define PC8XXXX_WDT 0x0A +#define PC8XXXX_GMP 0x0B +#define PC8XXXX_MIDI 0x0C +#define PC8XXXX_VLM 0x0D +#define PC8XXXX_TMS 0x0E +#define PC8XXXX_XBUS 0x0F +#define PC8XXXX_RTC 0x10 +#define PC8XXXX_MHC 0x14 +#define PC8XXXX_DOCK 0x19 + +#define PC8XXXX_GPIO_PIN_OE 0x01 +#define PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL 0x02 +#define PC8XXXX_GPIO_PIN_PULLUP 0x04 +#define PC8XXXX_GPIO_PIN_LOCK 0x08 +#define PC8XXXX_GPIO_PIN_TRIG_LEVEL 0x10 +#define PC8XXXX_GPIO_PIN_TRIG_LOW 0x20 +#define PC8XXXX_GPIO_PIN_DEBOUNCE 0x40 + +#define PC8XXXX_GPIO_PIN_TRIGGERS_IRQ 0x01 +#define PC8XXXX_GPIO_PIN_TRIGGERS_SMI 0x02 + +#endif /* SUPERIO_NSC_COMMON_SUPERIO_DEFS_H */ diff --git a/src/superio/nsc/pc87309/pc87309.h b/src/superio/nsc/pc87309/pc87309.h deleted file mode 100644 index 3b912ea..0000000 --- a/src/superio/nsc/pc87309/pc87309.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87309_H -#define SUPERIO_NSC_PC87309_H - -/* Datasheet: PC87309 SuperI/O Plug and Play Compatible Chip. */ - -#define PC87309_FDC 0x00 /* Floppy */ -#define PC87309_PP 0x01 /* Parallel port */ -#define PC87309_SP2 0x02 /* Com2 / IR */ -#define PC87309_SP1 0x03 /* Com1 */ -#define PC87309_PM 0x04 /* Power management */ -#define PC87309_KBCM 0x05 /* Mouse */ -#define PC87309_KBCK 0x06 /* Keyboard */ - -#endif /* SUPERIO_NSC_PC87309_H */ diff --git a/src/superio/nsc/pc87309/superio.c b/src/superio/nsc/pc87309/superio.c index 458c501..f63bea9 100644 --- a/src/superio/nsc/pc87309/superio.c +++ b/src/superio/nsc/pc87309/superio.c @@ -19,7 +19,7 @@ #include <device/pnp.h> #include <pc80/keyboard.h> #include <stdlib.h> -#include "pc87309.h" +#include <superio/nsc/common/superio_defs.h> static void init(struct device *dev) { @@ -28,7 +28,7 @@ return; switch (dev->path.pnp.device) { - case PC87309_KBCK: + case PC8XXXX_KBCK: pc_keyboard_init(NO_AUX_DEVICE); break; } @@ -43,14 +43,14 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87309_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87309_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87309_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, + { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, }, - { NULL, PC87309_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, /* TODO: PM. */ - { NULL, PC87309_KBCM, PNP_IRQ0, }, - { NULL, PC87309_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x7f8, }, + { NULL, PC8XXXX_KBCM, PNP_IRQ0, }, + { NULL, PC8XXXX_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x7f8, }, }; static void enable_dev(struct device *dev) diff --git a/src/superio/nsc/pc87360/pc87360.h b/src/superio/nsc/pc87360/pc87360.h deleted file mode 100644 index c969746..0000000 --- a/src/superio/nsc/pc87360/pc87360.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87360_H -#define SUPERIO_NSC_PC87360_H - -#define PC87360_FDC 0x00 /* Floppy */ -#define PC87360_PP 0x01 /* Parallel port */ -#define PC87360_SP2 0x02 /* Com2 */ -#define PC87360_SP1 0x03 /* Com1 */ -#define PC87360_SWC 0x04 -#define PC87360_KBCM 0x05 /* Mouse */ -#define PC87360_KBCK 0x06 /* Keyboard */ -#define PC87360_GPIO 0x07 -#define PC87360_ACB 0x08 -#define PC87360_FSCM 0x09 -#define PC87360_WDT 0x0A - -#endif /* SUPERIO_NSC_PC87360_H */ diff --git a/src/superio/nsc/pc87360/superio.c b/src/superio/nsc/pc87360/superio.c index cf5c7ca..85f21a2 100644 --- a/src/superio/nsc/pc87360/superio.c +++ b/src/superio/nsc/pc87360/superio.c @@ -21,7 +21,7 @@ #include <string.h> #include <pc80/keyboard.h> #include <stdlib.h> -#include "pc87360.h" +#include <superio/nsc/common/superio_defs.h> static void init(struct device *dev) { @@ -29,7 +29,7 @@ return; switch (dev->path.pnp.device) { - case PC87360_KBCK: + case PC8XXXX_KBCK: pc_keyboard_init(NO_AUX_DEVICE); break; } @@ -44,18 +44,18 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87360_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87360_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87360_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, + { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, }, - { NULL, PC87360_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, PC87360_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, - { NULL, PC87360_KBCM, PNP_IRQ0, }, - { NULL, PC87360_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, - { NULL, PC87360_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87360_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87360_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87360_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, + { NULL, PC8XXXX_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + { NULL, PC8XXXX_KBCM, PNP_IRQ0, }, + { NULL, PC8XXXX_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, + { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, }, }; static void enable_dev(struct device *dev) diff --git a/src/superio/nsc/pc87366/pc87366.h b/src/superio/nsc/pc87366/pc87366.h deleted file mode 100644 index b1df69f..0000000 --- a/src/superio/nsc/pc87366/pc87366.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87366_H -#define SUPERIO_NSC_PC87366_H - -#define PC87366_FDC 0x00 /* Floppy */ -#define PC87366_PP 0x01 /* Parallel port */ -#define PC87366_SP2 0x02 /* Com2 */ -#define PC87366_SP1 0x03 /* Com1 */ -#define PC87366_SWC 0x04 -#define PC87366_KBCM 0x05 /* Mouse */ -#define PC87366_KBCK 0x06 /* Keyboard */ -#define PC87366_GPIO 0x07 -#define PC87366_ACB 0x08 -#define PC87366_FSCM 0x09 -#define PC87366_WDT 0x0A -#define PC87366_GMP 0x0b -#define PC87366_MIDI 0x0C -#define PC87366_VLM 0x0D -#define PC87366_TMS 0x0E - -#endif /* SUPERIO_NSC_PC87366_H */ diff --git a/src/superio/nsc/pc87366/superio.c b/src/superio/nsc/pc87366/superio.c index e1cba17..60e5e23 100644 --- a/src/superio/nsc/pc87366/superio.c +++ b/src/superio/nsc/pc87366/superio.c @@ -21,7 +21,7 @@ #include <string.h> #include <pc80/keyboard.h> #include <stdlib.h> -#include "pc87366.h" +#include <superio/nsc/common/superio_defs.h> static void init(struct device *dev) { @@ -29,7 +29,7 @@ return; switch (dev->path.pnp.device) { - case PC87366_KBCK: + case PC8XXXX_KBCK: pc_keyboard_init(NO_AUX_DEVICE); break; } @@ -44,18 +44,18 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87366_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87366_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87366_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, + { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, }, - { NULL, PC87366_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, PC87366_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, - { NULL, PC87366_KBCM, PNP_IRQ0, }, - { NULL, PC87366_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, - { NULL, PC87366_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87366_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87366_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87366_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, + { NULL, PC8XXXX_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + { NULL, PC8XXXX_KBCM, PNP_IRQ0, }, + { NULL, PC8XXXX_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, + { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, }, }; static void enable_dev(struct device *dev) diff --git a/src/superio/nsc/pc87382/pc87382.h b/src/superio/nsc/pc87382/pc87382.h deleted file mode 100644 index 6826f45..0000000 --- a/src/superio/nsc/pc87382/pc87382.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87382_H -#define SUPERIO_NSC_PC87382_H - -#define PC87382_IR 0x02 -#define PC87382_SP1 0x03 -#define PC87382_GPIO 0x07 -#define PC87382_DOCK 0x19 -#endif diff --git a/src/superio/nsc/pc87382/superio.c b/src/superio/nsc/pc87382/superio.c index 688f08c..6a21f51 100644 --- a/src/superio/nsc/pc87382/superio.c +++ b/src/superio/nsc/pc87382/superio.c @@ -19,7 +19,7 @@ #include <device/pnp.h> #include <string.h> #include <stdlib.h> -#include "pc87382.h" +#include <superio/nsc/common/superio_defs.h> static void init(struct device *dev) { @@ -27,10 +27,10 @@ return; switch (dev->path.pnp.device) { - case PC87382_DOCK: + case PC8XXXX_DOCK: break; - case PC87382_GPIO: + case PC8XXXX_GPIO: break; } } @@ -44,11 +44,11 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87382_IR, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8 }, - { NULL, PC87382_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 }, - { NULL, PC87382_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0 }, - { NULL, PC87382_DOCK, PNP_IO0 | PNP_IRQ0, 0xfffe }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 }, + { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0 }, + { NULL, PC8XXXX_DOCK, PNP_IO0 | PNP_IRQ0, 0xfffe }, }; static void enable_dev(struct device *dev) diff --git a/src/superio/nsc/pc87384/pc87384.h b/src/superio/nsc/pc87384/pc87384.h deleted file mode 100644 index 2184584..0000000 --- a/src/superio/nsc/pc87384/pc87384.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87384_H -#define SUPERIO_NSC_PC87384_H - -#define PC87384_PP 0x01 -#define PC87384_SP2 0x02 -#define PC87384_SP1 0x03 -#define PC87384_GPIO 0x07 - -#define PC87384_GPIO_PIN_OE 0x01 -#define PC87384_GPIO_PIN_TYPE_PUSH_PULL 0x02 -#define PC87384_GPIO_PIN_PULLUP 0x04 -#define PC87384_GPIO_PIN_LOCK 0x08 -#define PC87384_GPIO_PIN_TRIG_LEVEL 0x10 -#define PC87384_GPIO_PIN_TRIG_LOW 0x20 -#define PC87384_GPIO_PIN_DEBOUNCE 0x40 - -#define PC87384_GPIO_PIN_TRIGGERS_IRQ 0x01 - -#endif diff --git a/src/superio/nsc/pc87384/superio.c b/src/superio/nsc/pc87384/superio.c index f34acd5..9548d2c 100644 --- a/src/superio/nsc/pc87384/superio.c +++ b/src/superio/nsc/pc87384/superio.c @@ -19,7 +19,7 @@ #include <device/pnp.h> #include <string.h> #include <stdlib.h> -#include "pc87384.h" +#include <superio/nsc/common/superio_defs.h> static struct device_operations ops = { .read_resources = pnp_read_resources, @@ -29,10 +29,10 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87384_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 }, - { NULL, PC87384_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 }, - { NULL, PC87384_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8 }, - { NULL, PC87384_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0 }, + { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 }, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8 }, + { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0 }, }; static void enable_dev(struct device *dev) diff --git a/src/superio/nsc/pc87392/pc87392.h b/src/superio/nsc/pc87392/pc87392.h deleted file mode 100644 index 5832435..0000000 --- a/src/superio/nsc/pc87392/pc87392.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87392_H -#define SUPERIO_NSC_PC87392_H - -#define PC87392_FDC 0x00 -#define PC87392_PP 0x01 -#define PC87392_SP2 0x02 -#define PC87392_SP1 0x03 -#define PC87392_GPIO 0x07 -#define PC87392_WDT 0x0A - -#define PC87392_GPIO_PIN_OE 0x01 -#define PC87392_GPIO_PIN_TYPE_PUSH_PULL 0x02 -#define PC87392_GPIO_PIN_PULLUP 0x04 -#define PC87392_GPIO_PIN_LOCK 0x08 -#define PC87392_GPIO_PIN_TRIG_LEVEL 0x10 -#define PC87392_GPIO_PIN_TRIG_LOW 0x20 -#define PC87392_GPIO_PIN_DEBOUNCE 0x40 - -#define PC87392_GPIO_PIN_TRIGGERS_IRQ 0x01 -#define PC87392_GPIO_PIN_TRIGGERS_SMI 0x02 - -#endif diff --git a/src/superio/nsc/pc87392/superio.c b/src/superio/nsc/pc87392/superio.c index edd4619..9971b5c 100644 --- a/src/superio/nsc/pc87392/superio.c +++ b/src/superio/nsc/pc87392/superio.c @@ -19,7 +19,7 @@ #include <device/pnp.h> #include <string.h> #include <stdlib.h> -#include "pc87392.h" +#include <superio/nsc/common/superio_defs.h> static void init(struct device *dev) { @@ -36,13 +36,13 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87392_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 }, - { NULL, PC87392_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 }, - { NULL, PC87392_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, + { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 }, + { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 }, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8 }, - { NULL, PC87392_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 }, - { NULL, PC87392_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8 }, - { NULL, PC87392_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 }, + { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8 }, + { NULL, PC8XXXX_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc }, }; static void enable_dev(struct device *dev) diff --git a/src/superio/nsc/pc87417/pc87417.h b/src/superio/nsc/pc87417/pc87417.h index b50a920..e6c7f79 100644 --- a/src/superio/nsc/pc87417/pc87417.h +++ b/src/superio/nsc/pc87417/pc87417.h @@ -19,17 +19,6 @@ #ifndef SUPERIO_NSC_PC87417_H #define SUPERIO_NSC_PC87417_H -#define PC87417_FDC 0x00 /* Floppy */ -#define PC87417_PP 0x01 /* Parallel Port */ -#define PC87417_SP2 0x02 /* Com2 */ -#define PC87417_SP1 0x03 /* Com1 */ -#define PC87417_SWC 0x04 /* System Wake-Up Controller (SWC) */ -#define PC87417_KBCM 0x05 /* Mouse */ -#define PC87417_KBCK 0x06 /* Keyboard */ -#define PC87417_GPIO 0x07 -#define PC87417_XBUS 0x0F -#define PC87417_RTC 0x10 - #define PC87417_GPIO_DEV PNP_DEV(0x2e, PC87417_GPIO) /* This is to get around a romcc bug */ /* #define PC87417_XBUS_DEV PNP_DEV(0x2e, PC87417_XBUS) */ diff --git a/src/superio/nsc/pc87417/superio.c b/src/superio/nsc/pc87417/superio.c index f0e0bb1..a4e8022 100644 --- a/src/superio/nsc/pc87417/superio.c +++ b/src/superio/nsc/pc87417/superio.c @@ -22,7 +22,7 @@ #include <string.h> #include <pc80/keyboard.h> #include <stdlib.h> -#include "pc87417.h" +#include <superio/nsc/common/superio_defs.h> static void init(struct device *dev) { @@ -30,7 +30,7 @@ return; switch (dev->path.pnp.device) { - case PC87417_KBCK: + case PC8XXXX_KBCK: pc_keyboard_init(NO_AUX_DEVICE); break; } @@ -45,17 +45,17 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87417_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87417_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87417_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, + { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, }, - { NULL, PC87417_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, PC87417_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, - { NULL, PC87417_KBCM, PNP_IRQ0, }, - { NULL, PC87417_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, - { NULL, PC87417_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87417_XBUS, PNP_IO0 | PNP_IRQ0, 0xffe0, }, - { NULL, PC87417_RTC, PNP_IO0 | PNP_IO1, 0xfffe, 0xfffe, }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, + { NULL, PC8XXXX_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + { NULL, PC8XXXX_KBCM, PNP_IRQ0, }, + { NULL, PC8XXXX_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, + { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_XBUS, PNP_IO0 | PNP_IRQ0, 0xffe0, }, + { NULL, PC8XXXX_RTC, PNP_IO0 | PNP_IO1, 0xfffe, 0xfffe, }, }; static void enable_dev(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/31427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffdb4752f3075b1a1b391d4cf8d4416748bfe485 Gerrit-Change-Number: 31427 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop

by mikeb mikeb (Code Review)

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31450 to review the following change. Change subject: lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop ...................................................................... lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop Make it possible to enable CONFIG_MULTIPLE_VGA_ADAPTERS option for G505S which is currently not used by any of coreboot-supported boards. Also enable the discrete graphics PCI bus leading to HD 8570M (1002,6663) or R5 M230 (1002,6665) discrete VGA and add the G505S-specific workaround for PCI resource allocation problems to AMD AGESA vendorcode. Based on the original patches by Hans Jürgen Kitter <eforname(a)freemail.hu>. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Signed-off-by: Hans Jürgen Kitter <eforname(a)freemail.hu> Change-Id: I98793fa3b1ad8ee7d0b7962a328f7d5c1b0c2f88 --- M src/device/Kconfig M src/mainboard/lenovo/g505s/devicetree.cb M src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c 3 files changed, 17 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/31450/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index 33c1e5b3..5d2087e 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -247,8 +247,15 @@ Enable this option for a good compromise between security and speed. config MULTIPLE_VGA_ADAPTERS + prompt "Multiple VGA Adapters" bool + depends on BOARD_LENOVO_G505S default n + help + Some motherboards may have more than one VGA adapter - for example, + there are versions of Lenovo G505S that have a discrete VGA adapter + in addition to its' integrated VGA adapter which is a part of APU. + Enable this option to try to initialize this discrete VGA adapter. menu "Display" depends on HAVE_VGA_TEXT_FRAMEBUFFER || HAVE_LINEAR_FRAMEBUFFER diff --git a/src/mainboard/lenovo/g505s/devicetree.cb b/src/mainboard/lenovo/g505s/devicetree.cb index 99f42d6..1f33c27 100644 --- a/src/mainboard/lenovo/g505s/devicetree.cb +++ b/src/mainboard/lenovo/g505s/devicetree.cb @@ -27,7 +27,7 @@ device pci 0.2 on end # IOMMU device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX device pci 1.1 on end # Internal Multimedia - device pci 2.0 off end + device pci 2.0 on end # Discrete Graphics PCI bus 0x666X device pci 3.0 off end device pci 4.0 on end # PCIE MINI0 device pci 5.0 on end # PCIE MINI1 diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c index c566061..ee6d2c2 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c @@ -437,8 +437,15 @@ RefPtr = MemPtr->ParameterListPtr; // Memory Map/Mgt. - // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB - RefPtr->BottomIo = 0xE0; + if ((IS_ENABLED(CONFIG_BOARD_LENOVO_G505S)) && + (IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS))) { + // Set to 0xD0 instead of 0xE0 to avoid the PCI resource allocation problems + RefPtr->BottomIo = 0xD0; + } + else { + // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB + RefPtr->BottomIo = 0xE0; + } RefPtr->UmaMode = UserOptions.CfgUmaMode; RefPtr->UmaSize = UserOptions.CfgUmaSize; RefPtr->MemHoleRemapping = TRUE; -- To view, visit https://review.coreboot.org/c/coreboot/+/31450 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98793fa3b1ad8ee7d0b7962a328f7d5c1b0c2f88 Gerrit-Change-Number: 31450 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

5 months, 3 weeks

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Change in ...coreboot[master]: cpu/intel: Use macro instead of numbers

by HAOUAS Elyes (Code Review)

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31196 Change subject: cpu/intel: Use macro instead of numbers ...................................................................... cpu/intel: Use macro instead of numbers Change-Id: Ic18c219beaec3dad197916a1e235a027c1c74a89 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/fsp_model_406dx/model_406dx_init.c M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/intel/model_106cx/model_106cx_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/cpu/intel/model_6ex/model_6ex_init.c M src/cpu/intel/model_6fx/model_6fx_init.c 7 files changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/31196/1 diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c index 7994f0b..06b37a9 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c +++ b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c @@ -47,9 +47,9 @@ msr_t msr; msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= (1 << 0); /* Fast String enable */ + msr.lo |= FAST_STRINGS_ENABLE_BIT; msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr.lo |= SPEED_STEP_ENABLE_BIT; wrmsr(IA32_MISC_ENABLE, msr); /* Disable Thermal interrupts */ diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index aa77964..08abdf5 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -578,9 +578,9 @@ msr_t msr; msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= (1 << 0); /* Fast String enable */ + msr.lo |= FAST_STRINGS_ENABLE_BIT; msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr.lo |= SPEED_STEP_ENABLE_BIT; wrmsr(IA32_MISC_ENABLE, msr); /* Disable Thermal interrupts */ diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 6068be1..97ed39d 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -199,7 +199,7 @@ msr.lo |= (1 << 10); /* FERR# multiplexing */ if (eist) - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr.lo |= SPEED_STEP_ENABLE_BIT; /* Enable C2E */ if (((sub_cstates >> (2 * 4)) & 0xf) >= 2) diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index e443026..1c0d081 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -65,7 +65,7 @@ msr.lo |= (1 << 10); /* FERR# multiplexing */ // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1 - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr.lo |= SPEED_STEP_ENABLE_BIT; // TODO Do we want Deep C4 and Dynamic L2 shrinking? wrmsr(IA32_MISC_ENABLE, msr); diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 33ad1e7..c2e0364 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -338,9 +338,9 @@ msr_t msr; msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= (1 << 0); /* Fast String enable */ + msr.lo |= FAST_STRINGS_ENABLE_BIT; msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr.lo |= SPEED_STEP_ENABLE_BIT; wrmsr(IA32_MISC_ENABLE, msr); /* Disable Thermal interrupts */ diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 19a22f1..fbc6964 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -67,7 +67,7 @@ msr.lo |= (1 << 10); /* FERR# multiplexing */ // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1 - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr.lo |= SPEED_STEP_ENABLE_BIT; /* Enable C2E */ msr.lo |= (1 << 26); diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 4e19896..adc0265 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -70,7 +70,7 @@ msr.lo |= (1 << 10); /* FERR# multiplexing */ // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1 - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr.lo |= SPEED_STEP_ENABLE_BIT; /* Enable C2E */ msr.lo |= (1 << 26); -- To view, visit https://review.coreboot.org/c/coreboot/+/31196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic18c219beaec3dad197916a1e235a027c1c74a89 Gerrit-Change-Number: 31196 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/device/pci: Add support for discrete VGA initialization and OpROM...

by mikeb mikeb (Code Review)

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31448 to review the following change. Change subject: src/device/pci: Add support for discrete VGA initialization and OpROM loading ...................................................................... src/device/pci: Add support for discrete VGA initialization and OpROM loading Required to make the discrete VGA working at some boards like AMD Lenovo G505S. If CONFIG_MULTIPLE_VGA_ADAPTERS is enabled, coreboot will try to initialize the discrete VGA and load OpROM on it. ACPI VFCT table will be created only for discrete VGA instead of integrated, but everything seems to be working fine. Maybe later we would find a way to make a common VFCT table for both adapters. Based on the original patches by Hans Jürgen Kitter <eforname(a)freemail.hu>. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Signed-off-by: Hans Jürgen Kitter <eforname(a)freemail.hu> Change-Id: If3269a0911e86ea07014484365c7c830485e52ec --- M src/device/pci_device.c M src/device/pci_rom.c 2 files changed, 68 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/31448/1 diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 82033a6..96dec0b 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -764,7 +764,9 @@ * ROMs when coming out of an S3 resume. */ if (!IS_ENABLED(CONFIG_S3_VGA_ROM_RUN) && acpi_is_wakeup_s3() && - ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)) + (((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) || + (IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) && + ((dev->class >> 8) == PCI_CLASS_DISPLAY_OTHER)))) return 0; if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM)) return 1; @@ -778,25 +780,41 @@ void pci_dev_init(struct device *dev) { struct rom_header *rom, *ram; + unsigned int pci_class = (dev->class >> 8); if (!IS_ENABLED(CONFIG_VGA_ROM_RUN)) return; - /* Only execute VGA ROMs. */ - if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)) - return; + /* Only load VGA ROMs. */ + if (pci_class != PCI_CLASS_DISPLAY_VGA) { + if (!IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)) { + return; + } else if (pci_class != PCI_CLASS_DISPLAY_OTHER) { + return; + } + } if (!should_load_oprom(dev)) return; timestamp_add_now(TS_OPROM_INITIALIZE); rom = pci_rom_probe(dev); - if (rom == NULL) + if (rom == NULL) { + if (pci_class == PCI_CLASS_DISPLAY_VGA) + printk(BIOS_DEBUG, "Integrated VGA ROM probe failed\n"); + else + printk(BIOS_DEBUG, "Discrete VGA ROM probe failed\n"); return; + } ram = pci_rom_load(dev, rom); - if (ram == NULL) + if (ram == NULL) { + if (pci_class == PCI_CLASS_DISPLAY_VGA) + printk(BIOS_DEBUG, "Integrated VGA ROM load failed\n"); + else + printk(BIOS_DEBUG, "Discrete VGA ROM load failed\n"); return; + } timestamp_add_now(TS_OPROM_COPY_END); if (!should_run_oprom(dev)) @@ -804,7 +822,11 @@ run_bios(dev, (unsigned long)ram); gfx_set_init_done(1); - printk(BIOS_DEBUG, "VGA Option ROM was run\n"); + if (pci_class == PCI_CLASS_DISPLAY_VGA) + printk(BIOS_DEBUG, "Integrated VGA Option ROM was run\n"); + else + printk(BIOS_DEBUG, "Discrete VGA Option ROM was run\n"); + timestamp_add_now(TS_OPROM_END); } diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 82d9a30..60f9aed 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -179,13 +179,24 @@ /* VBIOS may be modified after oprom init so use the copy if present. */ static struct rom_header *check_initialized(struct device *dev) { - struct rom_header *run_rom; + struct rom_header *run_rom = NULL; struct pci_data *rom_data; if (!IS_ENABLED(CONFIG_VGA_ROM_RUN)) return NULL; - run_rom = (struct rom_header *)(uintptr_t)PCI_VGA_RAM_IMAGE_START; + /* Set the start of shadow memory for this Integrated or Discrete VGA. */ + if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) { + run_rom = (struct rom_header *)(uintptr_t)PCI_VGA_RAM_IMAGE_START; + } else if (IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)) { + if ((dev->class >> 8) == PCI_CLASS_DISPLAY_OTHER) { + run_rom = (struct rom_header *)(uintptr_t)PCI_RAM_IMAGE_START; + } + } + + if (run_rom == NULL) + return NULL; + if (read_le16(&run_rom->signature) != PCI_ROM_HDR) return NULL; @@ -217,11 +228,22 @@ return current; } - printk(BIOS_DEBUG, " Copying %sVBIOS image from %p\n", + if (!IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)) { + /* Copy Integrated VGA VBIOS from CBFS to ACPI VFCT. */ + printk(BIOS_DEBUG, " Copying %sVBIOS image from %p\n", rom == (struct rom_header *) (uintptr_t)PCI_VGA_RAM_IMAGE_START ? "initialized " : "", rom); + } else { + /* Copy Discrete VGA VBIOS from CBFS to ACPI VFCT. */ + printk(BIOS_DEBUG, " Copying %sVBIOS image from %p\n", + rom == (struct rom_header *) + (uintptr_t)PCI_RAM_IMAGE_START ? + "initialized " : "", + rom); + /* TODO: do this also for Integrated VGA VBIOS. */ + } header->DeviceID = device->device; header->VendorID = device->vendor; @@ -243,8 +265,20 @@ struct rom_header *rom; /* Only handle VGA devices */ - if ((device->class >> 8) != PCI_CLASS_DISPLAY_VGA) - return current; + + if (!IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)) { + if ((device->class >> 8) != PCI_CLASS_DISPLAY_VGA) { + return current; + } + } else { + /* Write ACPI VFCT only for Discrete VGA. */ + if ((device->class >> 8) == PCI_CLASS_DISPLAY_OTHER) { + ; + } else { + return current; + } + /* TODO: do this also for Integrated VGA. */ + } /* Only handle enabled devices */ if (!device->enabled) -- To view, visit https://review.coreboot.org/c/coreboot/+/31448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3269a0911e86ea07014484365c7c830485e52ec Gerrit-Change-Number: 31448 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

6 months, 1 week

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Change in ...coreboot[master]: security/vboot: Add fmap measurements

by Philipp Deppenwiese (Code Review)

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31597 Change subject: security/vboot: Add fmap measurements ...................................................................... security/vboot: Add fmap measurements * Hook into fmap location * Add static measurements for IFD to the CRTM Change-Id: If7e4972805fbc8d19ab55d1f5e506836791c7bf0 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/lib/fmap.c M src/security/vboot/vboot_crtm.c M src/security/vboot/vboot_crtm.h 3 files changed, 76 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/31597/1 diff --git a/src/lib/fmap.c b/src/lib/fmap.c index 9602134..ae0aaf8 100644 --- a/src/lib/fmap.c +++ b/src/lib/fmap.c @@ -20,6 +20,7 @@ #include <commonlib/fmap_serialized.h> #include <stddef.h> #include <string.h> +#include <security/vboot/vboot_crtm.h> #include "fmap_config.h" @@ -77,7 +78,12 @@ if (fmap_locate_area(name, &ar)) return -1; - return boot_device_ro_subregion(&ar, area); + int ret = boot_device_ro_subregion(&ar, area); + if (!ret) + if (vboot_measure_fmap_hook(area, name)) + return -1; + + return ret; } int fmap_locate_area_as_rdev_rw(const char *name, struct region_device *area) @@ -87,7 +93,12 @@ if (fmap_locate_area(name, &ar)) return -1; - return boot_device_rw_subregion(&ar, area); + int ret = boot_device_rw_subregion(&ar, area); + if (!ret) + if (vboot_measure_fmap_hook(area, name)) + return -1; + + return ret; } int fmap_locate_area(const char *name, struct region *ar) diff --git a/src/security/vboot/vboot_crtm.c b/src/security/vboot/vboot_crtm.c index 1914f20..a474fd0 100644 --- a/src/security/vboot/vboot_crtm.c +++ b/src/security/vboot/vboot_crtm.c @@ -18,6 +18,16 @@ #include <security/vboot/vboot_crtm.h> #include <security/vboot/misc.h> +const static char *fmap_runtime_data[] = { + "UNIFIED_MRC_CACHE", + "RW_MRC_CACHE", + "RW_ELOG", + "RW_VPD", + "RW_NVRAM", + "RECOVERY_MRC_CACHE", + "RW_VAR_MRC_CACHE", + "SMMSTORE"}; + uint32_t vboot_init_crtm(void) { struct prog bootblock = PROG_INIT(PROG_BOOTBLOCK, "bootblock"); @@ -88,6 +98,36 @@ } } + /* IFD measurements */ + struct region_device fmap; + if (fmap_locate_area_as_rdev("RO_VPD", &fmap) == 0) + if (tpm_measure_region(&fmap, TPM_CRTM_PCR, "Read-only VPD") != TPM_SUCCESS) + return VB2_ERROR_UNKNOWN; + + if (fmap_locate_area_as_rdev("GBB", &fmap) == 0) + if (tpm_measure_region(&fmap, TPM_CRTM_PCR, "Google Binary Blob") != TPM_SUCCESS) + return VB2_ERROR_UNKNOWN; + + if (fmap_locate_area_as_rdev("SI_DESC", &fmap) == 0) + if (tpm_measure_region(&fmap, TPM_CRTM_PCR, "Intel Flash Descriptor") != TPM_SUCCESS) + return VB2_ERROR_UNKNOWN; + + if (fmap_locate_area_as_rdev("SI_ME", &fmap) == 0) + if (tpm_measure_region(&fmap, TPM_RUNTIME_DATA_PCR, "Intel ME") != TPM_SUCCESS) + return VB2_ERROR_UNKNOWN; + + if (fmap_locate_area_as_rdev("SI_EC", &fmap) == 0) + if (tpm_measure_region(&fmap, TPM_RUNTIME_DATA_PCR, "EC firmware") != TPM_SUCCESS) + return VB2_ERROR_UNKNOWN; + + if (fmap_locate_area_as_rdev("SI_GBE", &fmap) == 0) + if (tpm_measure_region(&fmap, TPM_CRTM_PCR, "Intel GbE") != TPM_SUCCESS) + return VB2_ERROR_UNKNOWN; + + if (fmap_locate_area_as_rdev("SI_PDR", &fmap) == 0) + if (tpm_measure_region(&fmap, TPM_RUNTIME_DATA_PCR, "Platform Data") != TPM_SUCCESS) + return VB2_ERROR_UNKNOWN; + return VB2_SUCCESS; } @@ -142,3 +182,18 @@ return tpm_measure_region(&rdev, pcr_index, name); } + +uint32_t vboot_measure_fmap_hook(struct region_device *rdev, const char *name) +{ + int i; + + if (!vb2_logic_executed()) + return 0; + + for (i = 0; i < sizeof(fmap_runtime_data) / sizeof(fmap_runtime_data[0]); i++) { + if (!strncmp(fmap_runtime_data[i], name, sizeof(fmap_runtime_data[i]))) + return tpm_measure_region(rdev, TPM_RUNTIME_DATA_PCR, name); + } + + return 0; +} diff --git a/src/security/vboot/vboot_crtm.h b/src/security/vboot/vboot_crtm.h index d28e96e..259e486 100644 --- a/src/security/vboot/vboot_crtm.h +++ b/src/security/vboot/vboot_crtm.h @@ -54,8 +54,16 @@ */ uint32_t vboot_measure_cbfs_hook(struct cbfsf *fh, const char *name); +/* + * Measures fmap data via hook (fmap) + * rdev is the region device handle to measure + * return 0 if successful, else an error + */ +uint32_t vboot_measure_fmap_hook(struct region_device *rdev, const char *name); + #else #define vboot_measure_cbfs_hook(fh, name) 0 +#define vboot_measure_fmap_hook(rdev, name) 0 #endif #endif /* __VBOOT_VBOOT_CRTM_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31597 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7e4972805fbc8d19ab55d1f5e506836791c7bf0 Gerrit-Change-Number: 31597 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2019