SANTHOSH JANARDHANA HASSAN has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31426
Change subject: google/mistrtal: Add board ID API.
......................................................................
google/mistrtal: Add board ID API.
BUG=None
TEST=Verified GPIO assignment and board ID values.
BRANCH=None
Change-Id: Ic81b41f799c7bfc47a0daee705db1c01cd0af1a3
Signed-off-by: Santhosh Hassan <sahassan(a)google.com>
---
M src/mainboard/google/mistral/Makefile.inc
A src/mainboard/google/mistral/boardid.c
2 files changed, 49 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/31426/1
diff --git a/src/mainboard/google/mistral/Makefile.inc b/src/mainboard/google/mistral/Makefile.inc
index e9013af..ae418f2 100644
--- a/src/mainboard/google/mistral/Makefile.inc
+++ b/src/mainboard/google/mistral/Makefile.inc
@@ -3,6 +3,7 @@
bootblock-y += chromeos.c
bootblock-y += bootblock.c
+verstage-y += boardid.c
verstage-y += memlayout.ld
verstage-y += chromeos.c
verstage-y += verstage.c
@@ -10,7 +11,9 @@
romstage-y += memlayout.ld
romstage-y += chromeos.c
romstage-y += romstage.c
+romstage-y += boardid.c
+ramstage-y += boardid.c
ramstage-y += memlayout.ld
ramstage-y += chromeos.c
ramstage-y += mainboard.c
diff --git a/src/mainboard/google/mistral/boardid.c b/src/mainboard/google/mistral/boardid.c
new file mode 100644
index 0000000..f20960c
--- /dev/null
+++ b/src/mainboard/google/mistral/boardid.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <boardid.h>
+#include <gpio.h>
+#include <console/console.h>
+#include <stdlib.h>
+
+/*
+ * Mistral boards dedicate to the board ID three GPIOs in ternary mode: 105, 106
+ * and 107.
+ */
+
+static uint32_t board_id_val = UNDEFINED_STRAPPING_ID;
+
+static uint32_t get_board_id(void)
+{
+ uint32_t bid;
+ const gpio_t pins[] = {[2] = GPIO(107), [1] = GPIO(106), [0] = GPIO(105)};
+
+ bid = gpio_binary_first_base3_value(pins, ARRAY_SIZE(pins));
+ printk(BIOS_INFO, "Board ID %d\n", bid);
+
+ return bid;
+}
+
+uint32_t board_id(void)
+{
+ if (board_id_val == UNDEFINED_STRAPPING_ID)
+ board_id_val = get_board_id();
+
+ return board_id_val;
+}
+
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic81b41f799c7bfc47a0daee705db1c01cd0af1a3
Gerrit-Change-Number: 31426
Gerrit-PatchSet: 1
Gerrit-Owner: SANTHOSH JANARDHANA HASSAN <sahassan(a)google.com>
Gerrit-MessageType: newchange
Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30965
Change subject: google/mistral: move bootblock and fmap to their previous location
......................................................................
google/mistral: move bootblock and fmap to their previous location
Helps with the current boot hack that requires them to be at certain
locations.
Also make GBB smaller. We don't store graphics in there anymore.
Change-Id: I09c3a6d4221990cd51d4793693a7c7ae2df85105
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
---
M src/mainboard/google/mistral/chromeos.fmd
1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/30965/1
diff --git a/src/mainboard/google/mistral/chromeos.fmd b/src/mainboard/google/mistral/chromeos.fmd
index a9bdd7b..ffeec16 100644
--- a/src/mainboard/google/mistral/chromeos.fmd
+++ b/src/mainboard/google/mistral/chromeos.fmd
@@ -2,9 +2,9 @@
WP_RO@0x0 0x400000 {
RO_SECTION@0x0 0x3e0000 {
BOOTBLOCK@0 128K
- COREBOOT(CBFS)@0x20000 0x2e0000
- FMAP@0x300000 0x1000
- GBB@0x301000 0xdef00
+ COREBOOT(CBFS)@0x3e000 0x1e0000
+ FMAP@0x21e000 0x1000
+ GBB@0x3dd000 0x2f00
RO_FRID@0x3dff00 0x100
}
RO_VPD@0x3e0000 0x20000
--
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Gerrit-Change-Id: I09c3a6d4221990cd51d4793693a7c7ae2df85105
Gerrit-Change-Number: 30965
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-MessageType: newchange
Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30931
Change subject: soc/intel/denverton_ns: Allow using FSP repo
......................................................................
soc/intel/denverton_ns: Allow using FSP repo
Change-Id: I615305da5865bef305f560f5c90482cf0937b25a
Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de>
---
M src/drivers/intel/fsp2_0/Kconfig
M src/soc/intel/denverton_ns/Kconfig
2 files changed, 12 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/30931/1
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index 8156d18..6f5ed2a 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -85,7 +85,8 @@
bool "Use the IntelFSP based binaries"
depends on ADD_FSP_BINARIES
depends on SOC_INTEL_APOLLOLAKE || SOC_INTEL_SKYLAKE || \
- SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE
+ SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE || \
+ SOC_INTEL_DENVERTON_NS
help
When selecting this option, the SoC must set FSP_HEADER_PATH
and FSP_FD_PATH correctly so FSP splitting works.
diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig
index 1096549..dfb5c37 100644
--- a/src/soc/intel/denverton_ns/Kconfig
+++ b/src/soc/intel/denverton_ns/Kconfig
@@ -78,6 +78,16 @@
help
The memory location of the Intel FSP-S binary for this platform.
+config FSP_HEADER_PATH
+ string "Location of FSP headers"
+ depends on MAINBOARD_USES_FSP2_0
+ default "3rdparty/fsp/DenvertonNSFspBinPkg/Include/"
+
+config FSP_FD_PATH
+ string
+ depends on FSP_USE_REPO
+ default "3rdparty/fsp/DenvertonNSFspBinPkg/FspBin/DenvertonNSFsp.fd"
+
# CAR memory layout on DENVERTON_NS hardware:
## CAR base address - 0xfef00000
## CAR size 1MB - 0x100 (0xfff00)
--
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Gerrit-Change-Id: I615305da5865bef305f560f5c90482cf0937b25a
Gerrit-Change-Number: 30931
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Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de>
Gerrit-MessageType: newchange
Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31384
Change subject: README: Spell Web site with one space
......................................................................
README: Spell Web site with one space
Change-Id: I4119ae6df01dbafb60b2a132c887844739839de6
Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de>
---
M payloads/libpayload/README
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/31384/1
diff --git a/payloads/libpayload/README b/payloads/libpayload/README
index fdf9b18..7348934 100644
--- a/payloads/libpayload/README
+++ b/payloads/libpayload/README
@@ -49,10 +49,10 @@
Please see the sample/ directory for details.
-Website and Mailing List
+Web site and Mailing List
------------------------
-The main website is https://www.coreboot.org/Libpayload.
+The main web site is https://www.coreboot.org/Libpayload.
For additional information, patches, and discussions, please join the
coreboot mailing list at https://www.coreboot.org/Mailinglist, where most
--
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