Change in ...coreboot[master]: Adding Asus A88XM-E FM2+ motherboard with documentation
by Balázs Vinarz (Code Review) 06 Dec '20
by Balázs Vinarz (Code Review) 06 Dec '20
06 Dec '20
Balázs Vinarz has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30987
Change subject: Adding Asus A88XM-E FM2+ motherboard with documentation
......................................................................
Adding Asus A88XM-E FM2+ motherboard with documentation
Signed-off-by: Balazs Vinarz <vinibali1(a)gmail.com>
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
---
A Documentation/mainboard/asus/a88xm-e.md
A src/mainboard/asus/a88xm-e/BiosCallOuts.c
A src/mainboard/asus/a88xm-e/Kconfig
A src/mainboard/asus/a88xm-e/Kconfig.name
A src/mainboard/asus/a88xm-e/Makefile.inc
A src/mainboard/asus/a88xm-e/OemCustomize.c
A src/mainboard/asus/a88xm-e/OptionsIds.h
A src/mainboard/asus/a88xm-e/acpi/cpstate.asl
A src/mainboard/asus/a88xm-e/acpi/gpe.asl
A src/mainboard/asus/a88xm-e/acpi/mainboard.asl
A src/mainboard/asus/a88xm-e/acpi/routing.asl
A src/mainboard/asus/a88xm-e/acpi/sata.asl
A src/mainboard/asus/a88xm-e/acpi/si.asl
A src/mainboard/asus/a88xm-e/acpi/sleep.asl
A src/mainboard/asus/a88xm-e/acpi/superio.asl
A src/mainboard/asus/a88xm-e/acpi/thermal.asl
A src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
A src/mainboard/asus/a88xm-e/acpi_tables.c
A src/mainboard/asus/a88xm-e/board_info.txt
A src/mainboard/asus/a88xm-e/buildOpts.c
A src/mainboard/asus/a88xm-e/cmos.layout
A src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb
A src/mainboard/asus/a88xm-e/dsdt.asl
A src/mainboard/asus/a88xm-e/irq_tables.c
A src/mainboard/asus/a88xm-e/mainboard.c
A src/mainboard/asus/a88xm-e/mptable.c
A src/mainboard/asus/a88xm-e/romstage.c
27 files changed, 2,371 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/30987/1
diff --git a/Documentation/mainboard/asus/a88xm-e.md b/Documentation/mainboard/asus/a88xm-e.md
new file mode 100644
index 0000000..5f50c5a
--- /dev/null
+++ b/Documentation/mainboard/asus/a88xm-e.md
@@ -0,0 +1,131 @@
+# ASUS A88XM-E
+
+This page describes how to run coreboot on the [ASUS A88XM-E].
+
+## Technology
+
+Both "Trinity" and "Richland" FM2 desktop processing units are working,
+the CPU architecture in these CPUs/APUs are [Piledriver],
+and their GPU is [TeraScale 3] (VLIW4-based).
+
+Kaveri is non-working at the moment (FM2+),
+the CPU architecture in these CPUs/APUs are [Steamroller],
+and their GPU is [Sea Islands] (GCN2-based).
+
+```eval_rst
++------------------+--------------------------------------------------+
+| A88XM-E | |
++------------------+--------------------------------------------------+
+| DDR voltage IC | Nuvoton 3101S |
++------------------+--------------------------------------------------+
+| Network | Realtek RTL8111G - Not working |
++------------------+--------------------------------------------------+
+| Northbridge | Integrated into CPU with IMC and GPU (APUs only) |
++------------------+--------------------------------------------------+
+| Southbridge | Bolton-D4 |
++------------------+--------------------------------------------------+
+| Sound IC | Realtek ALC887 |
++------------------+--------------------------------------------------+
+| Super I/O | ITE 8603E |
++------------------+--------------------------------------------------+
+| VRM controller | DIGI VRM ASP1206 |
++------------------+--------------------------------------------------+
+```
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+------------+
+| Type | Value |
++=====================+============+
+| Socketed flash | yes |
++---------------------+------------+
+| Model | [GD25Q64] |
++---------------------+------------+
+| Size | 8 MiB |
++---------------------+------------+
+| Package | DIP-8 |
++---------------------+------------+
+| Write protection | yes |
++---------------------+------------+
+| Dual BIOS feature | no |
++---------------------+------------+
+| Internal flashing | yes |
++---------------------+------------+
+```
+
+### Internal programming
+
+The main SPI flash can be accessed using [flashrom], if the
+AmdSpiRomProtect modules have been deleted in the factory image previously.
+
+## Integrated graphics
+
+### Retrieve the VGA optionrom from the vendor EFI binary by running:
+
+ # dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768
+
+This version is usable for all the GPUs.
+1002,9901 Trinity (Radeon HD 7660D)
+1002,9904 Trinity (Radeon HD 7560D)
+1002,990c Richland (Radeon HD 8670D)
+1002,990e Richland (Radeon HD 8570D)
+1002,9991 Trinity (Radeon HD 7540D)
+1002,9993 Trinity (Radeon HD 7480D)
+1002,9996 Richland (Radeon HD 8470D)
+1002,9998 Richland (Radeon HD 8370D)
+1002,999d Richland (Radeon HD 8550D)
+1002,130f Kaveri (Radeon R7)
+
+## Known issues
+
+- AHCI hot-plug
+- Integrated ethernet
+- S3 resume
+- XHCI
+
+### XHCI ports can broke after using any of the blobs, restarting the
+board with factory image makes it work again as fallback.
+Tested even with/without the Bolton and Hudson blobs.
+
+## Untested
+
+- audio over HDMI
+- IOMMU
+- PS/2 mouse
+
+## TODOs
+
+- one ATOMBIOS module for all the integrated GPUs
+- manage to work with Kaveri/Godavary (missing PSP firmware?)
+
+## Working
+
+- ACPI
+- CPU frequency scaling
+- flashrom under coreboot
+- Hardware monitoring
+- Integrated graphics
+- Keyboard
+- KVM virtualization
+- Onboard audio
+- PCI
+- PCIe
+- PS/2 keyboard (during payload, bootloader)
+- SATA
+- Serial port
+- SuperIO based fan control
+- USB (disabling XHCI controller makes to work as fallback USB2.0 ports)
+
+## Extra resources
+
+- [Board manual]
+
+[ASUS A88XM-E]: https://www.asus.com/Motherboards/A88XME/
+[Board manual]: https://dlcdnets.asus.com/pub/ASUS/mb/SocketFM2/A88XM-E/E9125_A88XM-E.pdf
+[flashrom]: https://flashrom.org/Flashrom
+[GD25Q64]: http://www.elm-tech.com/ja/products/spi-flash-memory/gd25q64/gd25q64.pdf
+[Piledriver]: https://en.wikipedia.org/wiki/Piledriver_%28microarchitecture%29#APU_lines
+[Sea Islands]: https://en.wikipedia.org/wiki/Graphics_Core_Next#GCN_2nd_generation
+[Steamroller]: https://en.wikipedia.org/wiki/Steamroller_(microarchitecture)
+[TeraScale 3]: https://en.wikipedia.org/wiki/TeraScale_%28microarchitecture%29#TeraScale_3
diff --git a/src/mainboard/asus/a88xm-e/BiosCallOuts.c b/src/mainboard/asus/a88xm-e/BiosCallOuts.c
new file mode 100644
index 0000000..56c1753
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/BiosCallOuts.c
@@ -0,0 +1,98 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <AGESA.h>
+#include <northbridge/amd/agesa/BiosCallOuts.h>
+#include <northbridge/amd/agesa/state_machine.h>
+
+#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h>
+#include <stdlib.h>
+
+const BIOS_CALLOUT_STRUCT BiosCallouts[] =
+{
+ {AGESA_DO_RESET, agesa_Reset },
+ {AGESA_READ_SPD, agesa_ReadSpd },
+ {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
+ {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
+ {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
+ {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
+ {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
+ {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }
+};
+const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
+
+/**
+ * ASUS A88XM-E board ALC887-VD Verb Table
+ *
+ * Copied from `/sys/class/sound/hwC1D0/init_pin_configs` when running
+ * the vendor BIOS.
+ */
+#if !IS_ENABLED(CONFIG_BOARD_ASUS_A88XM_E)
+const CODEC_ENTRY a88xm_e_alc887_VerbTbl[] = {
+ {0x11, 0x90460130},
+ {0x12, 0x40330000},
+ {0x14, 0x01014010},
+ {0x15, 0x411111f0},
+ {0x16, 0x411111f0},
+ {0x17, 0x411111f0},
+ {0x18, 0x01a19040},
+ {0x19, 0x02a19050},
+ {0x1a, 0x0181304f},
+ {0x1b, 0x02214020},
+ {0x1c, 0x411111f0},
+ {0x1d, 0x4044c601},
+ {0x1e, 0x411111f0},
+ {0x1f, 0x411111f0}
+ };
+#else
+const CODEC_ENTRY a88xm_e_alc887_VerbTbl[] = {
+ {0x11, 0x90460130},
+ {0x12, 0x40330000},
+ {0x14, 0x01014010},
+ {0x15, 0x411111f0},
+ {0x16, 0x411111f0},
+ {0x17, 0x411111f0},
+ {0x18, 0x01a19040},
+ {0x19, 0x02a19050},
+ {0x1a, 0x0181304f},
+ {0x1b, 0x02214020},
+ {0x1c, 0x411111f0},
+ {0x1d, 0x4044c601},
+ {0x1e, 0x411111f0},
+ {0x1f, 0x411111f0}
+};
+#endif
+
+static const CODEC_TBL_LIST CodecTableList[] =
+{
+ {0x10ec0887, (CODEC_ENTRY*)&a88xm_e_alc887_VerbTbl[0]},
+ {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
+};
+
+void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
+{
+ FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE);
+}
+
+void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
+{
+ /* Azalia Controller OEM Codec Table Pointer */
+ FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]);
+
+ /* Fan Control */
+ FchParams_env->Imc.ImcEnable = FALSE;
+ FchParams_env->Hwm.HwMonitorEnable = FALSE;
+ FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */
+}
diff --git a/src/mainboard/asus/a88xm-e/Kconfig b/src/mainboard/asus/a88xm-e/Kconfig
new file mode 100644
index 0000000..70be2f1
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/Kconfig
@@ -0,0 +1,117 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+# Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+if BOARD_ASUS_A88XM_E
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select CPU_AMD_AGESA_FAMILY15_TN
+ select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
+ select SOUTHBRIDGE_AMD_AGESA_HUDSON
+ select HAVE_OPTION_TABLE
+ select HAVE_PIRQ_TABLE
+ select HAVE_MP_TABLE
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select SUPERIO_ITE_IT8728F
+ select BOARD_ROMSIZE_KB_8192
+ select GFXUMA
+
+choice
+ prompt "DDR3 memory voltage"
+ default BOARD_ASUS_A88XM_E_DDR3_VOLT_150
+
+config BOARD_ASUS_A88XM_E_DDR3_VOLT_135
+ bool "1.35V"
+ help
+ Set DRR3 memory voltage to 1.35V
+config BOARD_ASUS_A88XM_E_DDR3_VOLT_150
+ bool "1.50V"
+ help
+ Set DRR3 memory voltage to 1.50V
+config BOARD_ASUS_A88XM_E_DDR3_VOLT_165
+ bool "1.65V"
+ help
+ Set DRR3 memory voltage to 1.65V
+endchoice
+
+config BOARD_ASUS_A88XM_E_DDR3_VOLT_VAL
+ hex
+ default 0x9e if BOARD_ASUS_A88XM_E_DDR3_VOLT_135
+ default 0x0 if BOARD_ASUS_A88XM_E_DDR3_VOLT_150
+ default 0x1e if BOARD_ASUS_A88XM_E_DDR3_VOLT_165
+
+config MAINBOARD_DIR
+ string
+ default asus/a88xm-e
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "A88XM-E" if BOARD_ASUS_A88XM_E
+
+config HW_MEM_HOLE_SIZEK
+ hex
+ default 0x200000
+
+config MAX_CPUS
+ int
+ default 4
+
+config HUDSON_XHCI_FWM
+ bool
+ default n
+
+config HUDSON_IMC_FWM
+ bool
+ default n
+
+config IRQ_SLOT_COUNT
+ int
+ default 11
+
+config ONBOARD_VGA_IS_PRIMARY
+ bool
+ default y
+
+config VGA_BIOS_ID
+ string
+ default "1002,990e"
+
+config CONFIG_DRIVERS_PS2_KEYBOARD
+ bool
+ default y
+
+config CONFIG_HUDSON_XHCI_ENABLE
+ bool
+ default n
+
+config HUDSON_LEGACY_FREE
+ bool
+ default n
+
+config POST_IO
+ bool
+ default n
+
+config CONFIG_POST_DEVICE_PCI_PCIE
+ bool
+ default y
+
+config DEVICETREE
+ string
+ default "devicetree_a88xm-e.cb"
+
+endif # BOARD_ASUS_A88XM_E
diff --git a/src/mainboard/asus/a88xm-e/Kconfig.name b/src/mainboard/asus/a88xm-e/Kconfig.name
new file mode 100644
index 0000000..492d610
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_ASUS_A88XM_E
+ bool "A88XM-E"
diff --git a/src/mainboard/asus/a88xm-e/Makefile.inc b/src/mainboard/asus/a88xm-e/Makefile.inc
new file mode 100644
index 0000000..f8895fa
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/Makefile.inc
@@ -0,0 +1,22 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+romstage-y += buildOpts.c
+romstage-y += BiosCallOuts.c
+romstage-y += OemCustomize.c
+
+ramstage-y += buildOpts.c
+ramstage-y += BiosCallOuts.c
+ramstage-y += OemCustomize.c
diff --git a/src/mainboard/asus/a88xm-e/OemCustomize.c b/src/mainboard/asus/a88xm-e/OemCustomize.c
new file mode 100644
index 0000000..4c4c5bf
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/OemCustomize.c
@@ -0,0 +1,177 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <Porting.h>
+#include <AGESA.h>
+
+#include <northbridge/amd/agesa/state_machine.h>
+#include <PlatformMemoryConfiguration.h>
+
+/*
+ * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)
+ *
+ * Lane Id
+ * 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8
+ * 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8
+ * 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8
+ * 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8
+ * 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7
+ * 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7
+ * 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7
+ * 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7
+ * 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI
+ * 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI
+ * 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI
+ * 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI
+ * 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI
+ * 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI
+ * 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI
+ * 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI
+ * 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI
+ * 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI
+ * 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI
+ * 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI
+ * 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI
+ * 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI
+ * 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI
+ * 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI
+ * 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs)
+ * 25 DP0_TX[P,N]1
+ * 26 DP0_TX[P,N]2
+ * 27 DP0_TX[P,N]3
+ * 28 DP1_TX[P,N]0
+ * 29 DP1_TX[P,N]1
+ * 30 DP1_TX[P,N]2
+ * 31 DP1_TX[P,N]3
+ * 32 DP2_TX[P,N]0
+ * 33 DP2_TX[P,N]1
+ * 34 DP2_TX[P,N]2
+ * 35 DP2_TX[P,N]3
+ * 36 DP2_TX[P,N]4
+ * 37 DP2_TX[P,N]5
+ * 38 DP2_TX[P,N]6
+ */
+
+static const PCIe_PORT_DESCRIPTOR PortList[] = {
+ /* PCIe port, Lanes 8:23, PCI Device Number 2, blue x16 slot */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23),
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
+ },
+ /* PCIe port, Lanes 4:7, PCI Device Number 4, black x16 slot (in fact x4) */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
+ },
+ /* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */
+ {
+ DESCRIPTOR_TERMINATE_LIST,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0)
+ },
+};
+
+/*
+ * It is not known, if the setup is complete.
+ *
+ * Tested and works: VGA/DVI
+ * Untested: HDMI
+ */
+static const PCIe_DDI_DESCRIPTOR DdiList[] = {
+ // DP0 to HDMI0/DP
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1)
+ },
+ // DP1 to FCH
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
+ },
+ // DP2 to HDMI1/DP
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3)
+ },
+};
+
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+ .Flags = DESCRIPTOR_TERMINATE_LIST,
+ .SocketId = 0,
+ .PciePortList = PortList,
+ .DdiLinkList = DdiList,
+};
+
+void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
+{
+ FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
+ FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchReset->Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+}
+
+void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
+{
+ InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
+ InitEarly->GnbConfig.PsppPolicy = 0;
+}
+
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+
+static CONST PSO_ENTRY ROMDATA MemoryTable_XM_E[] = {
+
+ NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
+ NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
+
+ PSO_END
+};
+
+void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
+{
+ if (IS_ENABLED(CONFIG_BOARD_ASUS_A88XM_E))
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *) MemoryTable_XM_E;
+}
+
+void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)
+{
+ /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
+ InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
+}
diff --git a/src/mainboard/asus/a88xm-e/OptionsIds.h b/src/mainboard/asus/a88xm-e/OptionsIds.h
new file mode 100644
index 0000000..b45f5a8
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/OptionsIds.h
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/**
+ * @file
+ *
+ * IDS Option File
+ *
+ * This file is used to switch on/off IDS features.
+ *
+ */
+#ifndef _OPTION_IDS_H_
+#define _OPTION_IDS_H_
+
+/**
+ *
+ * This file generates the defaults tables for the Integrated Debug Support
+ * Module. The documented build options are imported from a user controlled
+ * file for processing. The build options for the Integrated Debug Support
+ * Module are listed below:
+ *
+ * IDSOPT_IDS_ENABLED
+ * IDSOPT_ERROR_TRAP_ENABLED
+ * IDSOPT_CONTROL_ENABLED
+ * IDSOPT_TRACING_ENABLED
+ * IDSOPT_PERF_ANALYSIS
+ * IDSOPT_ASSERT_ENABLED
+ * IDS_DEBUG_PORT
+ * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+ *
+ **/
+
+//#define IDSOPT_IDS_ENABLED TRUE
+//#define IDSOPT_CONTROL_ENABLED TRUE
+#define IDSOPT_TRACING_ENABLED TRUE
+#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
+//#define IDSOPT_PERF_ANALYSIS TRUE
+#define IDSOPT_ASSERT_ENABLED TRUE
+//#undef IDSOPT_DEBUG_ENABLED
+//#define IDSOPT_DEBUG_ENABLED FALSE
+//#undef IDSOPT_HOST_SIMNOW
+//#define IDSOPT_HOST_SIMNOW FALSE
+//#undef IDSOPT_HOST_HDT
+//#define IDSOPT_HOST_HDT FALSE
+//#define IDS_DEBUG_PORT 0x80
+
+#endif
diff --git a/src/mainboard/asus/a88xm-e/acpi/cpstate.asl b/src/mainboard/asus/a88xm-e/acpi/cpstate.asl
new file mode 100644
index 0000000..69de2d8
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/cpstate.asl
@@ -0,0 +1,112 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* This file defines the processor and performance state capability
+ * for each core in the system. It is included into the DSDT for each
+ * core. It assumes that each core of the system has the same performance
+ * characteristics.
+*/
+/*
+#include <arch/acpi.h>
+DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001)
+ {
+ Scope (\_PR) {
+ Processor(CPU0,0,0x808,0x06) {
+ #include "cpstate.asl"
+ }
+ Processor(CPU1,1,0x0,0x0) {
+ #include "cpstate.asl"
+ }
+ Processor(CPU2,2,0x0,0x0) {
+ #include "cpstate.asl"
+ }
+ Processor(CPU3,3,0x0,0x0) {
+ #include "cpstate.asl"
+ }
+ }
+*/
+ /* P-state support: The maximum number of P-states supported by the */
+ /* CPUs we'll use is 6. */
+ /* Get from AMI BIOS. */
+ Name(_PSS, Package(){
+ Package()
+ {
+ 0x00000D48,
+ 0x00011170,
+ 0x00000004,
+ 0x00000004,
+ 0x00000000,
+ 0x00000000
+ },
+
+ Package()
+ {
+ 0x00000AF0,
+ 0x0000C544,
+ 0x00000004,
+ 0x00000004,
+ 0x00000001,
+ 0x00000001
+ },
+
+ Package()
+ {
+ 0x000009C4,
+ 0x0000B3B0,
+ 0x00000004,
+ 0x00000004,
+ 0x00000002,
+ 0x00000002
+ },
+
+ Package()
+ {
+ 0x00000898,
+ 0x0000ABE0,
+ 0x00000004,
+ 0x00000004,
+ 0x00000003,
+ 0x00000003
+ },
+
+ Package()
+ {
+ 0x00000708,
+ 0x0000A410,
+ 0x00000004,
+ 0x00000004,
+ 0x00000004,
+ 0x00000004
+ },
+
+ Package()
+ {
+ 0x00000578,
+ 0x00006F54,
+ 0x00000004,
+ 0x00000004,
+ 0x00000005,
+ 0x00000005
+ }
+ })
+
+ Name(_PCT, Package(){
+ ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
+ ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
+ })
+
+ Method(_PPC, 0){
+ Return(0)
+ }
diff --git a/src/mainboard/asus/a88xm-e/acpi/gpe.asl b/src/mainboard/asus/a88xm-e/acpi/gpe.asl
new file mode 100644
index 0000000..297db37
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/gpe.asl
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope(\_GPE) { /* Start Scope GPE */
+
+ /* General event 3 */
+ Method(_L03) {
+ /* DBGO("\\_GPE\\_L00\n") */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* Legacy PM event */
+ Method(_L08) {
+ /* DBGO("\\_GPE\\_L08\n") */
+ }
+
+ /* Temp warning (TWarn) event */
+ Method(_L09) {
+ /* DBGO("\\_GPE\\_L09\n") */
+ /* Notify (\_TZ.TZ00, 0x80) */
+ }
+
+ /* USB controller PME# */
+ Method(_L0B) {
+ /* DBGO("\\_GPE\\_L0B\n") */
+ Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* ExtEvent0 SCI event */
+ Method(_L10) {
+ /* DBGO("\\_GPE\\_L10\n") */
+ }
+
+
+ /* ExtEvent1 SCI event */
+ Method(_L11) {
+ /* DBGO("\\_GPE\\_L11\n") */
+ }
+
+ /* GPIO0 or GEvent8 event */
+ Method(_L18) {
+ /* DBGO("\\_GPE\\_L18\n") */
+ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* Azalia SCI event */
+ Method(_L1B) {
+ /* DBGO("\\_GPE\\_L1B\n") */
+ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+} /* End Scope GPE */
diff --git a/src/mainboard/asus/a88xm-e/acpi/mainboard.asl b/src/mainboard/asus/a88xm-e/acpi/mainboard.asl
new file mode 100644
index 0000000..8398c88
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/mainboard.asl
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+ /* Data to be patched by the BIOS during POST */
+ /* FIXME the patching is not done yet! */
+ /* Memory related values */
+ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
+ Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+ Name(PBLN, 0x0) /* Length of BIOS area */
+
+ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
+ Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
+ Name(HPBA, 0xFED00000) /* Base address of HPET table */
+
+ /* Some global data */
+ Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+ Name(OSV, Ones) /* Assume nothing */
+ Name(PMOD, One) /* Assume APIC */
diff --git a/src/mainboard/asus/a88xm-e/acpi/routing.asl b/src/mainboard/asus/a88xm-e/acpi/routing.asl
new file mode 100644
index 0000000..0af6b42
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/routing.asl
@@ -0,0 +1,258 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+ /* Routing is in System Bus scope */
+ Name(PR0, Package(){
+ /* NB devices */
+ /* Bus 0, Dev 0 - F15 Host Controller */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ Package(){0x0001FFFF, 0, INTB, 0 },
+ Package(){0x0001FFFF, 1, INTC, 0 },
+
+ /* Bus 0, Dev 2 - PCIe Bridge for x16 slot */
+ Package(){0x0002FFFF, 0, INTC, 0 },
+ Package(){0x0002FFFF, 1, INTD, 0 },
+ Package(){0x0002FFFF, 2, INTA, 0 },
+ Package(){0x0002FFFF, 3, INTB, 0 },
+
+ /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+
+ /* Bus 0, Dev 4 - PCIe Bridge for 4x slot */
+ Package(){0x0004FFFF, 0, INTA, 0 },
+ Package(){0x0004FFFF, 1, INTB, 0 },
+ Package(){0x0004FFFF, 2, INTC, 0 },
+ Package(){0x0004FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+ /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
+ /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
+ /* Bus 0, Dev 8 - Southbridge port (normally hidden) */
+
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
+ Package(){0x0014FFFF, 0, INTA, 0 },
+ Package(){0x0014FFFF, 1, INTB, 0 },
+ Package(){0x0014FFFF, 2, INTC, 0 },
+ Package(){0x0014FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
+ * EHCI @ func 2 */
+ Package(){0x0012FFFF, 0, INTC, 0 },
+ Package(){0x0012FFFF, 1, INTB, 0 },
+
+ Package(){0x0013FFFF, 0, INTC, 0 },
+ Package(){0x0013FFFF, 1, INTB, 0 },
+
+ Package(){0x0016FFFF, 0, INTC, 0 },
+ Package(){0x0016FFFF, 1, INTB, 0 },
+
+ /* SB devices */
+ /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, INTC, 0 },
+ Package(){0x0010FFFF, 1, INTB, 0 },
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, INTD, 0 },
+
+ /* Bus 0, Dev 21 Pcie Bridge */
+ Package(){0x0015FFFF, 0, INTA, 0 },
+ Package(){0x0015FFFF, 1, INTB, 0 },
+ Package(){0x0015FFFF, 2, INTC, 0 },
+ Package(){0x0015FFFF, 3, INTD, 0 },
+ })
+
+ Name(APR0, Package(){
+ /* NB devices in APIC mode */
+ /* Bus 0, Dev 0 - F15 Host Controller */
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ Package(){0x0001FFFF, 0, 0, 17 },
+ Package(){0x0001FFFF, 1, 0, 18 },
+
+ /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */
+ Package(){0x0002FFFF, 0, 0, 18 },
+ Package(){0x0002FFFF, 1, 0, 19 },
+ Package(){0x0002FFFF, 2, 0, 16 },
+ Package(){0x0002FFFF, 3, 0, 17 },
+
+ /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+
+ /* Bus 0, Dev 4 - PCIe Bridge for x4 PCIe Slot black */
+ Package(){0x0004FFFF, 0, 0, 16 },
+ Package(){0x0004FFFF, 1, 0, 17 },
+ Package(){0x0004FFFF, 2, 0, 18 },
+ Package(){0x0004FFFF, 3, 0, 19 },
+
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+ /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
+ /* Bus 0, Dev 7 - PCIe Bridge for network card */
+ /* Bus 0, Dev 8 - Southbridge port (normally hidden) */
+
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
+ Package(){0x0014FFFF, 0, 0, 16 },
+ Package(){0x0014FFFF, 1, 0, 17 },
+ Package(){0x0014FFFF, 2, 0, 18 },
+ Package(){0x0014FFFF, 3, 0, 19 },
+
+ /* SB devices in APIC mode */
+ /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
+ * EHCI @ func 2 */
+ Package(){0x0012FFFF, 0, 0, 18 },
+ Package(){0x0012FFFF, 1, 0, 17 },
+
+ Package(){0x0013FFFF, 0, 0, 18 },
+ Package(){0x0013FFFF, 1, 0, 17 },
+
+ Package(){0x0016FFFF, 0, 0, 18 },
+ Package(){0x0016FFFF, 1, 0, 17 },
+
+ /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, 0, 0x12},
+ Package(){0x0010FFFF, 1, 0, 0x11},
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, 0, 19 },
+
+ /* Bus 0, Dev 21 PCIE Bridge */
+ Package(){0x0015FFFF, 0, 0, 17 },
+ Package(){0x0015FFFF, 1, 0, 18 },
+ Package(){0x0015FFFF, 2, 0, 19 },
+ Package(){0x0015FFFF, 3, 0, 16 },
+ })
+
+ Name(PS2, Package(){
+ /* The external GFX - Hooked to PCIe slot 2 */
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+ Name(APS2, Package(){
+ /* The external GFX - Hooked to PCIe slot 2 */
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+ /* black slot */
+ Name(PS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+ })
+ Name(APS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name(PS5, Package(){
+ /* PCIe slot - Hooked to PCIe slot 5 */
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+ })
+ Name(APS5, Package(){
+ /* PCIe slot - Hooked to PCIe slot 5 */
+ Package(){0x0000FFFF, 0, 0, 17 },
+ Package(){0x0000FFFF, 1, 0, 18 },
+ Package(){0x0000FFFF, 2, 0, 19 },
+ Package(){0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name(PS6, Package(){
+ /* PCIe slot - Hooked to PCIe slot 6 */
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+ })
+ Name(APS6, Package(){
+ /* PCIe slot - Hooked to PCIe slot 6 */
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name(PS7, Package(){
+ /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+
+ Name(APS7, Package(){
+ /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+ Package(){0x0000FFFF, 0, 0, 19 },
+ Package(){0x0000FFFF, 1, 0, 16 },
+ Package(){0x0000FFFF, 2, 0, 17 },
+ Package(){0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name(PBR0, Package(){
+ /* PCIx1 on SB */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+ })
+ Name(ABR0, Package(){
+ /* PCIx1 on SB */
+ Package(){0x0000FFFF, 0, 0, 0x10 },
+ Package(){0x0000FFFF, 1, 0, 0x11 },
+ Package(){0x0000FFFF, 2, 0, 0x12 },
+ Package(){0x0000FFFF, 3, 0, 0x13 },
+ })
+
+ Name(PBR1, Package(){
+ /* Onboard network */
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+ })
+ Name(ABR1, Package(){
+ /* Onboard network */
+ Package(){0x0000FFFF, 0, 0, 0x11 },
+ Package(){0x0000FFFF, 1, 0, 0x12 },
+ Package(){0x0000FFFF, 2, 0, 0x13 },
+ Package(){0x0000FFFF, 3, 0, 0x10 },
+ })
+
+ /* SB PCI Bridge */
+ Name(PCIB, Package(){
+ /* PCI slots: slot 0 behind Dev14, Fun4. */
+ Package(){0x0005FFFF, 0, 0, 0x14 },
+ Package(){0x0005FFFF, 1, 0, 0x15 },
+ Package(){0x0005FFFF, 2, 0, 0x16 },
+ Package(){0x0005FFFF, 3, 0, 0x17 },
+ })
diff --git a/src/mainboard/asus/a88xm-e/acpi/sata.asl b/src/mainboard/asus/a88xm-e/acpi/sata.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/sata.asl
diff --git a/src/mainboard/asus/a88xm-e/acpi/si.asl b/src/mainboard/asus/a88xm-e/acpi/si.asl
new file mode 100644
index 0000000..ff0c3cf
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/si.asl
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+ Scope(\_SI) {
+ Method(_SST, 1) {
+ /* DBGO("\\_SI\\_SST\n") */
+ /* DBGO(" New Indicator state: ") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+ }
+ } /* End Scope SI */
diff --git a/src/mainboard/asus/a88xm-e/acpi/sleep.asl b/src/mainboard/asus/a88xm-e/acpi/sleep.asl
new file mode 100644
index 0000000..08b7de4
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/sleep.asl
@@ -0,0 +1,96 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Wake status package */
+Name(WKST,Package(){Zero, Zero})
+
+/*
+* \_PTS - Prepare to Sleep method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2, etc
+*
+* Exit:
+* -none-
+*
+* The _PTS control method is executed at the beginning of the sleep process
+* for S1-S5. The sleeping value is passed to the _PTS control method. This
+* control method may be executed a relatively long time before entering the
+* sleep state and the OS may abort the operation without notification to
+* the ACPI driver. This method cannot modify the configuration or power
+* state of any device in the system.
+*/
+Method(\_PTS, 1) {
+ /* DBGO("\\_PTS\n") */
+ /* DBGO("From S0 to S") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+
+ /* Clear sleep SMI status flag and enable sleep SMI trap. */
+ /*Store(One, CSSM)
+ Store(One, SSEN)*/
+
+ /* On older chips, clear PciExpWakeDisEn */
+ /*if (LLessEqual(\_SB.SBRI, 0x13)) {
+ * Store(0,\_SB.PWDE)
+ *}
+ */
+
+ /* Clear wake status structure. */
+ Store(0, Index(WKST,0))
+ Store(0, Index(WKST,1))
+
+ Store (0x07, UPWS)
+} /* End Method(\_PTS) */
+
+/*
+* \_BFS OEM Back From Sleep method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2
+*
+* Exit:
+* -none-
+*/
+Method(\_BFS, 1) {
+ /* DBGO("\\_BFS\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+}
+
+/*
+* \_WAK System Wake method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2
+*
+* Exit:
+* Return package of 2 DWords
+* Dword 1 - Status
+* 0x00000000 wake succeeded
+* 0x00000001 Wake was signaled but failed due to lack of power
+* 0x00000002 Wake was signaled but failed due to thermal condition
+* Dword 2 - Power Supply state
+* if non-zero the effective S-state the power supply entered
+*/
+Method(\_WAK, 1) {
+ /* DBGO("\\_WAK\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+
+ Return(WKST)
+} /* End Method(\_WAK) */
diff --git a/src/mainboard/asus/a88xm-e/acpi/superio.asl b/src/mainboard/asus/a88xm-e/acpi/superio.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/superio.asl
diff --git a/src/mainboard/asus/a88xm-e/acpi/thermal.asl b/src/mainboard/asus/a88xm-e/acpi/thermal.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/thermal.asl
diff --git a/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl b/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
new file mode 100644
index 0000000..f5d6980
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* USB overcurrent mapping pins. */
+Name(UOM0, 0)
+Name(UOM1, 2)
+Name(UOM2, 0)
+Name(UOM3, 7)
+Name(UOM4, 2)
+Name(UOM5, 2)
+Name(UOM6, 6)
+Name(UOM7, 2)
+Name(UOM8, 6)
+Name(UOM9, 6)
diff --git a/src/mainboard/asus/a88xm-e/acpi_tables.c b/src/mainboard/asus/a88xm-e/acpi_tables.c
new file mode 100644
index 0000000..f94fde0
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi_tables.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <string.h>
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* create all subtables for processors */
+ current = acpi_create_madt_lapics(current);
+
+ /* Write Hudson IOAPIC, only one */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
+ IO_APIC_ADDR, 0);
+
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, 0xF);
+ /* 0: mean bus 0--->ISA */
+ /* 0: PIC 0 */
+ /* 2: APIC 2 */
+ /* 5 mean: 0101 --> Edge-triggered, Active high */
+
+ /* create all subtables for processors */
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
+ /* 1: LINT1 connect to NMI */
+
+ return current;
+}
diff --git a/src/mainboard/asus/a88xm-e/board_info.txt b/src/mainboard/asus/a88xm-e/board_info.txt
new file mode 100644
index 0000000..bc090ff
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://www.asus.com/Motherboards/A88XME/
+ROM package: DIP8
+ROM protocol: [http://www.winbond.com/hq/product/code-storage-flash-memory/serial-nor-flas… SPI]
+ROM socketed: y
+Flashrom support: y (without AmdSpiRomProtect modules)
+Release year: 2014
diff --git a/src/mainboard/asus/a88xm-e/buildOpts.c b/src/mainboard/asus/a88xm-e/buildOpts.c
new file mode 100644
index 0000000..c324532
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/buildOpts.c
@@ -0,0 +1,346 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/**
+ * @file
+ *
+ * AMD User options selection for a Brazos platform solution system
+ *
+ * This file is placed in the user's platform directory and contains the
+ * build option selections desired for that platform.
+ *
+ * For Information about this file, see @ref platforminstall.
+ *
+ */
+
+#include <stdlib.h>
+
+#include <vendorcode/amd/agesa/f15tn/AGESA.h>
+
+/* Include the files that instantiate the configuration definitions. */
+#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
+/* the next two headers depend on heapManager.h */
+#include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h>
+/* These tables are optional and may be used to adjust memory timing settings */
+#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h>
+
+
+/* Select the CPU family. */
+#define INSTALL_FAMILY_10_SUPPORT FALSE
+#define INSTALL_FAMILY_12_SUPPORT FALSE
+#define INSTALL_FAMILY_14_SUPPORT FALSE
+#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
+
+/* Select the CPU socket type. */
+#define INSTALL_G34_SOCKET_SUPPORT FALSE
+#define INSTALL_C32_SOCKET_SUPPORT FALSE
+#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
+#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
+#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
+#define INSTALL_FS1_SOCKET_SUPPORT FALSE
+#define INSTALL_FM1_SOCKET_SUPPORT FALSE
+#define INSTALL_FP2_SOCKET_SUPPORT FALSE
+#define INSTALL_FT1_SOCKET_SUPPORT FALSE
+#define INSTALL_AM3_SOCKET_SUPPORT FALSE
+
+#define INSTALL_FM2_SOCKET_SUPPORT TRUE
+
+//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
+#define BLDOPT_REMOVE_SODIMMS_SUPPORT TRUE
+#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
+#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
+//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
+//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
+#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
+#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
+#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
+//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
+#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
+//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
+#define BLDOPT_REMOVE_SRAT FALSE //TRUE
+#define BLDOPT_REMOVE_SLIT FALSE //TRUE
+#define BLDOPT_REMOVE_WHEA FALSE //TRUE
+#define BLDOPT_REMOVE_CRAT TRUE
+#define BLDOPT_REMOVE_DMI TRUE
+//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
+
+//This element selects whether P-States should be forced to be independent,
+// as reported by the ACPI _PSD object. For single-link processors,
+// setting TRUE for OS to support this feature.
+
+//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE
+
+#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
+#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
+/* Build configuration values here.
+ */
+#define BLDCFG_VRM_CURRENT_LIMIT 90000
+#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
+#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0
+#define BLDCFG_PLAT_NUM_IO_APICS 3
+#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
+#define BLDCFG_MEM_INIT_PSTATE 0
+
+#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
+
+#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY
+#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
+#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
+#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
+#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE
+#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE
+#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
+#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
+#define BLDCFG_MEMORY_POWER_DOWN TRUE
+#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
+#define BLDCFG_ONLINE_SPARE FALSE
+#define BLDCFG_BANK_SWIZZLE TRUE
+#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
+#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY
+#define BLDCFG_DQS_TRAINING_CONTROL TRUE
+#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
+#define BLDCFG_USE_BURST_MODE FALSE
+#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
+#define BLDCFG_ENABLE_ECC_FEATURE FALSE
+#define BLDCFG_ECC_REDIRECTION FALSE
+#define BLDCFG_SCRUB_DRAM_RATE 0
+#define BLDCFG_SCRUB_L2_RATE 0
+#define BLDCFG_SCRUB_L3_RATE 0
+#define BLDCFG_SCRUB_IC_RATE 0
+#define BLDCFG_SCRUB_DC_RATE 0
+#define BLDCFG_ECC_SYMBOL_SIZE 4
+#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
+#define BLDCFG_ECC_SYNC_FLOOD FALSE
+#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
+#define BLDCFG_1GB_ALIGN FALSE
+#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
+#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36%
+#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770
+
+#define BLDOPT_REMOVE_ALIB FALSE
+#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
+#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P'
+#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
+#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6
+
+#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200
+#define BLDCFG_CFG_ABM_SUPPORT 0
+
+//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
+
+// Specify the default values for the VRM controlling the VDDNB plane.
+// If not specified, the values used for the core VRM will be applied
+//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity
+//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L
+//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime
+//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity
+//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity
+//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity
+
+#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000
+
+#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3
+#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
+
+#if IS_ENABLED(CONFIG_GFXUMA)
+#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
+#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
+//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
+#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M
+#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
+#endif
+
+#define BLDCFG_IOMMU_SUPPORT TRUE
+
+#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
+//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
+//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID
+//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
+
+/* Process the options...
+ * This file include MUST occur AFTER the user option selection settings
+ */
+/*
+ * Customized OEM build configurations for FCH component
+ */
+// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00
+// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20
+// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00
+// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
+// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
+// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
+// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
+// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420
+// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000
+// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000
+// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000
+// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0
+// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00
+// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000
+// #define BLDCFG_AZALIA_SSID 0x780D1022
+// #define BLDCFG_SMBUS_SSID 0x780B1022
+// #define BLDCFG_IDE_SSID 0x780C1022
+// #define BLDCFG_SATA_AHCI_SSID 0x78011022
+// #define BLDCFG_SATA_IDE_SSID 0x78001022
+// #define BLDCFG_SATA_RAID5_SSID 0x78031022
+// #define BLDCFG_SATA_RAID_SSID 0x78021022
+// #define BLDCFG_EHCI_SSID 0x78081022
+// #define BLDCFG_OHCI_SSID 0x78071022
+// #define BLDCFG_LPC_SSID 0x780E1022
+// #define BLDCFG_SD_SSID 0x78061022
+// #define BLDCFG_XHCI_SSID 0x78121022
+// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE
+// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
+// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4
+// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE
+// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE
+// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
+// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
+
+CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
+{
+ { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
+ { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
+ { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
+ { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
+ { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
+ { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
+ { CPU_LIST_TERMINAL }
+};
+
+#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
+
+ // This is the delivery package title, "BrazosPI"
+ // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
+
+ // This is the release version number of the AGESA component
+ // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
+
+/* MEMORY_BUS_SPEED */
+#define DDR400_FREQUENCY 200 ///< DDR 400
+#define DDR533_FREQUENCY 266 ///< DDR 533
+#define DDR667_FREQUENCY 333 ///< DDR 667
+#define DDR800_FREQUENCY 400 ///< DDR 800
+#define DDR1066_FREQUENCY 533 ///< DDR 1066
+#define DDR1333_FREQUENCY 667 ///< DDR 1333
+#define DDR1600_FREQUENCY 800 ///< DDR 1600
+#define DDR1866_FREQUENCY 933 ///< DDR 1866
+#define DDR2100_FREQUENCY 1050 ///< DDR 2100
+#define DDR2133_FREQUENCY 1066 ///< DDR 2133
+#define DDR2400_FREQUENCY 1200 ///< DDR 2400
+#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
+
+/* QUANDRANK_TYPE*/
+#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
+#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
+
+/* USER_MEMORY_TIMING_MODE */
+#define TIMING_MODE_AUTO 0 ///< Use best rate possible
+#define TIMING_MODE_LIMITED 1 ///< Set user top limit
+#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
+
+/* POWER_DOWN_MODE */
+#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
+#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
+
+/*
+ * Agesa optional capabilities selection.
+ * Uncomment and mark FALSE those features you wish to include in the build.
+ * Comment out or mark TRUE those features you want to REMOVE from the build.
+ */
+
+#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
+#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
+/* The AGESA likes to enable 512 bytes region on this base for LPC bus */
+#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
+#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800
+#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804
+#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808
+#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810
+#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820
+#define DFLT_SPI_BASE_ADDRESS 0xFEC10000
+#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0
+#define DFLT_HPET_BASE_ADDRESS 0xFED00000
+#define DFLT_SMI_CMD_PORT 0xB0
+#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
+#define DFLT_GEC_BASE_ADDRESS 0xFED61000
+#define DFLT_AZALIA_SSID 0x780D1022
+#define DFLT_SMBUS_SSID 0x780B1022
+#define DFLT_IDE_SSID 0x780C1022
+#define DFLT_SATA_AHCI_SSID 0x78011022
+#define DFLT_SATA_IDE_SSID 0x78001022
+#define DFLT_SATA_RAID5_SSID 0x78031022
+#define DFLT_SATA_RAID_SSID 0x78021022
+#define DFLT_EHCI_SSID 0x78081022
+#define DFLT_OHCI_SSID 0x78071022
+#define DFLT_LPC_SSID 0x780E1022
+#define DFLT_SD_SSID 0x78061022
+#define DFLT_XHCI_SSID 0x78121022
+#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE
+#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
+#define DFLT_FCH_GPP_LINK_CONFIG PortA1B1C1D1
+#define DFLT_FCH_GPP_PORT0_PRESENT TRUE
+#define DFLT_FCH_GPP_PORT1_PRESENT TRUE
+#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
+//#define BLDCFG_IR_PIN_CONTROL 0x33
+//#define FCH_NO_XHCI_SUPPORT FALSE
+GPIO_CONTROL a88xm_e_gpio[] = {
+// {183, Function1, PullUpB},
+ {-1}
+};
+#define BLDCFG_FCH_GPIO_CONTROL_LIST (&a88xm_e_gpio[0])
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file. The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE (0)
+#define DFLT_SCRUB_L2_RATE (0)
+#define DFLT_SCRUB_L3_RATE (0)
+#define DFLT_SCRUB_IC_RATE (0)
+#define DFLT_SCRUB_DC_RATE (0)
+#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
+#define DFLT_VRM_SLEW_RATE (5000)
+
+/* Moving this include up will break AGESA. */
+#include <PlatformInstall.h>
diff --git a/src/mainboard/asus/a88xm-e/cmos.layout b/src/mainboard/asus/a88xm-e/cmos.layout
new file mode 100644
index 0000000..e1dbd9a
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/cmos.layout
@@ -0,0 +1,66 @@
+#*****************************************************************************
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#*****************************************************************************
+
+entries
+
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+#392 3 r 0 unused
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
+399 1 e 2 multi_core
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+445 1 e 1 iommu
+456 1 e 1 ECC_memory
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 amd_reserved
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+8 0 400Mhz
+8 1 333Mhz
+8 2 266Mhz
+8 3 200Mhz
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb b/src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb
new file mode 100644
index 0000000..e2b0eea
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb
@@ -0,0 +1,143 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+chip northbridge/amd/agesa/family15tn/root_complex
+
+ device cpu_cluster 0 on
+ chip cpu/amd/agesa/family15tn
+ device lapic 10 on end
+ end
+ end
+
+ device domain 0 on
+ subsystemid 0x1022 0x1410 inherit
+ chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
+
+ chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
+ device pci 0.0 on end # Root Complex
+ device pci 0.2 on end # IOMMU
+ device pci 1.0 on end # Internal Graphics
+ device pci 1.1 on end # Internal Audio (iGPU)
+ device pci 2.0 on end # PCIE x4/x16 yellow (?)
+ device pci 3.0 on end # unused?
+ device pci 4.0 on end # PCIE x4/x16 yellow (?)
+ device pci 5.0 off end # unused
+ device pci 6.0 off end # unused?
+ device pci 7.0 off end # LAN
+ device pci 8.0 off end # NB/SB Link P2P bridge
+ end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
+
+ chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
+ device pci 10.0 on end # XHCI HC0
+ device pci 10.1 on end # XHCI HC1
+ device pci 11.0 on end # SATA
+ device pci 12.0 on end # USB
+ device pci 12.2 on end # USB
+ device pci 13.0 on end # USB
+ device pci 13.2 on end # USB
+ device pci 14.0 on # SMBUS
+ chip drivers/generic/generic #dimm 0
+ device i2c 50 on end # 7-bit SPD address
+ end
+ chip drivers/generic/generic #dimm 1
+ device i2c 51 on end # 7-bit SPD address
+ end
+ end # SM
+ device pci 14.1 off end # IDE 0x439c
+ device pci 14.2 on end # HDA 0x4383
+ device pci 14.3 on # LPC 0x439d
+ chip superio/ite/it8728f
+ register "TMPIN1.mode" = "THERMAL_RESISTOR"
+ register "TMPIN2.mode" = "THERMAL_RESISTOR"
+ register "TMPIN3.mode" = "THERMAL_RESISTOR"
+
+ register "FAN1.mode" = "FAN_SMART_AUTOMATIC"
+ register "FAN1.smart.tmpin" = "1"
+ register "FAN1.smart.tmp_off" = "0x80" # never
+ register "FAN1.smart.tmp_start" = "20"
+ register "FAN1.smart.tmp_full" = "70"
+ register "FAN1.smart.tmp_delta" = "0"
+ register "FAN1.smart.smoothing" = "1"
+ register "FAN1.smart.pwm_start" = "20"
+ register "FAN1.smart.slope" = "32"
+
+ # Enable tacho reading for chassis fan.
+ register "FAN2.mode" = "FAN_MODE_OFF"
+
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.2 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.4 on # Env Controller
+ io 0x60 = 0x290
+ io 0x62 = 0x220
+ irq 0x70 = 0
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.6 off # Mouse
+ irq 0x70 = 12
+ end
+ device pnp 2e.7 on # GPIO
+ io 0x60 = 0x228 #SMI
+ io 0x62 = 0x300 #Simple I/O
+ io 0x64 = 0x238 #Phony resource IT8603E does not have it
+ irq 0x70 = 0
+ end
+ device pnp 2e.a off end # CIR
+ end #superio/ite/it8728f
+ end #
+ device pci 14.3 off end # LPC
+ device pci 14.4 on end # PCI 0x4384
+ device pci 14.5 off end # USB 2
+ device pci 14.6 off end # Gec
+ device pci 14.7 off end # SD
+ device pci 15.0 on end # PCIe 0 - onboard PCIe 1x
+ device pci 15.1 off end # unused
+ device pci 15.2 on end # PCI bridge
+ device pci 15.3 off end # unused
+ end #chip southbridge/amd/agesa/hudson
+
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+ device pci 18.5 on end
+
+ register "spdAddrLookup" = "
+ {
+ { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
+ { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
+ }"
+
+ end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
+ end #domain
+end #chip northbridge/amd/agesa/family15tn/root_complex
diff --git a/src/mainboard/asus/a88xm-e/dsdt.asl b/src/mainboard/asus/a88xm-e/dsdt.asl
new file mode 100644
index 0000000..45a2606
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/dsdt.asl
@@ -0,0 +1,110 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* DefinitionBlock Statement */
+#include <arch/acpi.h>
+DefinitionBlock (
+ "DSDT.AML", /* Output filename */
+ "DSDT", /* Signature */
+ 0x02, /* DSDT Revision, needs to be 2 for 64bit */
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x00010001 /* OEM Revision */
+ )
+{ /* Start of ASL file */
+ /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
+
+ /* Globals for the platform */
+ #include "acpi/mainboard.asl"
+
+ /* Describe the USB Overcurrent pins */
+ #include "acpi/usb_oc.asl"
+
+ /* PCI IRQ mapping for the Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
+
+ /* Describe the processor tree (\_PR) */
+ #include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
+
+ /* Describe the supported Sleep States for this Southbridge */
+ #include <southbridge/amd/common/acpi/sleepstates.asl>
+
+ /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */
+ #include "acpi/sleep.asl"
+
+ Scope(\_SB) {
+ /* global utility methods expected within the \_SB scope */
+ #include <arch/x86/acpi/globutil.asl>
+
+ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
+ #include "acpi/routing.asl"
+
+ Device(PWRB) {
+ Name(_HID, EISAID("PNP0C0C"))
+ Name(_UID, 0xAA)
+ Name(_PRW, Package () {3, 0x04})
+ Name(_STA, 0x0B)
+ }
+
+ Device(PCI0) {
+ /* Describe the AMD Northbridge */
+ #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl>
+
+ /* Describe the AMD Fusion Controller Hub Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/fch.asl>
+
+ /**
+ * TODO: The devices listed here (SBR0 and SBR1) do not appear to
+ * be referenced anywhere and could possibly be removed.
+ */
+ Device(SBR0) { /* PCIe 1x SB */
+ Name(_ADR, 0x00150000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(ABR0) } /* APIC mode */
+ Return (PBR0) /* PIC mode */
+ }
+ }
+
+ Device(SBR1) { /* Onboard network */
+ Name(_ADR, 0x00150001)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT, 0) {
+ If(PMOD){ Return(ABR1) } /* APIC mode */
+ Return (PBR1) /* PIC mode */
+ }
+ }
+ }
+
+ /* Describe PCI INT[A-H] for the Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
+
+ } /* End Scope(_SB) */
+
+ /* Describe SMBUS for the Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
+
+ /* Define the General Purpose Events for the platform */
+ #include "acpi/gpe.asl"
+
+ /* Define the Thermal zones and methods for the platform */
+ #include "acpi/thermal.asl"
+
+ /* Define the System Indicators for the platform */
+ #include "acpi/si.asl"
+
+}
+/* End of ASL file */
diff --git a/src/mainboard/asus/a88xm-e/irq_tables.c b/src/mainboard/asus/a88xm-e/irq_tables.c
new file mode 100644
index 0000000..88d2160
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/irq_tables.c
@@ -0,0 +1,101 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/pirq_routing.h>
+#include <console/console.h>
+#include <device/pci_def.h>
+#include <stdint.h>
+#include <string.h>
+
+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
+ u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+ u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+ u8 slot, u8 rfu)
+{
+ pirq_info->bus = bus;
+ pirq_info->devfn = devfn;
+ pirq_info->irq[0].link = link0;
+ pirq_info->irq[0].bitmap = bitmap0;
+ pirq_info->irq[1].link = link1;
+ pirq_info->irq[1].bitmap = bitmap1;
+ pirq_info->irq[2].link = link2;
+ pirq_info->irq[2].bitmap = bitmap2;
+ pirq_info->irq[3].link = link3;
+ pirq_info->irq[3].bitmap = bitmap3;
+ pirq_info->slot = slot;
+ pirq_info->rfu = rfu;
+}
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ struct irq_routing_table *pirq;
+ struct irq_info *pirq_info;
+ u32 slot_num;
+ u8 *v;
+
+ u8 sum = 0;
+ int i;
+
+ /* Align the table to be 16 byte aligned. */
+ addr += 15;
+ addr &= ~15;
+
+ /* This table must be between 0xf0000 & 0x100000 */
+ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+ pirq = (void *)(addr);
+ v = (u8 *) (addr);
+
+ pirq->signature = PIRQ_SIGNATURE;
+ pirq->version = PIRQ_VERSION;
+
+ pirq->rtr_bus = 0;
+ pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
+
+ pirq->exclusive_irqs = 0;
+
+ pirq->rtr_vendor = 0x1002;
+ pirq->rtr_device = 0x4384;
+
+ pirq->miniport_data = 0;
+
+ memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+ pirq_info = (void *)(&pirq->checksum + 1);
+ slot_num = 0;
+
+ /* pci bridge */
+ write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
+ 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
+ 0);
+ pirq_info++;
+
+ slot_num++;
+
+ pirq->size = 32 + 16 * slot_num;
+
+ for (i = 0; i < pirq->size; i++)
+ sum += v[i];
+
+ sum = pirq->checksum - sum;
+
+ if (sum != pirq->checksum) {
+ pirq->checksum = sum;
+ }
+
+ printk(BIOS_INFO, "write_pirq_routing_table done.\n");
+
+ return (unsigned long)pirq_info;
+}
diff --git a/src/mainboard/asus/a88xm-e/mainboard.c b/src/mainboard/asus/a88xm-e/mainboard.c
new file mode 100644
index 0000000..2a0e618
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/mainboard.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/msr.h>
+#include <device/device.h>
+
+/*************************************************
+ * enable the dedicated function in thatcher board.
+ *************************************************/
+static void mainboard_enable(struct device *dev)
+{
+ msr_t msr;
+
+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+
+ msr = rdmsr(LS_CFG_MSR);
+ msr.lo &= ~(1 << 28);
+ wrmsr(LS_CFG_MSR, msr);
+
+ msr = rdmsr(DC_CFG_MSR);
+ msr.lo &= ~(1 << 4);
+ msr.lo &= ~(1 << 13);
+ wrmsr(DC_CFG_MSR, msr);
+
+ msr = rdmsr(BU_CFG_MSR);
+ msr.lo &= ~(1 << 23);
+ wrmsr(BU_CFG_MSR, msr);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/asus/a88xm-e/mptable.c b/src/mainboard/asus/a88xm-e/mptable.c
new file mode 100644
index 0000000..d97663d
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/mptable.c
@@ -0,0 +1,181 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include <arch/smp/mpspec.h>
+#include <cpu/x86/lapic.h>
+#include <device/pci.h>
+#include <stdint.h>
+#include <string.h>
+#include <southbridge/amd/agesa/hudson/hudson.h>
+
+u8 picr_data[] = {
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ 0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x1F,0x1F
+};
+u8 intr_data[0x54] = {
+ 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x10,0x11,0x12,0x13
+};
+
+static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
+{
+ mc->mpc_length += length;
+ mc->mpc_entry_count++;
+}
+
+static void my_smp_write_bus(struct mp_config_table *mc,
+ unsigned char id, const char *bustype)
+{
+ struct mpc_config_bus *mpc;
+ mpc = smp_next_mpc_entry(mc);
+ memset(mpc, '\0', sizeof(*mpc));
+ mpc->mpc_type = MP_BUS;
+ mpc->mpc_busid = id;
+ memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
+ smp_add_mpc_entry(mc, sizeof(*mpc));
+}
+
+static void *smp_write_config_table(void *v)
+{
+ struct mp_config_table *mc;
+ int bus_isa;
+ u8 byte;
+
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+ mptable_init(mc, LOCAL_APIC_ADDR);
+ memcpy(mc->mpc_oem, "AMD ", 8);
+
+ smp_write_processors(mc);
+
+ //mptable_write_buses(mc, NULL, &bus_isa);
+ my_smp_write_bus(mc, 0, "PCI ");
+ my_smp_write_bus(mc, 1, "PCI ");
+ bus_isa = 0x02;
+ my_smp_write_bus(mc, bus_isa, "ISA ");
+
+ /* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
+
+ /* PIC IRQ routine */
+ for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
+ outb(byte, 0xC00);
+ outb(picr_data[byte], 0xC01);
+ }
+
+ /* APIC IRQ routine */
+ for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+ outb(byte | 0x80, 0xC00);
+ outb(intr_data[byte], 0xC01);
+ }
+
+ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
+
+ /* PCI interrupts are level triggered, and are
+ * associated with a specific bus/device/function tuple.
+ */
+#define PCI_INT(bus, dev, int_sign, pin) \
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+
+ /* IOMMU */
+ PCI_INT(0x0, 0x0, 0x0, 0x10);
+ PCI_INT(0x0, 0x0, 0x1, 0x11);
+ PCI_INT(0x0, 0x0, 0x2, 0x12);
+ PCI_INT(0x0, 0x0, 0x3, 0x13);
+
+ /* Internal VGA */
+ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+
+ /* SMBUS */
+ PCI_INT(0x0, 0x14, 0x0, 0x10);
+
+ /* HD Audio */
+ PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+
+ /* USB */
+ PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
+ PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+ PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+
+ /* sata */
+ PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+
+ /* on board NIC & Slot PCIE. */
+
+ /* PCI slots */
+ struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+ }
+
+ /* PCIe Lan*/
+ PCI_INT(0x0, 0x06, 0x0, 0x13);
+
+ /* FCH PCIe PortA */
+ PCI_INT(0x0, 0x15, 0x0, 0x10);
+ /* FCH PCIe PortB */
+ PCI_INT(0x0, 0x15, 0x1, 0x11);
+ /* FCH PCIe PortC */
+ PCI_INT(0x0, 0x15, 0x2, 0x12);
+ /* FCH PCIe PortD */
+ PCI_INT(0x0, 0x15, 0x3, 0x13);
+
+ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
+ IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
+ /* There is no extension information... */
+
+ /* Compute the checksums */
+ return mptable_finalize(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr, 0);
+ return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/asus/a88xm-e/romstage.c b/src/mainboard/asus/a88xm-e/romstage.c
new file mode 100644
index 0000000..0a85c27
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/romstage.c
@@ -0,0 +1,102 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+
+#include <northbridge/amd/agesa/state_machine.h>
+#include <southbridge/amd/common/amd_defs.h>
+#include <southbridge/amd/agesa/hudson/hudson.h>
+#include <southbridge/amd/agesa/hudson/smbus.h>
+#include <stdint.h>
+#include <string.h>
+
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8728f/it8728f.h>
+
+#define MMIO_NON_POSTED_START 0xfed00000
+#define MMIO_NON_POSTED_END 0xfedfffff
+#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x))
+
+static void sbxxx_enable_48mhzout(void)
+{
+ /* most likely programming to 48MHz out signal */
+ u32 reg32;
+ reg32 = SB_MMIO_MISC32(0x28);
+ reg32 &= 0xffc7ffff;
+ reg32 |= 0x00100000;
+ SB_MMIO_MISC32(0x28) = reg32;
+
+ reg32 = SB_MMIO_MISC32(0x40);
+ reg32 &= ~0x80u;
+ SB_MMIO_MISC32(0x40) = reg32;
+}
+
+static void superio_init_e(void)
+{
+ pnp_devfn_t uart = PNP_DEV(0x2e, IT8728F_SP1);
+ pnp_devfn_t gpio = PNP_DEV(0x2e, IT8728F_GPIO);
+
+ ite_kill_watchdog(gpio);
+ ite_enable_serial(uart, CONFIG_TTYS0_BASE);
+ ite_enable_3vsbsw(gpio);
+}
+
+void board_BeforeAgesa(struct sysinfo *cb)
+{
+ u8 byte;
+ pci_devfn_t dev;
+
+ if (IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE))
+ hudson_pci_port80();
+ else if (IS_ENABLED(CONFIG_POST_DEVICE_LPC))
+ hudson_lpc_port80();
+
+ /* enable SIO LPC decode */
+ dev = PCI_DEV(0, 0x14, 3);
+ byte = pci_read_config8(dev, 0x48);
+ byte |= 3; /* 2e, 2f */
+ pci_write_config8(dev, 0x48, byte);
+
+ /* enable serial decode */
+ byte = pci_read_config8(dev, 0x44);
+ byte |= (1 << 6); /* 0x3f8 */
+ pci_write_config8(dev, 0x44, byte);
+
+ post_code(0x30);
+
+ /* enable SB MMIO space */
+ outb(0x24, 0xcd6);
+ outb(0x1, 0xcd7);
+
+ /* enable SIO clock */
+ sbxxx_enable_48mhzout();
+
+ if (IS_ENABLED(CONFIG_BOARD_ASUS_A88XM_E))
+ superio_init_e();
+
+ /* turn on secondary smbus at b20 */
+ outb(0x28, 0xcd6);
+ byte = inb(0xcd7);
+ byte |= 1;
+ outb(byte, 0xcd7);
+
+ /* set DDR3 voltage */
+ byte = CONFIG_BOARD_ASUS_A88XM_E_DDR3_VOLT_VAL;
+
+ /* default is byte = 0x0, so no need to set it in this case */
+ if (byte)
+ do_smbus_write_byte(0xb20, 0x15, 0x3, byte);
+}
--
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9
252
Change in ...coreboot[master]: payloads/iPXE: Enable support for verifying images
by Felix Singer (Code Review) 12 Oct '20
by Felix Singer (Code Review) 12 Oct '20
12 Oct '20
Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31087
Change subject: payloads/iPXE: Enable support for verifying images
......................................................................
payloads/iPXE: Enable support for verifying images
Change-Id: Ic3356062758dba80f74116ff3ab82b3b9e8375b1
Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de>
---
M payloads/external/iPXE/Makefile
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/31087/1
diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile
index a8b1245..a5bf7be 100644
--- a/payloads/external/iPXE/Makefile
+++ b/payloads/external/iPXE/Makefile
@@ -54,6 +54,7 @@
sed 's|#define\s*COMCONSOLE.*|#define COMCONSOLE $(IPXE_UART)|' "$(project_dir)/src/config/serial.h" > "$(project_dir)/src/config/serial.h.tmp"
sed 's|#define\s*COMSPEED.*|#define COMSPEED $(CONFIG_TTYS0_BAUD)|' "$(project_dir)/src/config/serial.h.tmp" > "$(project_dir)/src/config/serial.h"
endif
+ sed -ie 's|.*IMAGE_TRUST_CMD|#define IMAGE_TRUST_CMD|g' "$(project_dir)/src/config/general.h"
build: config
echo " MAKE $(project_name) $(TAG-y)"
--
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Gerrit-Branch: master
Gerrit-Change-Id: Ic3356062758dba80f74116ff3ab82b3b9e8375b1
Gerrit-Change-Number: 31087
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de>
Gerrit-MessageType: newchange
1
2
Change in ...coreboot[master]: cpu/intel: Use macro instead of numbers
by HAOUAS Elyes (Code Review) 11 Oct '20
by HAOUAS Elyes (Code Review) 11 Oct '20
11 Oct '20
HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31196
Change subject: cpu/intel: Use macro instead of numbers
......................................................................
cpu/intel: Use macro instead of numbers
Change-Id: Ic18c219beaec3dad197916a1e235a027c1c74a89
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
M src/cpu/intel/fsp_model_406dx/model_406dx_init.c
M src/cpu/intel/haswell/haswell_init.c
M src/cpu/intel/model_1067x/model_1067x_init.c
M src/cpu/intel/model_106cx/model_106cx_init.c
M src/cpu/intel/model_206ax/model_206ax_init.c
M src/cpu/intel/model_6ex/model_6ex_init.c
M src/cpu/intel/model_6fx/model_6fx_init.c
7 files changed, 10 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/31196/1
diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c
index 7994f0b..06b37a9 100644
--- a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c
+++ b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c
@@ -47,9 +47,9 @@
msr_t msr;
msr = rdmsr(IA32_MISC_ENABLE);
- msr.lo |= (1 << 0); /* Fast String enable */
+ msr.lo |= FAST_STRINGS_ENABLE_BIT;
msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
- msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
+ msr.lo |= SPEED_STEP_ENABLE_BIT;
wrmsr(IA32_MISC_ENABLE, msr);
/* Disable Thermal interrupts */
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index aa77964..08abdf5 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -578,9 +578,9 @@
msr_t msr;
msr = rdmsr(IA32_MISC_ENABLE);
- msr.lo |= (1 << 0); /* Fast String enable */
+ msr.lo |= FAST_STRINGS_ENABLE_BIT;
msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
- msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
+ msr.lo |= SPEED_STEP_ENABLE_BIT;
wrmsr(IA32_MISC_ENABLE, msr);
/* Disable Thermal interrupts */
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index 6068be1..97ed39d 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -199,7 +199,7 @@
msr.lo |= (1 << 10); /* FERR# multiplexing */
if (eist)
- msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
+ msr.lo |= SPEED_STEP_ENABLE_BIT;
/* Enable C2E */
if (((sub_cstates >> (2 * 4)) & 0xf) >= 2)
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
index e443026..1c0d081 100644
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -65,7 +65,7 @@
msr.lo |= (1 << 10); /* FERR# multiplexing */
// TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1
- msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
+ msr.lo |= SPEED_STEP_ENABLE_BIT;
// TODO Do we want Deep C4 and Dynamic L2 shrinking?
wrmsr(IA32_MISC_ENABLE, msr);
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index 33ad1e7..c2e0364 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -338,9 +338,9 @@
msr_t msr;
msr = rdmsr(IA32_MISC_ENABLE);
- msr.lo |= (1 << 0); /* Fast String enable */
+ msr.lo |= FAST_STRINGS_ENABLE_BIT;
msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
- msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
+ msr.lo |= SPEED_STEP_ENABLE_BIT;
wrmsr(IA32_MISC_ENABLE, msr);
/* Disable Thermal interrupts */
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
index 19a22f1..fbc6964 100644
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -67,7 +67,7 @@
msr.lo |= (1 << 10); /* FERR# multiplexing */
// TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1
- msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
+ msr.lo |= SPEED_STEP_ENABLE_BIT;
/* Enable C2E */
msr.lo |= (1 << 26);
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index 4e19896..adc0265 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -70,7 +70,7 @@
msr.lo |= (1 << 10); /* FERR# multiplexing */
// TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1
- msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
+ msr.lo |= SPEED_STEP_ENABLE_BIT;
/* Enable C2E */
msr.lo |= (1 << 26);
--
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Gerrit-Change-Id: Ic18c219beaec3dad197916a1e235a027c1c74a89
Gerrit-Change-Number: 31196
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Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr>
Gerrit-MessageType: newchange
4
11
Change in ...coreboot[master]: configs: Build test experimental x86_64 code
by Patrick Rudolph (Code Review) 19 Aug '20
by Patrick Rudolph (Code Review) 19 Aug '20
19 Aug '20
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31472
Change subject: configs: Build test experimental x86_64 code
......................................................................
configs: Build test experimental x86_64 code
Add additional build config to test qemu-i440fx x86_64 code.
Change-Id: I63f7a6e1602728e4d5ff67f9bd702efebe315c16
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
A configs/config.emulation_qemu_x86_i440fx_x86_64
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/31472/1
diff --git a/configs/config.emulation_qemu_x86_i440fx_x86_64 b/configs/config.emulation_qemu_x86_i440fx_x86_64
new file mode 100644
index 0000000..0ddb3f1
--- /dev/null
+++ b/configs/config.emulation_qemu_x86_i440fx_x86_64
@@ -0,0 +1 @@
+CONFIG_CPU_QEMU_X86_64=y
--
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4
7
Change in ...coreboot[master]: [WIP] AGESA: Fix CAR_GLOBAL use for AP CPUs
by Kyösti Mälkki (Code Review) 31 Jul '20
by Kyösti Mälkki (Code Review) 31 Jul '20
31 Jul '20
Hello Marshall Dawson,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/31361
to review the following change.
Change subject: [WIP] AGESA: Fix CAR_GLOBAL use for AP CPUs
......................................................................
[WIP] AGESA: Fix CAR_GLOBAL use for AP CPUs
The memory between _car_region_start .. _car_region_end has to
be set up as WB in MTRRs for all the cores executing through
bootblock, verstage and romstage. Otherwise CAR_GLOBALs may
fail on AP CPUs.
Fixes combination of CBMEM_CONSOLE=y with SQUELCH_EARLY_SMP=n,
which previously did not boot at all.
Does not fix family14.
Change-Id: I3a8a389ca0d7a88c779f27f4ead0d9581465edfd
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
---
M src/vendorcode/amd/agesa/f12/gcccar.inc
M src/vendorcode/amd/agesa/f14/gcccar.inc
M src/vendorcode/amd/agesa/f15tn/gcccar.inc
M src/vendorcode/amd/agesa/f16kb/gcccar.inc
4 files changed, 28 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/31361/1
diff --git a/src/vendorcode/amd/agesa/f12/gcccar.inc b/src/vendorcode/amd/agesa/f12/gcccar.inc
index 95dd74d..e6dba6a 100644
--- a/src/vendorcode/amd/agesa/f12/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f12/gcccar.inc
@@ -1451,6 +1451,13 @@
0:
_WRMSR #
+ # All cores must see BSP stack region that is also used to
+ # communicate global variables before DRAM is up.
+ mov $AMD_MTRR_FIX64k_00000, %ecx # MSR:0000_0250
+ _RDMSR
+ or $0x1e000000, %eax
+ _WRMSR
+
# Enable MTRR defaults as UC type
mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF
_RDMSR # Read-modify-write the MSR
diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc
index 95dd74d..e6dba6a 100644
--- a/src/vendorcode/amd/agesa/f14/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f14/gcccar.inc
@@ -1451,6 +1451,13 @@
0:
_WRMSR #
+ # All cores must see BSP stack region that is also used to
+ # communicate global variables before DRAM is up.
+ mov $AMD_MTRR_FIX64k_00000, %ecx # MSR:0000_0250
+ _RDMSR
+ or $0x1e000000, %eax
+ _WRMSR
+
# Enable MTRR defaults as UC type
mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF
_RDMSR # Read-modify-write the MSR
diff --git a/src/vendorcode/amd/agesa/f15tn/gcccar.inc b/src/vendorcode/amd/agesa/f15tn/gcccar.inc
index b13e02a..e96c7f7 100644
--- a/src/vendorcode/amd/agesa/f15tn/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f15tn/gcccar.inc
@@ -1767,6 +1767,13 @@
0:
_WRMSR #
+ # All cores must see BSP stack region that is also used to
+ # communicate global variables before DRAM is up.
+ mov $AMD_MTRR_FIX64k_00000, %ecx # MSR:0000_0250
+ _RDMSR
+ or $0x1e000000, %eax
+ _WRMSR
+
# Enable MTRR defaults as UC type
mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF
_RDMSR # Read-modify-write the MSR
diff --git a/src/vendorcode/amd/agesa/f16kb/gcccar.inc b/src/vendorcode/amd/agesa/f16kb/gcccar.inc
index c818d97..26745c9 100644
--- a/src/vendorcode/amd/agesa/f16kb/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f16kb/gcccar.inc
@@ -1131,6 +1131,13 @@
0:
_WRMSR #
+ # All cores must see BSP stack region that is also used to
+ # communicate global variables before DRAM is up.
+ mov $AMD_MTRR_FIX64k_00000, %ecx # MSR:0000_0250
+ _RDMSR
+ or $0x1e000000, %eax
+ _WRMSR
+
# Enable MTRR defaults as UC type
mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF
_RDMSR # Read-modify-write the MSR
--
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Gerrit-Change-Id: I3a8a389ca0d7a88c779f27f4ead0d9581465edfd
Gerrit-Change-Number: 31361
Gerrit-PatchSet: 1
Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Gerrit-MessageType: newchange
4
5
Change in ...coreboot[master]: util/inteltool: Refactoring #2
by Felix Singer (Code Review) 05 Jul '20
by Felix Singer (Code Review) 05 Jul '20
05 Jul '20
Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31634
Change subject: util/inteltool: Refactoring #2
......................................................................
util/inteltool: Refactoring #2
Change-Id: Ie92a5af141a907251fc847d53c767984949d9312
Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de>
---
M util/inteltool/Makefile
M util/inteltool/gpio.h
A util/inteltool/gpio_test.c
A util/inteltool/gpio_test.h
4 files changed, 447 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/31634/1
diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile
index d88063b..0097831 100644
--- a/util/inteltool/Makefile
+++ b/util/inteltool/Makefile
@@ -28,7 +28,7 @@
CPPFLAGS += -I$(top)/src/commonlib/include
OBJS = inteltool.o pcr.o cpu.o gpio.o gpio_groups.o rootcmplx.o powermgt.o \
- memory.o pcie.o amb.o ivy_memory.o spi.o gfx.o ahci.o \
+ memory.o pcie.o amb.o ivy_memory.o spi.o gfx.o ahci.o gpio_test.o \
OS_ARCH = $(shell uname)
ifeq ($(OS_ARCH), Darwin)
diff --git a/util/inteltool/gpio.h b/util/inteltool/gpio.h
index c89f393..161e9bb 100644
--- a/util/inteltool/gpio.h
+++ b/util/inteltool/gpio.h
@@ -17,6 +17,36 @@
#ifndef GPIO_H
#define GPIO_H
+
+// Describes a native function
+struct native_mode {
+ uint8_t mode;
+ char *name;
+};
+
+/*
+ * Describes a GPIO pad, which optionally can
+ * have one or more native functions and a default
+ * mode. If no default mode is set,
+ * default_mode to -1, else set it to the
+ * function number.
+ */
+struct gpio_pad {
+ const char *name;
+ uint8_t default_mode;
+ const struct native_mode *modes;
+ uint64_t default_config;
+ uint64_t config;
+};
+
+/*
+struct gpio_pad {
+ const char *name;
+ size_t defaultMode;
+ const char **functions;
+};
+*/
+
struct gpio_group {
const char *display;
size_t pad_count;
diff --git a/util/inteltool/gpio_test.c b/util/inteltool/gpio_test.c
new file mode 100644
index 0000000..9052623
--- /dev/null
+++ b/util/inteltool/gpio_test.c
@@ -0,0 +1,66 @@
+/*
+ * inteltool - dump all registers on an Intel CPU + chipset based system.
+ *
+ * Copyright (C) 2017 secunet Security Networks AG
+ * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <assert.h>
+#include <inttypes.h>
+#include "inteltool.h"
+#include "pcr.h"
+#include "gpio.h"
+#include "gpio_test.h"
+
+#define SBBAR_SIZE (16 * MiB)
+#define PCR_PORT_SIZE (64 * KiB)
+
+void select_gpio_community(struct pci_dev *const sb)
+{
+ size_t community_count;
+ const struct gpio_community *const *communities;
+
+ switch (sb->device_id) {
+ case PCI_DEVICE_ID_INTEL_B150:
+ case PCI_DEVICE_ID_INTEL_CM236:
+// community_count = ARRAY_SIZE(sunrise_communities);
+// communities = sunrise_communities;
+// pcr_init(sb);
+ break;
+ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE:
+ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM:
+ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM:
+ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE:
+ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM:
+ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM:
+// community_count = ARRAY_SIZE(sunrise_lp_communities);
+// communities = sunrise_lp_communities;
+// pcr_init(sb);
+ break;
+ case PCI_DEVICE_ID_INTEL_DNV_LPC:
+// community_count = ARRAY_SIZE(denverton_communities);
+// communities = denverton_communities;
+// pcr_init(sb);
+ break;
+ default:
+ return;
+ }
+
+ printf("\n============= GPIOS =============\n\n");
+
+// for (; community_count; --community_count)
+// print_gpio_community(*communities++);
+}
diff --git a/util/inteltool/gpio_test.h b/util/inteltool/gpio_test.h
new file mode 100644
index 0000000..9edc4fe
--- /dev/null
+++ b/util/inteltool/gpio_test.h
@@ -0,0 +1,350 @@
+/*
+ * inteltool - dump all registers on an Intel CPU + chipset based system.
+ *
+ * Copyright (C) 2017 secunet Security Networks AG
+ * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de>
+ * Copyright (C) 2019 by 9elements Agency GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "gpio.h"
+
+#ifndef GPIO_TEST_H
+#define GPIO_TEST_H
+
+/*
+const struct gpio_pad test[] = {
+ { "gpio1", 2, (const char *[]) { "function1", "function2", NULL, } },
+};
+*/
+
+const struct gpio_pad test[] = {
+ { "GPP_A0", -1, (const struct native_mode[]) { {1, "RCIN#" }, }, },
+ { "GPP_A1", -1, (const struct native_mode[]) { {1, "LAD0" }, {3, "ESPI_IO0" }, }, },
+ { "GPP_A2", -1, (const struct native_mode[]) { {1, "LAD1" }, {3, "ESPI_IO1" }, }, },
+ { "GPP_A3", -1, (const struct native_mode[]) { {1, "LAD2" }, {3, "ESPI_IO2" }, }, },
+ { "GPP_A4", -1, (const struct native_mode[]) { {1, "LAD3" }, {3, "ESPI_IO3" }, }, },
+ { "GPP_A5", -1, (const struct native_mode[]) { {1, "LFRAME#" }, {3, "ESPI_CS#" }, }, },
+ { "GPP_A6", -1, (const struct native_mode[]) { {1, "SERIRQ#" }, }, },
+ { "GPP_A7", -1, (const struct native_mode[]) { {1, "PIRQA#" }, }, },
+ { "GPP_A8", -1, (const struct native_mode[]) { {1, "CLKRUN#" }, }, },
+ { "GPP_A9", -1, (const struct native_mode[]) { {1, "CLKOUT_LPC0" }, {3, "ESPI_CLK" }, }, },
+ { "GPP_A10", -1, (const struct native_mode[]) { {1, "CLKOUT_LPC1" }, }, },
+ { "GPP_A11", -1, (const struct native_mode[]) { {1, "PME#" }, }, },
+ { "GPP_A12", -1, (const struct native_mode[]) { {1, "BM_BUSY#" }, {2, "ISH_GP6" }, {3, "SX_EXIT_HOLDOFF#" }, }, },
+ { "GPP_A13", -1, (const struct native_mode[]) { {1, "SUSWARN#/SUSPWRDNACK" }, }, },
+ { "GPP_A14", -1, (const struct native_mode[]) { {1, "SUS_STAT#" }, {3, "ESPI_RESET#" }, }, },
+ { "GPP_A15", -1, (const struct native_mode[]) { {1, "SUS_ACK#" }, }, },
+ { "GPP_A16", -1, (const struct native_mode[]) { {1, "SD_1P8_SEL" }, }, },
+ { "GPP_A17", -1, (const struct native_mode[]) { {1, "SD_PWR_EN#" }, {2, "ISH_GP7" }, }, },
+ { "GPP_A18", -1, (const struct native_mode[]) { {1, "ISH_GP0" }, }, },
+ { "GPP_A19", -1, (const struct native_mode[]) { {1, "ISH_GP1" }, }, },
+ { "GPP_A20", -1, (const struct native_mode[]) { {1, "ISH_GP2" }, }, },
+ { "GPP_A21", -1, (const struct native_mode[]) { {1, "ISH_GP3" }, }, },
+ { "GPP_A22", -1, (const struct native_mode[]) { {1, "ISH_GP4" }, }, },
+ { "GPP_A23", -1, (const struct native_mode[]) { {1, "ISH_GP5" }, }, },
+};
+
+/*
+const char *const sunrise_lp_group_a_names[] = {
+ "GPP_A0", "RCIN#", "n/a", "n/a",
+ "GPP_A1", "LAD0", "n/a", "ESPI_IO0",
+ "GPP_A2", "LAD1", "n/a", "ESPI_IO1",
+ "GPP_A3", "LAD2", "n/a", "ESPI_IO2",
+ "GPP_A4", "LAD3", "n/a", "ESPI_IO3",
+ "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#",
+ "GPP_A6", "SERIRQ", "n/a", "n/a",
+ "GPP_A7", "PIRQA#", "n/a", "n/a",
+ "GPP_A8", "CLKRUN#", "n/a", "n/a",
+ "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK",
+ "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a",
+ "GPP_A11", "PME#", "n/a", "n/a",
+ "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#",
+ "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a",
+ "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#",
+ "GPP_A15", "SUS_ACK#", "n/a", "n/a",
+ "GPP_A16", "SD_1P8_SEL", "n/a", "n/a",
+ "GPP_A17", "SD_PWR_EN#", "ISH_GP7", "n/a",
+ "GPP_A18", "ISH_GP0", "n/a", "n/a",
+ "GPP_A19", "ISH_GP1", "n/a", "n/a",
+ "GPP_A20", "ISH_GP2", "n/a", "n/a",
+ "GPP_A21", "ISH_GP3", "n/a", "n/a",
+ "GPP_A22", "ISH_GP4", "n/a", "n/a",
+ "GPP_A23", "ISH_GP5", "n/a", "n/a",
+};
+
+const struct gpio_group sunrise_lp_group_a = {
+ .display = "------- GPIO group GPP_A -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_a_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_a_names,
+};
+
+const char *const sunrise_lp_group_b_names[] = {
+ "GPP_B0", "CORE_VID0", "n/a", "n/a",
+ "GPP_B1", "CORE_VID1", "n/a", "n/a",
+ "GPP_B2", "VRALERT#", "n/a", "n/a",
+ "GPP_B3", "CPU_GP2", "n/a", "n/a",
+ "GPP_B4", "CPU_GP3", "n/a", "n/a",
+ "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a",
+ "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a",
+ "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a",
+ "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a",
+ "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a",
+ "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a",
+ "GPP_B11", "EXT_PWR_GATE#", "n/a", "n/a",
+ "GPP_B12", "SLP_S0#", "n/a", "n/a",
+ "GPP_B13", "PLTRST#", "n/a", "n/a",
+ "GPP_B14", "SPKR", "n/a", "n/a",
+ "GPP_B15", "GSPI0_CS#", "n/a", "n/a",
+ "GPP_B16", "GSPI0_CLK", "n/a", "n/a",
+ "GPP_B17", "GSPI0_MISO", "n/a", "n/a",
+ "GPP_B18", "GSPI0_MOSI", "n/a", "n/a",
+ "GPP_B19", "GSPI1_CS#", "n/a", "n/a",
+ "GPP_B20", "GSPI1_CLK", "n/a", "n/a",
+ "GPP_B21", "GSPI1_MISO", "n/a", "n/a",
+ "GPP_B22", "GSPI1_MOSI", "n/a", "n/a",
+ "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a",
+};
+
+const struct gpio_group sunrise_lp_group_b = {
+ .display = "------- GPIO Group GPP_B -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_b_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_b_names,
+};
+
+const struct gpio_group *const sunrise_lp_community_ab_groups[] = {
+ &sunrise_lp_group_a, &sunrise_lp_group_b,
+};
+
+const struct gpio_community sunrise_lp_community_ab = {
+ .name = "------- GPIO Community 0 -------",
+ .pcr_port_id = 0xaf,
+ .group_count = ARRAY_SIZE(sunrise_lp_community_ab_groups),
+ .groups = sunrise_lp_community_ab_groups,
+};
+
+const char *const sunrise_group_c_names[] = {
+ "GPP_C0", "SMBCLK", "n/a", "n/a",
+ "GPP_C1", "SMBDATA", "n/a", "n/a",
+ "GPP_C2", "SMBALERT#", "n/a", "n/a",
+ "GPP_C3", "SML0CLK", "n/a", "n/a",
+ "GPP_C4", "SML0DATA", "n/a", "n/a",
+ "GPP_C5", "SML0ALERT#", "n/a", "n/a",
+ "GPP_C6", "SML1CLK", "n/a", "n/a",
+ "GPP_C7", "SML1DATA", "n/a", "n/a",
+ "GPP_C8", "UART0_RXD", "n/a", "n/a",
+ "GPP_C9", "UART0_TXD", "n/a", "n/a",
+ "GPP_C10", "UART0_RTS#", "n/a", "n/a",
+ "GPP_C11", "UART0_CTS#", "n/a", "n/a",
+ "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", "n/a",
+ "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", "n/a",
+ "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", "n/a",
+ "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", "n/a",
+ "GPP_C16", "I2C0_SDA", "n/a", "n/a",
+ "GPP_C17", "I2C0_SCL", "n/a", "n/a",
+ "GPP_C18", "I2C1_SDA", "n/a", "n/a",
+ "GPP_C19", "I2C1_SCL", "n/a", "n/a",
+ "GPP_C20", "UART2_RXD", "n/a", "n/a",
+ "GPP_C21", "UART2_TXD", "n/a", "n/a",
+ "GPP_C22", "UART2_RTS#", "n/a", "n/a",
+ "GPP_C23", "UART2_CTS#", "n/a", "n/a",
+};
+
+const struct gpio_group sunrise_group_c = {
+ .display = "------- GPIO Group GPP_C -------",
+ .pad_count = ARRAY_SIZE(sunrise_group_c_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_c_names,
+};
+
+const char *const sunrise_lp_group_d_names[] = {
+ "GPP_D0", "SPI1_CS#", "n/a", "n/a",
+ "GPP_D1", "SPI1_CLK", "n/a", "n/a",
+ "GPP_D2", "SPI1_MISO", "n/a", "n/a",
+ "GPP_D3", "SPI1_MOSI", "n/a", "n/a",
+ "GPP_D4", "FLASHTRIG", "n/a", "n/a",
+ "GPP_D5", "ISH_I2C0_SDA", "n/a", "n/a",
+ "GPP_D6", "ISH_I2C0_SCL", "n/a", "n/a",
+ "GPP_D7", "ISH_I2C1_SDA", "n/a", "n/a",
+ "GPP_D8", "ISH_I2C1_SCL", "n/a", "n/a",
+ "GPP_D9", "n/a", "n/a", "n/a",
+ "GPP_D10", "n/a", "n/a", "n/a",
+ "GPP_D11", "n/a", "n/a", "n/a",
+ "GPP_D12", "n/a", "n/a", "n/a",
+ "GPP_D13", "ISH_UART0_RXD", "n/a", "n/a",
+ "GPP_D14", "ISH_UART0_TXD", "n/a", "n/a",
+ "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a",
+ "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a",
+ "GPP_D17", "DMIC_CLK1", "n/a", "n/a",
+ "GPP_D18", "DMIC_DATA1", "n/a", "n/a",
+ "GPP_D19", "DMIC_CLK0", "n/a", "n/a",
+ "GPP_D20", "DMIC_DATA0", "n/a", "n/a",
+ "GPP_D21", "SPI1_IO2", "n/a", "n/a",
+ "GPP_D22", "SPI1_IO3", "n/a", "n/a",
+ "GPP_D23", "I2S_MCLK", "n/a", "n/a",
+};
+
+const struct gpio_group sunrise_lp_group_d = {
+ .display = "------- GPIO Group GPP_D -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_d_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_d_names,
+};
+
+const char *const sunrise_lp_group_e_names[] = {
+ "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a",
+ "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a",
+ "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a",
+ "GPP_E3", "CPU_GP0", "n/a", "n/a",
+ "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a",
+ "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a",
+ "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a",
+ "GPP_E7", "CPU_GP1", "n/a", "n/a",
+ "GPP_E8", "SATALED#", "n/a", "n/a",
+ "GPP_E9", "USB2_OC0#", "n/a", "n/a",
+ "GPP_E10", "USB2_OC1#", "n/a", "n/a",
+ "GPP_E11", "USB2_OC2#", "n/a", "n/a",
+ "GPP_E12", "USB2_OC3#", "n/a", "n/a",
+ "GPP_E13", "DDPB_HPD0", "n/a", "n/a",
+ "GPP_E14", "DDPC_HPD1", "n/a", "n/a",
+ "GPP_E15", "DDPD_HPD2", "n/a", "n/a",
+ "GPP_E16", "DDPE_HPD3", "n/a", "n/a",
+ "GPP_E17", "EDP_HPD", "n/a", "n/a",
+ "GPP_E18", "DDPB_CTRLCLK", "n/a", "n/a",
+ "GPP_E19", "DDPB_CTRLDATA", "n/a", "n/a",
+ "GPP_E20", "DDPC_CTRLCLK", "n/a", "n/a",
+ "GPP_E21", "DDPC_CTRLDATA", "n/a", "n/a",
+ "GPP_E22", "n/a", "n/a", "n/a",
+ "GPP_E23", "n/a", "n/a", "n/a",
+};
+
+const struct gpio_group sunrise_lp_group_e = {
+ .display = "------- GPIO Group GPP_E -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_e_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_e_names,
+};
+
+const char *const sunrise_lp_group_f_names[] = {
+ "GPP_F0", "I2S2_SCLK", "n/a", "n/a",
+ "GPP_F1", "I2S2_SFRM", "n/a", "n/a",
+ "GPP_F2", "I2S2_TXD", "n/a", "n/a",
+ "GPP_F3", "I2S2_RXD", "n/a", "n/a",
+ "GPP_F4", "I2C2_SDA", "n/a", "n/a",
+ "GPP_F5", "I2C2_SCL", "n/a", "n/a",
+ "GPP_F6", "I2C3_SDA", "n/a", "n/a",
+ "GPP_F7", "I2C3_SCL", "n/a", "n/a",
+ "GPP_F8", "I2C4_SDA", "n/a", "n/a",
+ "GPP_F9", "I2C4_SCL", "n/a", "n/a",
+ "GPP_F10", "I2C5_SDA", "ISH_I2C2_SDA", "n/a",
+ "GPP_F11", "I2C5_SCL", "ISH_I2C2_SCL", "n/a",
+ "GPP_F12", "EMMC_CMD", "n/a", "n/a",
+ "GPP_F13", "EMMC_DATA0", "n/a", "n/a",
+ "GPP_F14", "EMMC_DATA1", "n/a", "n/a",
+ "GPP_F15", "EMMC_DATA2", "n/a", "n/a",
+ "GPP_F16", "EMMC_DATA3", "n/a", "n/a",
+ "GPP_F17", "EMMC_DATA4", "n/a", "n/a",
+ "GPP_F18", "EMMC_DATA5", "n/a", "n/a",
+ "GPP_F19", "EMMC_DATA6", "n/a", "n/a",
+ "GPP_F20", "EMMC_DATA7", "n/a", "n/a",
+ "GPP_F21", "EMMC_RCLK", "n/a", "n/a",
+ "GPP_F22", "EMMC_CLK", "n/a", "n/a",
+ "GPP_F23", "n/a", "n/a", "n/a",
+};
+
+const struct gpio_group sunrise_lp_group_f = {
+ .display = "------- GPIO Group GPP_F -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_f_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_f_names,
+};
+
+const char *const sunrise_lp_group_g_names[] = {
+ "GPP_G0", "SD_CMD", "n/a", "n/a",
+ "GPP_G1", "SD_DATA0", "n/a", "n/a",
+ "GPP_G2", "SD_DATA1", "n/a", "n/a",
+ "GPP_G3", "SD_DATA2", "n/a", "n/a",
+ "GPP_G4", "SD_DATA3", "n/a", "n/a",
+ "GPP_G5", "SD_CD#", "n/a", "n/a",
+ "GPP_G6", "SD_CLK", "n/a", "n/a",
+ "GPP_G7", "SD_WP", "n/a", "n/a",
+};
+
+const struct gpio_group sunrise_lp_group_g = {
+ .display = "------- GPIO Group GPP_G -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_g_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_g_names,
+};
+
+const struct gpio_group *const sunrise_lp_community_cde_groups[] = {
+ &sunrise_group_c, &sunrise_lp_group_d, &sunrise_lp_group_e,
+};
+
+const struct gpio_community sunrise_lp_community_cde = {
+ .name = "------- GPIO Community 1 -------",
+ .pcr_port_id = 0xae,
+ .group_count = ARRAY_SIZE(sunrise_lp_community_cde_groups),
+ .groups = sunrise_lp_community_cde_groups,
+};
+
+const char *const sunrise_group_gpd_names[] = {
+ "GPD0", "BATLOW#", "n/a", "n/a",
+ "GPD1", "ACPRESENT", "n/a", "n/a",
+ "GPD2", "LAN_WAKE#", "n/a", "n/a",
+ "GPD3", "PWRBTN#", "n/a", "n/a",
+ "GPD4", "SLP_S3#", "n/a", "n/a",
+ "GPD5", "SLP_S4#", "n/a", "n/a",
+ "GPD6", "SLP_A#", "n/a", "n/a",
+ "GPD7", "RESERVED", "n/a", "n/a",
+ "GPD8", "SUSCLK", "n/a", "n/a",
+ "GPD9", "SLP_WLAN#", "n/a", "n/a",
+ "GPD10", "SLP_S5#", "n/a", "n/a",
+ "GPD11", "LANPHYPC", "n/a", "n/a",
+};
+
+const struct gpio_group sunrise_group_gpd = {
+ .display = "-------- GPIO Group GPD --------",
+ .pad_count = ARRAY_SIZE(sunrise_group_gpd_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_gpd_names,
+};
+
+const struct gpio_group *const sunrise_community_gpd_groups[] = {
+ &sunrise_group_gpd,
+};
+
+const struct gpio_community sunrise_community_gpd = {
+ .name = "------- GPIO Community 2 -------",
+ .pcr_port_id = 0xad,
+ .group_count = ARRAY_SIZE(sunrise_community_gpd_groups),
+ .groups = sunrise_community_gpd_groups,
+};
+
+const struct gpio_group *const sunrise_lp_community_fg_groups[] = {
+ &sunrise_lp_group_f, &sunrise_lp_group_g,
+};
+
+const struct gpio_community sunrise_lp_community_fg = {
+ .name = "------- GPIO Community 3 -------",
+ .pcr_port_id = 0xac,
+ .group_count = ARRAY_SIZE(sunrise_lp_community_fg_groups),
+ .groups = sunrise_lp_community_fg_groups,
+};
+
+const struct gpio_community *const sunrise_lp_communities[] = {
+ &sunrise_lp_community_ab, &sunrise_lp_community_cde,
+ &sunrise_community_gpd, &sunrise_lp_community_fg,
+};
+*/
+#endif
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ie92a5af141a907251fc847d53c767984949d9312
Gerrit-Change-Number: 31634
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de>
Gerrit-MessageType: newchange
3
10
Change in ...coreboot[master]: util/inteltool: Refactor code of GPIO groups
by Felix Singer (Code Review) 05 Jul '20
by Felix Singer (Code Review) 05 Jul '20
05 Jul '20
Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31504
Change subject: util/inteltool: Refactor code of GPIO groups
......................................................................
util/inteltool: Refactor code of GPIO groups
Change-Id: Ic61871f5cf95ac3da93892fa2f7721e682176c8d
Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de>
---
A util/inteltool/gpio.h
A util/inteltool/gpio_denverton.h
M util/inteltool/gpio_groups.c
A util/inteltool/gpio_sunrise.h
4 files changed, 865 insertions(+), 816 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/31504/1
diff --git a/util/inteltool/gpio.h b/util/inteltool/gpio.h
new file mode 100644
index 0000000..64f62f8
--- /dev/null
+++ b/util/inteltool/gpio.h
@@ -0,0 +1,29 @@
+/*
+ * inteltool - dump all registers on an Intel CPU + chipset based system.
+ *
+ * Copyright (C) 2017 secunet Security Networks AG
+ * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+struct gpio_group {
+ const char *display;
+ size_t pad_count;
+ size_t func_count;
+ const char *const *pad_names; /* indexed by 'pad * func_count + func' */
+};
+
+struct gpio_community {
+ const char *name;
+ uint8_t pcr_port_id;
+ size_t group_count;
+ const struct gpio_group *const *groups;
+};
diff --git a/util/inteltool/gpio_denverton.h b/util/inteltool/gpio_denverton.h
new file mode 100644
index 0000000..e745b44
--- /dev/null
+++ b/util/inteltool/gpio_denverton.h
@@ -0,0 +1,237 @@
+/*
+ * inteltool - dump all registers on an Intel CPU + chipset based system.
+ *
+ * Copyright (C) 2017 secunet Security Networks AG
+ * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+static const char *const denverton_group_north_all_names[] = {
+ "NORTH_ALL_GBE0_SDP0",
+ "NORTH_ALL_GBE1_SDP0",
+ "NORTH_ALL_GBE0_SDP1",
+ "NORTH_ALL_GBE1_SDP1",
+ "NORTH_ALL_GBE0_SDP2",
+ "NORTH_ALL_GBE1_SDP2",
+ "NORTH_ALL_GBE0_SDP3",
+ "NORTH_ALL_GBE1_SDP3",
+ "NORTH_ALL_GBE2_LED0",
+ "NORTH_ALL_GBE2_LED1",
+ "NORTH_ALL_GBE0_I2C_CLK",
+ "NORTH_ALL_GBE0_I2C_DATA",
+ "NORTH_ALL_GBE1_I2C_CLK",
+ "NORTH_ALL_GBE1_I2C_DATA",
+ "NORTH_ALL_NCSI_RXD0",
+ "NORTH_ALL_NCSI_CLK_IN",
+ "NORTH_ALL_NCSI_RXD1",
+ "NORTH_ALL_NCSI_CRS_DV",
+ "NORTH_ALL_NCSI_ARB_IN",
+ "NORTH_ALL_NCSI_TX_EN",
+ "NORTH_ALL_NCSI_TXD0",
+ "NORTH_ALL_NCSI_TXD1",
+ "NORTH_ALL_NCSI_ARB_OUT",
+ "NORTH_ALL_GBE0_LED0",
+ "NORTH_ALL_GBE0_LED1",
+ "NORTH_ALL_GBE1_LED0",
+ "NORTH_ALL_GBE1_LED1",
+ "NORTH_ALL_GPIO_0",
+ "NORTH_ALL_PCIE_CLKREQ0_N",
+ "NORTH_ALL_PCIE_CLKREQ1_N",
+ "NORTH_ALL_PCIE_CLKREQ2_N",
+ "NORTH_ALL_PCIE_CLKREQ3_N",
+ "NORTH_ALL_PCIE_CLKREQ4_N",
+ "NORTH_ALL_GPIO_1",
+ "NORTH_ALL_GPIO_2",
+ "NORTH_ALL_SVID_ALERT_N",
+ "NORTH_ALL_SVID_DATA",
+ "NORTH_ALL_SVID_CLK",
+ "NORTH_ALL_THERMTRIP_N",
+ "NORTH_ALL_PROCHOT_N",
+ "NORTH_ALL_MEMHOT_N",
+};
+
+static const struct gpio_group denverton_group_north_all = {
+ .display = "------- GPIO Group North All -------",
+ .pad_count = ARRAY_SIZE(denverton_group_north_all_names) / 1,
+ .func_count = 1,
+ .pad_names = denverton_group_north_all_names,
+};
+
+static const struct gpio_group *const denverton_community_north_groups[] = {
+ &denverton_group_north_all,
+};
+
+static const struct gpio_community denverton_community_north = {
+ .name = "------- GPIO Community 0 -------",
+ .pcr_port_id = 0xc2,
+ .group_count = ARRAY_SIZE(denverton_community_north_groups),
+ .groups = denverton_community_north_groups,
+};
+
+static const char *const denverton_group_south_dfx_names[] = {
+ "SOUTH_DFX_DFX_PORT_CLK0",
+ "SOUTH_DFX_DFX_PORT_CLK1",
+ "SOUTH_DFX_DFX_PORT0",
+ "SOUTH_DFX_DFX_PORT1",
+ "SOUTH_DFX_DFX_PORT2",
+ "SOUTH_DFX_DFX_PORT3",
+ "SOUTH_DFX_DFX_PORT4",
+ "SOUTH_DFX_DFX_PORT5",
+ "SOUTH_DFX_DFX_PORT6",
+ "SOUTH_DFX_DFX_PORT7",
+ "SOUTH_DFX_DFX_PORT8",
+ "SOUTH_DFX_DFX_PORT9",
+ "SOUTH_DFX_DFX_PORT10",
+ "SOUTH_DFX_DFX_PORT11",
+ "SOUTH_DFX_DFX_PORT12",
+ "SOUTH_DFX_DFX_PORT13",
+ "SOUTH_DFX_DFX_PORT14",
+ "SOUTH_DFX_DFX_PORT15",
+};
+
+static const struct gpio_group denverton_group_south_dfx = {
+ .display = "------- GPIO Group South DFX -------",
+ .pad_count = ARRAY_SIZE(denverton_group_south_dfx_names) / 1,
+ .func_count = 1,
+ .pad_names = denverton_group_south_dfx_names,
+};
+
+static const char *const denverton_group_south_group0_names[] = {
+ "SOUTH_GROUP0_GPIO_12",
+ "SOUTH_GROUP0_SMB5_GBE_ALRT_N",
+ "SOUTH_GROUP0_PCIE_CLKREQ5_N",
+ "SOUTH_GROUP0_PCIE_CLKREQ6_N",
+ "SOUTH_GROUP0_PCIE_CLKREQ7_N",
+ "SOUTH_GROUP0_UART0_RXD",
+ "SOUTH_GROUP0_UART0_TXD",
+ "SOUTH_GROUP0_SMB5_GBE_CLK",
+ "SOUTH_GROUP0_SMB5_GBE_DATA",
+ "SOUTH_GROUP0_ERROR2_N",
+ "SOUTH_GROUP0_ERROR1_N",
+ "SOUTH_GROUP0_ERROR0_N",
+ "SOUTH_GROUP0_IERR_N",
+ "SOUTH_GROUP0_MCERR_N",
+ "SOUTH_GROUP0_SMB0_LEG_CLK",
+ "SOUTH_GROUP0_SMB0_LEG_DATA",
+ "SOUTH_GROUP0_SMB0_LEG_ALRT_N",
+ "SOUTH_GROUP0_SMB1_HOST_DATA",
+ "SOUTH_GROUP0_SMB1_HOST_CLK",
+ "SOUTH_GROUP0_SMB2_PECI_DATA",
+ "SOUTH_GROUP0_SMB2_PECI_CLK",
+ "SOUTH_GROUP0_SMB4_CSME0_DATA",
+ "SOUTH_GROUP0_SMB4_CSME0_CLK",
+ "SOUTH_GROUP0_SMB4_CSME0_ALRT_N",
+ "SOUTH_GROUP0_USB_OC0_N",
+ "SOUTH_GROUP0_FLEX_CLK_SE0",
+ "SOUTH_GROUP0_FLEX_CLK_SE1",
+ "SOUTH_GROUP0_GPIO_4",
+ "SOUTH_GROUP0_GPIO_5",
+ "SOUTH_GROUP0_GPIO_6",
+ "SOUTH_GROUP0_GPIO_7",
+ "SOUTH_GROUP0_SATA0_LED_N",
+ "SOUTH_GROUP0_SATA1_LED_N",
+ "SOUTH_GROUP0_SATA_PDETECT0",
+ "SOUTH_GROUP0_SATA_PDETECT1",
+ "SOUTH_GROUP0_SATA0_SDOUT",
+ "SOUTH_GROUP0_SATA1_SDOUT",
+ "SOUTH_GROUP0_UART1_RXD",
+ "SOUTH_GROUP0_UART1_TXD",
+ "SOUTH_GROUP0_GPIO_8",
+ "SOUTH_GROUP0_GPIO_9",
+ "SOUTH_GROUP0_TCK",
+ "SOUTH_GROUP0_TRST_N",
+ "SOUTH_GROUP0_TMS",
+ "SOUTH_GROUP0_TDI",
+ "SOUTH_GROUP0_TDO",
+ "SOUTH_GROUP0_CX_PRDY_N",
+ "SOUTH_GROUP0_CX_PREQ_N",
+ "SOUTH_GROUP0_CTBTRIGINOUT",
+ "SOUTH_GROUP0_CTBTRIGOUT",
+ "SOUTH_GROUP0_DFX_SPARE2",
+ "SOUTH_GROUP0_DFX_SPARE3",
+ "SOUTH_GROUP0_DFX_SPARE4",
+};
+
+static const struct gpio_group denverton_group_south_group0 = {
+ .display = "------- GPIO Group South Group0 -------",
+ .pad_count = ARRAY_SIZE(denverton_group_south_group0_names) / 1,
+ .func_count = 1,
+ .pad_names = denverton_group_south_group0_names,
+};
+
+static const char *const denverton_group_south_group1_names[] = {
+ "SOUTH_GROUP1_SUSPWRDNACK",
+ "SOUTH_GROUP1_PMU_SUSCLK",
+ "SOUTH_GROUP1_ADR_TRIGGER",
+ "SOUTH_GROUP1_PMU_SLP_S45_N",
+ "SOUTH_GROUP1_PMU_SLP_S3_N",
+ "SOUTH_GROUP1_PMU_WAKE_N",
+ "SOUTH_GROUP1_PMU_PWRBTN_N",
+ "SOUTH_GROUP1_PMU_RESETBUTTON_N",
+ "SOUTH_GROUP1_PMU_PLTRST_N",
+ "SOUTH_GROUP1_SUS_STAT_N",
+ "SOUTH_GROUP1_SLP_S0IX_N",
+ "SOUTH_GROUP1_SPI_CS0_N",
+ "SOUTH_GROUP1_SPI_CS1_N",
+ "SOUTH_GROUP1_SPI_MOSI_IO0",
+ "SOUTH_GROUP1_SPI_MISO_IO1",
+ "SOUTH_GROUP1_SPI_IO2",
+ "SOUTH_GROUP1_SPI_IO3",
+ "SOUTH_GROUP1_SPI_CLK",
+ "SOUTH_GROUP1_SPI_CLK_LOOPBK",
+ "SOUTH_GROUP1_ESPI_IO0",
+ "SOUTH_GROUP1_ESPI_IO1",
+ "SOUTH_GROUP1_ESPI_IO2",
+ "SOUTH_GROUP1_ESPI_IO3",
+ "SOUTH_GROUP1_ESPI_CS0_N",
+ "SOUTH_GROUP1_ESPI_CLK",
+ "SOUTH_GROUP1_ESPI_RST_N",
+ "SOUTH_GROUP1_ESPI_ALRT0_N",
+ "SOUTH_GROUP1_GPIO_10",
+ "SOUTH_GROUP1_GPIO_11",
+ "SOUTH_GROUP1_ESPI_CLK_LOOPBK",
+ "SOUTH_GROUP1_EMMC_CMD",
+ "SOUTH_GROUP1_EMMC_STROBE",
+ "SOUTH_GROUP1_EMMC_CLK",
+ "SOUTH_GROUP1_EMMC_D0",
+ "SOUTH_GROUP1_EMMC_D1",
+ "SOUTH_GROUP1_EMMC_D2",
+ "SOUTH_GROUP1_EMMC_D3",
+ "SOUTH_GROUP1_EMMC_D4",
+ "SOUTH_GROUP1_EMMC_D5",
+ "SOUTH_GROUP1_EMMC_D6",
+ "SOUTH_GROUP1_EMMC_D7",
+ "SOUTH_GROUP1_GPIO_3",
+};
+
+static const struct gpio_group denverton_group_south_group1 = {
+ .display = "------- GPIO Group South Group1 -------",
+ .pad_count = ARRAY_SIZE(denverton_group_south_group1_names) / 1,
+ .func_count = 1,
+ .pad_names = denverton_group_south_group1_names,
+};
+
+static const struct gpio_group *const denverton_community_south_groups[] = {
+ &denverton_group_south_dfx,
+ &denverton_group_south_group0,
+ &denverton_group_south_group1,
+};
+
+static const struct gpio_community denverton_community_south = {
+ .name = "------- GPIO Community 1 -------",
+ .pcr_port_id = 0xc5,
+ .group_count = ARRAY_SIZE(denverton_community_south_groups),
+ .groups = denverton_community_south_groups,
+};
+
+static const struct gpio_community *const denverton_communities[] = {
+ &denverton_community_north, &denverton_community_south,
+};
diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c
index 53a8eb9..c7ab186 100644
--- a/util/inteltool/gpio_groups.c
+++ b/util/inteltool/gpio_groups.c
@@ -2,6 +2,7 @@
* inteltool - dump all registers on an Intel CPU + chipset based system.
*
* Copyright (C) 2017 secunet Security Networks AG
+ * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -21,826 +22,13 @@
#include <inttypes.h>
#include "inteltool.h"
#include "pcr.h"
+#include "gpio.h"
+#include "gpio_denverton.h"
+#include "gpio_sunrise.h"
#define SBBAR_SIZE (16 * MiB)
#define PCR_PORT_SIZE (64 * KiB)
-struct gpio_group {
- const char *display;
- size_t pad_count;
- size_t func_count;
- const char *const *pad_names; /* indexed by 'pad * func_count + func' */
-};
-
-struct gpio_community {
- const char *name;
- uint8_t pcr_port_id;
- size_t group_count;
- const struct gpio_group *const *groups;
-};
-
-static const char *const sunrise_group_a_names[] = {
- "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#",
- "GPP_A1", "LAD0", "n/a", "ESPI_IO0",
- "GPP_A2", "LAD1", "n/a", "ESPI_IO1",
- "GPP_A3", "LAD2", "n/a", "ESPI_IO2",
- "GPP_A4", "LAD3", "n/a", "ESPI_IO3",
- "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#",
- "GPP_A6", "SERIRQ", "n/a", "ESPI_CS1#",
- "GPP_A7", "PIRQA#", "n/a", "ESPI_ALERT0#",
- "GPP_A8", "CLKRUN#", "n/a", "n/a",
- "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK",
- "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a",
- "GPP_A11", "PME#", "n/a", "n/a",
- "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#",
- "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a",
- "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#",
- "GPP_A15", "SUS_ACK#", "n/a", "n/a",
- "GPP_A16", "CLKOUT_48", "n/a", "n/a",
- "GPP_A17", "ISH_GP7", "n/a", "n/a",
- "GPP_A18", "ISH_GP0", "n/a", "n/a",
- "GPP_A19", "ISH_GP1", "n/a", "n/a",
- "GPP_A20", "ISH_GP2", "n/a", "n/a",
- "GPP_A21", "ISH_GP3", "n/a", "n/a",
- "GPP_A22", "ISH_GP4", "n/a", "n/a",
- "GPP_A23", "ISH_GP5", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_group_a = {
- .display = "------- GPIO Group GPP_A -------",
- .pad_count = ARRAY_SIZE(sunrise_group_a_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_group_a_names,
-};
-
-static const char *const sunrise_lp_group_a_names[] = {
- "GPP_A0", "RCIN#", "n/a", "n/a",
- "GPP_A1", "LAD0", "n/a", "ESPI_IO0",
- "GPP_A2", "LAD1", "n/a", "ESPI_IO1",
- "GPP_A3", "LAD2", "n/a", "ESPI_IO2",
- "GPP_A4", "LAD3", "n/a", "ESPI_IO3",
- "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#",
- "GPP_A6", "SERIRQ", "n/a", "n/a",
- "GPP_A7", "PIRQA#", "n/a", "n/a",
- "GPP_A8", "CLKRUN#", "n/a", "n/a",
- "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK",
- "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a",
- "GPP_A11", "PME#", "n/a", "n/a",
- "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#",
- "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a",
- "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#",
- "GPP_A15", "SUS_ACK#", "n/a", "n/a",
- "GPP_A16", "SD_1P8_SEL", "n/a", "n/a",
- "GPP_A17", "SD_PWR_EN#", "ISH_GP7", "n/a",
- "GPP_A18", "ISH_GP0", "n/a", "n/a",
- "GPP_A19", "ISH_GP1", "n/a", "n/a",
- "GPP_A20", "ISH_GP2", "n/a", "n/a",
- "GPP_A21", "ISH_GP3", "n/a", "n/a",
- "GPP_A22", "ISH_GP4", "n/a", "n/a",
- "GPP_A23", "ISH_GP5", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_lp_group_a = {
- .display = "------- GPIO group GPP_A -------",
- .pad_count = ARRAY_SIZE(sunrise_lp_group_a_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_lp_group_a_names,
-};
-
-static const char *const sunrise_group_b_names[] = {
- "GPP_B0", "n/a", "n/a", "n/a",
- "GPP_B1", "n/a", "n/a", "n/a",
- "GPP_B2", "VRALERT#", "n/a", "n/a",
- "GPP_B3", "CPU_GP2", "n/a", "n/a",
- "GPP_B4", "CPU_GP3", "n/a", "n/a",
- "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a",
- "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a",
- "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a",
- "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a",
- "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a",
- "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a",
- "GPP_B11", "n/a", "n/a", "n/a",
- "GPP_B12", "SLP_S0#", "n/a", "n/a",
- "GPP_B13", "PLTRST#", "n/a", "n/a",
- "GPP_B14", "SPKR", "n/a", "n/a",
- "GPP_B15", "GSPIO_CS#", "n/a", "n/a",
- "GPP_B16", "GSPIO_CLK", "n/a", "n/a",
- "GPP_B17", "GSPIO_MISO", "n/a", "n/a",
- "GPP_B18", "GSPIO_MOSI", "n/a", "n/a",
- "GPP_B19", "GSPI1_CS#", "n/a", "n/a",
- "GPP_B20", "GSPI1_CLK", "n/a", "n/a",
- "GPP_B21", "GSPI1_MISO", "n/a", "n/a",
- "GPP_B22", "GSPI1_MOSI", "n/a", "n/a",
- "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a",
-};
-
-static const struct gpio_group sunrise_group_b = {
- .display = "------- GPIO Group GPP_B -------",
- .pad_count = ARRAY_SIZE(sunrise_group_b_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_group_b_names,
-};
-
-static const char *const sunrise_lp_group_b_names[] = {
- "GPP_B0", "CORE_VID0", "n/a", "n/a",
- "GPP_B1", "CORE_VID1", "n/a", "n/a",
- "GPP_B2", "VRALERT#", "n/a", "n/a",
- "GPP_B3", "CPU_GP2", "n/a", "n/a",
- "GPP_B4", "CPU_GP3", "n/a", "n/a",
- "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a",
- "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a",
- "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a",
- "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a",
- "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a",
- "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a",
- "GPP_B11", "EXT_PWR_GATE#", "n/a", "n/a",
- "GPP_B12", "SLP_S0#", "n/a", "n/a",
- "GPP_B13", "PLTRST#", "n/a", "n/a",
- "GPP_B14", "SPKR", "n/a", "n/a",
- "GPP_B15", "GSPI0_CS#", "n/a", "n/a",
- "GPP_B16", "GSPI0_CLK", "n/a", "n/a",
- "GPP_B17", "GSPI0_MISO", "n/a", "n/a",
- "GPP_B18", "GSPI0_MOSI", "n/a", "n/a",
- "GPP_B19", "GSPI1_CS#", "n/a", "n/a",
- "GPP_B20", "GSPI1_CLK", "n/a", "n/a",
- "GPP_B21", "GSPI1_MISO", "n/a", "n/a",
- "GPP_B22", "GSPI1_MOSI", "n/a", "n/a",
- "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a",
-};
-
-static const struct gpio_group sunrise_lp_group_b = {
- .display = "------- GPIO Group GPP_B -------",
- .pad_count = ARRAY_SIZE(sunrise_lp_group_b_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_lp_group_b_names,
-};
-
-static const struct gpio_group *const sunrise_community_ab_groups[] = {
- &sunrise_group_a, &sunrise_group_b,
-};
-
-static const struct gpio_group *const sunrise_lp_community_ab_groups[] = {
- &sunrise_lp_group_a, &sunrise_lp_group_b,
-};
-
-static const struct gpio_community sunrise_community_ab = {
- .name = "------- GPIO Community 0 -------",
- .pcr_port_id = 0xaf,
- .group_count = ARRAY_SIZE(sunrise_community_ab_groups),
- .groups = sunrise_community_ab_groups,
-};
-
-static const struct gpio_community sunrise_lp_community_ab = {
- .name = "------- GPIO Community 0 -------",
- .pcr_port_id = 0xaf,
- .group_count = ARRAY_SIZE(sunrise_lp_community_ab_groups),
- .groups = sunrise_lp_community_ab_groups,
-};
-
-static const char *const sunrise_group_c_names[] = {
- "GPP_C0", "SMBCLK", "n/a", "n/a",
- "GPP_C1", "SMBDATA", "n/a", "n/a",
- "GPP_C2", "SMBALERT#", "n/a", "n/a",
- "GPP_C3", "SML0CLK", "n/a", "n/a",
- "GPP_C4", "SML0DATA", "n/a", "n/a",
- "GPP_C5", "SML0ALERT#", "n/a", "n/a",
- "GPP_C6", "SML1CLK", "n/a", "n/a",
- "GPP_C7", "SML1DATA", "n/a", "n/a",
- "GPP_C8", "UART0_RXD", "n/a", "n/a",
- "GPP_C9", "UART0_TXD", "n/a", "n/a",
- "GPP_C10", "UART0_RTS#", "n/a", "n/a",
- "GPP_C11", "UART0_CTS#", "n/a", "n/a",
- "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", "n/a",
- "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", "n/a",
- "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", "n/a",
- "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", "n/a",
- "GPP_C16", "I2C0_SDA", "n/a", "n/a",
- "GPP_C17", "I2C0_SCL", "n/a", "n/a",
- "GPP_C18", "I2C1_SDA", "n/a", "n/a",
- "GPP_C19", "I2C1_SCL", "n/a", "n/a",
- "GPP_C20", "UART2_RXD", "n/a", "n/a",
- "GPP_C21", "UART2_TXD", "n/a", "n/a",
- "GPP_C22", "UART2_RTS#", "n/a", "n/a",
- "GPP_C23", "UART2_CTS#", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_group_c = {
- .display = "------- GPIO Group GPP_C -------",
- .pad_count = ARRAY_SIZE(sunrise_group_c_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_group_c_names,
-};
-
-static const char *const sunrise_group_d_names[] = {
- "GPP_D0", "n/a", "n/a", "n/a",
- "GPP_D1", "n/a", "n/a", "n/a",
- "GPP_D2", "n/a", "n/a", "n/a",
- "GPP_D3", "n/a", "n/a", "n/a",
- "GPP_D4", "ISH_I2C2_SDA", "I2C3_SDA", "n/a",
- "GPP_D5", "I2S_SFRM", "n/a", "n/a",
- "GPP_D6", "I2S_TXD", "n/a", "n/a",
- "GPP_D7", "I2S_RXD", "n/a", "n/a",
- "GPP_D8", "I2S_SCLK", "n/a", "n/a",
- "GPP_D9", "n/a", "n/a", "n/a",
- "GPP_D10", "n/a", "n/a", "n/a",
- "GPP_D11", "n/a", "n/a", "n/a",
- "GPP_D12", "n/a", "n/a", "n/a",
- "GPP_D13", "ISH_UART0_RXD", "n/a", "I2C2_SDA",
- "GPP_D14", "ISH_UART0_TXD", "n/a", "I2C2_SCL",
- "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a",
- "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a",
- "GPP_D17", "DMIC_CLK1", "n/a", "n/a",
- "GPP_D18", "DMIC_DATA1", "n/a", "n/a",
- "GPP_D19", "DMIC_CLK0", "n/a", "n/a",
- "GPP_D20", "DMIC_DATA0", "n/a", "n/a",
- "GPP_D21", "n/a", "n/a", "n/a",
- "GPP_D22", "n/a", "n/a", "n/a",
- "GPP_D23", "ISH_I2C2_SCL", "I2C3_SCL", "n/a",
-};
-
-static const struct gpio_group sunrise_group_d = {
- .display = "------- GPIO Group GPP_D -------",
- .pad_count = ARRAY_SIZE(sunrise_group_d_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_group_d_names,
-};
-
-static const char *const sunrise_lp_group_d_names[] = {
- "GPP_D0", "SPI1_CS#", "n/a", "n/a",
- "GPP_D1", "SPI1_CLK", "n/a", "n/a",
- "GPP_D2", "SPI1_MISO", "n/a", "n/a",
- "GPP_D3", "SPI1_MOSI", "n/a", "n/a",
- "GPP_D4", "FLASHTRIG", "n/a", "n/a",
- "GPP_D5", "ISH_I2C0_SDA", "n/a", "n/a",
- "GPP_D6", "ISH_I2C0_SCL", "n/a", "n/a",
- "GPP_D7", "ISH_I2C1_SDA", "n/a", "n/a",
- "GPP_D8", "ISH_I2C1_SCL", "n/a", "n/a",
- "GPP_D9", "n/a", "n/a", "n/a",
- "GPP_D10", "n/a", "n/a", "n/a",
- "GPP_D11", "n/a", "n/a", "n/a",
- "GPP_D12", "n/a", "n/a", "n/a",
- "GPP_D13", "ISH_UART0_RXD", "n/a", "n/a",
- "GPP_D14", "ISH_UART0_TXD", "n/a", "n/a",
- "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a",
- "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a",
- "GPP_D17", "DMIC_CLK1", "n/a", "n/a",
- "GPP_D18", "DMIC_DATA1", "n/a", "n/a",
- "GPP_D19", "DMIC_CLK0", "n/a", "n/a",
- "GPP_D20", "DMIC_DATA0", "n/a", "n/a",
- "GPP_D21", "SPI1_IO2", "n/a", "n/a",
- "GPP_D22", "SPI1_IO3", "n/a", "n/a",
- "GPP_D23", "I2S_MCLK", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_lp_group_d = {
- .display = "------- GPIO Group GPP_D -------",
- .pad_count = ARRAY_SIZE(sunrise_lp_group_d_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_lp_group_d_names,
-};
-
-static const char *const sunrise_group_e_names[] = {
- "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a",
- "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a",
- "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a",
- "GPP_E3", "CPU_GP0", "n/a", "n/a",
- "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a",
- "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a",
- "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a",
- "GPP_E7", "CPU_GP1", "n/a", "n/a",
- "GPP_E8", "SATA_LED#", "n/a", "n/a",
- "GPP_E9", "USB_OC0#", "n/a", "n/a",
- "GPP_E10", "USB_OC1#", "n/a", "n/a",
- "GPP_E11", "USB_OC2#", "n/a", "n/a",
- "GPP_E12", "USB_OC3#", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_group_e = {
- .display = "------- GPIO Group GPP_E -------",
- .pad_count = ARRAY_SIZE(sunrise_group_e_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_group_e_names,
-};
-
-static const char *const sunrise_lp_group_e_names[] = {
- "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a",
- "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a",
- "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a",
- "GPP_E3", "CPU_GP0", "n/a", "n/a",
- "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a",
- "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a",
- "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a",
- "GPP_E7", "CPU_GP1", "n/a", "n/a",
- "GPP_E8", "SATALED#", "n/a", "n/a",
- "GPP_E9", "USB2_OC0#", "n/a", "n/a",
- "GPP_E10", "USB2_OC1#", "n/a", "n/a",
- "GPP_E11", "USB2_OC2#", "n/a", "n/a",
- "GPP_E12", "USB2_OC3#", "n/a", "n/a",
- "GPP_E13", "DDPB_HPD0", "n/a", "n/a",
- "GPP_E14", "DDPC_HPD1", "n/a", "n/a",
- "GPP_E15", "DDPD_HPD2", "n/a", "n/a",
- "GPP_E16", "DDPE_HPD3", "n/a", "n/a",
- "GPP_E17", "EDP_HPD", "n/a", "n/a",
- "GPP_E18", "DDPB_CTRLCLK", "n/a", "n/a",
- "GPP_E19", "DDPB_CTRLDATA", "n/a", "n/a",
- "GPP_E20", "DDPC_CTRLCLK", "n/a", "n/a",
- "GPP_E21", "DDPC_CTRLDATA", "n/a", "n/a",
- "GPP_E22", "n/a", "n/a", "n/a",
- "GPP_E23", "n/a", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_lp_group_e = {
- .display = "------- GPIO Group GPP_E -------",
- .pad_count = ARRAY_SIZE(sunrise_lp_group_e_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_lp_group_e_names,
-};
-
-static const char *const sunrise_group_f_names[] = {
- "GPP_F0", "SATAXPCIE3", "SATAGP3", "n/a",
- "GPP_F1", "SATAXPCIE4", "SATAGP4", "n/a",
- "GPP_F2", "SATAXPCIE5", "SATAGP5", "n/a",
- "GPP_F3", "SATAXPCIE6", "SATAGP6", "n/a",
- "GPP_F4", "SATAXPCIE7", "SATAGP7", "n/a",
- "GPP_F5", "SATA_DEVSLP3", "n/a", "n/a",
- "GPP_F6", "SATA_DEVSLP4", "n/a", "n/a",
- "GPP_F7", "SATA_DEVSLP5", "n/a", "n/a",
- "GPP_F8", "SATA_DEVSLP6", "n/a", "n/a",
- "GPP_F9", "SATA_DEVSLP7", "n/a", "n/a",
- "GPP_F10", "SATA_SCLOCK", "n/a", "n/a",
- "GPP_F11", "SATA_SLOAD", "n/a", "n/a",
- "GPP_F12", "SATA_SDATAOUT1", "n/a", "n/a",
- "GPP_F13", "SATA_SDATAOUT2", "n/a", "n/a",
- "GPP_F14", "n/a", "n/a", "n/a",
- "GPP_F15", "USB_OC4#", "n/a", "n/a",
- "GPP_F16", "USB_OC5#", "n/a", "n/a",
- "GPP_F17", "USB_OC6#", "n/a", "n/a",
- "GPP_F18", "USB_OC7#", "n/a", "n/a",
- "GPP_F19", "eDP_VDDEN", "n/a", "n/a",
- "GPP_F20", "eDP_BKLTEN", "n/a", "n/a",
- "GPP_F21", "eDP_BKLTCTL", "n/a", "n/a",
- "GPP_F22", "n/a", "n/a", "n/a",
- "GPP_F23", "n/a", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_group_f = {
- .display = "------- GPIO Group GPP_F -------",
- .pad_count = ARRAY_SIZE(sunrise_group_f_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_group_f_names,
-};
-
-static const char *const sunrise_lp_group_f_names[] = {
- "GPP_F0", "I2S2_SCLK", "n/a", "n/a",
- "GPP_F1", "I2S2_SFRM", "n/a", "n/a",
- "GPP_F2", "I2S2_TXD", "n/a", "n/a",
- "GPP_F3", "I2S2_RXD", "n/a", "n/a",
- "GPP_F4", "I2C2_SDA", "n/a", "n/a",
- "GPP_F5", "I2C2_SCL", "n/a", "n/a",
- "GPP_F6", "I2C3_SDA", "n/a", "n/a",
- "GPP_F7", "I2C3_SCL", "n/a", "n/a",
- "GPP_F8", "I2C4_SDA", "n/a", "n/a",
- "GPP_F9", "I2C4_SCL", "n/a", "n/a",
- "GPP_F10", "I2C5_SDA", "ISH_I2C2_SDA", "n/a",
- "GPP_F11", "I2C5_SCL", "ISH_I2C2_SCL", "n/a",
- "GPP_F12", "EMMC_CMD", "n/a", "n/a",
- "GPP_F13", "EMMC_DATA0", "n/a", "n/a",
- "GPP_F14", "EMMC_DATA1", "n/a", "n/a",
- "GPP_F15", "EMMC_DATA2", "n/a", "n/a",
- "GPP_F16", "EMMC_DATA3", "n/a", "n/a",
- "GPP_F17", "EMMC_DATA4", "n/a", "n/a",
- "GPP_F18", "EMMC_DATA5", "n/a", "n/a",
- "GPP_F19", "EMMC_DATA6", "n/a", "n/a",
- "GPP_F20", "EMMC_DATA7", "n/a", "n/a",
- "GPP_F21", "EMMC_RCLK", "n/a", "n/a",
- "GPP_F22", "EMMC_CLK", "n/a", "n/a",
- "GPP_F23", "n/a", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_lp_group_f = {
- .display = "------- GPIO Group GPP_F -------",
- .pad_count = ARRAY_SIZE(sunrise_lp_group_f_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_lp_group_f_names,
-};
-
-static const char *const sunrise_group_g_names[] = {
- "GPP_G0", "FAN_TACH_0", "n/a", "n/a",
- "GPP_G1", "FAN_TACH_1", "n/a", "n/a",
- "GPP_G2", "FAN_TACH_2", "n/a", "n/a",
- "GPP_G3", "FAN_TACH_3", "n/a", "n/a",
- "GPP_G4", "FAN_TACH_4", "n/a", "n/a",
- "GPP_G5", "FAN_TACH_5", "n/a", "n/a",
- "GPP_G6", "FAN_TACH_6", "n/a", "n/a",
- "GPP_G7", "FAN_TACH_7", "n/a", "n/a",
- "GPP_G8", "FAN_PWM_0", "n/a", "n/a",
- "GPP_G9", "FAN_PWM_1", "n/a", "n/a",
- "GPP_G10", "FAN_PWM_2", "n/a", "n/a",
- "GPP_G11", "FAN_PWM_3", "n/a", "n/a",
- "GPP_G12", "GSXDOUT", "n/a", "n/a",
- "GPP_G13", "GSXSLOAD", "n/a", "n/a",
- "GPP_G14", "GSXDIN", "n/a", "n/a",
- "GPP_G15", "GSXRESET#", "n/a", "n/a",
- "GPP_G16", "GSXCLK", "n/a", "n/a",
- "GPP_G17", "ADR_COMPLETE", "n/a", "n/a",
- "GPP_G18", "NMI#", "n/a", "n/a",
- "GPP_G19", "SMI#", "n/a", "n/a",
- "GPP_G20", "n/a", "n/a", "n/a",
- "GPP_G21", "n/a", "n/a", "n/a",
- "GPP_G22", "n/a", "n/a", "n/a",
- "GPP_G23", "n/a", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_group_g = {
- .display = "------- GPIO Group GPP_G -------",
- .pad_count = ARRAY_SIZE(sunrise_group_g_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_group_g_names,
-};
-
-static const char *const sunrise_lp_group_g_names[] = {
- "GPP_G0", "SD_CMD", "n/a", "n/a",
- "GPP_G1", "SD_DATA0", "n/a", "n/a",
- "GPP_G2", "SD_DATA1", "n/a", "n/a",
- "GPP_G3", "SD_DATA2", "n/a", "n/a",
- "GPP_G4", "SD_DATA3", "n/a", "n/a",
- "GPP_G5", "SD_CD#", "n/a", "n/a",
- "GPP_G6", "SD_CLK", "n/a", "n/a",
- "GPP_G7", "SD_WP", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_lp_group_g = {
- .display = "------- GPIO Group GPP_G -------",
- .pad_count = ARRAY_SIZE(sunrise_lp_group_g_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_lp_group_g_names,
-};
-
-static const char *const sunrise_group_h_names[] = {
- "GPP_H0", "SRCCLKREQ6#", "n/a", "n/a",
- "GPP_H1", "SRCCLKREQ7#", "n/a", "n/a",
- "GPP_H2", "SRCCLKREQ8#", "n/a", "n/a",
- "GPP_H3", "SRCCLKREQ9#", "n/a", "n/a",
- "GPP_H4", "SRCCLKREQ10#", "n/a", "n/a",
- "GPP_H5", "SRCCLKREQ11#", "n/a", "n/a",
- "GPP_H6", "SRCCLKREQ12#", "n/a", "n/a",
- "GPP_H7", "SRCCLKREQ13#", "n/a", "n/a",
- "GPP_H8", "SRCCLKREQ14#", "n/a", "n/a",
- "GPP_H9", "SRCCLKREQ15#", "n/a", "n/a",
- "GPP_H10", "SML2CLK", "n/a", "n/a",
- "GPP_H11", "SML2DATA", "n/a", "n/a",
- "GPP_H12", "SML2ALERT#", "n/a", "n/a",
- "GPP_H13", "SML3CLK", "n/a", "n/a",
- "GPP_H14", "SML3DATA", "n/a", "n/a",
- "GPP_H15", "SML3ALERT#", "n/a", "n/a",
- "GPP_H16", "SML4CLK", "n/a", "n/a",
- "GPP_H17", "SML4DATA", "n/a", "n/a",
- "GPP_H18", "SML4ALERT#", "n/a", "n/a",
- "GPP_H19", "ISH_I2C0_SDA", "n/a", "n/a",
- "GPP_H20", "ISH_I2C0_SCL", "n/a", "n/a",
- "GPP_H21", "ISH_I2C1_SDA", "n/a", "n/a",
- "GPP_H22", "ISH_I2C1_SCL", "n/a", "n/a",
- "GPP_H23", "n/a", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_group_h = {
- .display = "------- GPIO Group GPP_H -------",
- .pad_count = ARRAY_SIZE(sunrise_group_h_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_group_h_names,
-};
-
-static const struct gpio_group *const sunrise_community_cdefgh_groups[] = {
- &sunrise_group_c, &sunrise_group_d, &sunrise_group_e,
- &sunrise_group_f, &sunrise_group_g, &sunrise_group_h,
-};
-
-static const struct gpio_group *const sunrise_lp_community_cde_groups[] = {
- &sunrise_group_c, &sunrise_lp_group_d, &sunrise_lp_group_e,
-};
-
-static const struct gpio_community sunrise_community_cdefgh = {
- .name = "------- GPIO Community 1 -------",
- .pcr_port_id = 0xae,
- .group_count = ARRAY_SIZE(sunrise_community_cdefgh_groups),
- .groups = sunrise_community_cdefgh_groups,
-};
-
-static const struct gpio_community sunrise_lp_community_cde = {
- .name = "------- GPIO Community 1 -------",
- .pcr_port_id = 0xae,
- .group_count = ARRAY_SIZE(sunrise_lp_community_cde_groups),
- .groups = sunrise_lp_community_cde_groups,
-};
-
-static const char *const sunrise_group_gpd_names[] = {
- "GPD0", "BATLOW#", "n/a", "n/a",
- "GPD1", "ACPRESENT", "n/a", "n/a",
- "GPD2", "LAN_WAKE#", "n/a", "n/a",
- "GPD3", "PWRBTN#", "n/a", "n/a",
- "GPD4", "SLP_S3#", "n/a", "n/a",
- "GPD5", "SLP_S4#", "n/a", "n/a",
- "GPD6", "SLP_A#", "n/a", "n/a",
- "GPD7", "RESERVED", "n/a", "n/a",
- "GPD8", "SUSCLK", "n/a", "n/a",
- "GPD9", "SLP_WLAN#", "n/a", "n/a",
- "GPD10", "SLP_S5#", "n/a", "n/a",
- "GPD11", "LANPHYPC", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_group_gpd = {
- .display = "-------- GPIO Group GPD --------",
- .pad_count = ARRAY_SIZE(sunrise_group_gpd_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_group_gpd_names,
-};
-
-static const struct gpio_group *const sunrise_community_gpd_groups[] = {
- &sunrise_group_gpd,
-};
-
-static const struct gpio_community sunrise_community_gpd = {
- .name = "------- GPIO Community 2 -------",
- .pcr_port_id = 0xad,
- .group_count = ARRAY_SIZE(sunrise_community_gpd_groups),
- .groups = sunrise_community_gpd_groups,
-};
-
-static const char *const sunrise_group_i_names[] = {
- "GPP_I0", "DDPB_HPD0", "n/a", "n/a",
- "GPP_I1", "DDPC_HPD1", "n/a", "n/a",
- "GPP_I2", "DDPD_HPD2", "n/a", "n/a",
- "GPP_I3", "DDPE_HPD3", "n/a", "n/a",
- "GPP_I4", "EDP_HPD", "n/a", "n/a",
- "GPP_I5", "DDPB_CTRLCLK", "n/a", "n/a",
- "GPP_I6", "DDPB_CTRLDATA", "n/a", "n/a",
- "GPP_I7", "DDPC_CTRLCLK", "n/a", "n/a",
- "GPP_I8", "DDPC_CTRLDATA", "n/a", "n/a",
- "GPP_I9", "DDPD_CTRLCLK", "n/a", "n/a",
- "GPP_I10", "DDPD_CTRLDATA", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_group_i = {
- .display = "------- GPIO Group GPP_I -------",
- .pad_count = ARRAY_SIZE(sunrise_group_i_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_group_i_names,
-};
-
-static const struct gpio_group *const sunrise_community_i_groups[] = {
- &sunrise_group_i,
-};
-
-static const struct gpio_group *const sunrise_lp_community_fg_groups[] = {
- &sunrise_lp_group_f, &sunrise_lp_group_g,
-};
-
-static const struct gpio_community sunrise_community_i = {
- .name = "------- GPIO Community 3 -------",
- .pcr_port_id = 0xac,
- .group_count = ARRAY_SIZE(sunrise_community_i_groups),
- .groups = sunrise_community_i_groups,
-};
-
-static const struct gpio_community sunrise_lp_community_fg = {
- .name = "------- GPIO Community 3 -------",
- .pcr_port_id = 0xac,
- .group_count = ARRAY_SIZE(sunrise_lp_community_fg_groups),
- .groups = sunrise_lp_community_fg_groups,
-};
-
-static const struct gpio_community *const sunrise_communities[] = {
- &sunrise_community_ab, &sunrise_community_cdefgh,
- &sunrise_community_gpd, &sunrise_community_i,
-};
-
-static const struct gpio_community *const sunrise_lp_communities[] = {
- &sunrise_lp_community_ab, &sunrise_lp_community_cde,
- &sunrise_community_gpd, &sunrise_lp_community_fg,
-};
-
-static const char *const denverton_group_north_all_names[] = {
- "NORTH_ALL_GBE0_SDP0",
- "NORTH_ALL_GBE1_SDP0",
- "NORTH_ALL_GBE0_SDP1",
- "NORTH_ALL_GBE1_SDP1",
- "NORTH_ALL_GBE0_SDP2",
- "NORTH_ALL_GBE1_SDP2",
- "NORTH_ALL_GBE0_SDP3",
- "NORTH_ALL_GBE1_SDP3",
- "NORTH_ALL_GBE2_LED0",
- "NORTH_ALL_GBE2_LED1",
- "NORTH_ALL_GBE0_I2C_CLK",
- "NORTH_ALL_GBE0_I2C_DATA",
- "NORTH_ALL_GBE1_I2C_CLK",
- "NORTH_ALL_GBE1_I2C_DATA",
- "NORTH_ALL_NCSI_RXD0",
- "NORTH_ALL_NCSI_CLK_IN",
- "NORTH_ALL_NCSI_RXD1",
- "NORTH_ALL_NCSI_CRS_DV",
- "NORTH_ALL_NCSI_ARB_IN",
- "NORTH_ALL_NCSI_TX_EN",
- "NORTH_ALL_NCSI_TXD0",
- "NORTH_ALL_NCSI_TXD1",
- "NORTH_ALL_NCSI_ARB_OUT",
- "NORTH_ALL_GBE0_LED0",
- "NORTH_ALL_GBE0_LED1",
- "NORTH_ALL_GBE1_LED0",
- "NORTH_ALL_GBE1_LED1",
- "NORTH_ALL_GPIO_0",
- "NORTH_ALL_PCIE_CLKREQ0_N",
- "NORTH_ALL_PCIE_CLKREQ1_N",
- "NORTH_ALL_PCIE_CLKREQ2_N",
- "NORTH_ALL_PCIE_CLKREQ3_N",
- "NORTH_ALL_PCIE_CLKREQ4_N",
- "NORTH_ALL_GPIO_1",
- "NORTH_ALL_GPIO_2",
- "NORTH_ALL_SVID_ALERT_N",
- "NORTH_ALL_SVID_DATA",
- "NORTH_ALL_SVID_CLK",
- "NORTH_ALL_THERMTRIP_N",
- "NORTH_ALL_PROCHOT_N",
- "NORTH_ALL_MEMHOT_N",
-};
-
-static const struct gpio_group denverton_group_north_all = {
- .display = "------- GPIO Group North All -------",
- .pad_count = ARRAY_SIZE(denverton_group_north_all_names) / 1,
- .func_count = 1,
- .pad_names = denverton_group_north_all_names,
-};
-
-static const struct gpio_group *const denverton_community_north_groups[] = {
- &denverton_group_north_all,
-};
-
-static const struct gpio_community denverton_community_north = {
- .name = "------- GPIO Community 0 -------",
- .pcr_port_id = 0xc2,
- .group_count = ARRAY_SIZE(denverton_community_north_groups),
- .groups = denverton_community_north_groups,
-};
-
-static const char *const denverton_group_south_dfx_names[] = {
- "SOUTH_DFX_DFX_PORT_CLK0",
- "SOUTH_DFX_DFX_PORT_CLK1",
- "SOUTH_DFX_DFX_PORT0",
- "SOUTH_DFX_DFX_PORT1",
- "SOUTH_DFX_DFX_PORT2",
- "SOUTH_DFX_DFX_PORT3",
- "SOUTH_DFX_DFX_PORT4",
- "SOUTH_DFX_DFX_PORT5",
- "SOUTH_DFX_DFX_PORT6",
- "SOUTH_DFX_DFX_PORT7",
- "SOUTH_DFX_DFX_PORT8",
- "SOUTH_DFX_DFX_PORT9",
- "SOUTH_DFX_DFX_PORT10",
- "SOUTH_DFX_DFX_PORT11",
- "SOUTH_DFX_DFX_PORT12",
- "SOUTH_DFX_DFX_PORT13",
- "SOUTH_DFX_DFX_PORT14",
- "SOUTH_DFX_DFX_PORT15",
-};
-
-static const struct gpio_group denverton_group_south_dfx = {
- .display = "------- GPIO Group South DFX -------",
- .pad_count = ARRAY_SIZE(denverton_group_south_dfx_names) / 1,
- .func_count = 1,
- .pad_names = denverton_group_south_dfx_names,
-};
-
-static const char *const denverton_group_south_group0_names[] = {
- "SOUTH_GROUP0_GPIO_12",
- "SOUTH_GROUP0_SMB5_GBE_ALRT_N",
- "SOUTH_GROUP0_PCIE_CLKREQ5_N",
- "SOUTH_GROUP0_PCIE_CLKREQ6_N",
- "SOUTH_GROUP0_PCIE_CLKREQ7_N",
- "SOUTH_GROUP0_UART0_RXD",
- "SOUTH_GROUP0_UART0_TXD",
- "SOUTH_GROUP0_SMB5_GBE_CLK",
- "SOUTH_GROUP0_SMB5_GBE_DATA",
- "SOUTH_GROUP0_ERROR2_N",
- "SOUTH_GROUP0_ERROR1_N",
- "SOUTH_GROUP0_ERROR0_N",
- "SOUTH_GROUP0_IERR_N",
- "SOUTH_GROUP0_MCERR_N",
- "SOUTH_GROUP0_SMB0_LEG_CLK",
- "SOUTH_GROUP0_SMB0_LEG_DATA",
- "SOUTH_GROUP0_SMB0_LEG_ALRT_N",
- "SOUTH_GROUP0_SMB1_HOST_DATA",
- "SOUTH_GROUP0_SMB1_HOST_CLK",
- "SOUTH_GROUP0_SMB2_PECI_DATA",
- "SOUTH_GROUP0_SMB2_PECI_CLK",
- "SOUTH_GROUP0_SMB4_CSME0_DATA",
- "SOUTH_GROUP0_SMB4_CSME0_CLK",
- "SOUTH_GROUP0_SMB4_CSME0_ALRT_N",
- "SOUTH_GROUP0_USB_OC0_N",
- "SOUTH_GROUP0_FLEX_CLK_SE0",
- "SOUTH_GROUP0_FLEX_CLK_SE1",
- "SOUTH_GROUP0_GPIO_4",
- "SOUTH_GROUP0_GPIO_5",
- "SOUTH_GROUP0_GPIO_6",
- "SOUTH_GROUP0_GPIO_7",
- "SOUTH_GROUP0_SATA0_LED_N",
- "SOUTH_GROUP0_SATA1_LED_N",
- "SOUTH_GROUP0_SATA_PDETECT0",
- "SOUTH_GROUP0_SATA_PDETECT1",
- "SOUTH_GROUP0_SATA0_SDOUT",
- "SOUTH_GROUP0_SATA1_SDOUT",
- "SOUTH_GROUP0_UART1_RXD",
- "SOUTH_GROUP0_UART1_TXD",
- "SOUTH_GROUP0_GPIO_8",
- "SOUTH_GROUP0_GPIO_9",
- "SOUTH_GROUP0_TCK",
- "SOUTH_GROUP0_TRST_N",
- "SOUTH_GROUP0_TMS",
- "SOUTH_GROUP0_TDI",
- "SOUTH_GROUP0_TDO",
- "SOUTH_GROUP0_CX_PRDY_N",
- "SOUTH_GROUP0_CX_PREQ_N",
- "SOUTH_GROUP0_CTBTRIGINOUT",
- "SOUTH_GROUP0_CTBTRIGOUT",
- "SOUTH_GROUP0_DFX_SPARE2",
- "SOUTH_GROUP0_DFX_SPARE3",
- "SOUTH_GROUP0_DFX_SPARE4",
-};
-
-static const struct gpio_group denverton_group_south_group0 = {
- .display = "------- GPIO Group South Group0 -------",
- .pad_count = ARRAY_SIZE(denverton_group_south_group0_names) / 1,
- .func_count = 1,
- .pad_names = denverton_group_south_group0_names,
-};
-
-static const char *const denverton_group_south_group1_names[] = {
- "SOUTH_GROUP1_SUSPWRDNACK",
- "SOUTH_GROUP1_PMU_SUSCLK",
- "SOUTH_GROUP1_ADR_TRIGGER",
- "SOUTH_GROUP1_PMU_SLP_S45_N",
- "SOUTH_GROUP1_PMU_SLP_S3_N",
- "SOUTH_GROUP1_PMU_WAKE_N",
- "SOUTH_GROUP1_PMU_PWRBTN_N",
- "SOUTH_GROUP1_PMU_RESETBUTTON_N",
- "SOUTH_GROUP1_PMU_PLTRST_N",
- "SOUTH_GROUP1_SUS_STAT_N",
- "SOUTH_GROUP1_SLP_S0IX_N",
- "SOUTH_GROUP1_SPI_CS0_N",
- "SOUTH_GROUP1_SPI_CS1_N",
- "SOUTH_GROUP1_SPI_MOSI_IO0",
- "SOUTH_GROUP1_SPI_MISO_IO1",
- "SOUTH_GROUP1_SPI_IO2",
- "SOUTH_GROUP1_SPI_IO3",
- "SOUTH_GROUP1_SPI_CLK",
- "SOUTH_GROUP1_SPI_CLK_LOOPBK",
- "SOUTH_GROUP1_ESPI_IO0",
- "SOUTH_GROUP1_ESPI_IO1",
- "SOUTH_GROUP1_ESPI_IO2",
- "SOUTH_GROUP1_ESPI_IO3",
- "SOUTH_GROUP1_ESPI_CS0_N",
- "SOUTH_GROUP1_ESPI_CLK",
- "SOUTH_GROUP1_ESPI_RST_N",
- "SOUTH_GROUP1_ESPI_ALRT0_N",
- "SOUTH_GROUP1_GPIO_10",
- "SOUTH_GROUP1_GPIO_11",
- "SOUTH_GROUP1_ESPI_CLK_LOOPBK",
- "SOUTH_GROUP1_EMMC_CMD",
- "SOUTH_GROUP1_EMMC_STROBE",
- "SOUTH_GROUP1_EMMC_CLK",
- "SOUTH_GROUP1_EMMC_D0",
- "SOUTH_GROUP1_EMMC_D1",
- "SOUTH_GROUP1_EMMC_D2",
- "SOUTH_GROUP1_EMMC_D3",
- "SOUTH_GROUP1_EMMC_D4",
- "SOUTH_GROUP1_EMMC_D5",
- "SOUTH_GROUP1_EMMC_D6",
- "SOUTH_GROUP1_EMMC_D7",
- "SOUTH_GROUP1_GPIO_3",
-};
-
-static const struct gpio_group denverton_group_south_group1 = {
- .display = "------- GPIO Group South Group1 -------",
- .pad_count = ARRAY_SIZE(denverton_group_south_group1_names) / 1,
- .func_count = 1,
- .pad_names = denverton_group_south_group1_names,
-};
-
-static const struct gpio_group *const denverton_community_south_groups[] = {
- &denverton_group_south_dfx,
- &denverton_group_south_group0,
- &denverton_group_south_group1,
-};
-
-static const struct gpio_community denverton_community_south = {
- .name = "------- GPIO Community 1 -------",
- .pcr_port_id = 0xc5,
- .group_count = ARRAY_SIZE(denverton_community_south_groups),
- .groups = denverton_community_south_groups,
-};
-
-static const struct gpio_community *const denverton_communities[] = {
- &denverton_community_north, &denverton_community_south,
-};
-
static const char *decode_pad_mode(const struct gpio_group *const group,
const size_t pad, const uint32_t dw0)
{
diff --git a/util/inteltool/gpio_sunrise.h b/util/inteltool/gpio_sunrise.h
new file mode 100644
index 0000000..5553b7d
--- /dev/null
+++ b/util/inteltool/gpio_sunrise.h
@@ -0,0 +1,595 @@
+/*
+ * inteltool - dump all registers on an Intel CPU + chipset based system.
+ *
+ * Copyright (C) 2017 secunet Security Networks AG
+ * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+static const char *const sunrise_group_a_names[] = {
+ "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#",
+ "GPP_A1", "LAD0", "n/a", "ESPI_IO0",
+ "GPP_A2", "LAD1", "n/a", "ESPI_IO1",
+ "GPP_A3", "LAD2", "n/a", "ESPI_IO2",
+ "GPP_A4", "LAD3", "n/a", "ESPI_IO3",
+ "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#",
+ "GPP_A6", "SERIRQ", "n/a", "ESPI_CS1#",
+ "GPP_A7", "PIRQA#", "n/a", "ESPI_ALERT0#",
+ "GPP_A8", "CLKRUN#", "n/a", "n/a",
+ "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK",
+ "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a",
+ "GPP_A11", "PME#", "n/a", "n/a",
+ "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#",
+ "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a",
+ "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#",
+ "GPP_A15", "SUS_ACK#", "n/a", "n/a",
+ "GPP_A16", "CLKOUT_48", "n/a", "n/a",
+ "GPP_A17", "ISH_GP7", "n/a", "n/a",
+ "GPP_A18", "ISH_GP0", "n/a", "n/a",
+ "GPP_A19", "ISH_GP1", "n/a", "n/a",
+ "GPP_A20", "ISH_GP2", "n/a", "n/a",
+ "GPP_A21", "ISH_GP3", "n/a", "n/a",
+ "GPP_A22", "ISH_GP4", "n/a", "n/a",
+ "GPP_A23", "ISH_GP5", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_group_a = {
+ .display = "------- GPIO Group GPP_A -------",
+ .pad_count = ARRAY_SIZE(sunrise_group_a_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_a_names,
+};
+
+static const char *const sunrise_lp_group_a_names[] = {
+ "GPP_A0", "RCIN#", "n/a", "n/a",
+ "GPP_A1", "LAD0", "n/a", "ESPI_IO0",
+ "GPP_A2", "LAD1", "n/a", "ESPI_IO1",
+ "GPP_A3", "LAD2", "n/a", "ESPI_IO2",
+ "GPP_A4", "LAD3", "n/a", "ESPI_IO3",
+ "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#",
+ "GPP_A6", "SERIRQ", "n/a", "n/a",
+ "GPP_A7", "PIRQA#", "n/a", "n/a",
+ "GPP_A8", "CLKRUN#", "n/a", "n/a",
+ "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK",
+ "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a",
+ "GPP_A11", "PME#", "n/a", "n/a",
+ "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#",
+ "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a",
+ "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#",
+ "GPP_A15", "SUS_ACK#", "n/a", "n/a",
+ "GPP_A16", "SD_1P8_SEL", "n/a", "n/a",
+ "GPP_A17", "SD_PWR_EN#", "ISH_GP7", "n/a",
+ "GPP_A18", "ISH_GP0", "n/a", "n/a",
+ "GPP_A19", "ISH_GP1", "n/a", "n/a",
+ "GPP_A20", "ISH_GP2", "n/a", "n/a",
+ "GPP_A21", "ISH_GP3", "n/a", "n/a",
+ "GPP_A22", "ISH_GP4", "n/a", "n/a",
+ "GPP_A23", "ISH_GP5", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_lp_group_a = {
+ .display = "------- GPIO group GPP_A -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_a_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_a_names,
+};
+
+static const char *const sunrise_group_b_names[] = {
+ "GPP_B0", "n/a", "n/a", "n/a",
+ "GPP_B1", "n/a", "n/a", "n/a",
+ "GPP_B2", "VRALERT#", "n/a", "n/a",
+ "GPP_B3", "CPU_GP2", "n/a", "n/a",
+ "GPP_B4", "CPU_GP3", "n/a", "n/a",
+ "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a",
+ "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a",
+ "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a",
+ "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a",
+ "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a",
+ "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a",
+ "GPP_B11", "n/a", "n/a", "n/a",
+ "GPP_B12", "SLP_S0#", "n/a", "n/a",
+ "GPP_B13", "PLTRST#", "n/a", "n/a",
+ "GPP_B14", "SPKR", "n/a", "n/a",
+ "GPP_B15", "GSPIO_CS#", "n/a", "n/a",
+ "GPP_B16", "GSPIO_CLK", "n/a", "n/a",
+ "GPP_B17", "GSPIO_MISO", "n/a", "n/a",
+ "GPP_B18", "GSPIO_MOSI", "n/a", "n/a",
+ "GPP_B19", "GSPI1_CS#", "n/a", "n/a",
+ "GPP_B20", "GSPI1_CLK", "n/a", "n/a",
+ "GPP_B21", "GSPI1_MISO", "n/a", "n/a",
+ "GPP_B22", "GSPI1_MOSI", "n/a", "n/a",
+ "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a",
+};
+
+static const struct gpio_group sunrise_group_b = {
+ .display = "------- GPIO Group GPP_B -------",
+ .pad_count = ARRAY_SIZE(sunrise_group_b_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_b_names,
+};
+
+static const char *const sunrise_lp_group_b_names[] = {
+ "GPP_B0", "CORE_VID0", "n/a", "n/a",
+ "GPP_B1", "CORE_VID1", "n/a", "n/a",
+ "GPP_B2", "VRALERT#", "n/a", "n/a",
+ "GPP_B3", "CPU_GP2", "n/a", "n/a",
+ "GPP_B4", "CPU_GP3", "n/a", "n/a",
+ "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a",
+ "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a",
+ "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a",
+ "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a",
+ "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a",
+ "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a",
+ "GPP_B11", "EXT_PWR_GATE#", "n/a", "n/a",
+ "GPP_B12", "SLP_S0#", "n/a", "n/a",
+ "GPP_B13", "PLTRST#", "n/a", "n/a",
+ "GPP_B14", "SPKR", "n/a", "n/a",
+ "GPP_B15", "GSPI0_CS#", "n/a", "n/a",
+ "GPP_B16", "GSPI0_CLK", "n/a", "n/a",
+ "GPP_B17", "GSPI0_MISO", "n/a", "n/a",
+ "GPP_B18", "GSPI0_MOSI", "n/a", "n/a",
+ "GPP_B19", "GSPI1_CS#", "n/a", "n/a",
+ "GPP_B20", "GSPI1_CLK", "n/a", "n/a",
+ "GPP_B21", "GSPI1_MISO", "n/a", "n/a",
+ "GPP_B22", "GSPI1_MOSI", "n/a", "n/a",
+ "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a",
+};
+
+static const struct gpio_group sunrise_lp_group_b = {
+ .display = "------- GPIO Group GPP_B -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_b_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_b_names,
+};
+
+static const struct gpio_group *const sunrise_community_ab_groups[] = {
+ &sunrise_group_a, &sunrise_group_b,
+};
+
+static const struct gpio_group *const sunrise_lp_community_ab_groups[] = {
+ &sunrise_lp_group_a, &sunrise_lp_group_b,
+};
+
+static const struct gpio_community sunrise_community_ab = {
+ .name = "------- GPIO Community 0 -------",
+ .pcr_port_id = 0xaf,
+ .group_count = ARRAY_SIZE(sunrise_community_ab_groups),
+ .groups = sunrise_community_ab_groups,
+};
+
+static const struct gpio_community sunrise_lp_community_ab = {
+ .name = "------- GPIO Community 0 -------",
+ .pcr_port_id = 0xaf,
+ .group_count = ARRAY_SIZE(sunrise_lp_community_ab_groups),
+ .groups = sunrise_lp_community_ab_groups,
+};
+
+static const char *const sunrise_group_c_names[] = {
+ "GPP_C0", "SMBCLK", "n/a", "n/a",
+ "GPP_C1", "SMBDATA", "n/a", "n/a",
+ "GPP_C2", "SMBALERT#", "n/a", "n/a",
+ "GPP_C3", "SML0CLK", "n/a", "n/a",
+ "GPP_C4", "SML0DATA", "n/a", "n/a",
+ "GPP_C5", "SML0ALERT#", "n/a", "n/a",
+ "GPP_C6", "SML1CLK", "n/a", "n/a",
+ "GPP_C7", "SML1DATA", "n/a", "n/a",
+ "GPP_C8", "UART0_RXD", "n/a", "n/a",
+ "GPP_C9", "UART0_TXD", "n/a", "n/a",
+ "GPP_C10", "UART0_RTS#", "n/a", "n/a",
+ "GPP_C11", "UART0_CTS#", "n/a", "n/a",
+ "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", "n/a",
+ "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", "n/a",
+ "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", "n/a",
+ "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", "n/a",
+ "GPP_C16", "I2C0_SDA", "n/a", "n/a",
+ "GPP_C17", "I2C0_SCL", "n/a", "n/a",
+ "GPP_C18", "I2C1_SDA", "n/a", "n/a",
+ "GPP_C19", "I2C1_SCL", "n/a", "n/a",
+ "GPP_C20", "UART2_RXD", "n/a", "n/a",
+ "GPP_C21", "UART2_TXD", "n/a", "n/a",
+ "GPP_C22", "UART2_RTS#", "n/a", "n/a",
+ "GPP_C23", "UART2_CTS#", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_group_c = {
+ .display = "------- GPIO Group GPP_C -------",
+ .pad_count = ARRAY_SIZE(sunrise_group_c_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_c_names,
+};
+
+static const char *const sunrise_group_d_names[] = {
+ "GPP_D0", "n/a", "n/a", "n/a",
+ "GPP_D1", "n/a", "n/a", "n/a",
+ "GPP_D2", "n/a", "n/a", "n/a",
+ "GPP_D3", "n/a", "n/a", "n/a",
+ "GPP_D4", "ISH_I2C2_SDA", "I2C3_SDA", "n/a",
+ "GPP_D5", "I2S_SFRM", "n/a", "n/a",
+ "GPP_D6", "I2S_TXD", "n/a", "n/a",
+ "GPP_D7", "I2S_RXD", "n/a", "n/a",
+ "GPP_D8", "I2S_SCLK", "n/a", "n/a",
+ "GPP_D9", "n/a", "n/a", "n/a",
+ "GPP_D10", "n/a", "n/a", "n/a",
+ "GPP_D11", "n/a", "n/a", "n/a",
+ "GPP_D12", "n/a", "n/a", "n/a",
+ "GPP_D13", "ISH_UART0_RXD", "n/a", "I2C2_SDA",
+ "GPP_D14", "ISH_UART0_TXD", "n/a", "I2C2_SCL",
+ "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a",
+ "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a",
+ "GPP_D17", "DMIC_CLK1", "n/a", "n/a",
+ "GPP_D18", "DMIC_DATA1", "n/a", "n/a",
+ "GPP_D19", "DMIC_CLK0", "n/a", "n/a",
+ "GPP_D20", "DMIC_DATA0", "n/a", "n/a",
+ "GPP_D21", "n/a", "n/a", "n/a",
+ "GPP_D22", "n/a", "n/a", "n/a",
+ "GPP_D23", "ISH_I2C2_SCL", "I2C3_SCL", "n/a",
+};
+
+static const struct gpio_group sunrise_group_d = {
+ .display = "------- GPIO Group GPP_D -------",
+ .pad_count = ARRAY_SIZE(sunrise_group_d_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_d_names,
+};
+
+static const char *const sunrise_lp_group_d_names[] = {
+ "GPP_D0", "SPI1_CS#", "n/a", "n/a",
+ "GPP_D1", "SPI1_CLK", "n/a", "n/a",
+ "GPP_D2", "SPI1_MISO", "n/a", "n/a",
+ "GPP_D3", "SPI1_MOSI", "n/a", "n/a",
+ "GPP_D4", "FLASHTRIG", "n/a", "n/a",
+ "GPP_D5", "ISH_I2C0_SDA", "n/a", "n/a",
+ "GPP_D6", "ISH_I2C0_SCL", "n/a", "n/a",
+ "GPP_D7", "ISH_I2C1_SDA", "n/a", "n/a",
+ "GPP_D8", "ISH_I2C1_SCL", "n/a", "n/a",
+ "GPP_D9", "n/a", "n/a", "n/a",
+ "GPP_D10", "n/a", "n/a", "n/a",
+ "GPP_D11", "n/a", "n/a", "n/a",
+ "GPP_D12", "n/a", "n/a", "n/a",
+ "GPP_D13", "ISH_UART0_RXD", "n/a", "n/a",
+ "GPP_D14", "ISH_UART0_TXD", "n/a", "n/a",
+ "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a",
+ "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a",
+ "GPP_D17", "DMIC_CLK1", "n/a", "n/a",
+ "GPP_D18", "DMIC_DATA1", "n/a", "n/a",
+ "GPP_D19", "DMIC_CLK0", "n/a", "n/a",
+ "GPP_D20", "DMIC_DATA0", "n/a", "n/a",
+ "GPP_D21", "SPI1_IO2", "n/a", "n/a",
+ "GPP_D22", "SPI1_IO3", "n/a", "n/a",
+ "GPP_D23", "I2S_MCLK", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_lp_group_d = {
+ .display = "------- GPIO Group GPP_D -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_d_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_d_names,
+};
+
+static const char *const sunrise_group_e_names[] = {
+ "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a",
+ "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a",
+ "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a",
+ "GPP_E3", "CPU_GP0", "n/a", "n/a",
+ "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a",
+ "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a",
+ "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a",
+ "GPP_E7", "CPU_GP1", "n/a", "n/a",
+ "GPP_E8", "SATA_LED#", "n/a", "n/a",
+ "GPP_E9", "USB_OC0#", "n/a", "n/a",
+ "GPP_E10", "USB_OC1#", "n/a", "n/a",
+ "GPP_E11", "USB_OC2#", "n/a", "n/a",
+ "GPP_E12", "USB_OC3#", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_group_e = {
+ .display = "------- GPIO Group GPP_E -------",
+ .pad_count = ARRAY_SIZE(sunrise_group_e_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_e_names,
+};
+
+static const char *const sunrise_lp_group_e_names[] = {
+ "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a",
+ "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a",
+ "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a",
+ "GPP_E3", "CPU_GP0", "n/a", "n/a",
+ "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a",
+ "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a",
+ "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a",
+ "GPP_E7", "CPU_GP1", "n/a", "n/a",
+ "GPP_E8", "SATALED#", "n/a", "n/a",
+ "GPP_E9", "USB2_OC0#", "n/a", "n/a",
+ "GPP_E10", "USB2_OC1#", "n/a", "n/a",
+ "GPP_E11", "USB2_OC2#", "n/a", "n/a",
+ "GPP_E12", "USB2_OC3#", "n/a", "n/a",
+ "GPP_E13", "DDPB_HPD0", "n/a", "n/a",
+ "GPP_E14", "DDPC_HPD1", "n/a", "n/a",
+ "GPP_E15", "DDPD_HPD2", "n/a", "n/a",
+ "GPP_E16", "DDPE_HPD3", "n/a", "n/a",
+ "GPP_E17", "EDP_HPD", "n/a", "n/a",
+ "GPP_E18", "DDPB_CTRLCLK", "n/a", "n/a",
+ "GPP_E19", "DDPB_CTRLDATA", "n/a", "n/a",
+ "GPP_E20", "DDPC_CTRLCLK", "n/a", "n/a",
+ "GPP_E21", "DDPC_CTRLDATA", "n/a", "n/a",
+ "GPP_E22", "n/a", "n/a", "n/a",
+ "GPP_E23", "n/a", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_lp_group_e = {
+ .display = "------- GPIO Group GPP_E -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_e_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_e_names,
+};
+
+static const char *const sunrise_group_f_names[] = {
+ "GPP_F0", "SATAXPCIE3", "SATAGP3", "n/a",
+ "GPP_F1", "SATAXPCIE4", "SATAGP4", "n/a",
+ "GPP_F2", "SATAXPCIE5", "SATAGP5", "n/a",
+ "GPP_F3", "SATAXPCIE6", "SATAGP6", "n/a",
+ "GPP_F4", "SATAXPCIE7", "SATAGP7", "n/a",
+ "GPP_F5", "SATA_DEVSLP3", "n/a", "n/a",
+ "GPP_F6", "SATA_DEVSLP4", "n/a", "n/a",
+ "GPP_F7", "SATA_DEVSLP5", "n/a", "n/a",
+ "GPP_F8", "SATA_DEVSLP6", "n/a", "n/a",
+ "GPP_F9", "SATA_DEVSLP7", "n/a", "n/a",
+ "GPP_F10", "SATA_SCLOCK", "n/a", "n/a",
+ "GPP_F11", "SATA_SLOAD", "n/a", "n/a",
+ "GPP_F12", "SATA_SDATAOUT1", "n/a", "n/a",
+ "GPP_F13", "SATA_SDATAOUT2", "n/a", "n/a",
+ "GPP_F14", "n/a", "n/a", "n/a",
+ "GPP_F15", "USB_OC4#", "n/a", "n/a",
+ "GPP_F16", "USB_OC5#", "n/a", "n/a",
+ "GPP_F17", "USB_OC6#", "n/a", "n/a",
+ "GPP_F18", "USB_OC7#", "n/a", "n/a",
+ "GPP_F19", "eDP_VDDEN", "n/a", "n/a",
+ "GPP_F20", "eDP_BKLTEN", "n/a", "n/a",
+ "GPP_F21", "eDP_BKLTCTL", "n/a", "n/a",
+ "GPP_F22", "n/a", "n/a", "n/a",
+ "GPP_F23", "n/a", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_group_f = {
+ .display = "------- GPIO Group GPP_F -------",
+ .pad_count = ARRAY_SIZE(sunrise_group_f_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_f_names,
+};
+
+static const char *const sunrise_lp_group_f_names[] = {
+ "GPP_F0", "I2S2_SCLK", "n/a", "n/a",
+ "GPP_F1", "I2S2_SFRM", "n/a", "n/a",
+ "GPP_F2", "I2S2_TXD", "n/a", "n/a",
+ "GPP_F3", "I2S2_RXD", "n/a", "n/a",
+ "GPP_F4", "I2C2_SDA", "n/a", "n/a",
+ "GPP_F5", "I2C2_SCL", "n/a", "n/a",
+ "GPP_F6", "I2C3_SDA", "n/a", "n/a",
+ "GPP_F7", "I2C3_SCL", "n/a", "n/a",
+ "GPP_F8", "I2C4_SDA", "n/a", "n/a",
+ "GPP_F9", "I2C4_SCL", "n/a", "n/a",
+ "GPP_F10", "I2C5_SDA", "ISH_I2C2_SDA", "n/a",
+ "GPP_F11", "I2C5_SCL", "ISH_I2C2_SCL", "n/a",
+ "GPP_F12", "EMMC_CMD", "n/a", "n/a",
+ "GPP_F13", "EMMC_DATA0", "n/a", "n/a",
+ "GPP_F14", "EMMC_DATA1", "n/a", "n/a",
+ "GPP_F15", "EMMC_DATA2", "n/a", "n/a",
+ "GPP_F16", "EMMC_DATA3", "n/a", "n/a",
+ "GPP_F17", "EMMC_DATA4", "n/a", "n/a",
+ "GPP_F18", "EMMC_DATA5", "n/a", "n/a",
+ "GPP_F19", "EMMC_DATA6", "n/a", "n/a",
+ "GPP_F20", "EMMC_DATA7", "n/a", "n/a",
+ "GPP_F21", "EMMC_RCLK", "n/a", "n/a",
+ "GPP_F22", "EMMC_CLK", "n/a", "n/a",
+ "GPP_F23", "n/a", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_lp_group_f = {
+ .display = "------- GPIO Group GPP_F -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_f_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_f_names,
+};
+
+static const char *const sunrise_group_g_names[] = {
+ "GPP_G0", "FAN_TACH_0", "n/a", "n/a",
+ "GPP_G1", "FAN_TACH_1", "n/a", "n/a",
+ "GPP_G2", "FAN_TACH_2", "n/a", "n/a",
+ "GPP_G3", "FAN_TACH_3", "n/a", "n/a",
+ "GPP_G4", "FAN_TACH_4", "n/a", "n/a",
+ "GPP_G5", "FAN_TACH_5", "n/a", "n/a",
+ "GPP_G6", "FAN_TACH_6", "n/a", "n/a",
+ "GPP_G7", "FAN_TACH_7", "n/a", "n/a",
+ "GPP_G8", "FAN_PWM_0", "n/a", "n/a",
+ "GPP_G9", "FAN_PWM_1", "n/a", "n/a",
+ "GPP_G10", "FAN_PWM_2", "n/a", "n/a",
+ "GPP_G11", "FAN_PWM_3", "n/a", "n/a",
+ "GPP_G12", "GSXDOUT", "n/a", "n/a",
+ "GPP_G13", "GSXSLOAD", "n/a", "n/a",
+ "GPP_G14", "GSXDIN", "n/a", "n/a",
+ "GPP_G15", "GSXRESET#", "n/a", "n/a",
+ "GPP_G16", "GSXCLK", "n/a", "n/a",
+ "GPP_G17", "ADR_COMPLETE", "n/a", "n/a",
+ "GPP_G18", "NMI#", "n/a", "n/a",
+ "GPP_G19", "SMI#", "n/a", "n/a",
+ "GPP_G20", "n/a", "n/a", "n/a",
+ "GPP_G21", "n/a", "n/a", "n/a",
+ "GPP_G22", "n/a", "n/a", "n/a",
+ "GPP_G23", "n/a", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_group_g = {
+ .display = "------- GPIO Group GPP_G -------",
+ .pad_count = ARRAY_SIZE(sunrise_group_g_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_g_names,
+};
+
+static const char *const sunrise_lp_group_g_names[] = {
+ "GPP_G0", "SD_CMD", "n/a", "n/a",
+ "GPP_G1", "SD_DATA0", "n/a", "n/a",
+ "GPP_G2", "SD_DATA1", "n/a", "n/a",
+ "GPP_G3", "SD_DATA2", "n/a", "n/a",
+ "GPP_G4", "SD_DATA3", "n/a", "n/a",
+ "GPP_G5", "SD_CD#", "n/a", "n/a",
+ "GPP_G6", "SD_CLK", "n/a", "n/a",
+ "GPP_G7", "SD_WP", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_lp_group_g = {
+ .display = "------- GPIO Group GPP_G -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_g_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_g_names,
+};
+
+static const char *const sunrise_group_h_names[] = {
+ "GPP_H0", "SRCCLKREQ6#", "n/a", "n/a",
+ "GPP_H1", "SRCCLKREQ7#", "n/a", "n/a",
+ "GPP_H2", "SRCCLKREQ8#", "n/a", "n/a",
+ "GPP_H3", "SRCCLKREQ9#", "n/a", "n/a",
+ "GPP_H4", "SRCCLKREQ10#", "n/a", "n/a",
+ "GPP_H5", "SRCCLKREQ11#", "n/a", "n/a",
+ "GPP_H6", "SRCCLKREQ12#", "n/a", "n/a",
+ "GPP_H7", "SRCCLKREQ13#", "n/a", "n/a",
+ "GPP_H8", "SRCCLKREQ14#", "n/a", "n/a",
+ "GPP_H9", "SRCCLKREQ15#", "n/a", "n/a",
+ "GPP_H10", "SML2CLK", "n/a", "n/a",
+ "GPP_H11", "SML2DATA", "n/a", "n/a",
+ "GPP_H12", "SML2ALERT#", "n/a", "n/a",
+ "GPP_H13", "SML3CLK", "n/a", "n/a",
+ "GPP_H14", "SML3DATA", "n/a", "n/a",
+ "GPP_H15", "SML3ALERT#", "n/a", "n/a",
+ "GPP_H16", "SML4CLK", "n/a", "n/a",
+ "GPP_H17", "SML4DATA", "n/a", "n/a",
+ "GPP_H18", "SML4ALERT#", "n/a", "n/a",
+ "GPP_H19", "ISH_I2C0_SDA", "n/a", "n/a",
+ "GPP_H20", "ISH_I2C0_SCL", "n/a", "n/a",
+ "GPP_H21", "ISH_I2C1_SDA", "n/a", "n/a",
+ "GPP_H22", "ISH_I2C1_SCL", "n/a", "n/a",
+ "GPP_H23", "n/a", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_group_h = {
+ .display = "------- GPIO Group GPP_H -------",
+ .pad_count = ARRAY_SIZE(sunrise_group_h_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_h_names,
+};
+
+static const struct gpio_group *const sunrise_community_cdefgh_groups[] = {
+ &sunrise_group_c, &sunrise_group_d, &sunrise_group_e,
+ &sunrise_group_f, &sunrise_group_g, &sunrise_group_h,
+};
+
+static const struct gpio_group *const sunrise_lp_community_cde_groups[] = {
+ &sunrise_group_c, &sunrise_lp_group_d, &sunrise_lp_group_e,
+};
+
+static const struct gpio_community sunrise_community_cdefgh = {
+ .name = "------- GPIO Community 1 -------",
+ .pcr_port_id = 0xae,
+ .group_count = ARRAY_SIZE(sunrise_community_cdefgh_groups),
+ .groups = sunrise_community_cdefgh_groups,
+};
+
+static const struct gpio_community sunrise_lp_community_cde = {
+ .name = "------- GPIO Community 1 -------",
+ .pcr_port_id = 0xae,
+ .group_count = ARRAY_SIZE(sunrise_lp_community_cde_groups),
+ .groups = sunrise_lp_community_cde_groups,
+};
+
+static const char *const sunrise_group_gpd_names[] = {
+ "GPD0", "BATLOW#", "n/a", "n/a",
+ "GPD1", "ACPRESENT", "n/a", "n/a",
+ "GPD2", "LAN_WAKE#", "n/a", "n/a",
+ "GPD3", "PWRBTN#", "n/a", "n/a",
+ "GPD4", "SLP_S3#", "n/a", "n/a",
+ "GPD5", "SLP_S4#", "n/a", "n/a",
+ "GPD6", "SLP_A#", "n/a", "n/a",
+ "GPD7", "RESERVED", "n/a", "n/a",
+ "GPD8", "SUSCLK", "n/a", "n/a",
+ "GPD9", "SLP_WLAN#", "n/a", "n/a",
+ "GPD10", "SLP_S5#", "n/a", "n/a",
+ "GPD11", "LANPHYPC", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_group_gpd = {
+ .display = "-------- GPIO Group GPD --------",
+ .pad_count = ARRAY_SIZE(sunrise_group_gpd_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_gpd_names,
+};
+
+static const struct gpio_group *const sunrise_community_gpd_groups[] = {
+ &sunrise_group_gpd,
+};
+
+static const struct gpio_community sunrise_community_gpd = {
+ .name = "------- GPIO Community 2 -------",
+ .pcr_port_id = 0xad,
+ .group_count = ARRAY_SIZE(sunrise_community_gpd_groups),
+ .groups = sunrise_community_gpd_groups,
+};
+
+static const char *const sunrise_group_i_names[] = {
+ "GPP_I0", "DDPB_HPD0", "n/a", "n/a",
+ "GPP_I1", "DDPC_HPD1", "n/a", "n/a",
+ "GPP_I2", "DDPD_HPD2", "n/a", "n/a",
+ "GPP_I3", "DDPE_HPD3", "n/a", "n/a",
+ "GPP_I4", "EDP_HPD", "n/a", "n/a",
+ "GPP_I5", "DDPB_CTRLCLK", "n/a", "n/a",
+ "GPP_I6", "DDPB_CTRLDATA", "n/a", "n/a",
+ "GPP_I7", "DDPC_CTRLCLK", "n/a", "n/a",
+ "GPP_I8", "DDPC_CTRLDATA", "n/a", "n/a",
+ "GPP_I9", "DDPD_CTRLCLK", "n/a", "n/a",
+ "GPP_I10", "DDPD_CTRLDATA", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_group_i = {
+ .display = "------- GPIO Group GPP_I -------",
+ .pad_count = ARRAY_SIZE(sunrise_group_i_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_i_names,
+};
+
+static const struct gpio_group *const sunrise_community_i_groups[] = {
+ &sunrise_group_i,
+};
+
+static const struct gpio_group *const sunrise_lp_community_fg_groups[] = {
+ &sunrise_lp_group_f, &sunrise_lp_group_g,
+};
+
+static const struct gpio_community sunrise_community_i = {
+ .name = "------- GPIO Community 3 -------",
+ .pcr_port_id = 0xac,
+ .group_count = ARRAY_SIZE(sunrise_community_i_groups),
+ .groups = sunrise_community_i_groups,
+};
+
+static const struct gpio_community sunrise_lp_community_fg = {
+ .name = "------- GPIO Community 3 -------",
+ .pcr_port_id = 0xac,
+ .group_count = ARRAY_SIZE(sunrise_lp_community_fg_groups),
+ .groups = sunrise_lp_community_fg_groups,
+};
+
+static const struct gpio_community *const sunrise_communities[] = {
+ &sunrise_community_ab, &sunrise_community_cdefgh,
+ &sunrise_community_gpd, &sunrise_community_i,
+};
+
+static const struct gpio_community *const sunrise_lp_communities[] = {
+ &sunrise_lp_community_ab, &sunrise_lp_community_cde,
+ &sunrise_community_gpd, &sunrise_lp_community_fg,
+};
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic61871f5cf95ac3da93892fa2f7721e682176c8d
Gerrit-Change-Number: 31504
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de>
Gerrit-MessageType: newchange
7
34
Change in ...coreboot[master]: drivers/intel/mipi_camera: add functionality
by Matt Delco (Code Review) 26 Jun '20
by Matt Delco (Code Review) 26 Jun '20
26 Jun '20
Matt Delco has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31163
Change subject: drivers/intel/mipi_camera: add functionality
......................................................................
drivers/intel/mipi_camera: add functionality
Some boards & variants are using raw asl files to define the ACPI devices
(and related properties) required by Linux MIPI camera drivers. These asl
files lack the SSDB property that's required by Windows MIPI camera
drivers. The mipi_camera driver can provide a SSDB property, but it's
missing some properties needed for Linux (and my scan of the source code
didn't find any current users of it).
This change updates the mipi_camera driver so it can provide a combined
superset of what's required by Linux and Windows. I've also expanded
the support so it has support for the IMGU and CIO2 devices.
BUG=none
BRANCH=none
TEST=Verified that the ACPI state generated by the driver (with
appropriate devicetree changes) is extremely comparible to what's
generated by the asl files. Verified that the camera still works in
CrOS on Atlas.
Change-Id: Ie9d84519eae1333eeb67107281a2deafc24e8a08
Signed-off-by: Matt Delco <delco(a)chromium.org>
---
M src/drivers/intel/mipi_camera/camera.c
M src/drivers/intel/mipi_camera/chip.h
M src/mainboard/google/poppy/dsdt.asl
3 files changed, 624 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/31163/1
diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c
index 0cea0ba..8844206 100644
--- a/src/drivers/intel/mipi_camera/camera.c
+++ b/src/drivers/intel/mipi_camera/camera.c
@@ -15,69 +15,599 @@
#include <arch/acpi.h>
#include <arch/acpi_device.h>
+#include <arch/acpi_pld.h>
#include <arch/acpigen.h>
#include <console/console.h>
#include <device/i2c_simple.h>
#include <device/device.h>
#include <device/path.h>
+#include <device/pci_def.h>
#include <string.h>
#include "chip.h"
+#define CIO2_PCI_DEV 0x14
+#define CIO2_PCI_FN 0x3
+
+/*
+ * This implementation assumes there is only 1 endpoint at each end of every
+ * data port. It also assumes there are no clock lanes. It also assumes
+ * that any VCM or NVM for a CAM is on the same I2C bus as the CAM.
+ */
+
+/*
+ * Adds settings for a CIO2 device (typically at "\_SB.PCI0.CIO2"). A _DSD is
+ * added that specifies a child table for each port (e.g., PRT0 for "port0"
+ * and PRT1 for "port1"). Each PRTx table specifies a table for each endpoint
+ * (though only 1 endpoint is supported by this implementation so the table
+ * only has an "endpoint0" that points to a EPx0 table). The EPx0 table
+ * primarily describes the # of lanes in "data-lines" and specifies the name
+ * of the other side in "remote-endpoint" (the name is usually of the form
+ * "\_SB.PCI0.I2Cx.CAM0" for the first port/cam and "\_SB.PCI0.I2Cx.CAM1"
+ * if there's a second port/cam).
+ */
+static void camera_fill_cio2(struct device *dev)
+{
+ struct drivers_intel_mipi_camera_config *config = dev->chip_info;
+ struct acpi_dp *dsd = acpi_dp_new_table("_DSD");
+ char *ep_table_name[MAX_PORT_ENTRIES] = {NULL};
+ char *port_table_name[MAX_PORT_ENTRIES] = {NULL};
+ char *port_name[MAX_PORT_ENTRIES] = {NULL};
+ uint32_t i = 0;
+ char name[BUS_PATH_MAX];
+
+ if (!dsd)
+ return;
+
+ for (i = 0; i < config->cio2_num_ports; ++i) {
+ struct acpi_dp *ep_table = NULL;
+ struct acpi_dp *port_table = NULL;
+ snprintf(name, sizeof(name), "EP%u0", i);
+ ep_table_name[i] = strdup(name);
+ if (!ep_table_name[i])
+ break;
+ ep_table = acpi_dp_new_table(ep_table_name[i]);
+ if (!ep_table)
+ break;
+ acpi_dp_add_integer(ep_table, "endpoint", 0);
+ acpi_dp_add_integer(ep_table, "clock-lanes", 0);
+ if (config->cio2_lanes_used[i] > 0) {
+ struct acpi_dp *lanes = acpi_dp_new_table("data-lanes");
+ if (lanes) {
+ uint32_t j;
+ for (j = 1; j <= config->cio2_lanes_used[i];
+ ++j) {
+ acpi_dp_add_integer(lanes, NULL, j);
+ }
+ acpi_dp_add_array(ep_table, lanes);
+ }
+ }
+ if (config->cio2_lane_endpoint[i]) {
+ struct acpi_dp *remote =
+ acpi_dp_new_table("remote-endpoint");
+ if (remote) {
+ acpi_dp_add_reference(remote, NULL,
+ config->cio2_lane_endpoint[i]);
+ acpi_dp_add_integer(remote, NULL, 0);
+ acpi_dp_add_integer(remote, NULL, 0);
+ acpi_dp_add_array(ep_table, remote);
+ }
+ }
+ snprintf(name, sizeof(name), "PRT%u", i);
+ port_table_name[i] = strdup(name);
+ if (!port_table_name[i]) {
+ // acpi_dp_free(ep_table);
+ break;
+ }
+ port_table = acpi_dp_new_table(port_table_name[i]);
+ if (!port_table) {
+ // acpi_dp_free(ep_table);
+ break;
+ }
+ acpi_dp_add_integer(port_table, "port", i);
+ acpi_dp_add_child(port_table, "endpoint0", ep_table);
+
+ snprintf(name, sizeof(name), "port%u", i);
+ port_name[i] = strdup(name);
+ if (!port_name[i]) {
+ // acpi_dp_free(port_table);
+ break;
+ }
+ acpi_dp_add_child(dsd, port_name[i], port_table);
+ }
+ acpi_dp_write(dsd);
+
+ for (i = 0; i < config->cio2_num_ports; ++i) {
+ free(ep_table_name[i]);
+ free(port_table_name[i]);
+ free(port_name[i]);
+ }
+}
+
+/*
+ * Adds settings for a camera sensor device (typically at
+ * "\_SB.PCI0.I2Cx.CAMy"). The drivers for Linux tends to expect the camera
+ * sensor device and any related nvram / vcm devices to be separate ACPI
+ * devices, while the drivers for Windows want all of these to be grouped
+ * together in the camera sensor ACPI device. This implementation tries to
+ * satisfy both, though the unfortunate tradeoff is that the same I2C address
+ * for nvram and vcm is advertised by multiple devices in ACPI (via "_CRS").
+ * The Windows driver can use the "_DSM" method to disambiguate the I2C
+ * resources in the camera sensor ACPI device. Drivers for Windows typically
+ * query "SSDB" for configuration information (represented as a binary blob
+ * dump of struct), while Linux drivers typically consult individual parameters
+ * in "_DSD".
+ *
+ * The tree of tables in "_DSD" is analogous to what's used for the "CIO2"
+ * device. The _DSD specifies a child table for the sensor's port (e.g., PRT0
+ * for "port0"--this implementation assumes a camera only has 1 port). The
+ * PRT0 table specifies a table for each endpoint (though only 1 endpoint is
+ * supported by this implementation so the table only has an "endpoint0" that
+ * points to a EP00 table). The EP00 table primarily describes the # of lanes
+ * in "data-lines", a list of frequencies in "list-frequencies", and specifies
+ * the name of the other side in "remote-endpoint" (typically "\_SB.PCI0.CIO2").
+ */
+static void camera_fill_sensor(struct device *dev)
+{
+ struct drivers_intel_mipi_camera_config *config = dev->chip_info;
+ struct acpi_dp *ep00 = NULL;
+ struct acpi_dp *prt0 = NULL;
+ struct acpi_dp *dsd = NULL;
+ uint16_t i2c_bus = dev->bus ? dev->bus->secondary : 0xFFFF;
+ uint16_t i2c_addr = dev->path.i2c.device;
+
+ if (config->use_pld && !config->disable_pld_defaults) {
+ if (!config->pld.ignore_color)
+ config->pld.ignore_color = 1;
+ if (!config->pld.visible)
+ config->pld.visible = 1;
+ if (!config->pld.vertical_offset)
+ config->pld.vertical_offset = 0xffff;
+ if (!config->pld.horizontal_offset)
+ config->pld.horizontal_offset = 0xffff;
+ /*
+ * PLD_PANEL_TOP has a value of zero, so the following
+ * will change any instance of PLD_PANEL_TOP to
+ * PLD_PANEL_FRONT unless disable_pld_defaults is set.
+ */
+ if (!config->pld.panel)
+ config->pld.panel = PLD_PANEL_FRONT;
+ /*
+ * PLD_HORIZONTAL_POSITION_LEFT has a value of zero, so
+ * the following will change any instance of that value
+ * to PLD_HORIZONTAL_POSITION_CENTER unless
+ * disable_pld_defaults is set.
+ */
+ if (!config->pld.horizontal_position) {
+ config->pld.horizontal_position =
+ PLD_HORIZONTAL_POSITION_CENTER;
+ }
+ /*
+ * The desired default for |vertical_position| is
+ * PLD_VERTICAL_POSITION_UPPER, which has a value of
+ * zero so no work is needed to set a default. The
+ * same applies for setting |shape| to PLD_SHAPE_ROUND.
+ */
+ }
+ if (config->use_pld)
+ acpigen_write_pld(&config->pld);
+
+ if (!config->disable_ssdb_defaults) {
+ if (!config->ssdb.bdf_value) {
+ config->ssdb.bdf_value = (CIO2_PCI_DEV << 3) |
+ CIO2_PCI_FN;
+ }
+ if (!config->ssdb.platform)
+ config->ssdb.platform = 9;
+ if (!config->ssdb.flash_support)
+ config->ssdb.flash_support = 2;
+ if (!config->ssdb.privacy_led)
+ config->ssdb.privacy_led = 1;
+ if (!config->ssdb.mipi_define)
+ config->ssdb.mipi_define = 1;
+ if (!config->ssdb.mclk_speed)
+ config->ssdb.mclk_speed = 19200000;
+ if (!config->ssdb.lanes_used) {
+ struct device *cio2 = pcidev_on_root(CIO2_PCI_DEV,
+ CIO2_PCI_FN);
+ struct drivers_intel_mipi_camera_config *cio2_config;
+ cio2_config = cio2 ? cio2->chip_info : NULL;
+ if (!cio2_config) {
+ printk(BIOS_ERR, "Failed to get CIO2 config\n");
+ } else if (cio2_config->device_type !=
+ INTEL_ACPI_CAMERA_CIO2) {
+ printk(BIOS_ERR, "Device type isn't CIO2: %u\n",
+ (u32)cio2_config->device_type);
+ } else if (config->ssdb.link_used >=
+ cio2_config->cio2_num_ports) {
+ printk(BIOS_ERR, "%u exceeds CIO2's %u links\n",
+ (u32)config->ssdb.link_used,
+ (u32)cio2_config->cio2_num_ports);
+ } else {
+ config->ssdb.lanes_used =
+ cio2_config->cio2_lanes_used[
+ config->ssdb.link_used];
+ }
+ }
+ }
+
+ /* Method (_DSM, 4, NotSerialized) */
+ acpigen_write_method("_DSM", 0x4);
+
+ /* ToBuffer (Arg0, Local0) */
+ acpigen_write_to_buffer(ARG0_OP, LOCAL0_OP);
+
+ /* If (LEqual (Local0, ToUUID(uuid))) */
+ acpigen_write_if();
+ acpigen_emit_byte(LEQUAL_OP);
+ acpigen_emit_byte(LOCAL0_OP);
+ acpigen_write_uuid("822ace8f-2814-4174-a56b-5f029fe079ee");
+ acpigen_write_return_string(config->sensor_name ?
+ config->sensor_name : "UNKNOWN");
+ acpigen_pop_len(); /* If */
+
+ /* If (LEqual (Local0, ToUUID(uuid))) */
+ acpigen_write_if();
+ acpigen_emit_byte(LEQUAL_OP);
+ acpigen_emit_byte(LOCAL0_OP);
+ acpigen_write_uuid("26257549-9271-4ca4-bb43-c4899d5a4881");
+ /* ToInteger (Arg2, Local1) */
+ acpigen_write_to_integer(ARG2_OP, LOCAL1_OP);
+
+ /* If (LEqual (Local1, 1)) */
+ acpigen_write_if_lequal_op_int(LOCAL1_OP, 1);
+ acpigen_write_return_integer((config->ssdb.vcm_type ? 1 : 0) +
+ (config->ssdb.rom_type ? 1 : 0) + 1);
+ acpigen_pop_len(); /* If Arg2=1 */
+
+ /* If (LEqual (Local1, 2)) */
+ acpigen_write_if_lequal_op_int(LOCAL1_OP, 2);
+ acpigen_write_return_integer(((uint32_t)i2c_bus) << 24 |
+ ((uint32_t)i2c_addr) << 8 |
+ 0x0); /* type 0 for sensor */
+ acpigen_pop_len(); /* If Arg2=2 */
+
+ if (config->ssdb.vcm_type) {
+ /* If (LEqual (Local1, 3)) */
+ acpigen_write_if_lequal_op_int(LOCAL1_OP, 3);
+ acpigen_write_return_integer(((uint32_t)i2c_bus) << 24 |
+ ((uint32_t)config->vcm_address)
+ << 8 |
+ 0x01); /* type 1 for vcm */
+ acpigen_pop_len(); /* If Arg2=3 */
+ }
+ if (config->ssdb.rom_type) {
+ /* If (LEqual (Local1, 3 or 4)) */
+ acpigen_write_if_lequal_op_int(LOCAL1_OP, 3 +
+ (config->ssdb.vcm_type ? 1 : 0));
+ acpigen_write_return_integer(((uint32_t)i2c_bus) << 24 |
+ ((uint32_t)config->rom_address)
+ << 8 |
+ 0x02); /* type 2 for rom */
+ acpigen_pop_len(); /* If Arg2=3 or 4 */
+ }
+
+ acpigen_pop_len(); /* If uuid */
+
+ /* Return (Buffer (One) { 0x0 }) */
+ acpigen_write_return_singleton_buffer(0x0);
+
+ acpigen_pop_len(); /* Method _DSM */
+
+ /* end of _dsm */
+
+ ep00 = acpi_dp_new_table("EP00");
+ if (ep00) {
+ struct acpi_dp *remote = NULL;
+ acpi_dp_add_integer(ep00, "endpoint", 0);
+ acpi_dp_add_integer(ep00, "clock-lanes", 0);
+ if (config->ssdb.lanes_used > 0) {
+ struct acpi_dp *lanes = acpi_dp_new_table("data-lanes");
+ if (lanes) {
+ uint32_t i;
+ for (i = 1; i <= config->ssdb.lanes_used; ++i)
+ acpi_dp_add_integer(lanes, NULL, i);
+ acpi_dp_add_array(ep00, lanes);
+ }
+ }
+ if (config->num_freq_entries > 0) {
+ struct acpi_dp *freq =
+ acpi_dp_new_table("link-frequencies");
+ if (freq) {
+ uint32_t i;
+ for (i = 0; i < config->num_freq_entries &&
+ i < MAX_LINK_FREQ_ENTRIES; ++i) {
+ acpi_dp_add_integer(freq, NULL,
+ config->link_freq[i]);
+ }
+ acpi_dp_add_array(ep00, freq);
+ }
+ }
+ remote = acpi_dp_new_table("remote-endpoint");
+ if (remote) {
+ const char *remote_name = NULL;
+ struct device *cio2 = NULL;
+ if (config->remote_name) {
+ remote_name = config->remote_name;
+ } else {
+ cio2 = pcidev_on_root(CIO2_PCI_DEV,
+ CIO2_PCI_FN);
+ if (cio2)
+ remote_name = acpi_device_path(cio2);
+ else
+ remote_name = "\\_SB.PCI0.CIO2";
+ }
+ acpi_dp_add_reference(remote, NULL, remote_name);
+ acpi_dp_add_integer(remote, NULL,
+ config->ssdb.link_used);
+ acpi_dp_add_integer(remote, NULL, 0); /* endpoint? */
+ acpi_dp_add_array(ep00, remote);
+ }
+ prt0 = acpi_dp_new_table("PRT0");
+ }
+ if (!prt0) {
+ // acpi_dp_free(ep00);
+ } else {
+ acpi_dp_add_integer(prt0, "port", 0);
+ acpi_dp_add_child(prt0, "endpoint0", ep00);
+ dsd = acpi_dp_new_table("_DSD");
+ }
+ if (!dsd) {
+ // acpi_dp_free(prt0);
+ } else {
+ const char *vcm_name = NULL;
+ acpi_dp_add_integer(dsd, "clock-frequency",
+ config->ssdb.mclk_speed);
+ if (config->ssdb.degree)
+ acpi_dp_add_integer(dsd, "rotation", 180);
+ if (config->ssdb.vcm_type) {
+ if (config->vcm_name) {
+ vcm_name = config->vcm_name;
+ } else {
+ const struct device_path path = {
+ .type = DEVICE_PATH_I2C,
+ .i2c.device = config->vcm_address,
+ };
+ struct device *vcm_dev = find_dev_path(dev->bus,
+ &path);
+ struct drivers_intel_mipi_camera_config *
+ vcm_config;
+ vcm_config = vcm_dev ? vcm_dev->chip_info :
+ NULL;
+ if (!vcm_config) {
+ printk(BIOS_ERR, "Failed to get VCM\n");
+ } else if (vcm_config->device_type !=
+ INTEL_ACPI_CAMERA_VCM) {
+ printk(BIOS_ERR, "Device isn't VCM\n");
+ } else {
+ vcm_name = acpi_device_path(vcm_dev);
+ }
+ }
+ }
+ if (vcm_name)
+ acpi_dp_add_reference(dsd, "lens-focus", vcm_name);
+ acpi_dp_add_child(dsd, "port0", prt0);
+ acpi_dp_write(dsd);
+ }
+
+ acpigen_write_method_serialized("SSDB", 0);
+ acpigen_write_return_byte_buffer((uint8_t *)&config->ssdb,
+ sizeof(config->ssdb));
+ acpigen_pop_len(); /* Method */
+
+ /* Fill Power Sequencing Data */
+ if (config->num_pwdb_entries > 0) {
+ acpigen_write_method_serialized("PWDB", 0);
+ acpigen_write_return_byte_buffer((uint8_t *)&config->pwdb,
+ sizeof(struct intel_pwdb) *
+ config->num_pwdb_entries);
+ acpigen_pop_len(); /* Method */
+ }
+}
+
+static void camera_fill_nvm(struct device *dev)
+{
+ struct drivers_intel_mipi_camera_config *config = dev->chip_info;
+ struct acpi_dp *dsd = acpi_dp_new_table("_DSD");
+ if (!dsd)
+ return;
+
+ /* It might be possible to default size or width based on type. */
+ if (!config->disable_nvm_defaults && !config->nvm_pagesize)
+ config->nvm_pagesize = 1;
+ if (!config->disable_nvm_defaults && !config->nvm_readonly)
+ config->nvm_readonly = 1;
+
+ if (config->nvm_size)
+ acpi_dp_add_integer(dsd, "size", config->nvm_size);
+ if (config->nvm_pagesize)
+ acpi_dp_add_integer(dsd, "pagesize", config->nvm_pagesize);
+ if (config->nvm_readonly)
+ acpi_dp_add_integer(dsd, "read-only", config->nvm_readonly);
+ if (config->nvm_width)
+ acpi_dp_add_integer(dsd, "address-width", config->nvm_width);
+ acpi_dp_write(dsd);
+}
+
+static void camera_fill_vcm(struct device *dev)
+{
+ struct drivers_intel_mipi_camera_config *config = dev->chip_info;
+ struct acpi_dp *dsd;
+
+ if (!config->vcm_compat)
+ return;
+
+ dsd = acpi_dp_new_table("_DSD");
+ if (!dsd)
+ return;
+ acpi_dp_add_string(dsd, "compatible", config->vcm_compat);
+ acpi_dp_write(dsd);
+}
+
static void camera_fill_ssdt(struct device *dev)
{
struct drivers_intel_mipi_camera_config *config = dev->chip_info;
const char *scope = acpi_device_scope(dev);
- struct acpi_i2c i2c = {
- .address = dev->path.i2c.device,
- .mode_10bit = dev->path.i2c.mode_10bit,
- .speed = I2C_SPEED_FAST,
- .resource = scope,
- };
if (!dev->enabled || !scope)
return;
/* Device */
- acpigen_write_scope(scope);
- acpigen_write_device(acpi_device_name(dev));
- acpigen_write_name_string("_HID", config->acpi_hid);
- acpigen_write_name_integer("_UID", config->acpi_uid);
- acpigen_write_name_string("_DDN", config->chip_name);
- acpigen_write_STA(acpi_device_status(dev));
+ if (config->device_type == INTEL_ACPI_CAMERA_CIO2 ||
+ config->device_type == INTEL_ACPI_CAMERA_IMGU) {
+ u32 address;
- /* Resources */
- acpigen_write_name("_CRS");
- acpigen_write_resourcetemplate_header();
- acpi_device_write_i2c(&i2c);
- acpigen_write_resourcetemplate_footer();
+ if (dev->path.type != DEVICE_PATH_PCI) {
+ printk(BIOS_ERR, "CIO2/IMGU devices require PCI\n");
+ return;
+ }
+ acpigen_write_scope(scope);
+ acpigen_write_device(acpi_device_name(dev));
+ address = PCI_SLOT(dev->path.pci.devfn) & 0xffff;
+ address <<= 16;
+ address |= PCI_FUNC(dev->path.pci.devfn) & 0xffff;
+ acpigen_write_name_dword("_ADR", address);
+ acpigen_write_name_string("_DDN",
+ config->device_type == INTEL_ACPI_CAMERA_CIO2 ?
+ "Camera and Imaging Subsystem" : "Imaging Unit");
+ } else {
+ struct acpi_i2c i2c = {
+ .address = dev->path.i2c.device,
+ .mode_10bit = dev->path.i2c.mode_10bit,
+ .speed = I2C_SPEED_FAST,
+ .resource = scope,
+ };
- /* Mark it as Camera related device */
- acpigen_write_name_integer("CAMD", config->device_type);
+ if (dev->path.type != DEVICE_PATH_I2C) {
+ printk(BIOS_ERR, "Non-CIO2/IMGU devices require I2C\n");
+ return;
+ }
- /* Create Device specific data */
- if (config->device_type == INTEL_ACPI_CAMERA_SENSOR) {
- acpigen_write_method_serialized("SSDB", 0);
- acpigen_write_return_byte_buffer((uint8_t *)&config->ssdb,
- sizeof(config->ssdb));
- acpigen_pop_len(); /* Method */
+ acpigen_write_scope(scope);
+ acpigen_write_device(acpi_device_name(dev));
+ if (config->device_type == INTEL_ACPI_CAMERA_SENSOR)
+ acpigen_write_name_integer("_ADR", 0);
+ if (config->acpi_hid)
+ acpigen_write_name_string("_HID", config->acpi_hid);
+ else if (config->device_type == INTEL_ACPI_CAMERA_VCM)
+ acpigen_write_name_string("_HID",
+ ACPI_DT_NAMESPACE_HID);
+ else if (config->device_type == INTEL_ACPI_CAMERA_NVM)
+ acpigen_write_name_string("_HID", "INT3499");
+ acpigen_write_name_integer("_UID", config->acpi_uid);
+ acpigen_write_name_string("_DDN", config->chip_name);
+ acpigen_write_STA(acpi_device_status(dev));
+
+ /* Resources */
+ acpigen_write_name("_CRS");
+ acpigen_write_resourcetemplate_header();
+ acpi_device_write_i2c(&i2c);
+ /*
+ * The optional vcm/nvram devices are presumed to be on the
+ * same I2C bus as the camera sensor.
+ */
+ if (config->device_type == INTEL_ACPI_CAMERA_SENSOR &&
+ config->ssdb.vcm_type) {
+ struct acpi_i2c i2c_vcm = i2c;
+ i2c_vcm.address = config->vcm_address;
+ acpi_device_write_i2c(&i2c_vcm);
+ }
+ if (config->device_type == INTEL_ACPI_CAMERA_SENSOR &&
+ config->ssdb.rom_type) {
+ struct acpi_i2c i2c_rom = i2c;
+ i2c_rom.address = config->rom_address;
+ acpi_device_write_i2c(&i2c_rom);
+ }
+ acpigen_write_resourcetemplate_footer();
}
- /* Fill Power Sequencing Data */
- acpigen_write_method_serialized("PWDB", 0);
- acpigen_write_return_byte_buffer((uint8_t *)&config->pwdb,
- (sizeof(struct intel_pwdb) * config->num_pwdb_entries));
- acpigen_pop_len(); /* Method */
+ /* Mark it as Camera related device */
+ if (config->device_type == INTEL_ACPI_CAMERA_CIO2 ||
+ config->device_type == INTEL_ACPI_CAMERA_IMGU ||
+ config->device_type == INTEL_ACPI_CAMERA_SENSOR ||
+ config->device_type == INTEL_ACPI_CAMERA_VCM) {
+ acpigen_write_name_integer("CAMD", config->device_type);
+ }
+
+ if (config->dep) {
+ acpigen_write_name("_DEP");
+ acpigen_write_package(1);
+ acpigen_emit_namestring(config->dep);
+ acpigen_pop_len();
+ }
+ if (config->pr0) {
+ acpigen_write_name("_PR0");
+ acpigen_write_package(1);
+ acpigen_emit_namestring(config->pr0);
+ acpigen_pop_len();
+ }
+ /* It's very unlikely you need _PR3 for any camera device */
+ if (config->pr3) {
+ acpigen_write_name("_PR3");
+ acpigen_write_package(1);
+ acpigen_emit_namestring(config->pr3);
+ acpigen_pop_len();
+ }
+
+ if (config->device_type == INTEL_ACPI_CAMERA_CIO2)
+ camera_fill_cio2(dev);
+ else if (config->device_type == INTEL_ACPI_CAMERA_SENSOR)
+ camera_fill_sensor(dev);
+ else if (config->device_type == INTEL_ACPI_CAMERA_NVM)
+ camera_fill_nvm(dev);
+ else if (config->device_type == INTEL_ACPI_CAMERA_VCM)
+ camera_fill_vcm(dev);
acpigen_pop_len(); /* Device */
acpigen_pop_len(); /* Scope */
- printk(BIOS_INFO, "%s: %s address 0%xh\n", acpi_device_path(dev),
- dev->chip_ops->name, dev->path.i2c.device);
+ if (dev->path.type == DEVICE_PATH_PCI) {
+ printk(BIOS_INFO, "%s: %s PCI address 0%x\n",
+ acpi_device_path(dev),
+ dev->chip_ops->name, dev->path.pci.devfn);
+ } else {
+ printk(BIOS_INFO, "%s: %s I2C address 0%xh\n",
+ acpi_device_path(dev),
+ dev->chip_ops->name, dev->path.i2c.device);
+ }
}
static const char *camera_acpi_name(const struct device *dev)
{
+ const char *prefix = NULL;
+ static char name[BUS_PATH_MAX];
struct drivers_intel_mipi_camera_config *config = dev->chip_info;
- return config->acpi_name;
+ if (config->acpi_name)
+ return config->acpi_name;
+ if (config->device_type == INTEL_ACPI_CAMERA_CIO2)
+ return "CIO2";
+ else if (config->device_type == INTEL_ACPI_CAMERA_IMGU)
+ return "IMGU";
+ else if (config->device_type == INTEL_ACPI_CAMERA_PMIC)
+ return "PMIC";
+
+ switch (config->device_type) {
+ case INTEL_ACPI_CAMERA_SENSOR:
+ prefix = "CAM";
+ break;
+ case INTEL_ACPI_CAMERA_VCM:
+ prefix = "VCM";
+ break;
+ case INTEL_ACPI_CAMERA_NVM:
+ prefix = "NVM";
+ break;
+ default:
+ prefix = "ERR"; /* Error */
+ break;
+ }
+ /*
+ * The cameras know which link # they use, so that's used
+ * as the basis for the instance #. The VCM and NVM don't
+ * have this information, so the best we can go on is the
+ * _UID.
+ */
+ snprintf(name, sizeof(name), "%s%u", prefix,
+ config->device_type == INTEL_ACPI_CAMERA_SENSOR ?
+ config->ssdb.link_used : config->acpi_uid);
+ return name;
}
static struct device_operations camera_ops = {
diff --git a/src/drivers/intel/mipi_camera/chip.h b/src/drivers/intel/mipi_camera/chip.h
index 741ae8e..50b757c 100644
--- a/src/drivers/intel/mipi_camera/chip.h
+++ b/src/drivers/intel/mipi_camera/chip.h
@@ -17,14 +17,19 @@
#define __INTEL_MIPI_CAMERA_CHIP_H__
#include <stdint.h>
+#include <arch/acpi_pld.h>
#define MAX_PWDB_ENTRIES 12
+#define MAX_PORT_ENTRIES 4
+#define MAX_LINK_FREQ_ENTRIES 4
enum intel_camera_device_type {
INTEL_ACPI_CAMERA_CIO2,
INTEL_ACPI_CAMERA_IMGU,
INTEL_ACPI_CAMERA_SENSOR,
INTEL_ACPI_CAMERA_VCM,
+ /* Value for NVM might might not be appropriate for CAMD */
+ INTEL_ACPI_CAMERA_NVM,
INTEL_ACPI_CAMERA_PMIC = 100,
};
@@ -77,12 +82,14 @@
uint8_t degree; /* Camera Orientation */
uint8_t mipi_define; /* MIPI info defined in ACPI or
sensor driver */
- uint32_t mclk; /* Clock info for sensor */
+ uint32_t mclk_speed; /* Clock info for sensor */
uint8_t control_logic_id; /* PMIC device node used for
the camera sensor */
uint8_t mipi_data_format; /* MIPI data format */
uint8_t silicon_version; /* Silicon version */
uint8_t customer_id; /* Customer ID */
+ uint8_t mclk_port;
+ uint8_t reserved[13];
} __packed;
struct intel_pwdb {
@@ -95,14 +102,59 @@
} __packed;
struct drivers_intel_mipi_camera_config {
+ /* Generic settings */
+ enum intel_camera_device_type device_type;
+
+ /* Settings that should not need to be set since defaults sane. */
+ const char *acpi_name; /* defaults: CIO2,IMGU,PMIC,CAMx,VCMx,NVMx */
+
+ /*
+ * General settings that can be used for any type (but doesn't
+ * necessarily need to be used/specified for each device.
+ */
+ const char *chip_name;
+ const char *acpi_hid; /* vcm and nvm have defaults */
+ unsigned int acpi_uid;
+ const char *dep;
+ const char *pr0;
+ const char *pr3; /* _PR3 shouldn't be needed */
+
+ /* Settings specific to CIO2 device */
+ uint32_t cio2_num_ports;
+ uint32_t cio2_lanes_used[MAX_PORT_ENTRIES];
+ const char *cio2_lane_endpoint[MAX_PORT_ENTRIES];
+
+ /* Settings specific to camera sensor */
+ bool disable_ssdb_defaults;
struct intel_ssdb ssdb;
struct intel_pwdb pwdb[MAX_PWDB_ENTRIES];
- enum intel_camera_device_type device_type;
uint8_t num_pwdb_entries;
- const char *acpi_hid;
- const char *acpi_name;
- const char *chip_name;
- unsigned int acpi_uid;
+ uint8_t num_freq_entries; /* # of elements in link_freq */
+ uint32_t link_freq[MAX_LINK_FREQ_ENTRIES];
+ const char *sensor_name; /* default "UNKNOWN" */
+ const char *remote_name; /* default "\_SB.PCI0.CIO2" */
+ const char *vcm_name; /* defaults to |vcm_address| device */
+ bool use_pld;
+ bool disable_pld_defaults;
+ struct acpi_pld pld;
+ uint16_t rom_address; /* I2C to use if ssdb.rom_type != 0 */
+ uint16_t vcm_address; /* I2C to use if ssdb.vcm_type != 0 */
+
+ /*
+ * Settings specific to nvram. Many values, if left as zero,
+ * will be assigned a default. Set disable_nvm_defaults to
+ * non-zero if you want to disable the defaulting behavior so
+ * you can use zero for a value.
+ */
+
+ bool disable_nvm_defaults;
+ uint32_t nvm_size;
+ uint32_t nvm_pagesize;
+ uint32_t nvm_readonly;
+ uint32_t nvm_width;
+
+ /* Settings specific to vcm */
+ const char *vcm_compat;
};
#endif
diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl
index 0001867..d923ba5 100644
--- a/src/mainboard/google/poppy/dsdt.asl
+++ b/src/mainboard/google/poppy/dsdt.asl
@@ -39,8 +39,10 @@
{
Device (PCI0)
{
- /* Image processing unit */
+#if !IS_ENABLED(CONFIG_DRIVERS_INTEL_MIPI_CAMERA)
+ /* Image processing unit, if not using MIPI driver */
#include <soc/intel/skylake/acpi/ipu.asl>
+#endif
#include <soc/intel/skylake/acpi/systemagent.asl>
#include <soc/intel/skylake/acpi/pch.asl>
}
--
To view, visit https://review.coreboot.org/c/coreboot/+/31163
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ie9d84519eae1333eeb67107281a2deafc24e8a08
Gerrit-Change-Number: 31163
Gerrit-PatchSet: 1
Gerrit-Owner: Matt Delco <delco(a)chromium.org>
Gerrit-Reviewer: Matt Delco <delco(a)chromium.org>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
3
4
Change in ...coreboot[master]: google_chromeec_command: makes the error status consistent
by YH Lin (Code Review) 20 Jun '20
by YH Lin (Code Review) 20 Jun '20
20 Jun '20
YH Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31626
Change subject: google_chromeec_command: makes the error status consistent
......................................................................
google_chromeec_command: makes the error status consistent
Currently various google_chromeec_command() implementation the error
can be returned differently (LPC: -1 for v3, 1 for v1, SPI: -1/1,
I2C: 1). This patch attempts to make it consistent across all
implementations by using only negative number as error.
All direct/indirect callers of google_chromeec_command() have also
been modified accordingly as well.
BRANCH=None
BUG=chromium:935038
Signed-off-by: YH Lin <yueherngl(a)google.com>
Change-Id: I39f12502bc6982670dd200dcef0724e7eed2ed29
---
M src/ec/google/chromeec/crosec_proto.c
M src/ec/google/chromeec/ec.c
M src/ec/google/chromeec/ec.h
M src/ec/google/chromeec/ec_i2c.c
M src/ec/google/chromeec/ec_lpc.c
M src/ec/google/chromeec/smihandler.c
M src/ec/google/chromeec/vboot_storage.c
M src/ec/google/chromeec/vstore.c
M src/mainboard/google/gru/mainboard.c
M src/security/vboot/vboot_logic.c
10 files changed, 35 insertions(+), 31 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/31626/1
diff --git a/src/ec/google/chromeec/crosec_proto.c b/src/ec/google/chromeec/crosec_proto.c
index 2043347..603f1df 100644
--- a/src/ec/google/chromeec/crosec_proto.c
+++ b/src/ec/google/chromeec/crosec_proto.c
@@ -246,7 +246,7 @@
int rv = send_command_proto3(cec_command, crosec_io, context);
if (rv < 0) {
cec_command->cmd_code = rv;
- return 1;
+ return -1;
}
return 0;
}
diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index 09357b0..897dceb 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -363,7 +363,7 @@
cmd.cmd_size_out = sizeof(rsp);
cmd.cmd_dev_index = 0;
- if (google_chromeec_command(&cmd) == 0)
+ if (google_chromeec_command(&cmd) >= 0)
return rsp.event_mask;
return 0;
}
@@ -404,7 +404,7 @@
cmd.cmd_size_out = sizeof(rsp);
cmd.cmd_dev_index = 0;
- if (google_chromeec_command(&cmd) == 0)
+ if (google_chromeec_command(&cmd) >= 0)
return rsp.event_mask;
return 0;
}
@@ -507,7 +507,7 @@
cmd.cmd_size_out = sizeof(r);
cmd.cmd_dev_index = 0;
- if (google_chromeec_command(&cmd) != 0)
+ if (google_chromeec_command(&cmd) < 0)
return -1;
if (feature >= 8 * sizeof(r.flags))
@@ -531,7 +531,7 @@
cmd.cmd_size_out = 0;
cmd.cmd_dev_index = 0;
- if (google_chromeec_command(&cmd) != 0)
+ if (google_chromeec_command(&cmd) < 0)
return -1;
return 0;
@@ -550,7 +550,7 @@
cmd.cmd_size_out = sizeof(r);
cmd.cmd_dev_index = 0;
- if (google_chromeec_command(&cmd) != 0)
+ if (google_chromeec_command(&cmd) < 0)
return -1;
return rtc_to_tm(r.time, time);
@@ -658,7 +658,7 @@
cmd.cmd_data_out = &board_v;
cmd.cmd_dev_index = 0;
- if (google_chromeec_command(&cmd))
+ if (google_chromeec_command(&cmd) < 0)
return -1;
*version = board_v.board_version;
@@ -677,7 +677,7 @@
cmd.cmd_data_out = &sku_v;
cmd.cmd_dev_index = 0;
- if (google_chromeec_command(&cmd) != 0)
+ if (google_chromeec_command(&cmd) < 0)
return 0;
return sku_v.sku_id;
@@ -708,7 +708,7 @@
if (!is_read)
memcpy(&cmd_vbnvcontext.block, data, EC_VBNV_BLOCK_SIZE);
- if (google_chromeec_command(&cec_cmd)) {
+ if (google_chromeec_command(&cec_cmd) < 0) {
printk(BIOS_ERR, "ERROR: failed to %s vbnv_ec context: %d\n",
is_read ? "read" : "write", (int)cec_cmd.cmd_code);
mdelay(10); /* just in case */
@@ -792,7 +792,7 @@
cmd.cmd_size_out = sizeof(*r) + read_len;
cmd.cmd_dev_index = 0;
rv = google_chromeec_command(&cmd);
- if (rv != 0)
+ if (rv < 0)
return rv;
/* Parse response */
@@ -875,7 +875,7 @@
};
struct usb_chg_measures m;
int rv = google_chromeec_command(&cmd);
- if (rv != 0)
+ if (rv < 0)
return rv;
/* values are given in milliAmps and milliVolts */
*type = rsp.type;
diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
index 7a38336..51124f6 100644
--- a/src/ec/google/chromeec/ec.h
+++ b/src/ec/google/chromeec/ec.h
@@ -108,7 +108,7 @@
*
* @param type charger type
* @param max_watts charger max wattage
- * @return non-zero for error, otherwise 0.
+ * @return 0 on success or negative integer for errors.
*/
int google_chromeec_get_usb_pd_power_info(enum usb_chg_type *type,
u32 *max_watts);
@@ -118,7 +118,7 @@
*
* @param current_lim Max current in mA
* @param voltage_lim Max voltage in mV
- * @return non-zero for error, otherwise 0.
+ * @return 0 on success or negative integer for errors.
*/
int google_chromeec_override_dedicated_charger_limit(u16 current_lim,
u16 voltage_lim);
@@ -150,6 +150,8 @@
* The lower level transport works on the buffers handed out to the
* upper level. Therefore, only the size of the request and response
* are required.
+ *
+ * @return 0 on success or negative integer for errors.
*/
typedef int (*crosec_io_t)(size_t req_size, size_t resp_size, void *context);
int crosec_command_proto(struct chromeec_command *cec_command,
@@ -159,7 +161,7 @@
* Send a command to a CrOS EC
*
* @param cec_command: CrOS EC command to send
- * @return 0 for success. Non-zero for error.
+ * @return 0 on success or negative integer for errors.
*/
int google_chromeec_command(struct chromeec_command *cec_command);
diff --git a/src/ec/google/chromeec/ec_i2c.c b/src/ec/google/chromeec/ec_i2c.c
index 22b491a..7f2ead5 100644
--- a/src/ec/google/chromeec/ec_i2c.c
+++ b/src/ec/google/chromeec/ec_i2c.c
@@ -205,7 +205,7 @@
__func__, cec_command->cmd_size_in,
cec_command->cmd_size_out);
cec_command->cmd_code = EC_RES_INVALID_PARAM;
- return 1;
+ return -1;
}
/* Construct command. */
@@ -221,13 +221,13 @@
printk(BIOS_ERR, "%s: Cannot complete write to i2c-%d:%#x\n",
__func__, bus, chip);
cec_command->cmd_code = EC_RES_ERROR;
- return 1;
+ return -1;
}
if (i2c_read_raw(bus, chip, (uint8_t *)&resp, size_i2c_resp) != 0) {
printk(BIOS_ERR, "%s: Cannot complete read from i2c-%d:%#x\n",
__func__, bus, chip);
cec_command->cmd_code = EC_RES_ERROR;
- return 1;
+ return -1;
}
/* Verify and return response */
@@ -235,17 +235,17 @@
if (resp.response != EC_RES_SUCCESS) {
printk(BIOS_DEBUG, "%s: Received bad result code %d\n",
__func__, (int)resp.response);
- return 1;
+ return -1;
}
if (resp.length > cec_command->cmd_size_out) {
printk(BIOS_ERR, "%s: Received len %#02x too large\n",
__func__, (int)resp.length);
cec_command->cmd_code = EC_RES_INVALID_RESPONSE;
- return 1;
+ return -1;
}
if (!ec_verify_checksum(&resp)) {
cec_command->cmd_code = EC_RES_INVALID_CHECKSUM;
- return 1;
+ return -1;
}
cec_command->cmd_size_out = resp.length;
memcpy(cec_command->cmd_data_out, resp.data, resp.length);
diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c
index 61005d3..097b1b4 100644
--- a/src/ec/google/chromeec/ec_lpc.c
+++ b/src/ec/google/chromeec/ec_lpc.c
@@ -330,13 +330,13 @@
if (google_chromeec_wait_ready(EC_LPC_ADDR_HOST_CMD)) {
printk(BIOS_ERR, "Timeout waiting for EC process command %d!\n",
cec_command->cmd_code);
- return 1;
+ return -1;
}
/* Check result */
cec_command->cmd_code = read_byte(EC_LPC_ADDR_HOST_DATA);
if (cec_command->cmd_code)
- return 1;
+ return -1;
/* Read back args */
read_bytes(EC_LPC_ADDR_HOST_ARGS, sizeof(args), (u8*)&args, NULL);
@@ -348,12 +348,12 @@
*/
if (!(args.flags & EC_HOST_ARGS_FLAG_TO_HOST)) {
printk(BIOS_ERR, "EC protocol mismatch\n");
- return 1;
+ return -1;
}
if (args.data_size > cec_command->cmd_size_out) {
printk(BIOS_ERR, "EC returned too much data\n");
- return 1;
+ return -1;
}
cec_command->cmd_size_out = args.data_size;
@@ -369,7 +369,7 @@
/* Verify checksum */
if (args.checksum != csum) {
printk(BIOS_ERR, "EC response has invalid checksum\n");
- return 1;
+ return -1;
}
return 0;
diff --git a/src/ec/google/chromeec/smihandler.c b/src/ec/google/chromeec/smihandler.c
index cab7192..3f703f9 100644
--- a/src/ec/google/chromeec/smihandler.c
+++ b/src/ec/google/chromeec/smihandler.c
@@ -54,7 +54,7 @@
;
printk(BIOS_DEBUG,"Clearing pending EC events. Error code 1 is expected.\n");
- while (google_chromeec_get_mkbp_event(&mkbp_event) == 0)
+ while (google_chromeec_get_mkbp_event(&mkbp_event) >= 0)
;
}
diff --git a/src/ec/google/chromeec/vboot_storage.c b/src/ec/google/chromeec/vboot_storage.c
index f47c2f1..08af2f6 100644
--- a/src/ec/google/chromeec/vboot_storage.c
+++ b/src/ec/google/chromeec/vboot_storage.c
@@ -30,7 +30,7 @@
/* Ensure the digests being saved match the EC's slot size. */
assert(digest_size == EC_VSTORE_SLOT_SIZE);
- if (google_chromeec_vstore_write(slot, digest, digest_size))
+ if (google_chromeec_vstore_write(slot, digest, digest_size) < 0)
return -1;
/* Assert the slot is locked on successful write. */
diff --git a/src/ec/google/chromeec/vstore.c b/src/ec/google/chromeec/vstore.c
index 28c2603..39e59f8 100644
--- a/src/ec/google/chromeec/vstore.c
+++ b/src/ec/google/chromeec/vstore.c
@@ -42,7 +42,7 @@
.cmd_data_out = &info,
};
- if (google_chromeec_command(&cmd) != 0)
+ if (google_chromeec_command(&cmd) < 0)
return 0;
if (locked)
diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c
index 41307c7..245a70e 100644
--- a/src/mainboard/google/gru/mainboard.c
+++ b/src/mainboard/google/gru/mainboard.c
@@ -257,12 +257,14 @@
static void usb_power_cycle(int port)
{
- if (google_chromeec_set_usb_pd_role(port, USB_PD_CTRL_ROLE_FORCE_SINK))
+ if (google_chromeec_set_usb_pd_role(port, USB_PD_CTRL_ROLE_FORCE_SINK)
+ < 0)
printk(BIOS_ERR, "ERROR: Cannot force USB%d PD sink\n", port);
mdelay(10); /* Make sure USB stick is fully depowered. */
- if (google_chromeec_set_usb_pd_role(port, USB_PD_CTRL_ROLE_TOGGLE_ON))
+ if (google_chromeec_set_usb_pd_role(port, USB_PD_CTRL_ROLE_TOGGLE_ON)
+ < 0)
printk(BIOS_ERR, "ERROR: Cannot restore USB%d PD mode\n", port);
}
diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c
index 00bbae6..c379463 100644
--- a/src/security/vboot/vboot_logic.c
+++ b/src/security/vboot/vboot_logic.c
@@ -141,7 +141,7 @@
printk(BIOS_DEBUG, "Platform is resuming.\n");
- if (vboot_retrieve_hash(saved_hash, saved_hash_sz)) {
+ if (vboot_retrieve_hash(saved_hash, saved_hash_sz) < 0) {
printk(BIOS_ERR, "Couldn't retrieve saved hash.\n");
return -1;
}
--
To view, visit https://review.coreboot.org/c/coreboot/+/31626
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I39f12502bc6982670dd200dcef0724e7eed2ed29
Gerrit-Change-Number: 31626
Gerrit-PatchSet: 1
Gerrit-Owner: YH Lin <yueherngl(a)google.com>
Gerrit-MessageType: newchange
3
7
Change in ...coreboot[master]: src/mainboard: Add dell/inspiron_n5110
by Angel Pons (Code Review) 23 May '20
by Angel Pons (Code Review) 23 May '20
23 May '20
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30996
Change subject: src/mainboard: Add dell/inspiron_n5110
......................................................................
src/mainboard: Add dell/inspiron_n5110
Run autoport and clean up. It has Nvidia Optimus, a NPCE795 EC, a PCIe
xHCI controller and who knows what else. The 4MB flash is shared with
the EC, apparently.
Change-Id: I0a7dba0e4e7e80c51c5f5c0e8a2f1a2ac23451b9
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
A src/mainboard/dell/Kconfig
A src/mainboard/dell/Kconfig.name
A src/mainboard/dell/inspiron_n5110/Kconfig
A src/mainboard/dell/inspiron_n5110/Kconfig.name
A src/mainboard/dell/inspiron_n5110/Makefile.inc
A src/mainboard/dell/inspiron_n5110/acpi/ec.asl
A src/mainboard/dell/inspiron_n5110/acpi/platform.asl
A src/mainboard/dell/inspiron_n5110/acpi/superio.asl
A src/mainboard/dell/inspiron_n5110/acpi_tables.c
A src/mainboard/dell/inspiron_n5110/board_info.txt
A src/mainboard/dell/inspiron_n5110/devicetree.cb
A src/mainboard/dell/inspiron_n5110/dsdt.asl
A src/mainboard/dell/inspiron_n5110/gma-mainboard.ads
A src/mainboard/dell/inspiron_n5110/gpio.c
A src/mainboard/dell/inspiron_n5110/hda_verb.c
A src/mainboard/dell/inspiron_n5110/mainboard.c
A src/mainboard/dell/inspiron_n5110/romstage.c
17 files changed, 685 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/30996/1
diff --git a/src/mainboard/dell/Kconfig b/src/mainboard/dell/Kconfig
new file mode 100644
index 0000000..298c62b
--- /dev/null
+++ b/src/mainboard/dell/Kconfig
@@ -0,0 +1,16 @@
+if VENDOR_DELL
+
+choice
+ prompt "Mainboard model"
+
+source "src/mainboard/dell/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/dell/*/Kconfig"
+
+config MAINBOARD_VENDOR
+ string
+ default "Dell Inc."
+
+endif # VENDOR_DELL
diff --git a/src/mainboard/dell/Kconfig.name b/src/mainboard/dell/Kconfig.name
new file mode 100644
index 0000000..3d2fefd
--- /dev/null
+++ b/src/mainboard/dell/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_DELL
+ bool "Dell Inc."
diff --git a/src/mainboard/dell/inspiron_n5110/Kconfig b/src/mainboard/dell/inspiron_n5110/Kconfig
new file mode 100644
index 0000000..1a12055
--- /dev/null
+++ b/src/mainboard/dell/inspiron_n5110/Kconfig
@@ -0,0 +1,54 @@
+if BOARD_DELL_INSPIRON_N5110
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_4096
+ select CPU_INTEL_SOCKET_RPGA989
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_INT15
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select GFX_GMA_INTERNAL_IS_LVDS
+ select SERIRQ_CONTINUOUS_MODE
+ select NO_UART_ON_SUPERIO
+ select SOUTHBRIDGE_INTEL_BD82X6X
+ select SYSTEM_TYPE_LAPTOP
+ select USE_NATIVE_RAMINIT
+ select MAINBOARD_HAS_LIBGFXINIT
+
+config MAINBOARD_DIR
+ string
+ default dell/inspiron_n5110
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Inspiron N5110"
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0116.rom"
+
+config VGA_BIOS_ID
+ string
+ default "8086,0116"
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ default 0x4b0
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x1028
+
+config DRAM_RESET_GATE_GPIO # FIXME: check this
+ int
+ default 60
+
+config MAX_CPUS
+ int
+ default 8
+
+config USBDEBUG_HCD_INDEX # FIXME: check this
+ int
+ default 2
+endif
diff --git a/src/mainboard/dell/inspiron_n5110/Kconfig.name b/src/mainboard/dell/inspiron_n5110/Kconfig.name
new file mode 100644
index 0000000..06334cd
--- /dev/null
+++ b/src/mainboard/dell/inspiron_n5110/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_DELL_INSPIRON_N5110
+ bool "Inspiron N5110"
diff --git a/src/mainboard/dell/inspiron_n5110/Makefile.inc b/src/mainboard/dell/inspiron_n5110/Makefile.inc
new file mode 100644
index 0000000..ea035d3
--- /dev/null
+++ b/src/mainboard/dell/inspiron_n5110/Makefile.inc
@@ -0,0 +1,3 @@
+romstage-y += gpio.c
+
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/dell/inspiron_n5110/acpi/ec.asl b/src/mainboard/dell/inspiron_n5110/acpi/ec.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/dell/inspiron_n5110/acpi/ec.asl
diff --git a/src/mainboard/dell/inspiron_n5110/acpi/platform.asl b/src/mainboard/dell/inspiron_n5110/acpi/platform.asl
new file mode 100644
index 0000000..cf5d74f
--- /dev/null
+++ b/src/mainboard/dell/inspiron_n5110/acpi/platform.asl
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Method(_WAK,1)
+{
+ Return(Package(){0,0})
+}
+
+Method(_PTS,1)
+{
+}
diff --git a/src/mainboard/dell/inspiron_n5110/acpi/superio.asl b/src/mainboard/dell/inspiron_n5110/acpi/superio.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/dell/inspiron_n5110/acpi/superio.asl
diff --git a/src/mainboard/dell/inspiron_n5110/acpi_tables.c b/src/mainboard/dell/inspiron_n5110/acpi_tables.c
new file mode 100644
index 0000000..7d634a0
--- /dev/null
+++ b/src/mainboard/dell/inspiron_n5110/acpi_tables.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/nvs.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ // the lid is open by default.
+ gnvs->lids = 1;
+
+ gnvs->tcrt = 100;
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/dell/inspiron_n5110/board_info.txt b/src/mainboard/dell/inspiron_n5110/board_info.txt
new file mode 100644
index 0000000..f48c92b
--- /dev/null
+++ b/src/mainboard/dell/inspiron_n5110/board_info.txt
@@ -0,0 +1,6 @@
+Category: laptop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: n
+Release year: 2011
diff --git a/src/mainboard/dell/inspiron_n5110/devicetree.cb b/src/mainboard/dell/inspiron_n5110/devicetree.cb
new file mode 100644
index 0000000..be4f590
--- /dev/null
+++ b/src/mainboard/dell/inspiron_n5110/devicetree.cb
@@ -0,0 +1,73 @@
+chip northbridge/intel/sandybridge
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
+ register "gfx.link_frequency_270_mhz" = "1"
+ register "gfx.ndid" = "3"
+ register "gfx.use_spread_spectrum_clock" = "1"
+ register "gpu_cpu_backlight" = "0x0000035e"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "gpu_panel_port_select" = "0"
+ register "gpu_panel_power_backlight_off_delay" = "3000"
+ register "gpu_panel_power_backlight_on_delay" = "3000"
+ register "gpu_panel_power_cycle_delay" = "6"
+ register "gpu_panel_power_down_delay" = "300"
+ register "gpu_panel_power_up_delay" = "300"
+ register "gpu_pch_backlight" = "0x13121312"
+ device cpu_cluster 0x0 on
+ chip cpu/intel/socket_rPGA989
+ device lapic 0x0 on
+ end
+ end
+ chip cpu/intel/model_206ax
+ register "c1_acpower" = "1"
+ register "c1_battery" = "1"
+ register "c2_acpower" = "3"
+ register "c2_battery" = "3"
+ register "c3_acpower" = "5"
+ register "c3_battery" = "5"
+ device lapic 0xacac off
+ end
+ end
+ end
+ device domain 0x0 on
+ subsystemid 0x1028 0x04b0 inherit
+ device pci 00.0 on end # Host bridge Host bridge
+ device pci 01.0 on end # PCIe Bridge for discrete graphics
+ device pci 02.0 on end # Internal graphics VGA controller
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "c2_latency" = "0x0065"
+ register "docking_supported" = "1"
+ register "gen2_dec" = "0x0004006d"
+ register "p_cnt_throttling_supported" = "0"
+ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 1 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x21"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 19.0 off end # Intel Gigabit Ethernet
+ device pci 1a.0 on end # USB2 EHCI #2
+ device pci 1b.0 on end # High Definition Audio Audio controller
+ device pci 1c.0 on end # PCIe Port #1
+ device pci 1c.1 on end # PCIe Port #2
+ device pci 1c.2 off end # PCIe Port #3
+ device pci 1c.3 on end # PCIe Port #4
+ device pci 1c.4 on end # PCIe Port #5
+ device pci 1c.5 off end # PCIe Port #6
+ device pci 1c.6 off end # PCIe Port #7
+ device pci 1c.7 on end # PCIe Port #8
+ device pci 1d.0 on end # USB2 EHCI #1
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on end # LPC bridge PCI-LPC bridge
+ device pci 1f.2 on end # SATA Controller 1
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # SATA Controller 2
+ device pci 1f.6 off end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/dell/inspiron_n5110/dsdt.asl b/src/mainboard/dell/inspiron_n5110/dsdt.asl
new file mode 100644
index 0000000..1b0cae2
--- /dev/null
+++ b/src/mainboard/dell/inspiron_n5110/dsdt.asl
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
+
+#include <arch/acpi.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x03, // DSDT revision: ACPI v3.0
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 // OEM revision
+)
+{
+ #include "acpi/platform.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/bd82x6x/acpi/platform.asl>
+
+ /* global NVS and variables. */
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/dell/inspiron_n5110/gma-mainboard.ads b/src/mainboard/dell/inspiron_n5110/gma-mainboard.ads
new file mode 100644
index 0000000..d4a5d7d
--- /dev/null
+++ b/src/mainboard/dell/inspiron_n5110/gma-mainboard.ads
@@ -0,0 +1,34 @@
+--
+-- This file is part of the coreboot project.
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (DP1,
+ DP2,
+ DP3,
+ HDMI1,
+ HDMI2,
+ HDMI3,
+ Analog,
+ Internal,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/dell/inspiron_n5110/gpio.c b/src/mainboard/dell/inspiron_n5110/gpio.c
new file mode 100644
index 0000000..7926ee1
--- /dev/null
+++ b/src/mainboard/dell/inspiron_n5110/gpio.c
@@ -0,0 +1,231 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_NATIVE,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_GPIO,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_NATIVE,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_GPIO,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_GPIO,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio11 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_OUTPUT,
+ .gpio20 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_OUTPUT,
+ .gpio23 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_OUTPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio12 = GPIO_LEVEL_LOW,
+ .gpio19 = GPIO_LEVEL_LOW,
+ .gpio22 = GPIO_LEVEL_LOW,
+ .gpio24 = GPIO_LEVEL_HIGH,
+ .gpio27 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_LOW,
+ .gpio29 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio30 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio1 = GPIO_INVERT,
+ .gpio3 = GPIO_INVERT,
+ .gpio4 = GPIO_INVERT,
+ .gpio7 = GPIO_INVERT,
+ .gpio11 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+ .gpio15 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_GPIO,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_GPIO,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_GPIO,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_OUTPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio44 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_INPUT,
+ .gpio46 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio50 = GPIO_DIR_OUTPUT,
+ .gpio51 = GPIO_DIR_OUTPUT,
+ .gpio52 = GPIO_DIR_OUTPUT,
+ .gpio53 = GPIO_DIR_OUTPUT,
+ .gpio54 = GPIO_DIR_OUTPUT,
+ .gpio57 = GPIO_DIR_OUTPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio33 = GPIO_LEVEL_LOW,
+ .gpio34 = GPIO_LEVEL_LOW,
+ .gpio37 = GPIO_LEVEL_LOW,
+ .gpio50 = GPIO_LEVEL_HIGH,
+ .gpio51 = GPIO_LEVEL_LOW,
+ .gpio52 = GPIO_LEVEL_HIGH,
+ .gpio53 = GPIO_LEVEL_HIGH,
+ .gpio54 = GPIO_LEVEL_LOW,
+ .gpio57 = GPIO_LEVEL_LOW,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_GPIO,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_NATIVE,
+ .gpio71 = GPIO_MODE_NATIVE,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_GPIO,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio67 = GPIO_DIR_INPUT,
+ .gpio68 = GPIO_DIR_OUTPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio74 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+ .gpio68 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/dell/inspiron_n5110/hda_verb.c b/src/mainboard/dell/inspiron_n5110/hda_verb.c
new file mode 100644
index 0000000..a70733b
--- /dev/null
+++ b/src/mainboard/dell/inspiron_n5110/hda_verb.c
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x111d76d1, /* Codec Vendor / Device ID: IDT */
+ 0x102804b0, /* Subsystem ID */
+
+ 0x00000007, /* Number of 4 dword sets */
+ /* NID 0x01: Subsystem ID. */
+ AZALIA_SUBVENDOR(0x0, 0x102804b0),
+
+ /* NID 0x0a. */
+ AZALIA_PIN_CFG(0x0, 0x0a, 0x04a11020),
+
+ /* NID 0x0b. */
+ AZALIA_PIN_CFG(0x0, 0x0b, 0x0421101f),
+
+ /* NID 0x0c. */
+ AZALIA_PIN_CFG(0x0, 0x0c, 0x400000f0),
+
+ /* NID 0x0d. */
+ AZALIA_PIN_CFG(0x0, 0x0d, 0x90170110),
+
+ /* NID 0x0f. */
+ AZALIA_PIN_CFG(0x0, 0x0f, 0x400000f2),
+
+ /* NID 0x11. */
+ AZALIA_PIN_CFG(0x0, 0x11, 0xd5a30160),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/inspiron_n5110/mainboard.c b/src/mainboard/dell/inspiron_n5110/mainboard.c
new file mode 100644
index 0000000..02fe3a5
--- /dev/null
+++ b/src/mainboard/dell/inspiron_n5110/mainboard.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+static void mainboard_enable(struct device *dev)
+{
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/dell/inspiron_n5110/romstage.c b/src/mainboard/dell/inspiron_n5110/romstage.c
new file mode 100644
index 0000000..fd2f79f
--- /dev/null
+++ b/src/mainboard/dell/inspiron_n5110/romstage.c
@@ -0,0 +1,80 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <lib.h>
+#include <timestamp.h>
+#include <arch/byteorder.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <arch/acpi.h>
+#include <console/console.h>
+#include "northbridge/intel/sandybridge/sandybridge.h"
+#include "northbridge/intel/sandybridge/raminit_native.h"
+#include "southbridge/intel/bd82x6x/pch.h"
+#include <southbridge/intel/common/gpio.h>
+#include <arch/cpu.h>
+#include <cpu/x86/msr.h>
+
+void pch_enable_lpc(void)
+{
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3c00);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00000000);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x0004006d);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00000000);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
+}
+
+void mainboard_rcba_config(void)
+{
+}
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 1, 0 },
+ { 1, 1, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 1 },
+ { 1, 0, 2 },
+ { 1, 0, 2 },
+ { 1, 0, 3 },
+ { 1, 0, 3 },
+ { 1, 1, 4 },
+ { 1, 1, 4 },
+ { 1, 0, 5 },
+ { 1, 0, 5 },
+ { 1, 0, 6 },
+ { 1, 0, 6 },
+};
+
+void mainboard_early_init(int s3resume)
+{
+}
+
+void mainboard_config_superio(void)
+{
+}
+
+/* FIXME: Assumed completely. */
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[2], 0x52, id_only);
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0a7dba0e4e7e80c51c5f5c0e8a2f1a2ac23451b9
Gerrit-Change-Number: 30996
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-MessageType: newchange
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