Change in ...coreboot[master]: [WIP] soc/amd/common: Use static allocation for params
by Kyösti Mälkki (Code Review)
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31489
Change subject: [WIP] soc/amd/common: Use static allocation for params
......................................................................
[WIP] soc/amd/common: Use static allocation for params
Lifetime of the structure is the duration of call to
AGESA. There is no need to allocate and release these
from AGESA's internal heap for every single call.
Change-Id: Ibef6ca8481f926d4e18e1aef5136e69f5834feb1
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/soc/amd/common/block/pi/agesawrapper.c
1 file changed, 22 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/31489/1
diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c
index 821535d..e769a45 100644
--- a/src/soc/amd/common/block/pi/agesawrapper.c
+++ b/src/soc/amd/common/block/pi/agesawrapper.c
@@ -410,6 +410,26 @@
}
+union AMD_MAX_ALLOC_PARAMS {
+ AMD_INTERFACE_PARAMS p1;
+ AMD_RESET_PARAMS p2;
+ AMD_EARLY_PARAMS p3;
+ AMD_POST_PARAMS p4;
+ AMD_RESUME_PARAMS p5;
+ AMD_ENV_PARAMS p6;
+ AMD_MID_PARAMS p7;
+ AMD_LATE_PARAMS p8;
+#if 1
+ AMD_RTB_PARAMS p9;
+#else
+ AMD_S3SAVE_PARAMS p10;
+#endif
+ AMD_S3LATE_PARAMS p11;
+ AMD_S3FINAL_PARAMS p12;
+};
+
+static union AMD_MAX_ALLOC_PARAMS sp;
+
AGESA_STATUS agesa_execute_state(AGESA_STRUCT_NAME func)
{
AGESA_STATUS status = AGESA_UNSUPPORTED;
@@ -417,19 +437,9 @@
AMD_CONFIG_PARAMS *StdHeader = &template;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_INTERFACE_PARAMS *aip = &AmdParamStruct;
- union {
- AMD_RESET_PARAMS ResetParams;
- AMD_S3LATE_PARAMS S3LateParams;
- AMD_S3FINAL_PARAMS S3FinalParams;
- } sp;
- if ((func == AMD_INIT_RESET) || (func == AMD_S3LATE_RESTORE) ||
- (func == AMD_S3FINAL_RESTORE)) {
- memset(&sp, 0, sizeof(sp));
- amd_create_struct(aip, func, &sp, sizeof(sp));
- } else {
- amd_create_struct(aip, func, NULL, 0);
- }
+ memset(&sp, 0, sizeof(sp));
+ amd_create_struct(aip, func, &sp, sizeof(sp));
StdHeader = aip->NewStructPtr;
StdHeader->Func = func;
--
To view, visit https://review.coreboot.org/c/coreboot/+/31489
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ibef6ca8481f926d4e18e1aef5136e69f5834feb1
Gerrit-Change-Number: 31489
Gerrit-PatchSet: 1
Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-MessageType: newchange
2 months, 1 week
- 2
- 6
Change in ...coreboot[master]: device/hypertransport: Drop dev_find_slot() debugging
by Kyösti Mälkki (Code Review)
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30704
Change subject: device/hypertransport: Drop dev_find_slot() debugging
......................................................................
device/hypertransport: Drop dev_find_slot() debugging
Change-Id: I810ca9cfc72de9ea532d53cabdaf8845be837432
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/device/device.c
M src/device/device_const.c
M src/include/device/device.h
3 files changed, 5 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/30704/1
diff --git a/src/device/device.c b/src/device/device.c
index 20a4077..7836af1 100644
--- a/src/device/device.c
+++ b/src/device/device.c
@@ -1253,7 +1253,4 @@
final_link(link);
printk(BIOS_INFO, "Devices finalized\n");
-
- if (IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT))
- ht_report_devtree_sanity();
}
diff --git a/src/device/device_const.c b/src/device/device_const.c
index 480ac76..cdae33d 100644
--- a/src/device/device_const.c
+++ b/src/device/device_const.c
@@ -177,15 +177,6 @@
* Work around the devicetree topology being manipulated on-the-fly
* on systems with HyperTransport Support.
*/
-
-static int ht_tree_needs_fixing, ht_tree_fixup_failed;
-
-void ht_report_devtree_sanity(void)
-{
- printk(BIOS_INFO, "HT fixup counters %d / %d (rqrd/failed)\n",
- ht_tree_needs_fixing, ht_tree_fixup_failed);
-}
-
static const struct bus *ht_bus_reloc(const struct bus *parent,
pci_devfn_t devfn)
{
@@ -222,34 +213,20 @@
DEVTREE_CONST struct device *pcidev_path_on_root(pci_devfn_t devfn)
{
- DEVTREE_CONST struct device *dev;
DEVTREE_CONST struct device *pci_domain;
+ const struct bus *root;
pci_domain = dev_find_path(NULL, DEVICE_PATH_DOMAIN);
if (!pci_domain)
return NULL;
- dev = pcidev_path_behind(pci_domain->link_list, devfn);
+ root = pci_domain->link_list;
/* Static devicetree with HyperTransport has whacky topology. */
- if (!IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT))
- return dev;
+ if (IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT))
+ root = ht_bus_reloc(root, devfn);
- DEVTREE_CONST struct device *dev_fixup, *dev_old_method;
-
- const struct bus *root = ht_bus_reloc(pci_domain->link_list, devfn);
- dev_fixup = pcidev_path_behind(root, devfn);
- dev_old_method = dev_find_slot(0, devfn);
-
- if (ENV_RAMSTAGE) {
- if (dev != dev_old_method)
- ht_tree_needs_fixing++;
-
- if (dev_fixup != dev_old_method)
- ht_tree_fixup_failed++;
- }
-
- return dev_old_method;
+ return pcidev_path_behind(root, devfn);
}
DEVTREE_CONST struct device *pcidev_on_root(uint8_t dev, uint8_t fn)
diff --git a/src/include/device/device.h b/src/include/device/device.h
index 40a0f58..540b7e3 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -227,7 +227,6 @@
void show_one_resource(int debug_level, struct device *dev,
struct resource *resource, const char *comment);
void show_all_devs_resources(int debug_level, const char *msg);
-void ht_report_devtree_sanity(void);
/* Rounding for boundaries.
* Due to some chip bugs, go ahead and round IO to 16
--
To view, visit https://review.coreboot.org/c/coreboot/+/30704
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I810ca9cfc72de9ea532d53cabdaf8845be837432
Gerrit-Change-Number: 30704
Gerrit-PatchSet: 1
Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-MessageType: newchange
2 months, 1 week
- 1
- 1
Change in ...coreboot[master]: device/hypertransport: Fix regression on dev_find_slot() removal
by Kyösti Mälkki (Code Review)
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30703
Change subject: device/hypertransport: Fix regression on dev_find_slot() removal
......................................................................
device/hypertransport: Fix regression on dev_find_slot() removal
The regression is with the implementation of the functions
introduced in commit
ad7674e device: Introduce pcidev_on_root() and friends
For these platforms, the first PCI node on devicetree
is not the root of PCI bus hierarchy, and the topology
(bus->children and dev->sibling links) are being
manipulated during HyperTransport enumeration.
This workaround reverts to old method of using dev_find_slot()
while keeping track of whether the new method would give
equivalent result.
Change-Id: I05a54de542f97159266a1c127da32665957f58f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M Makefile.inc
M src/device/device.c
M src/device/device_const.c
M src/device/hypertransport.c
M src/include/device/device.h
M src/include/device/pci.h
6 files changed, 87 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/30703/1
diff --git a/Makefile.inc b/Makefile.inc
index 2741b19..24b5164 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -577,7 +577,10 @@
verstage-y+=$(DEVICETREE_STATIC_C)
bootblock-y+=$(DEVICETREE_STATIC_C)
postcar-y+=$(DEVICETREE_STATIC_C)
+
+ifneq ($(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT),y)
smm-y+=$(DEVICETREE_STATIC_C)
+endif
#######################################################################
# Clean up rules
diff --git a/src/device/device.c b/src/device/device.c
index 7836af1..20a4077 100644
--- a/src/device/device.c
+++ b/src/device/device.c
@@ -1253,4 +1253,7 @@
final_link(link);
printk(BIOS_INFO, "Devices finalized\n");
+
+ if (IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT))
+ ht_report_devtree_sanity();
}
diff --git a/src/device/device_const.c b/src/device/device_const.c
index ec128e8..480ac76 100644
--- a/src/device/device_const.c
+++ b/src/device/device_const.c
@@ -173,6 +173,43 @@
return child;
}
+/***
+ * Work around the devicetree topology being manipulated on-the-fly
+ * on systems with HyperTransport Support.
+ */
+
+static int ht_tree_needs_fixing, ht_tree_fixup_failed;
+
+void ht_report_devtree_sanity(void)
+{
+ printk(BIOS_INFO, "HT fixup counters %d / %d (rqrd/failed)\n",
+ ht_tree_needs_fixing, ht_tree_fixup_failed);
+}
+
+static const struct bus *ht_bus_reloc(const struct bus *parent,
+ pci_devfn_t devfn)
+{
+ DEVTREE_CONST struct device *dev;
+ DEVTREE_CONST struct bus *bus;
+
+ /* HyperTransport enumeration fixes up the whacky
+ * topology present in static devicetree.
+ */
+ if (ENV_RAMSTAGE && (SCAN_COMPLETE == ht_scanning_status()))
+ return parent;
+
+ if (devfn >= PCI_DEVFN(0x18, 0))
+ return parent;
+
+ /* One of the links is bus for devices 0:00.x to 0:17.x. */
+ dev = pcidev_path_behind(parent, PCI_DEVFN(0x18, 0));
+ for (bus = dev->link_list; bus; bus = bus->next)
+ if (bus->children)
+ return bus;
+
+ return NULL;
+}
+
DEVTREE_CONST struct device *pcidev_path_behind(
const struct bus *parent, pci_devfn_t devfn)
{
@@ -185,12 +222,34 @@
DEVTREE_CONST struct device *pcidev_path_on_root(pci_devfn_t devfn)
{
+ DEVTREE_CONST struct device *dev;
DEVTREE_CONST struct device *pci_domain;
pci_domain = dev_find_path(NULL, DEVICE_PATH_DOMAIN);
if (!pci_domain)
return NULL;
- return pcidev_path_behind(pci_domain->link_list, devfn);
+
+ dev = pcidev_path_behind(pci_domain->link_list, devfn);
+
+ /* Static devicetree with HyperTransport has whacky topology. */
+ if (!IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT))
+ return dev;
+
+ DEVTREE_CONST struct device *dev_fixup, *dev_old_method;
+
+ const struct bus *root = ht_bus_reloc(pci_domain->link_list, devfn);
+ dev_fixup = pcidev_path_behind(root, devfn);
+ dev_old_method = dev_find_slot(0, devfn);
+
+ if (ENV_RAMSTAGE) {
+ if (dev != dev_old_method)
+ ht_tree_needs_fixing++;
+
+ if (dev_fixup != dev_old_method)
+ ht_tree_fixup_failed++;
+ }
+
+ return dev_old_method;
}
DEVTREE_CONST struct device *pcidev_on_root(uint8_t dev, uint8_t fn)
diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c
index ed6b2dd..fd4961e 100644
--- a/src/device/hypertransport.c
+++ b/src/device/hypertransport.c
@@ -244,6 +244,13 @@
}
}
+static int ht_scan_chain_process = SCAN_NOT_STARTED;
+
+int ht_scanning_status(void)
+{
+ return ht_scan_chain_process;
+}
+
static unsigned int do_hypertransport_scan_chain(struct bus *bus, unsigned min_devfn,
unsigned max_devfn,
unsigned *ht_unitid_base,
@@ -276,6 +283,9 @@
/* Restore the hypertransport chain to it's uninitialized state. */
ht_collapse_early_enumeration(bus, offset_unitid);
+ if (bus->secondary == 0)
+ ht_scan_chain_process = SCAN_IN_PROGRESS;
+
/* See which static device nodes I have. */
old_devices = bus->children;
bus->children = 0;
@@ -472,6 +482,9 @@
last_func->sibling = old_devices;
}
+ if (bus->secondary == 0)
+ ht_scan_chain_process = SCAN_COMPLETE;
+
return next_unitid;
}
diff --git a/src/include/device/device.h b/src/include/device/device.h
index 540b7e3..40a0f58 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -227,6 +227,7 @@
void show_one_resource(int debug_level, struct device *dev,
struct resource *resource, const char *comment);
void show_all_devs_resources(int debug_level, const char *msg);
+void ht_report_devtree_sanity(void);
/* Rounding for boundaries.
* Due to some chip bugs, go ahead and round IO to 16
diff --git a/src/include/device/pci.h b/src/include/device/pci.h
index 7cf7e06..41ad281 100644
--- a/src/include/device/pci.h
+++ b/src/include/device/pci.h
@@ -122,6 +122,13 @@
int pci_msix_table_bar(struct device *dev, u32 *offset, u8 *idx);
struct msix_entry *pci_msix_get_table(struct device *dev);
+enum {
+ SCAN_NOT_STARTED = 0,
+ SCAN_IN_PROGRESS,
+ SCAN_COMPLETE
+};
+int ht_scanning_status(void);
+
#define PCI_IO_BRIDGE_ALIGN 4096
#define PCI_MEM_BRIDGE_ALIGN (1024*1024)
--
To view, visit https://review.coreboot.org/c/coreboot/+/30703
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I05a54de542f97159266a1c127da32665957f58f9
Gerrit-Change-Number: 30703
Gerrit-PatchSet: 1
Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-MessageType: newchange
2 months, 1 week
- 1
- 1
Change in ...coreboot[master]: [WIP]mb/asus/p5ql-em: Add mainboard
by Arthur Heymans (Code Review)
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31323
Change subject: [WIP]mb/asus/p5ql-em: Add mainboard
......................................................................
[WIP]mb/asus/p5ql-em: Add mainboard
Tested, working:
- First dimm slot of each channel
- USB, SATA
- CPU FSB at 1067MHz
- Libgfxinit on DVI and VGA slot
- PCI slot
- Realtek NIC (configure macaddress in Kconfig)
- PEG slot
Tested, not working:
- second dimm slot for each channel. Those are hooked up to the second
rank of the channel, instead of rank 3 and 4. The raminit does not
support such setups.
Untested:
- PCIe x1 slot, likely works fine
- HDMI
TODO:
- BSEL superio pins
Tested using SeaBIOS 1.12, Linux 4.19.
Change-Id: I88fe9c66dae079cd7eedcc9736c5922defbc0e5a
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
A src/mainboard/asus/p5ql-em/Kconfig
A src/mainboard/asus/p5ql-em/Kconfig.name
A src/mainboard/asus/p5ql-em/Makefile.inc
A src/mainboard/asus/p5ql-em/acpi/ec.asl
A src/mainboard/asus/p5ql-em/acpi/ich10_pci_irqs.asl
A src/mainboard/asus/p5ql-em/acpi/platform.asl
A src/mainboard/asus/p5ql-em/acpi/superio.asl
A src/mainboard/asus/p5ql-em/acpi_tables.c
A src/mainboard/asus/p5ql-em/board_info.txt
A src/mainboard/asus/p5ql-em/cmos.default
A src/mainboard/asus/p5ql-em/cmos.layout
A src/mainboard/asus/p5ql-em/cstates.c
A src/mainboard/asus/p5ql-em/data.vbt
A src/mainboard/asus/p5ql-em/devicetree.cb
A src/mainboard/asus/p5ql-em/dsdt.asl
A src/mainboard/asus/p5ql-em/gma-mainboard.ads
A src/mainboard/asus/p5ql-em/gpio.c
A src/mainboard/asus/p5ql-em/hda_verb.c
A src/mainboard/asus/p5ql-em/romstage.c
19 files changed, 811 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/31323/1
diff --git a/src/mainboard/asus/p5ql-em/Kconfig b/src/mainboard/asus/p5ql-em/Kconfig
new file mode 100644
index 0000000..07af627
--- /dev/null
+++ b/src/mainboard/asus/p5ql-em/Kconfig
@@ -0,0 +1,47 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com>
+# Copyright (C) 2018 Arthur Heymans <arthur(a)aheymans.xyz>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+if BOARD_ASUS_P5QL_EM
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select ARCH_X86
+ select CPU_INTEL_SOCKET_LGA775
+ select NORTHBRIDGE_INTEL_X4X
+ select SOUTHBRIDGE_INTEL_I82801JX
+ select SUPERIO_WINBOND_W83627DHG
+ select HAVE_ACPI_TABLES
+ select BOARD_ROMSIZE_KB_1024
+ select HAVE_OPTION_TABLE
+ select HAVE_CMOS_DEFAULT
+ select HAVE_ACPI_RESUME
+ select INTEL_GMA_HAVE_VBT
+ select MAINBOARD_HAS_LIBGFXINIT
+ select REALTEK_8168_RESET
+
+config MAINBOARD_DIR
+ string
+ default "asus/p5ql-em"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "P5QL EM"
+
+config MAX_CPUS
+ int
+ default 4
+
+endif # BOARD_ASUS_P5QL_EM
diff --git a/src/mainboard/asus/p5ql-em/Kconfig.name b/src/mainboard/asus/p5ql-em/Kconfig.name
new file mode 100644
index 0000000..92ead65
--- /dev/null
+++ b/src/mainboard/asus/p5ql-em/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_ASUS_P5QL_EM
+ bool "P5QL EM"
diff --git a/src/mainboard/asus/p5ql-em/Makefile.inc b/src/mainboard/asus/p5ql-em/Makefile.inc
new file mode 100644
index 0000000..6b3d94a
--- /dev/null
+++ b/src/mainboard/asus/p5ql-em/Makefile.inc
@@ -0,0 +1,17 @@
+#
+# This file is part of the coreboot project.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+ramstage-y += cstates.c
+romstage-y += gpio.c
+
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/asus/p5ql-em/acpi/ec.asl b/src/mainboard/asus/p5ql-em/acpi/ec.asl
new file mode 100644
index 0000000..2997587
--- /dev/null
+++ b/src/mainboard/asus/p5ql-em/acpi/ec.asl
@@ -0,0 +1 @@
+/* dummy */
diff --git a/src/mainboard/asus/p5ql-em/acpi/ich10_pci_irqs.asl b/src/mainboard/asus/p5ql-em/acpi/ich10_pci_irqs.asl
new file mode 100644
index 0000000..861561a
--- /dev/null
+++ b/src/mainboard/asus/p5ql-em/acpi/ich10_pci_irqs.asl
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Arthur Heymans <arthur(a)aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* This is board specific information:
+ * IRQ routing for the 0:1e.0 PCI bridge of the ICH10
+ */
+
+If (PICM) {
+ Return (Package() {
+ /* PCI slot */
+ Package() { 0x0000ffff, 0, 0, 0x10},
+ Package() { 0x0000ffff, 1, 0, 0x11},
+ Package() { 0x0000ffff, 2, 0, 0x12},
+ Package() { 0x0000ffff, 3, 0, 0x13},
+ })
+} Else {
+ Return (Package() {
+ Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
+ Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
+ Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0},
+ Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},
+ })
+}
diff --git a/src/mainboard/asus/p5ql-em/acpi/platform.asl b/src/mainboard/asus/p5ql-em/acpi/platform.asl
new file mode 100644
index 0000000..6c92a4e
--- /dev/null
+++ b/src/mainboard/asus/p5ql-em/acpi/platform.asl
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Method(_PIC, 1)
+{
+ /* Remember the OS' IRQ routing choice. */
+ Store(Arg0, PICM)
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+ Store (Arg0, SMIF) /* SMI Function */
+ Store (0, TRP0) /* Generate trap */
+ Return (SMIF) /* Return value of SMI handler */
+}
diff --git a/src/mainboard/asus/p5ql-em/acpi/superio.asl b/src/mainboard/asus/p5ql-em/acpi/superio.asl
new file mode 100644
index 0000000..8f414f5
--- /dev/null
+++ b/src/mainboard/asus/p5ql-em/acpi/superio.asl
@@ -0,0 +1 @@
+/* TODO */
diff --git a/src/mainboard/asus/p5ql-em/acpi_tables.c b/src/mainboard/asus/p5ql-em/acpi_tables.c
new file mode 100644
index 0000000..d609a0e
--- /dev/null
+++ b/src/mainboard/asus/p5ql-em/acpi_tables.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <southbridge/intel/i82801jx/nvs.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ memset((void *)gnvs, 0, sizeof(*gnvs));
+
+ gnvs->pwrs = 1; /* Power state (AC = 1) */
+ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */
+ gnvs->apic = 1; /* Enable APIC */
+ gnvs->mpen = 1; /* Enable Multi Processing */
+ gnvs->cmap = 0x01; /* Enable COM 1 port */
+}
diff --git a/src/mainboard/asus/p5ql-em/board_info.txt b/src/mainboard/asus/p5ql-em/board_info.txt
new file mode 100644
index 0000000..42d4812
--- /dev/null
+++ b/src/mainboard/asus/p5ql-em/board_info.txt
@@ -0,0 +1,6 @@
+Category: desktop
+Board URL: https://www.asus.com/Motherboards/P5QC/
+ROM package: DIP-8
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y
diff --git a/src/mainboard/asus/p5ql-em/cmos.default b/src/mainboard/asus/p5ql-em/cmos.default
new file mode 100644
index 0000000..ad822d5
--- /dev/null
+++ b/src/mainboard/asus/p5ql-em/cmos.default
@@ -0,0 +1,5 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable
+nmi=Enable
+sata_mode=AHCI
diff --git a/src/mainboard/asus/p5ql-em/cmos.layout b/src/mainboard/asus/p5ql-em/cmos.layout
new file mode 100644
index 0000000..09ba5c5
--- /dev/null
+++ b/src/mainboard/asus/p5ql-em/cmos.layout
@@ -0,0 +1,104 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+## Copyright (C) 2014 Vladimir Serbinenko
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+# Status Register A
+# -----------------------------------------------------------------
+# Status Register B
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+#390 5 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395 4 e 6 debug_level
+
+# coreboot config options: southbridge
+408 1 e 10 sata_mode
+409 2 e 7 power_on_after_fail
+411 1 e 1 nmi
+
+# coreboot config options: cpu
+#424 8 r 0 unused
+
+# coreboot config options: northbridge
+432 4 e 11 gfx_uma_size
+#436 548 r 0 unused
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 0 Emergency
+6 1 Alert
+6 2 Critical
+6 3 Error
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+10 0 AHCI
+10 1 Compatible
+11 6 64M
+11 7 128M
+11 8 256M
+11 9 96M
+11 10 160M
+11 11 224M
+11 12 352M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/asus/p5ql-em/cstates.c b/src/mainboard/asus/p5ql-em/cstates.c
new file mode 100644
index 0000000..aa7214d
--- /dev/null
+++ b/src/mainboard/asus/p5ql-em/cstates.c
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpigen.h>
+#include <device/device.h>
+#include <southbridge/intel/i82801jx/i82801jx.h>
+
+int get_cst_entries(acpi_cstate_t **entries)
+{
+ return 0;
+}
diff --git a/src/mainboard/asus/p5ql-em/data.vbt b/src/mainboard/asus/p5ql-em/data.vbt
new file mode 100644
index 0000000..5dd1803
--- /dev/null
+++ b/src/mainboard/asus/p5ql-em/data.vbt
Binary files differ
diff --git a/src/mainboard/asus/p5ql-em/devicetree.cb b/src/mainboard/asus/p5ql-em/devicetree.cb
new file mode 100644
index 0000000..e13d59b
--- /dev/null
+++ b/src/mainboard/asus/p5ql-em/devicetree.cb
@@ -0,0 +1,169 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com>
+# Copyright (C) 2018 Angel Pons <th3fanbus(a)gmail.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+chip northbridge/intel/x4x # Northbridge
+ device cpu_cluster 0 on # APIC cluster
+ chip cpu/intel/socket_LGA775
+ device lapic 0 on end
+ end
+ chip cpu/intel/model_1067x # CPU
+ device lapic 0xACAC off end
+ end
+ end
+ device domain 0 on # PCI domain
+ device pci 0.0 on # Host Bridge
+ subsystemid 0x1043 0x8336
+ end
+ device pci 1.0 on # PEG
+ subsystemid 0x1043 0x8336
+ end
+ device pci 2.0 on # Integrated graphics controller
+ subsystemid 0x1043 0x8336
+ end
+ device pci 2.1 on # Integrated graphics controller 2
+ subsystemid 0x1043 0x8336
+ end
+ device pci 3.0 off end # ME
+ device pci 3.1 off end # ME
+ device pci 3.2 off end # ME
+ device pci 3.3 off end # ME
+ device pci 6.0 off end # PEG 2
+ chip southbridge/intel/i82801jx # Southbridge
+ register "gpe0_en" = "0x40"
+
+ # Set AHCI mode.
+ register "sata_port_map" = "0x3f"
+ register "sata_clock_request" = "0"
+ register "sata_traffic_monitor" = "0"
+
+ # Enable PCIe ports 0,2,3 as slots.
+ register "pcie_slot_implemented" = "0x31"
+
+ device pci 19.0 off end # GBE
+ device pci 1a.0 on # USB
+ subsystemid 0x1043 0x82d4
+ end
+ device pci 1a.1 on # USB
+ subsystemid 0x1043 0x82d4
+ end
+ device pci 1a.2 on # USB
+ subsystemid 0x1043 0x82d4
+ end
+ device pci 1a.7 on # USB
+ subsystemid 0x1043 0x82d4
+ end
+ device pci 1b.0 on # Audio
+ subsystemid 0x1043 0x82fe
+ end
+ device pci 1c.0 on end # PCIe 1 PCIe x1 Slot #1
+ device pci 1c.1 off end # PCIe 2
+ device pci 1c.2 off end # PCIe 3
+ device pci 1c.3 on # PCIe 4 1394 controller
+ device pci 0.0 on
+ subsystemid 0x1043 0x8313
+ end
+ end
+ device pci 1c.4 on # PCIe 5 Marvell IDE
+ device pci 0.0 on
+ subsystemid 0x1043 0x82a2
+ end
+ end
+ device pci 1c.5 on # PCIe 6 Realtek LAN
+ device pci 0.0 on
+ subsystemid 0x1043 0x82c6
+ end
+ end
+ device pci 1d.0 on # USB
+ subsystemid 0x1043 0x82d4
+ end
+ device pci 1d.1 on # USB
+ subsystemid 0x1043 0x82d4
+ end
+ device pci 1d.2 on # USB
+ subsystemid 0x1043 0x82d4
+ end
+ device pci 1d.7 on # USB
+ subsystemid 0x1043 0x82d4
+ end
+ device pci 1e.0 on end # PCI bridge
+ device pci 1f.0 on # LPC bridge
+ subsystemid 0x1043 0x82d4
+ chip superio/winbond/w83627dhg
+ device pnp 2e.0 on # Floppy
+ # global
+ irq 0x2c = 0x92
+ #floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 0x06
+ drq 0x74 = 0x02
+ end
+ device pnp 2e.1 on # Parallel port
+ # parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+ device pnp 2e.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off end # COM2, IR
+ device pnp 2e.5 on # Keyboard, mouse
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off end # SPI
+ device pnp 2e.7 on end # GPIO6 (all input)
+ device pnp 2e.8 off end # WDT0#, PLED
+ device pnp 2e.9 off end # GPIO2
+ device pnp 2e.109 on # GPIO3
+ irq 0xf0 = 0xf3
+ irq 0xf1 = 0x0c
+ end
+ device pnp 2e.209 on # GPIO4
+ irq 0xf4 = 0x06
+ irq 0xf5 = 0x06
+ end
+ device pnp 2e.309 on # GPIO5
+ irq 0xe0 = 0xdf
+ irq 0xf3 = 0x09 # RSVD SUSLED settings
+ end
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HWM, front pannel LED
+ io 0x60 = 0x290
+ irq 0x70 = 0
+ end
+ device pnp 2e.c off end # PECI, SST
+ end
+ end
+ device pci 1f.1 off end # PATA/IDE
+ device pci 1f.2 on # SATA
+ subsystemid 0x1043 0x82d4
+ end
+ device pci 1f.3 on # SMbus
+ subsystemid 0x1043 0x82d4
+ end
+ device pci 1f.4 off end
+ device pci 1f.5 on # IDE
+ subsystemid 0x1043 0x82d4
+ end
+ device pci 1f.6 off end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/asus/p5ql-em/dsdt.asl b/src/mainboard/asus/p5ql-em/dsdt.asl
new file mode 100644
index 0000000..d7ce26e
--- /dev/null
+++ b/src/mainboard/asus/p5ql-em/dsdt.asl
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/i82801jx/i82801jx.h>
+
+#include <arch/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0 and up
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x00000001 // OEM revision
+)
+{
+ // global NVS and variables
+ #include "acpi/platform.asl"
+ #include <southbridge/intel/i82801jx/acpi/globalnvs.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/x4x/acpi/x4x.asl>
+ #include <southbridge/intel/i82801jx/acpi/ich10.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ }
+ }
+
+ /* Chipset specific sleep states */
+ #include <southbridge/intel/i82801jx/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/asus/p5ql-em/gma-mainboard.ads b/src/mainboard/asus/p5ql-em/gma-mainboard.ads
new file mode 100644
index 0000000..43a7d89
--- /dev/null
+++ b/src/mainboard/asus/p5ql-em/gma-mainboard.ads
@@ -0,0 +1,29 @@
+--
+-- This file is part of the coreboot project.
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (HDMI1,
+ HDMI2,
+ Analog,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/asus/p5ql-em/gpio.c b/src/mainboard/asus/p5ql-em/gpio.c
new file mode 100644
index 0000000..7bc8b9b
--- /dev/null
+++ b/src/mainboard/asus/p5ql-em/gpio.c
@@ -0,0 +1,128 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Arthur Heymans <arthur(a)aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio10 = GPIO_MODE_GPIO,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_GPIO,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_GPIO,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio10 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio18 = GPIO_DIR_OUTPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio20 = GPIO_DIR_OUTPUT,
+ .gpio21 = GPIO_DIR_OUTPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_OUTPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio12 = GPIO_LEVEL_LOW,
+ .gpio18 = GPIO_LEVEL_HIGH,
+ .gpio20 = GPIO_LEVEL_HIGH,
+ .gpio21 = GPIO_LEVEL_HIGH,
+ .gpio24 = GPIO_LEVEL_LOW,
+ .gpio27 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio7 = GPIO_INVERT,
+ .gpio10 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_GPIO,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio56 = GPIO_MODE_GPIO,
+ .gpio57 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_OUTPUT,
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_OUTPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_OUTPUT,
+ .gpio56 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio32 = GPIO_LEVEL_HIGH,
+ .gpio33 = GPIO_LEVEL_HIGH,
+ .gpio34 = GPIO_LEVEL_LOW,
+ .gpio35 = GPIO_LEVEL_LOW,
+ .gpio49 = GPIO_LEVEL_HIGH,
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
+};
diff --git a/src/mainboard/asus/p5ql-em/hda_verb.c b/src/mainboard/asus/p5ql-em/hda_verb.c
new file mode 100644
index 0000000..9e54df6
--- /dev/null
+++ b/src/mainboard/asus/p5ql-em/hda_verb.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Arthur Heymans <arthur(a)aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10ec0888,
+ 0x104382fe, // Subsystem ID
+ 13, // Number of entries
+
+ /* Pin Widget Verb Table */
+
+ AZALIA_PIN_CFG(0, 0x11, 0x99430130),
+ AZALIA_PIN_CFG(0, 0x14, 0x01014010),
+ AZALIA_PIN_CFG(0, 0x15, 0x01011012),
+ AZALIA_PIN_CFG(0, 0x16, 0x01016011),
+ AZALIA_PIN_CFG(0, 0x17, 0x01012014),
+ AZALIA_PIN_CFG(0, 0x18, 0x01a19840),
+ AZALIA_PIN_CFG(0, 0x19, 0x02a19c50),
+ AZALIA_PIN_CFG(0, 0x1a, 0x0181304f),
+ AZALIA_PIN_CFG(0, 0x1b, 0x02214c20),
+ AZALIA_PIN_CFG(0, 0x1c, 0x593301f0),
+ AZALIA_PIN_CFG(0, 0x1d, 0x4015e601),
+ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
+
+ 0x80862803,
+ 0x80860101,
+ 1,
+
+ AZALIA_PIN_CFG(1, 0x03, 0x18560010),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs);
+const u32 cim_verb_data_size = ARRAY_SIZE(cim_verb_data);
diff --git a/src/mainboard/asus/p5ql-em/romstage.c b/src/mainboard/asus/p5ql-em/romstage.c
new file mode 100644
index 0000000..da822ac
--- /dev/null
+++ b/src/mainboard/asus/p5ql-em/romstage.c
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Arthur Heymans <arthur(a)aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <southbridge/intel/i82801jx/i82801jx.h>
+#include <southbridge/intel/common/gpio.h>
+#include <northbridge/intel/x4x/x4x.h>
+#include <cpu/x86/bist.h>
+#include <cpu/intel/romstage.h>
+#include <superio/winbond/w83627dhg/w83627dhg.h>
+#include <superio/winbond/common/winbond.h>
+#include <northbridge/intel/x4x/iomap.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
+#define LPC_DEV PCI_DEV(0, 0x1f, 0)
+
+/* Early mainboard specific GPIO setup.
+ * We should use standard gpio.h eventually
+ */
+
+static void mb_gpio_init(void)
+{
+ /* Set the value for GPIO base address register and enable GPIO. */
+ pci_write_config32(LPC_DEV, D31F0_GPIO_BASE, (DEFAULT_GPIOBASE | 1));
+ pci_write_config8(LPC_DEV, D31F0_GPIO_CNTL, 0x10);
+
+ setup_pch_gpios(&mainboard_gpio_map);
+
+ /* Enable IOAPIC */
+ RCBA8(0x31ff) = 0x03;
+ RCBA8(0x31ff);
+}
+
+static void ich10_enable_lpc(void)
+{
+ /* Configure serial IRQs.*/
+ pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010);
+ pci_write_config16(LPC_DEV, D31F0_LPC_EN, CNF1_LPC_EN | KBC_LPC_EN
+ | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN
+ | COMA_LPC_EN);
+ /* HW EC */
+ pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x00000295);
+ /* TODO: FSB BSEL pins... */
+}
+
+void mainboard_romstage_entry(unsigned long bist)
+{
+ /* This board has first dimm slot of each channel hooked up to
+ rank0 and rank1, while the second dimm slot is only connected
+ to rank1. The raminit does not support such setups
+ const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 }; */
+ const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
+ u8 boot_path = 0;
+ u8 s3_resume;
+
+ /* Set southbridge and Super I/O GPIOs. */
+ ich10_enable_lpc();
+ mb_gpio_init();
+ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+
+ console_init();
+
+ report_bist_failure(bist);
+ enable_smbus();
+
+ x4x_early_init();
+
+ s3_resume = southbridge_detect_s3_resume();
+ if (s3_resume)
+ boot_path = BOOT_PATH_RESUME;
+ if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
+ boot_path = BOOT_PATH_WARM_RESET;
+
+ sdram_initialize(boot_path, spd_addrmap);
+
+ x4x_late_init(s3_resume);
+
+ printk(BIOS_DEBUG, "x4x late init complete\n");
+}
--
To view, visit https://review.coreboot.org/c/coreboot/+/31323
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I88fe9c66dae079cd7eedcc9736c5922defbc0e5a
Gerrit-Change-Number: 31323
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-MessageType: newchange
2 months, 2 weeks
- 5
- 40
Change in ...coreboot[master]: cpu/intel/car/core2: Update microcode in CAR setup
by Arthur Heymans (Code Review)
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30775
Change subject: cpu/intel/car/core2: Update microcode in CAR setup
......................................................................
cpu/intel/car/core2: Update microcode in CAR setup
This updates the BSP microcode during CAR setup.
Change-Id: I8ecd1b99e18c7e73ae47f850fdc4870751dc6e8c
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/intel/car/core2/cache_as_ram.S
1 file changed, 28 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/30775/1
diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S
index 981b12d..4fb8c66 100644
--- a/src/cpu/intel/car/core2/cache_as_ram.S
+++ b/src/cpu/intel/car/core2/cache_as_ram.S
@@ -111,6 +111,17 @@
movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr
+ /* Cache the whole rom to fetch microcode updates */
+ movl $MTRR_PHYS_BASE(1), %ecx
+ xorl %edx, %edx
+ movl $CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax
+ wrmsr
+
+ movl $MTRR_PHYS_MASK(1), %ecx
+ rdmsr
+ movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
+ wrmsr
+
post_code(0x25)
/* Enable MTRR. */
@@ -131,15 +142,17 @@
invd
movl %eax, %cr0
- /* Clear the cache memory region. This will also fill up the cache. */
- movl $CACHE_AS_RAM_BASE, %esi
- movl %esi, %edi
- movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
- xorl %eax, %eax
- rep stosl
+#if IS_ENABLED(CONFIG_MICROCODE_UPDATE_PRE_RAM)
+update_microcode:
+ /* put the return address in %esp */
+ movl $end_microcode_update, %esp
+ jmp update_bsp_microcode
+end_microcode_update:
+#endif
+cache_xip:
post_code(0x26)
- /* Enable Cache-as-RAM mode by disabling cache. */
+ /* Disable caching to set final MTRRs for speeding up XIP. */
movl %cr0, %eax
orl $CR0_CacheDisable, %eax
movl %eax, %cr0
@@ -165,8 +178,16 @@
/* Enable cache. */
movl %cr0, %eax
andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
+ invd
movl %eax, %cr0
+ /* Clear the cache memory region. This will also fill up the cache. */
+ movl $CACHE_AS_RAM_BASE, %esi
+ movl %esi, %edi
+ movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
+ xorl %eax, %eax
+ rep stosl
+
/* Setup the stack. */
mov $_car_stack_end, %esp
--
To view, visit https://review.coreboot.org/c/coreboot/+/30775
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I8ecd1b99e18c7e73ae47f850fdc4870751dc6e8c
Gerrit-Change-Number: 30775
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-MessageType: newchange
2 months, 2 weeks
- 4
- 9
Change in ...coreboot[master]: util/autoport: Make dsdt.asl prettier
by Angel Pons (Code Review)
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30971
Change subject: util/autoport: Make dsdt.asl prettier
......................................................................
util/autoport: Make dsdt.asl prettier
Small cosmetic changes which fix OCD-inducing aesthetic inaccuracies.
Change-Id: I8fef4bbe12b283cee2ab8d078de950171757bbfe
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M util/autoport/main.go
1 file changed, 7 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/30971/1
diff --git a/util/autoport/main.go b/util/autoport/main.go
index ee26966..5d660d1 100644
--- a/util/autoport/main.go
+++ b/util/autoport/main.go
@@ -842,13 +842,14 @@
for _, define := range DSDTDefines {
if define.Comment != "" {
- fmt.Fprintf(dsdt, "\t/* %s. */\n", define.Comment)
+ fmt.Fprintf(dsdt, "\t/* %s. */\n", define.Comment)
}
dsdt.WriteString("#define " + define.Key + " " + define.Value + "\n")
}
dsdt.WriteString(
- `#include <arch/acpi.h>
+ `
+#include <arch/acpi.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
@@ -858,7 +859,7 @@
0x20141018 // OEM revision
)
{
- // Some generic macros
+ /* Some generic macros */
#include "acpi/platform.asl"
`)
@@ -870,9 +871,8 @@
}
dsdt.WriteString(`
- Scope (\_SB) {
- Device (PCI0)
- {
+ Device (\_SB.PCI0)
+ {
`)
for _, x := range DSDTPCI0Includes {
if x.Comment != "" {
@@ -881,8 +881,7 @@
fmt.Fprintf(dsdt, "\t\t#include <%s>\n", x.File)
}
dsdt.WriteString(
- ` }
- }
+ ` }
}
`)
--
To view, visit https://review.coreboot.org/c/coreboot/+/30971
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I8fef4bbe12b283cee2ab8d078de950171757bbfe
Gerrit-Change-Number: 30971
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-MessageType: newchange
2 months, 3 weeks
- 4
- 8
Change in ...coreboot[master]: [WIP] Reduce (void **) pointer usage
by Arthur Heymans (Code Review)
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30684
Change subject: [WIP] Reduce (void **) pointer usage
......................................................................
[WIP] Reduce (void **) pointer usage
Use uintptr_t * instead.
Change-Id: I8ef5d9fad0298c79806fd94ca053027822022ac2
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/intel/haswell/stage_cache.c
M src/cpu/intel/model_206ax/stage_cache.c
M src/drivers/intel/fsp1_1/include/fsp/memmap.h
M src/drivers/intel/fsp1_1/raminit.c
M src/drivers/intel/fsp1_1/ramstage.c
M src/drivers/intel/fsp1_1/stack.c
M src/drivers/intel/fsp1_1/stage_cache.c
M src/drivers/intel/fsp2_0/include/fsp/memmap.h
M src/drivers/intel/fsp2_0/stage_cache.c
M src/include/stage_cache.h
M src/lib/ext_stage_cache.c
M src/soc/amd/stoneyridge/cpu.c
M src/soc/amd/stoneyridge/include/soc/northbridge.h
M src/soc/amd/stoneyridge/ramtop.c
M src/soc/amd/stoneyridge/romstage.c
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/apollolake/memmap.c
M src/soc/intel/baytrail/stage_cache.c
M src/soc/intel/braswell/cpu.c
M src/soc/intel/braswell/memmap.c
M src/soc/intel/braswell/northcluster.c
M src/soc/intel/broadwell/stage_cache.c
M src/soc/intel/cannonlake/memmap.c
M src/soc/intel/cannonlake/smmrelocate.c
M src/soc/intel/common/block/include/intelblocks/smm.h
M src/soc/intel/common/block/smm/smm.c
M src/soc/intel/denverton_ns/cpu.c
M src/soc/intel/denverton_ns/include/soc/smm.h
M src/soc/intel/denverton_ns/memmap.c
M src/soc/intel/denverton_ns/romstage.c
M src/soc/intel/icelake/memmap.c
M src/soc/intel/icelake/smmrelocate.c
M src/soc/intel/skylake/memmap.c
M src/soc/intel/skylake/romstage/romstage_fsp20.c
M src/soc/intel/skylake/smmrelocate.c
35 files changed, 102 insertions(+), 124 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/30684/1
diff --git a/src/cpu/intel/haswell/stage_cache.c b/src/cpu/intel/haswell/stage_cache.c
index 009cc09..fb4a6c3 100644
--- a/src/cpu/intel/haswell/stage_cache.c
+++ b/src/cpu/intel/haswell/stage_cache.c
@@ -17,10 +17,10 @@
#include <stage_cache.h>
#include "haswell.h"
-void stage_cache_external_region(void **base, size_t *size)
+void stage_cache_external_region(uintptr_t *base, size_t *size)
{
/* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
* The top of RAM is defined to be the TSEG base address. */
*size = RESERVED_SMM_SIZE;
- *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET);
+ *base = cbmem_top() + RESERVED_SMM_OFFSET;
}
diff --git a/src/cpu/intel/model_206ax/stage_cache.c b/src/cpu/intel/model_206ax/stage_cache.c
index 26dc5e0..a0aaba5 100644
--- a/src/cpu/intel/model_206ax/stage_cache.c
+++ b/src/cpu/intel/model_206ax/stage_cache.c
@@ -17,12 +17,12 @@
#include <stage_cache.h>
#include "model_206ax.h"
-void stage_cache_external_region(void **base, size_t *size)
+void stage_cache_external_region(uintptr_t *base, size_t *size)
{
/*
* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
* The top of RAM is defined to be the TSEG base address.
*/
*size = RESERVED_SMM_SIZE;
- *base = (void *)((uintptr_t)cbmem_top() + RESERVED_SMM_OFFSET);
+ *base = cbmem_top() + RESERVED_SMM_OFFSET;
}
diff --git a/src/drivers/intel/fsp1_1/include/fsp/memmap.h b/src/drivers/intel/fsp1_1/include/fsp/memmap.h
index 965bce6..49bd019 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/memmap.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/memmap.h
@@ -27,7 +27,7 @@
/* Fills in the arguments for the entire SMM region covered by chipset
* protections. e.g. TSEG. */
-void smm_region(void **start, size_t *size);
+void smm_region(uintptr_t *start, size_t *size);
enum {
/* SMM handler area. */
@@ -42,6 +42,6 @@
/* Fills in the start and size for the requested SMM subregion. Returns
* 0 on susccess, < 0 on failure. */
-int smm_subregion(int sub, void **start, size_t *size);
+int smm_subregion(int sub, uintptr_t *start, size_t *size);
#endif /* _COMMON_MEMMAP_H_ */
diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c
index 7fed2a1..ad9e9dd 100644
--- a/src/drivers/intel/fsp1_1/raminit.c
+++ b/src/drivers/intel/fsp1_1/raminit.c
@@ -147,12 +147,12 @@
/* Display SMM area */
#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
- char *smm_base;
+ uintptr_t smm_base;
size_t smm_size;
- smm_region((void **)&smm_base, &smm_size);
+ smm_region(&smm_base, &smm_size);
printk(BIOS_DEBUG, "0x%08x: smm_size\n", (unsigned int)smm_size);
- printk(BIOS_DEBUG, "0x%p: smm_base\n", smm_base);
+ printk(BIOS_DEBUG, "0x%08x: smm_base\n", (unsigned int)smm_base);
#endif
/* Migrate CAR data */
diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c
index 864ab45..41d5437 100644
--- a/src/drivers/intel/fsp1_1/ramstage.c
+++ b/src/drivers/intel/fsp1_1/ramstage.c
@@ -33,19 +33,19 @@
/* Display SMM memory map */
static void smm_memory_map(void)
{
- void *base;
+ uintptr_t base;
size_t size;
int i;
printk(BIOS_SPEW, "SMM Memory Map\n");
smm_region(&base, &size);
- printk(BIOS_SPEW, "SMRAM : %p 0x%zx\n", base, size);
+ printk(BIOS_SPEW, "SMRAM : 0x%08x 0x%zx\n", (unsigned int)base, size);
for (i = 0; i < SMM_SUBREGION_NUM; i++) {
if (smm_subregion(i, &base, &size))
continue;
- printk(BIOS_SPEW, " Subregion %d: %p 0x%zx\n", i, base, size);
+ printk(BIOS_SPEW, " Subregion %d: 0x%08x 0x%zx\n", i, (unsigned int)base, size);
}
}
diff --git a/src/drivers/intel/fsp1_1/stack.c b/src/drivers/intel/fsp1_1/stack.c
index eb2a637..1b748aa 100644
--- a/src/drivers/intel/fsp1_1/stack.c
+++ b/src/drivers/intel/fsp1_1/stack.c
@@ -117,9 +117,8 @@
num_mtrrs++;
#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
- void *smm_base;
+ uintptr_t smm_base;
size_t smm_size;
- uint32_t tseg_base;
/*
* Cache the TSEG region at the top of ram. This region is not
@@ -128,11 +127,10 @@
* the SMM handler as well as using the TSEG region for other purposes.
*/
smm_region(&smm_base, &smm_size);
- tseg_base = (uint32_t)smm_base;
slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
slot = stack_push32(slot, ~(alignment - 1) | MTRR_PHYS_MASK_VALID);
slot = stack_push32(slot, 0); /* upper base */
- slot = stack_push32(slot, tseg_base | MTRR_TYPE_WRBACK);
+ slot = stack_push32(slot, (uint32_t)smm_base | MTRR_TYPE_WRBACK);
num_mtrrs++;
#endif
diff --git a/src/drivers/intel/fsp1_1/stage_cache.c b/src/drivers/intel/fsp1_1/stage_cache.c
index 2d594e6..4895340 100644
--- a/src/drivers/intel/fsp1_1/stage_cache.c
+++ b/src/drivers/intel/fsp1_1/stage_cache.c
@@ -18,11 +18,11 @@
#include <fsp/memmap.h>
#include <stage_cache.h>
-void stage_cache_external_region(void **base, size_t *size)
+void stage_cache_external_region(uintptr_t *base, size_t *size)
{
if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) {
printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n");
- *base = NULL;
+ *base = 0;
*size = 0;
}
}
diff --git a/src/drivers/intel/fsp2_0/include/fsp/memmap.h b/src/drivers/intel/fsp2_0/include/fsp/memmap.h
index 965bce6..49bd019 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/memmap.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/memmap.h
@@ -27,7 +27,7 @@
/* Fills in the arguments for the entire SMM region covered by chipset
* protections. e.g. TSEG. */
-void smm_region(void **start, size_t *size);
+void smm_region(uintptr_t *start, size_t *size);
enum {
/* SMM handler area. */
@@ -42,6 +42,6 @@
/* Fills in the start and size for the requested SMM subregion. Returns
* 0 on susccess, < 0 on failure. */
-int smm_subregion(int sub, void **start, size_t *size);
+int smm_subregion(int sub, uintptr_t *start, size_t *size);
#endif /* _COMMON_MEMMAP_H_ */
diff --git a/src/drivers/intel/fsp2_0/stage_cache.c b/src/drivers/intel/fsp2_0/stage_cache.c
index 434eae9..2ea6656 100644
--- a/src/drivers/intel/fsp2_0/stage_cache.c
+++ b/src/drivers/intel/fsp2_0/stage_cache.c
@@ -20,11 +20,11 @@
#include <reset.h>
#include <program_loading.h>
-void stage_cache_external_region(void **base, size_t *size)
+void stage_cache_external_region(uintptr_t *base, size_t *size)
{
if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) {
printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n");
- *base = NULL;
+ *base = 0;
*size = 0;
}
}
diff --git a/src/include/stage_cache.h b/src/include/stage_cache.h
index 28cb859..2a6c3bc 100644
--- a/src/include/stage_cache.h
+++ b/src/include/stage_cache.h
@@ -41,7 +41,7 @@
/* Load the cached stage at given location returning the stage entry point. */
void stage_cache_load_stage(int stage_id, struct prog *stage);
/* Fill in parameters for the external stage cache, if utilized. */
-void stage_cache_external_region(void **base, size_t *size);
+void stage_cache_external_region(uintptr_t *base, size_t *size);
/* Metadata associated with each stage. */
struct stage_cache {
diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c
index c3d4aee..35bcce4 100644
--- a/src/lib/ext_stage_cache.c
+++ b/src/lib/ext_stage_cache.c
@@ -32,12 +32,12 @@
static void stage_cache_create_empty(void)
{
struct imd *imd;
- void *base;
+ uintptr_t base;
size_t size;
imd = imd_get();
stage_cache_external_region(&base, &size);
- imd_handle_init(imd, (void *)(size + (uintptr_t)base));
+ imd_handle_init(imd, (void *)(size + base));
printk(BIOS_DEBUG, "External stage cache:\n");
imd_create_tiered_empty(imd, 4096, 4096, 1024, 32);
@@ -48,12 +48,12 @@
static void stage_cache_recover(void)
{
struct imd *imd;
- void *base;
+ uintptr_t base;
size_t size;
imd = imd_get();
stage_cache_external_region(&base, &size);
- imd_handle_init(imd, (void *)(size + (uintptr_t)base));
+ imd_handle_init(imd, (void *)(size + base));
if (imd_recover(imd))
printk(BIOS_DEBUG, "Unable to recover external stage cache.\n");
}
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c
index 1d9804d..e5b8bea 100644
--- a/src/soc/amd/stoneyridge/cpu.c
+++ b/src/soc/amd/stoneyridge/cpu.c
@@ -62,21 +62,21 @@
static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
size_t *smm_save_state_size)
{
- void *smm_base;
+ uintptr_t smm_base;
size_t smm_size;
- void *handler_base;
+ uintptr_t handler_base;
size_t handler_size;
/* Initialize global tracking state. */
smm_region_info(&smm_base, &smm_size);
smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);
- relo_attrs.smbase = (uint32_t)smm_base;
+ relo_attrs.smbase = smm_base;
relo_attrs.tseg_base = relo_attrs.smbase;
relo_attrs.tseg_mask = ALIGN_DOWN(~(smm_size - 1), 128 * KiB);
relo_attrs.tseg_mask |= SMM_TSEG_WB;
- *perm_smbase = (uintptr_t)handler_base;
+ *perm_smbase = handler_base;
*perm_smsize = handler_size;
*smm_save_state_size = sizeof(amd64_smm_state_save_area_t);
}
diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h
index d62c791..82be938 100644
--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h
@@ -114,12 +114,12 @@
* Fills in the arguments for the entire SMM region covered by chipset
* protections. e.g. TSEG.
*/
-void smm_region_info(void **start, size_t *size);
+void smm_region_info(uintptr_t *start, size_t *size);
/*
* Fills in the start and size for the requested SMM subregion. Returns
* 0 on success, < 0 on failure.
*/
-int smm_subregion(int sub, void **start, size_t *size);
+int smm_subregion(int sub, uintptr_t *start, size_t *size);
void domain_enable_resources(struct device *dev);
void domain_read_resources(struct device *dev);
void domain_set_resources(struct device *dev);
diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c
index 15968ab..ea3bd8b 100644
--- a/src/soc/amd/stoneyridge/ramtop.c
+++ b/src/soc/amd/stoneyridge/ramtop.c
@@ -80,18 +80,18 @@
return CONFIG_SMM_TSEG_SIZE;
}
-void stage_cache_external_region(void **base, size_t *size)
+void stage_cache_external_region(uintptr_t *base, size_t *size)
{
if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) {
printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n");
- *base = NULL;
+ *base = 0;
*size = 0;
}
}
-void smm_region_info(void **start, size_t *size)
+void smm_region_info(uintptr_t *start, size_t *size)
{
- *start = (void *)smm_region_start();
+ *start = smm_region_start();
*size = smm_region_size();
}
@@ -117,7 +117,7 @@
wrmsr(SMM_MASK_MSR, mask);
}
-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
{
uintptr_t sub_base;
size_t sub_size;
@@ -143,7 +143,7 @@
return -1;
}
- *start = (void *)sub_base;
+ *start = sub_base;
*size = sub_size;
return 0;
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index 9314488..e89f9e6 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -82,7 +82,7 @@
{
struct postcar_frame pcf;
uintptr_t top_of_ram;
- void *smm_base;
+ uintptr_t smm_base;
size_t smm_size;
uintptr_t tseg_base;
msr_t base, mask;
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index bcec28e..89faa85 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -196,9 +196,9 @@
static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
size_t *smm_save_state_size)
{
- void *smm_base;
+ uintptr_t smm_base;
size_t smm_size;
- void *handler_base;
+ uintptr_t handler_base;
size_t handler_size;
/* All range registers are aligned to 4KiB */
diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c
index be15e16..50ececa 100644
--- a/src/soc/intel/apollolake/memmap.c
+++ b/src/soc/intel/apollolake/memmap.c
@@ -48,7 +48,7 @@
return tolum;
}
-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
{
uintptr_t sub_base;
size_t sub_size;
@@ -56,7 +56,6 @@
const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
smm_region_info(&smm_base, &sub_size);
- sub_base = (uintptr_t)smm_base;
assert(sub_size > CONFIG_SMM_RESERVED_SIZE);
@@ -74,7 +73,7 @@
return -1;
}
- *start = (void *)sub_base;
+ *start = smm_base;
*size = sub_size;
return 0;
diff --git a/src/soc/intel/baytrail/stage_cache.c b/src/soc/intel/baytrail/stage_cache.c
index 4c2a976..8e8c67f 100644
--- a/src/soc/intel/baytrail/stage_cache.c
+++ b/src/soc/intel/baytrail/stage_cache.c
@@ -17,7 +17,7 @@
#include <stage_cache.h>
#include <soc/smm.h>
-void stage_cache_external_region(void **base, size_t *size)
+void stage_cache_external_region(uintptr_t *base, size_t *size)
{
char *smm_base;
/* 1MiB cache size */
@@ -27,5 +27,5 @@
* cbmem_top(). */
smm_base = cbmem_top();
*size = cache_size;
- *base = &smm_base[smm_region_size() - cache_size];
+ *base = smm_base + smm_region_size() - cache_size;
}
diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c
index 12f34fb..b4face2 100644
--- a/src/soc/intel/braswell/cpu.c
+++ b/src/soc/intel/braswell/cpu.c
@@ -147,7 +147,7 @@
static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
size_t *smm_save_state_size)
{
- void *smm_base;
+ uintptr_t smm_base;
size_t smm_size;
/* All range registers are aligned to 4KiB */
diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c
index d7c9952..89c3ab0 100644
--- a/src/soc/intel/braswell/memmap.c
+++ b/src/soc/intel/braswell/memmap.c
@@ -29,9 +29,9 @@
return smm_size;
}
-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
{
- *start = (void *)((iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20);
+ *start = (iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20;
*size = smm_region_size();
}
@@ -51,15 +51,13 @@
* | (TSEG) |
* +-------------------------+ BUNIT_SMRRL
*/
-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
{
uintptr_t sub_base;
- void *sub_ptr;
size_t sub_size;
const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
- smm_region(&sub_ptr, &sub_size);
- sub_base = (uintptr_t)sub_ptr;
+ smm_region(&sub_base, &sub_size);
switch (sub) {
case SMM_SUBREGION_HANDLER:
@@ -75,7 +73,7 @@
return -1;
}
- *start = (void *)sub_base;
+ *start = sub_base;
*size = sub_size;
return 0;
@@ -83,7 +81,7 @@
void *cbmem_top(void)
{
- char *smm_base;
+ uintptr_t smm_base;
size_t smm_size;
/*
@@ -114,6 +112,6 @@
* +-------------------------+
*/
- smm_region((void **)&smm_base, &smm_size);
+ smm_region(&smm_base, &smm_size);
return (void *)smm_base;
}
diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c
index 6e148b9..36b4377 100644
--- a/src/soc/intel/braswell/northcluster.c
+++ b/src/soc/intel/braswell/northcluster.c
@@ -87,7 +87,7 @@
unsigned long mmconf;
unsigned long bmbound_k;
unsigned long bmbound_hi;
- void *smm_base;
+ uintptr_t smm_base;
size_t smm_size;
unsigned long tseg_base_k;
unsigned long tseg_top_k;
diff --git a/src/soc/intel/broadwell/stage_cache.c b/src/soc/intel/broadwell/stage_cache.c
index dc59ab7..b812ced 100644
--- a/src/soc/intel/broadwell/stage_cache.c
+++ b/src/soc/intel/broadwell/stage_cache.c
@@ -18,7 +18,7 @@
#include <stage_cache.h>
#include <stdint.h>
-void stage_cache_external_region(void **base, size_t *size)
+void stage_cache_external_region(uintptr_t *base, size_t *size)
{
/* The ramstage cache lives in the TSEG region.
* The top of RAM is defined to be the TSEG base address. */
@@ -26,6 +26,6 @@
offset -= CONFIG_IED_REGION_SIZE;
offset -= CONFIG_SMM_RESERVED_SIZE;
- *base = (void *)(cbmem_top() + offset);
+ *base = cbmem_top() + offset;
*size = CONFIG_SMM_RESERVED_SIZE;
}
diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c
index 64e07be..8aeabac 100644
--- a/src/soc/intel/cannonlake/memmap.c
+++ b/src/soc/intel/cannonlake/memmap.c
@@ -29,9 +29,9 @@
#include <soc/systemagent.h>
#include <stdlib.h>
-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
{
- *start = (void *)sa_get_tseg_base();
+ *start = sa_get_tseg_base();
*size = sa_get_tseg_size();
}
@@ -46,16 +46,14 @@
* | (TSEG) |
* +-------------------------+ TSEG
*/
-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
{
uintptr_t sub_base;
size_t sub_size;
- void *smm_base;
const size_t ied_size = CONFIG_IED_REGION_SIZE;
const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
- smm_region(&smm_base, &sub_size);
- sub_base = (uintptr_t)smm_base;
+ smm_region(&sub_base, &sub_size);
switch (sub) {
case SMM_SUBREGION_HANDLER:
@@ -77,7 +75,7 @@
return -1;
}
- *start = (void *)sub_base;
+ *start = sub_base;
*size = sub_size;
return 0;
diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c
index e688592..59ae790 100644
--- a/src/soc/intel/cannonlake/smmrelocate.c
+++ b/src/soc/intel/cannonlake/smmrelocate.c
@@ -173,11 +173,11 @@
static void fill_in_relocation_params(struct device *dev,
struct smm_relocation_params *params)
{
- void *handler_base;
+ uintptr_t handler_base;
size_t handler_size;
- void *ied_base;
+ uintptr_t *ied_base;
size_t ied_size;
- void *tseg_base;
+ uintptr_t tseg_base;
size_t tseg_size;
u32 emrr_base;
u32 emrr_size;
@@ -196,9 +196,9 @@
smm_subregion(SMM_SUBREGION_CHIPSET, &ied_base, &ied_size);
params->smram_size = handler_size;
- params->smram_base = (uintptr_t)handler_base;
+ params->smram_base = handler_base;
- params->ied_base = (uintptr_t)ied_base;
+ params->ied_base = ied_base;
params->ied_size = ied_size;
/* SMRR has 32-bits of valid address aligned to 4KiB. */
@@ -232,24 +232,21 @@
static void setup_ied_area(struct smm_relocation_params *params)
{
- char *ied_base;
-
struct ied_header ied = {
.signature = "INTEL RSVD",
.size = params->ied_size,
.reserved = {0},
};
- ied_base = (void *)params->ied_base;
printk(BIOS_DEBUG, "IED base = 0x%08x\n", params->ied_base);
printk(BIOS_DEBUG, "IED size = 0x%08x\n", params->ied_size);
/* Place IED header at IEDBASE. */
- memcpy(ied_base, &ied, sizeof(ied));
+ memcpy(params->ied_base, &ied, sizeof(ied));
/* Zero out 32KiB at IEDBASE + 1MiB */
- memset(ied_base + 1 * MiB, 0, 32 * KiB);
+ memset(params->ied_base + 1 * MiB, 0, 32 * KiB);
}
void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
diff --git a/src/soc/intel/common/block/include/intelblocks/smm.h b/src/soc/intel/common/block/include/intelblocks/smm.h
index c04ec46..e2d38fd 100644
--- a/src/soc/intel/common/block/include/intelblocks/smm.h
+++ b/src/soc/intel/common/block/include/intelblocks/smm.h
@@ -33,6 +33,6 @@
void smm_southbridge_clear_state(void);
void smm_southbridge_enable(uint16_t pm1_events);
/* API to get SMM region start and size based on Host Bridge register */
-void smm_region_info(void **start, size_t *size);
+void smm_region_info(uintptr_t *start, size_t *size);
#endif
diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c
index d929975..d9b5645 100644
--- a/src/soc/intel/common/block/smm/smm.c
+++ b/src/soc/intel/common/block/smm/smm.c
@@ -89,9 +89,9 @@
);
}
-void smm_region_info(void **start, size_t *size)
+void smm_region_info(uintptr_t *start, size_t *size)
{
- *start = (void *)sa_get_tseg_base();
+ *start = sa_get_tseg_base();
*size = sa_get_tseg_size();
}
diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c
index 676fab7..683af8e 100644
--- a/src/soc/intel/denverton_ns/cpu.c
+++ b/src/soc/intel/denverton_ns/cpu.c
@@ -91,9 +91,9 @@
static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
size_t *smm_save_state_size)
{
- void *smm_base;
+ uintptr_t smm_base;
size_t smm_size;
- void *handler_base;
+ uintptr_t handler_base;
size_t handler_size;
/* All range registers are aligned to 4KiB */
@@ -108,7 +108,7 @@
relo_attrs.smrr_mask = ~(smm_size - 1) & rmask;
relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID;
- *perm_smbase = (uintptr_t)handler_base;
+ *perm_smbase = handler_base;
*perm_smsize = handler_size;
*smm_save_state_size = sizeof(em64t100_smm_state_save_area_t);
}
diff --git a/src/soc/intel/denverton_ns/include/soc/smm.h b/src/soc/intel/denverton_ns/include/soc/smm.h
index 771c3d8..e597e9d 100644
--- a/src/soc/intel/denverton_ns/include/soc/smm.h
+++ b/src/soc/intel/denverton_ns/include/soc/smm.h
@@ -33,7 +33,7 @@
/* Fills in the arguments for the entire SMM region covered by chipset
* protections. e.g. TSEG. */
-void smm_region(void **start, size_t *size);
+void smm_region(uintptr_t *start, size_t *size);
enum {
/* SMM handler area. */
@@ -48,7 +48,7 @@
/* Fills in the start and size for the requested SMM subregion. Returns
* 0 on success, < 0 on failure. */
-int smm_subregion(int sub, void **start, size_t *size);
+int smm_subregion(int sub, uintptr_t *start, size_t *size);
#if !defined(__PRE_RAM__) && !defined(__SMM___)
#include <stdint.h>
diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c
index a42d861..b4812ab 100644
--- a/src/soc/intel/denverton_ns/memmap.c
+++ b/src/soc/intel/denverton_ns/memmap.c
@@ -71,13 +71,13 @@
return system_agent_region_base(TOLUD) - smm_region_start();
}
-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
{
- *start = (void *)smm_region_start();
+ *start = smm_region_start();
*size = smm_region_size();
}
-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
{
uintptr_t sub_base;
size_t sub_size;
@@ -102,7 +102,7 @@
return -1;
}
- *start = (void *)sub_base;
+ *start = sub_base;
*size = sub_size;
return 0;
diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c
index 617b64a..712ec83 100644
--- a/src/soc/intel/denverton_ns/romstage.c
+++ b/src/soc/intel/denverton_ns/romstage.c
@@ -147,9 +147,8 @@
uintptr_t top_of_ram;
#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
- void *smm_base;
+ uintptr_t smm_base;
size_t smm_size;
- uintptr_t tseg_base;
#endif
console_init();
@@ -190,8 +189,7 @@
* region for other purposes.
*/
smm_region(&smm_base, &smm_size);
- tseg_base = (uintptr_t)smm_base;
- postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK);
+ postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
#endif
run_postcar_phase(&pcf);
diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c
index 027b8b0..20ae6e8 100644
--- a/src/soc/intel/icelake/memmap.c
+++ b/src/soc/intel/icelake/memmap.c
@@ -28,9 +28,9 @@
#include <soc/systemagent.h>
#include <stdlib.h>
-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
{
- *start = (void *)sa_get_tseg_base();
+ *start = sa_get_tseg_base();
*size = sa_get_tseg_size();
}
@@ -45,16 +45,14 @@
* | (TSEG) |
* +-------------------------+ TSEG
*/
-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
{
- uintptr_t sub_base;
size_t sub_size;
- void *smm_base;
+ uintptr_t smm_base;
const size_t ied_size = CONFIG_IED_REGION_SIZE;
const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
smm_region(&smm_base, &sub_size);
- sub_base = (uintptr_t)smm_base;
switch (sub) {
case SMM_SUBREGION_HANDLER:
@@ -76,7 +74,7 @@
return -1;
}
- *start = (void *)sub_base;
+ *start = smm_base;
*size = sub_size;
return 0;
diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c
index 57a366a..bb81799 100644
--- a/src/soc/intel/icelake/smmrelocate.c
+++ b/src/soc/intel/icelake/smmrelocate.c
@@ -172,11 +172,11 @@
static void fill_in_relocation_params(struct device *dev,
struct smm_relocation_params *params)
{
- void *handler_base;
+ uintptr_t handler_base;
size_t handler_size;
- void *ied_base;
+ uintptr_t ied_base;
size_t ied_size;
- void *tseg_base;
+ uintptr_t tseg_base;
size_t tseg_size;
u32 emrr_base;
u32 emrr_size;
@@ -195,9 +195,9 @@
smm_subregion(SMM_SUBREGION_CHIPSET, &ied_base, &ied_size);
params->smram_size = handler_size;
- params->smram_base = (uintptr_t)handler_base;
+ params->smram_base = handler_base;
- params->ied_base = (uintptr_t)ied_base;
+ params->ied_base = ied_base;
params->ied_size = ied_size;
/* SMRR has 32-bits of valid address aligned to 4KiB. */
@@ -231,24 +231,21 @@
static void setup_ied_area(struct smm_relocation_params *params)
{
- char *ied_base;
-
struct ied_header ied = {
.signature = "INTEL RSVD",
.size = params->ied_size,
.reserved = {0},
};
- ied_base = (void *)params->ied_base;
printk(BIOS_DEBUG, "IED base = 0x%08x\n", params->ied_base);
printk(BIOS_DEBUG, "IED size = 0x%08x\n", params->ied_size);
/* Place IED header at IEDBASE. */
- memcpy(ied_base, &ied, sizeof(ied));
+ memcpy(params->ied_base, &ied, sizeof(ied));
/* Zero out 32KiB at IEDBASE + 1MiB */
- memset(ied_base + 1 * MiB, 0, 32 * KiB);
+ memset(params->ied_base + 1 * MiB, 0, 32 * KiB);
}
void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c
index f0ccb1d..c33787a 100644
--- a/src/soc/intel/skylake/memmap.c
+++ b/src/soc/intel/skylake/memmap.c
@@ -40,9 +40,9 @@
return 8*MiB;
}
-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
{
- *start = (void *)sa_get_tseg_base();
+ *start = sa_get_tseg_base();
*size = sa_get_tseg_size();
}
@@ -57,16 +57,14 @@
* | (TSEG) |
* +-------------------------+ TSEG
*/
-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
{
- uintptr_t sub_base;
size_t sub_size;
- void *smm_base;
+ uintptr_t smm_base;
const size_t ied_size = CONFIG_IED_REGION_SIZE;
const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
smm_region(&smm_base, &sub_size);
- sub_base = (uintptr_t)smm_base;
switch (sub) {
case SMM_SUBREGION_HANDLER:
@@ -88,7 +86,7 @@
return -1;
}
- *start = (void *)sub_base;
+ *start = smm_base;
*size = sub_size;
return 0;
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index 2a60158..248f50f 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -167,7 +167,7 @@
postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
- void *smm_base;
+ uintptr_t *smm_base;
size_t smm_size;
uintptr_t tseg_base;
@@ -179,7 +179,7 @@
* region for other purposes.
*/
smm_region(&smm_base, &smm_size);
- tseg_base = (uintptr_t)smm_base;
+ tseg_base = smm_base;
postcar_frame_add_mtrr(&pcf, tseg_base, smm_size,
MTRR_TYPE_WRBACK);
}
diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c
index cb4e23f..82aacd4 100644
--- a/src/soc/intel/skylake/smmrelocate.c
+++ b/src/soc/intel/skylake/smmrelocate.c
@@ -241,24 +241,21 @@
static void setup_ied_area(struct smm_relocation_params *params)
{
- char *ied_base;
-
struct ied_header ied = {
.signature = "INTEL RSVD",
.size = params->ied_size,
.reserved = {0},
};
- ied_base = (void *)params->ied_base;
printk(BIOS_DEBUG, "IED base = 0x%08x\n", params->ied_base);
printk(BIOS_DEBUG, "IED size = 0x%08x\n", params->ied_size);
/* Place IED header at IEDBASE. */
- memcpy(ied_base, &ied, sizeof(ied));
+ memcpy(params->ied_base, &ied, sizeof(ied));
/* Zero out 32KiB at IEDBASE + 1MiB */
- memset(ied_base + (1 << 20), 0, (32 << 10));
+ memset(params->ied_base + 1 * MiB, 0, 32 * KiB);
}
void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
--
To view, visit https://review.coreboot.org/c/coreboot/+/30684
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I8ef5d9fad0298c79806fd94ca053027822022ac2
Gerrit-Change-Number: 30684
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-MessageType: newchange
2 months, 3 weeks
- 7
- 19
Change in ...coreboot[master]: lib/prog_loaders.c: Add prog_locate_hook() for measured and verified ...
by Frans Hendriks (Code Review)
Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30811
Change subject: lib/prog_loaders.c: Add prog_locate_hook() for measured and verified boot.
......................................................................
lib/prog_loaders.c: Add prog_locate_hook() for measured and verified boot.
Before images are loaded from cbfs it needs to be measured and/or verified.
prog_locate_hook() is added and can be used to start measured/verified boot.
BUG=N/A
TEST=Created verified binary and verify logging on Facebook FBG-1701
Change-Id: I12207fc8f2e9ca45d048cf8c8d9c057f53e5c2c7
Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com>
---
M src/include/program_loading.h
M src/lib/prog_loaders.c
2 files changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/30811/1
diff --git a/src/include/program_loading.h b/src/include/program_loading.h
index 468f0b3..a382daf 100644
--- a/src/include/program_loading.h
+++ b/src/include/program_loading.h
@@ -3,6 +3,7 @@
*
* Copyright 2015 Google Inc.
* Copyright (C) 2014 Imagination Technologies
+ * Copyright (C) 2018 Eltan B.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -136,6 +137,7 @@
/* Locate the identified program to run. Return 0 on success. < 0 on error. */
int prog_locate(struct prog *prog);
+int prog_locate_hook(struct prog *prog);
/* Run the program described by prog. */
void prog_run(struct prog *prog);
diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c
index b763417..4fa9a03 100644
--- a/src/lib/prog_loaders.c
+++ b/src/lib/prog_loaders.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc.
+ * Copyright (C) 2018 Eltan B.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -39,6 +40,9 @@
{
struct cbfsf file;
+ if (prog_locate_hook(prog))
+ return -1;
+
cbfs_prepare_program_locate();
if (cbfs_boot_locate(&file, prog_name(prog), NULL))
@@ -74,6 +78,7 @@
halt();
}
+int __weak prog_locate_hook(struct prog *prog) {return 0; }
void __weak stage_cache_add(int stage_id,
const struct prog *stage) {}
void __weak stage_cache_load_stage(int stage_id,
--
To view, visit https://review.coreboot.org/c/coreboot/+/30811
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I12207fc8f2e9ca45d048cf8c8d9c057f53e5c2c7
Gerrit-Change-Number: 30811
Gerrit-PatchSet: 1
Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>
Gerrit-MessageType: newchange
2 months, 4 weeks
- 9
- 45
Change in ...coreboot[master]: src/soc/intel/fsp_baytrail/smm.c: add bootstate entry for locking SMI
by Michał Żygowski (Code Review)
Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30753
Change subject: src/soc/intel/fsp_baytrail/smm.c: add bootstate entry for locking SMI
......................................................................
src/soc/intel/fsp_baytrail/smm.c: add bootstate entry for locking SMI
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: Ia296a680217a38136c063cae6ed619df0c497795
---
M src/soc/intel/fsp_baytrail/smm.c
1 file changed, 14 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/30753/1
diff --git a/src/soc/intel/fsp_baytrail/smm.c b/src/soc/intel/fsp_baytrail/smm.c
index 84f8d28..149272d 100644
--- a/src/soc/intel/fsp_baytrail/smm.c
+++ b/src/soc/intel/fsp_baytrail/smm.c
@@ -20,6 +20,7 @@
#include <arch/io.h>
#include <cpu/x86/smm.h>
#include <string.h>
+#include <bootstate.h>
#include <soc/iomap.h>
#include <soc/pmc.h>
@@ -124,3 +125,16 @@
"d" (APM_CNT)
);
}
+
+static void finalize_chipset(void *unused)
+{
+ printk(BIOS_DEBUG, "Finalizing SMM.\n");
+ /* Lock sleep stretching policy and set SMI lock. */
+ write32((void *)(PMC_BASE_ADDRESS + GEN_PMCON2),
+ read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON2))
+ | SLPSX_STR_POL_LOCK | SMI_LOCK);
+ outb(APM_CNT_FINALIZE, APM_CNT);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL);
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, finalize_chipset, NULL);
--
To view, visit https://review.coreboot.org/c/coreboot/+/30753
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ia296a680217a38136c063cae6ed619df0c497795
Gerrit-Change-Number: 30753
Gerrit-PatchSet: 1
Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Gerrit-MessageType: newchange
3 months, 1 week
- 4
- 4
Change in ...coreboot[master]: [UNTESTED]cpu/intel/model_1067x/mp_init: Implement get_microcode_info
by Arthur Heymans (Code Review)
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31600
Change subject: [UNTESTED]cpu/intel/model_1067x/mp_init: Implement get_microcode_info
......................................................................
[UNTESTED]cpu/intel/model_1067x/mp_init: Implement get_microcode_info
Fixes microcode not being updated.
Change-Id: Iee7a3897362b63bc6d7b9827da47c1cb24135278
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/intel/model_1067x/mp_init.c
1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/31600/1
diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
index acd56c8..1a6110b 100644
--- a/src/cpu/intel/model_1067x/mp_init.c
+++ b/src/cpu/intel/model_1067x/mp_init.c
@@ -49,6 +49,13 @@
smm_initialize();
}
+static void get_microcode_info(const void **microcode, int *parallel)
+{
+ microcode_patch = intel_microcode_find();
+ *microcode = microcode_patch;
+ *parallel = 1;
+}
+
#define SMRR_SUPPORTED (1 << 11)
static void per_cpu_smm_trigger(void)
@@ -98,6 +105,7 @@
.pre_mp_init = pre_mp_init,
.get_cpu_count = get_cpu_count,
.get_smm_info = smm_info,
+ .get_microcode_info = get_microcode_info,
.pre_mp_smm_init = pre_mp_smm_init,
.per_cpu_smm_trigger = per_cpu_smm_trigger,
.relocation_handler = smm_relocation_handler,
--
To view, visit https://review.coreboot.org/c/coreboot/+/31600
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iee7a3897362b63bc6d7b9827da47c1cb24135278
Gerrit-Change-Number: 31600
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-MessageType: newchange
3 months, 2 weeks
- 5
- 13