February 2019 - coreboot-gerrit

Change in ...coreboot[master]: google/mistrtal: Add board ID API.

by SANTHOSH JANARDHANA HASSAN (Code Review)

SANTHOSH JANARDHANA HASSAN has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31426 Change subject: google/mistrtal: Add board ID API. ...................................................................... google/mistrtal: Add board ID API. BUG=None TEST=Verified GPIO assignment and board ID values. BRANCH=None Change-Id: Ic81b41f799c7bfc47a0daee705db1c01cd0af1a3 Signed-off-by: Santhosh Hassan <sahassan(a)google.com> --- M src/mainboard/google/mistral/Makefile.inc A src/mainboard/google/mistral/boardid.c 2 files changed, 49 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/31426/1 diff --git a/src/mainboard/google/mistral/Makefile.inc b/src/mainboard/google/mistral/Makefile.inc index e9013af..ae418f2 100644 --- a/src/mainboard/google/mistral/Makefile.inc +++ b/src/mainboard/google/mistral/Makefile.inc @@ -3,6 +3,7 @@ bootblock-y += chromeos.c bootblock-y += bootblock.c +verstage-y += boardid.c verstage-y += memlayout.ld verstage-y += chromeos.c verstage-y += verstage.c @@ -10,7 +11,9 @@ romstage-y += memlayout.ld romstage-y += chromeos.c romstage-y += romstage.c +romstage-y += boardid.c +ramstage-y += boardid.c ramstage-y += memlayout.ld ramstage-y += chromeos.c ramstage-y += mainboard.c diff --git a/src/mainboard/google/mistral/boardid.c b/src/mainboard/google/mistral/boardid.c new file mode 100644 index 0000000..f20960c --- /dev/null +++ b/src/mainboard/google/mistral/boardid.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <gpio.h> +#include <console/console.h> +#include <stdlib.h> + +/* + * Mistral boards dedicate to the board ID three GPIOs in ternary mode: 105, 106 + * and 107. + */ + +static uint32_t board_id_val = UNDEFINED_STRAPPING_ID; + +static uint32_t get_board_id(void) +{ + uint32_t bid; + const gpio_t pins[] = {[2] = GPIO(107), [1] = GPIO(106), [0] = GPIO(105)}; + + bid = gpio_binary_first_base3_value(pins, ARRAY_SIZE(pins)); + printk(BIOS_INFO, "Board ID %d\n", bid); + + return bid; +} + +uint32_t board_id(void) +{ + if (board_id_val == UNDEFINED_STRAPPING_ID) + board_id_val = get_board_id(); + + return board_id_val; +} + -- To view, visit https://review.coreboot.org/c/coreboot/+/31426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic81b41f799c7bfc47a0daee705db1c01cd0af1a3 Gerrit-Change-Number: 31426 Gerrit-PatchSet: 1 Gerrit-Owner: SANTHOSH JANARDHANA HASSAN <sahassan(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: google/mistrtal: Setup required Chromeos GPIOs.

by SANTHOSH JANARDHANA HASSAN (Code Review)

SANTHOSH JANARDHANA HASSAN has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31459 Change subject: google/mistrtal: Setup required Chromeos GPIOs. ...................................................................... google/mistrtal: Setup required Chromeos GPIOs. Setup Flash write protect, recovery and h1 interrupt gpios to requires state at boot. BUG=None TEST=Verified GPIO state and its functionalities. BRANCH=None Change-Id: I5d98737a3b4e6376fd1c7115c42e795bba3b56ef Signed-off-by: Santhosh Hassan <sahassan(a)google.com> --- M src/mainboard/google/mistral/bootblock.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/31459/1 diff --git a/src/mainboard/google/mistral/bootblock.c b/src/mainboard/google/mistral/bootblock.c index 6718d52..c72856d 100644 --- a/src/mainboard/google/mistral/bootblock.c +++ b/src/mainboard/google/mistral/bootblock.c @@ -15,8 +15,9 @@ #include <bootblock_common.h> #include <timestamp.h> +#include "board.h" void bootblock_mainboard_init(void) { - + setup_chromeos_gpios(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/31459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d98737a3b4e6376fd1c7115c42e795bba3b56ef Gerrit-Change-Number: 31459 Gerrit-PatchSet: 1 Gerrit-Owner: SANTHOSH JANARDHANA HASSAN <sahassan(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: google/mistral: Support triggering Recovery/FDR.

by SANTHOSH JANARDHANA HASSAN (Code Review)

SANTHOSH JANARDHANA HASSAN has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31173 Change subject: google/mistral: Support triggering Recovery/FDR. ...................................................................... google/mistral: Support triggering Recovery/FDR. Implement triggering factory data reset and recovery mechanism based on Recovery/FDR switch(GPIO77) value. Change-Id: Ifdbd696ee3fd9f073cc44a49ad341cad7e33845e Signed-off-by: Santhosh Hassan <sahassan(a)google.com> --- M src/mainboard/google/mistral/Kconfig A src/mainboard/google/mistral/board.h M src/mainboard/google/mistral/chromeos.c M src/mainboard/google/mistral/verstage.c 4 files changed, 142 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/31173/1 diff --git a/src/mainboard/google/mistral/Kconfig b/src/mainboard/google/mistral/Kconfig index 5e97bb6..f28a382 100644 --- a/src/mainboard/google/mistral/Kconfig +++ b/src/mainboard/google/mistral/Kconfig @@ -23,6 +23,7 @@ select GBB_FLAG_DEV_SCREEN_SHORT_DELAY select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_MANUAL_RECOVERY + select VBOOT_WIPEOUT_SUPPORTED config MAINBOARD_DIR string diff --git a/src/mainboard/google/mistral/board.h b/src/mainboard/google/mistral/board.h new file mode 100644 index 0000000..2e23ce3 --- /dev/null +++ b/src/mainboard/google/mistral/board.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __COREBOOT_SRC_MAINBOARD_GOOGLE_MISTRAL_BOARD_H +#define __COREBOOT_SRC_MAINBOARD_GOOGLE_MISTRAL_BOARD_H + +#include <gpio.h> +#include <soc/gpio.h> + + +#define GPIO_H1_AP_INT GPIO(53) +#define GPIO_WP_STATE GPIO(54) +#define GPIO_REC_STATE GPIO(77) + +void setup_chromeos_gpios(void); + +#endif /* ! __COREBOOT_SRC_MAINBOARD_GOOGLE_MISTRAL_BOARD_H */ diff --git a/src/mainboard/google/mistral/chromeos.c b/src/mainboard/google/mistral/chromeos.c index ba0b1da..0405c4e 100644 --- a/src/mainboard/google/mistral/chromeos.c +++ b/src/mainboard/google/mistral/chromeos.c @@ -14,11 +14,18 @@ */ #include <boot/coreboot_tables.h> -#include <gpio.h> #include <security/tpm/tis.h> -#include <soc/gpio.h> +#include <bootmode.h> +#include <timer.h> +#include <console/console.h> +#include "board.h" -#define GPIO_H1_AP_INT GPIO(53) +void setup_chromeos_gpios(void) +{ + gpio_input_pullup(GPIO_H1_AP_INT); + gpio_input(GPIO_WP_STATE); + gpio_input(GPIO_REC_STATE); +} void fill_lb_gpios(struct lb_gpios *gpios) { @@ -27,9 +34,109 @@ {GPIO_H1_AP_INT.addr, ACTIVE_LOW, gpio_get(GPIO_H1_AP_INT), "TPM interrupt"}, }; +#endif + struct lb_gpio chromeos_gpios[] = { + {GPIO_REC_STATE.addr, ACTIVE_LOW, + gpio_get(GPIO_REC_STATE), "recovery"}, + {GPIO_WP_STATE.addr, ACTIVE_LOW, + gpio_get(GPIO_WP_STATE), "write protect"}, + {-1, ACTIVE_LOW, 1, "power"}, + {-1, ACTIVE_LOW, 0, "lid"}, + }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); -#endif +} + +#define WIPEOUT_MODE_DELAY_MS (8 * 1000) +#define RECOVERY_MODE_EXTRA_DELAY_MS (8 * 1000) + +/* + * The recovery switch: it needs to be pressed for a + * certain duration at startup to signal different requests: + * + * - keeping it pressed for 8 to 16 seconds after startup signals the need for + * factory reset (wipeout); + * - keeping it pressed for longer than 16 seconds signals the need for Chrome + * OS recovery. + * + * The state is read once and cached for following inquiries. The below enum + * lists possible states. + */ +enum switch_state { + not_probed = -1, + no_req, + recovery_req, + wipeout_req +}; + +static enum switch_state get_rec_sw_state(void) +{ + struct stopwatch sw; + int sampled_value; + gpio_t rec_sw; + static enum switch_state saved_state = not_probed; + + if (saved_state != not_probed) + return saved_state; + + rec_sw = GPIO_REC_STATE; + sampled_value = !gpio_get(rec_sw); + + if (!sampled_value) { + saved_state = no_req; + //display_pattern(WWR_NORMAL_BOOT); + return saved_state; + } + + //display_pattern(WWR_RECOVERY_PUSHED); + printk(BIOS_INFO, "recovery button pressed\n"); + + stopwatch_init_msecs_expire(&sw, WIPEOUT_MODE_DELAY_MS); + + do { + sampled_value = !gpio_get(rec_sw); + if (!sampled_value) + break; + } while (!stopwatch_expired(&sw)); + + if (sampled_value) { + //display_pattern(WWR_WIPEOUT_REQUEST); + printk(BIOS_INFO, "wipeout requested, checking recovery\n"); + stopwatch_init_msecs_expire(&sw, RECOVERY_MODE_EXTRA_DELAY_MS); + do { + sampled_value = !gpio_get(rec_sw); + if (!sampled_value) + break; + } while (!stopwatch_expired(&sw)); + + if (sampled_value) { + saved_state = recovery_req; + //display_pattern(WWR_RECOVERY_REQUEST); + printk(BIOS_INFO, "recovery requested\n"); + } else { + saved_state = wipeout_req; + } + } else { + saved_state = no_req; + //display_pattern(WWR_NORMAL_BOOT); + } + + return saved_state; +} + +int get_recovery_mode_switch(void) +{ + return get_rec_sw_state() == recovery_req; +} + +int get_wipeout_mode_switch(void) +{ + return get_rec_sw_state() == wipeout_req; +} + +int get_write_protect_state(void) +{ + return !gpio_get(GPIO_WP_STATE); } #if 0 diff --git a/src/mainboard/google/mistral/verstage.c b/src/mainboard/google/mistral/verstage.c index 7ea21c7..a63f61e 100644 --- a/src/mainboard/google/mistral/verstage.c +++ b/src/mainboard/google/mistral/verstage.c @@ -15,18 +15,10 @@ */ #include <console/console.h> -#include <gpio.h> #include <security/vboot/vboot_common.h> #include <spi-generic.h> #include <soc/clock.h> -#include <soc/gpio.h> - -#define GPIO_H1_AP_INT GPIO(53) - -static void setup_chromeos_gpios(void) -{ - gpio_input_pullup(GPIO_H1_AP_INT); -} +#include "board.h" void verstage_mainboard_init(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/31173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdbd696ee3fd9f073cc44a49ad341cad7e33845e Gerrit-Change-Number: 31173 Gerrit-PatchSet: 1 Gerrit-Owner: SANTHOSH JANARDHANA HASSAN <sahassan(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: google/mistral: add CR50

by Patrick Georgi (Code Review)

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30716 Change subject: google/mistral: add CR50 ...................................................................... google/mistral: add CR50 Change-Id: Ia8184e48a43866b7d065952c13e7176bb3b52e4d Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/google/mistral/Kconfig 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/30716/1 diff --git a/src/mainboard/google/mistral/Kconfig b/src/mainboard/google/mistral/Kconfig index b614a37..eddc1a3 100644 --- a/src/mainboard/google/mistral/Kconfig +++ b/src/mainboard/google/mistral/Kconfig @@ -14,6 +14,8 @@ select SPI_FLASH_WINBOND select MAINBOARD_HAS_CHROMEOS select MISSING_BOARD_RESET + select MAINBOARD_HAS_TPM2 + select MAINBOARD_HAS_SPI_TPM_CR50 config VBOOT select VBOOT_VBNV_FLASH @@ -29,6 +31,10 @@ string default "Google" +config DRIVER_TPM_SPI_BUS + hex + default 0x4 + ########################################################## #### Update below when adding a new derivative board. #### ########################################################## -- To view, visit https://review.coreboot.org/c/coreboot/+/30716 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8184e48a43866b7d065952c13e7176bb3b52e4d Gerrit-Change-Number: 30716 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: google/mistral: Enable additional GBB flags in vboot.

by SANTHOSH JANARDHANA HASSAN (Code Review)

SANTHOSH JANARDHANA HASSAN has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31171 Change subject: google/mistral: Enable additional GBB flags in vboot. ...................................................................... google/mistral: Enable additional GBB flags in vboot. Enable GBB_FLAG_FORCE_MANUAL_RECOVERY and GBB_FLAG_DEV_SCREEN_SHORT_DELAY as additional default flags. Change-Id: If1e7effb2d74b861f196ce861a3c8779ce89b3b2 Signed-off-by: Santhosh Hassan <sahassan(a)google.com> Change-Id: Ic0a00c6a7bfa5090461c2c9da0bc6ee73118ca74 --- M src/mainboard/google/mistral/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/31171/1 diff --git a/src/mainboard/google/mistral/Kconfig b/src/mainboard/google/mistral/Kconfig index c369472..5e97bb6 100644 --- a/src/mainboard/google/mistral/Kconfig +++ b/src/mainboard/google/mistral/Kconfig @@ -20,7 +20,9 @@ config VBOOT select VBOOT_VBNV_FLASH select VBOOT_NO_BOARD_SUPPORT + select GBB_FLAG_DEV_SCREEN_SHORT_DELAY select GBB_FLAG_FORCE_DEV_SWITCH_ON + select GBB_FLAG_FORCE_MANUAL_RECOVERY config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/31171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0a00c6a7bfa5090461c2c9da0bc6ee73118ca74 Gerrit-Change-Number: 31171 Gerrit-PatchSet: 1 Gerrit-Owner: SANTHOSH JANARDHANA HASSAN <sahassan(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: qclib: Differentiate between ES_1.0 and ES1.1 silicon

by Name of user not set (Code Review)

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30903 Change subject: qclib: Differentiate between ES_1.0 and ES1.1 silicon ...................................................................... qclib: Differentiate between ES_1.0 and ES1.1 silicon The PBL data ptr gets passed at a different location for 1.0 vs 1.1. So let us read the revision from TCSR and pass the right value. Change-Id: Id23493c8cfc64f62964a453cd32a0ddc4bff9e84 Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/qclib_execute.c 1 file changed, 14 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/30903/1 diff --git a/src/soc/qualcomm/qcs405/qclib_execute.c b/src/soc/qualcomm/qcs405/qclib_execute.c index 917a04c..214128f 100644 --- a/src/soc/qualcomm/qcs405/qclib_execute.c +++ b/src/soc/qualcomm/qcs405/qclib_execute.c @@ -14,6 +14,7 @@ */ #include <string.h> +#include <arch/io.h> #include <arch/cache.h> #include <arch/mmu.h> #include <cbfs.h> @@ -28,7 +29,12 @@ #define DCB_NAME "/dcb" #define QCLIB_NAME "/qclib" -#define PBL_DATA_PTR 0x8c101a0 //0x14810188 +#define TCSR_SOC_HW_VERSION 0x0194D000 +#define ES_1_0 0x20140100 +#define ES_1_1 0x20140101 + +#define PBL_DATA_PTR_ES_1_0 0x8c101a0 +#define PBL_DATA_PTR_ES_1_1 0x8c111a0 void qclib_load_and_run(void) { @@ -36,6 +42,7 @@ void *arg; int ret_code; struct mmu_context pre_qclib_mmu_context; + void *pbl_data_ptr; struct prog qclib = PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX QCLIB_NAME); @@ -67,7 +74,12 @@ if (cbfs_prog_stage_load(&qclib)) goto fail; - prog_set_entry(&qclib, qclib.entry, (void *)PBL_DATA_PTR); + if (read32((void *) TCSR_SOC_HW_VERSION) == ES_1_1) + pbl_data_ptr = (void *) 0x8c111a0; + else + pbl_data_ptr = (void *) 0x8c101a0; + + prog_set_entry(&qclib, qclib.entry, (void *)pbl_data_ptr); printk(BIOS_DEBUG, "\n\n\nQCLib is about to Initialize PMIC and DDR\n"); printk(BIOS_DEBUG, "Jumping to QCLib code at %p(%p)\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/30903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id23493c8cfc64f62964a453cd32a0ddc4bff9e84 Gerrit-Change-Number: 30903 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

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Change in ...coreboot[master]: google/mistral: move bootblock and fmap to their previous location

by Patrick Georgi (Code Review)

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30965 Change subject: google/mistral: move bootblock and fmap to their previous location ...................................................................... google/mistral: move bootblock and fmap to their previous location Helps with the current boot hack that requires them to be at certain locations. Also make GBB smaller. We don't store graphics in there anymore. Change-Id: I09c3a6d4221990cd51d4793693a7c7ae2df85105 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/google/mistral/chromeos.fmd 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/30965/1 diff --git a/src/mainboard/google/mistral/chromeos.fmd b/src/mainboard/google/mistral/chromeos.fmd index a9bdd7b..ffeec16 100644 --- a/src/mainboard/google/mistral/chromeos.fmd +++ b/src/mainboard/google/mistral/chromeos.fmd @@ -2,9 +2,9 @@ WP_RO@0x0 0x400000 { RO_SECTION@0x0 0x3e0000 { BOOTBLOCK@0 128K - COREBOOT(CBFS)@0x20000 0x2e0000 - FMAP@0x300000 0x1000 - GBB@0x301000 0xdef00 + COREBOOT(CBFS)@0x3e000 0x1e0000 + FMAP@0x21e000 0x1000 + GBB@0x3dd000 0x2f00 RO_FRID@0x3dff00 0x100 } RO_VPD@0x3e0000 0x20000 -- To view, visit https://review.coreboot.org/c/coreboot/+/30965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09c3a6d4221990cd51d4793693a7c7ae2df85105 Gerrit-Change-Number: 30965 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/common: Add more GPIO definition macros

by Thomas Heijligen (Code Review)

Hello Nico Huber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31350 to review the following change. Change subject: soc/intel/common: Add more GPIO definition macros ...................................................................... soc/intel/common: Add more GPIO definition macros Change-Id: Id1a3c00aa8a857afa08e745b0b6a578b01fa6d47 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/31350/1 diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 35f89c9..4d9f2be 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -236,6 +236,16 @@ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)) +#define PAD_CFG_GPI_IOSSTATE(pad, pull, rst, iosstate) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ + PAD_PULL(pull) | PAD_IOSSTATE(iosstate)) + +#define PAD_CFG_GPI_IOSSTATE_IOSTERM(pad, pull, rst, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ + PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + /* General purpose input. The following macro sets the * Host Software Pad Ownership to GPIO Driver mode. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1a3c00aa8a857afa08e745b0b6a578b01fa6d47 Gerrit-Change-Number: 31350 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/denverton_ns: Allow using FSP repo

by Felix Singer (Code Review)

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30931 Change subject: soc/intel/denverton_ns: Allow using FSP repo ...................................................................... soc/intel/denverton_ns: Allow using FSP repo Change-Id: I615305da5865bef305f560f5c90482cf0937b25a Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/denverton_ns/Kconfig 2 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/30931/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 8156d18..6f5ed2a 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -85,7 +85,8 @@ bool "Use the IntelFSP based binaries" depends on ADD_FSP_BINARIES depends on SOC_INTEL_APOLLOLAKE || SOC_INTEL_SKYLAKE || \ - SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE + SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE || \ + SOC_INTEL_DENVERTON_NS help When selecting this option, the SoC must set FSP_HEADER_PATH and FSP_FD_PATH correctly so FSP splitting works. diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 1096549..dfb5c37 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -78,6 +78,16 @@ help The memory location of the Intel FSP-S binary for this platform. +config FSP_HEADER_PATH + string "Location of FSP headers" + depends on MAINBOARD_USES_FSP2_0 + default "3rdparty/fsp/DenvertonNSFspBinPkg/Include/" + +config FSP_FD_PATH + string + depends on FSP_USE_REPO + default "3rdparty/fsp/DenvertonNSFspBinPkg/FspBin/DenvertonNSFsp.fd" + # CAR memory layout on DENVERTON_NS hardware: ## CAR base address - 0xfef00000 ## CAR size 1MB - 0x100 (0xfff00) -- To view, visit https://review.coreboot.org/c/coreboot/+/30931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I615305da5865bef305f560f5c90482cf0937b25a Gerrit-Change-Number: 30931 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

4 months, 1 week

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Change in ...coreboot[master]: README: Spell Web site with one space

by Paul Menzel (Code Review)

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31384 Change subject: README: Spell Web site with one space ...................................................................... README: Spell Web site with one space Change-Id: I4119ae6df01dbafb60b2a132c887844739839de6 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M payloads/libpayload/README 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/31384/1 diff --git a/payloads/libpayload/README b/payloads/libpayload/README index fdf9b18..7348934 100644 --- a/payloads/libpayload/README +++ b/payloads/libpayload/README @@ -49,10 +49,10 @@ Please see the sample/ directory for details. -Website and Mailing List +Web site and Mailing List ------------------------ -The main website is https://www.coreboot.org/Libpayload. +The main web site is https://www.coreboot.org/Libpayload. For additional information, patches, and discussions, please join the coreboot mailing list at https://www.coreboot.org/Mailinglist, where most -- To view, visit https://review.coreboot.org/c/coreboot/+/31384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4119ae6df01dbafb60b2a132c887844739839de6 Gerrit-Change-Number: 31384 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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coreboot-gerrit February 2019