coreboot-gerrit February 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: 3rdparty/chromeec: Update to latest master
by Nico Huber (Code Review) 16 Sep '19

16 Sep '19

Hello HAOUAS Elyes, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30679 to review the following change. Change subject: 3rdparty/chromeec: Update to latest master ...................................................................... 3rdparty/chromeec: Update to latest master It's been some time and there are 1420 new commits. Including one that allows reproducible builds \o/ and one that breaks building with empty $(CC) :-/ Change-Id: I5e81d5a2f1018481b9103fc5a1f4b8c72fb9deec Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M 3rdparty/chromeec M src/ec/google/chromeec/Makefile.inc 2 files changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/30679/1 diff --git a/3rdparty/chromeec b/3rdparty/chromeec index 11bd4c0..860fe29 160000 --- a/3rdparty/chromeec +++ b/3rdparty/chromeec @@ -1 +1 @@ -Subproject commit 11bd4c0f4d11357ab830982d7dec164813c886dd +Subproject commit 860fe2962d40ee901369d1dc67f4aa7a7a42ba4d diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 85e2599..f005cbc 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -62,6 +62,8 @@ $(obj)/mainboard/$(MAINBOARDDIR)/ecrw: $(MAKE) -C $(CHROMEEC_SOURCE) $(if $(CONFIG_CCACHE),,CCACHE=) \ out=$(abspath $(obj)/external/chromeec/$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME)) \ + REPRODUCIBLE_BUILD=1 \ + CC=$(GCC_CC_arm) \ CROSS_COMPILE=$(subst -cpp,-,$(CPP_arm)) \ HOST_CROSS_COMPILE= \ BOARD=$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME) \ @@ -99,6 +101,8 @@ $(obj)/mainboard/$(MAINBOARDDIR)/pdrw: $(MAKE) -C $(CHROMEEC_SOURCE) $(if $(CONFIG_CCACHE),,CCACHE=) \ out=$(abspath $(obj)/external/chromeec/$(CONFIG_EC_GOOGLE_CHROMEEC_PD_BOARDNAME)) \ + REPRODUCIBLE_BUILD=1 \ + CC=$(GCC_CC_arm) \ CROSS_COMPILE=$(subst -cpp,-,$(CPP_arm)) \ HOST_CROSS_COMPILE= \ BOARD=$(CONFIG_EC_GOOGLE_CHROMEEC_PD_BOARDNAME) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/30679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e81d5a2f1018481b9103fc5a1f4b8c72fb9deec Gerrit-Change-Number: 30679 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mediatek: Pass board specific message to BL31
by Tristan Hsieh (Code Review) 05 Sep '19

05 Sep '19

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31604 Change subject: mediatek: Pass board specific message to BL31 ...................................................................... mediatek: Pass board specific message to BL31 Sometimes we need to pass board specific messages to BL31, so that BL31 can do board specific operation based on common code. BUG=b:80501386 BRANCH=none TEST=emerge-kukui coreboot Change-Id: I60b09423d479b356ac5c04517906042fc8d512ca Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- A src/soc/mediatek/common/bl31_plat_params.c A src/soc/mediatek/common/include/soc/bl31_plat_params.h M src/soc/mediatek/mt8183/Makefile.inc 3 files changed, 54 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/31604/1 diff --git a/src/soc/mediatek/common/bl31_plat_params.c b/src/soc/mediatek/common/bl31_plat_params.c new file mode 100644 index 0000000..eb7477a --- /dev/null +++ b/src/soc/mediatek/common/bl31_plat_params.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arm_tf.h> +#include <soc/bl31_plat_params.h> + +static struct bl31_plat_param *plat_params; + +void register_bl31_param(struct bl31_plat_param *param) +{ + param->next = plat_params; + plat_params = param; +} + +void *soc_get_bl31_plat_params(bl31_params_t *bl31_params) +{ + return plat_params; +} diff --git a/src/soc/mediatek/common/include/soc/bl31_plat_params.h b/src/soc/mediatek/common/include/soc/bl31_plat_params.h new file mode 100644 index 0000000..399b0d5 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/bl31_plat_params.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __BL31_PLAT_PARAMS_H__ +#define __BL31_PLAT_PARAMS_H__ + +#include <arm-trusted-firmware/plat/mediatek/common/plat_params.h> + +void register_bl31_param(struct bl31_plat_param *param); + +#endif diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 8af3d68..fc2bbe2 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -50,6 +50,7 @@ ramstage-y += ../common/usb.c ramstage-y += ../common/wdt.c +ramstage-y += ../common/bl31_plat_params.c BL31_MAKEARGS += PLAT=mt8183 CPPFLAGS_common += -Isrc/soc/mediatek/mt8183/include -- To view, visit https://review.coreboot.org/c/coreboot/+/31604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60b09423d479b356ac5c04517906042fc8d512ca Gerrit-Change-Number: 31604 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: ec/kontron/kempld: Select DRIVERS_UART_8250IO
by Thomas Heijligen (Code Review) 02 Sep '19

02 Sep '19

Hello Nico Huber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31366 to review the following change. Change subject: ec/kontron/kempld: Select DRIVERS_UART_8250IO ...................................................................... ec/kontron/kempld: Select DRIVERS_UART_8250IO Change-Id: I1d0a46b6e4fc3aea403e2adce987de30703358c7 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/ec/kontron/kempld/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/31366/1 diff --git a/src/ec/kontron/kempld/Kconfig b/src/ec/kontron/kempld/Kconfig index 647bd12..08401c9 100644 --- a/src/ec/kontron/kempld/Kconfig +++ b/src/ec/kontron/kempld/Kconfig @@ -1,5 +1,6 @@ config EC_KONTRON_KEMPLD bool + select DRIVERS_UART_8250IO help Driver for Kontron's express module programmable logic device used on their COMexpress modules. -- To view, visit https://review.coreboot.org/c/coreboot/+/31366 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d0a46b6e4fc3aea403e2adce987de30703358c7 Gerrit-Change-Number: 31366 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: google/buddy: adjust CID for realtek audio codec
by Matt DeVillier (Code Review) 30 Aug '19

30 Aug '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30564 Change subject: google/buddy: adjust CID for realtek audio codec ...................................................................... google/buddy: adjust CID for realtek audio codec Adjust CID to allow for Windows driver to attach without breaking functionality under Linux. Same change made as to google/cyan (which uses same Realtek RT5650 codec) in commit 607d72b. Test: build/boot Windowns 10 on google/buddy, observe audio drivers correctly attached to codec and Intel SST devices. Change-Id: I839acc8427ee9b5c425885858a513e9b0b9d0f93 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/30564/1 diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl index 788fbdc..f4ed69e 100644 --- a/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl @@ -19,7 +19,7 @@ Device (RTEK) { Name (_HID, "10EC5650") - Name (_CID, "10EC5650") + Name (_CID, "INTCCFFD") Name (_DDN, "RTEK Codec Controller ") Name (_UID, 1) -- To view, visit https://review.coreboot.org/c/coreboot/+/30564 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I839acc8427ee9b5c425885858a513e9b0b9d0f93 Gerrit-Change-Number: 30564 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: arch/arm: Make ARM specific options depend on select ARCH_ARM
by Arthur Heymans (Code Review) 29 Aug '19

29 Aug '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31313 Change subject: arch/arm: Make ARM specific options depend on select ARCH_ARM ...................................................................... arch/arm: Make ARM specific options depend on select ARCH_ARM Also don't define the default as this result in spurious lines in the .config. Change-Id: I1ed4a71599641db606510e5304b9f0acf9b7eb88 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/arm/Kconfig M src/soc/nvidia/tegra124/Kconfig M src/soc/nvidia/tegra210/Kconfig M src/soc/qualcomm/ipq40xx/Kconfig M src/soc/qualcomm/ipq806x/Kconfig M src/soc/rockchip/rk3288/Kconfig M src/soc/samsung/exynos5250/Kconfig M src/soc/samsung/exynos5420/Kconfig 8 files changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/31313/1 diff --git a/src/arch/arm/Kconfig b/src/arch/arm/Kconfig index 6d9cc78..14d054a 100644 --- a/src/arch/arm/Kconfig +++ b/src/arch/arm/Kconfig @@ -1,11 +1,11 @@ config ARCH_ARM bool - default n + +if ARCH_ARM config ARCH_BOOTBLOCK_ARM bool default n - select ARCH_ARM select C_ENVIRONMENT_BOOTBLOCK config ARCH_VERSTAGE_ARM @@ -26,3 +26,5 @@ config ARM_LPAE bool default n + +endif #if ARCH_ARM diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index eecb59b..e9e43a5 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -1,6 +1,7 @@ config SOC_NVIDIA_TEGRA124 bool default n + select ARCH_ARM select ARCH_BOOTBLOCK_ARMV4 select BOOTBLOCK_CUSTOM select ARCH_VERSTAGE_ARMV7 diff --git a/src/soc/nvidia/tegra210/Kconfig b/src/soc/nvidia/tegra210/Kconfig index 8883baa..52118c3 100644 --- a/src/soc/nvidia/tegra210/Kconfig +++ b/src/soc/nvidia/tegra210/Kconfig @@ -1,6 +1,7 @@ config SOC_NVIDIA_TEGRA210 bool default n + select ARCH_ARM select ARCH_BOOTBLOCK_ARMV4 select BOOTBLOCK_CUSTOM select ARCH_VERSTAGE_ARMV4 diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig index 72e05fa..7a0648c 100644 --- a/src/soc/qualcomm/ipq40xx/Kconfig +++ b/src/soc/qualcomm/ipq40xx/Kconfig @@ -1,6 +1,7 @@ config SOC_QC_IPQ40XX bool default n + select ARCH_ARM select ARCH_BOOTBLOCK_ARMV7 select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 0b112d9..3bea529 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -1,6 +1,7 @@ config SOC_QC_IPQ806X bool default n + select ARCH_ARM select ARCH_BOOTBLOCK_ARMV7 select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 53666c2..654374c 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -16,6 +16,7 @@ config SOC_ROCKCHIP_RK3288 bool default n + select ARCH_ARM select ARCH_BOOTBLOCK_ARMV7 select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 diff --git a/src/soc/samsung/exynos5250/Kconfig b/src/soc/samsung/exynos5250/Kconfig index 5b39724..149d703 100644 --- a/src/soc/samsung/exynos5250/Kconfig +++ b/src/soc/samsung/exynos5250/Kconfig @@ -1,4 +1,5 @@ config CPU_SAMSUNG_EXYNOS5250 + select ARCH_ARM select ARCH_BOOTBLOCK_ARMV7 select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 diff --git a/src/soc/samsung/exynos5420/Kconfig b/src/soc/samsung/exynos5420/Kconfig index 7b87650..4ffbf7f 100644 --- a/src/soc/samsung/exynos5420/Kconfig +++ b/src/soc/samsung/exynos5420/Kconfig @@ -1,4 +1,5 @@ config CPU_SAMSUNG_EXYNOS5420 + select ARCH_ARM select ARCH_BOOTBLOCK_ARMV7 select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 -- To view, visit https://review.coreboot.org/c/coreboot/+/31313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ed4a71599641db606510e5304b9f0acf9b7eb88 Gerrit-Change-Number: 31313 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/sifive/fu540: add support boot from sdcard
by Xiang Wang (Code Review) 27 Aug '19

27 Aug '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30901 Change subject: soc/sifive/fu540: add support boot from sdcard ...................................................................... soc/sifive/fu540: add support boot from sdcard Change-Id: Id97d293aee33082191cfaf47844769bdfa3d7a1b Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/mainboard/sifive/hifive-unleashed/Makefile.inc D src/mainboard/sifive/hifive-unleashed/bootblock.c A src/mainboard/sifive/hifive-unleashed/media.c M src/soc/sifive/fu540/Makefile.inc M src/soc/sifive/fu540/include/soc/memlayout.ld A src/soc/sifive/fu540/include/soc/sd.h D src/soc/sifive/fu540/media.c A src/soc/sifive/fu540/sd.c 8 files changed, 490 insertions(+), 58 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/30901/1 diff --git a/src/mainboard/sifive/hifive-unleashed/Makefile.inc b/src/mainboard/sifive/hifive-unleashed/Makefile.inc index 2dac283..54d97f7 100644 --- a/src/mainboard/sifive/hifive-unleashed/Makefile.inc +++ b/src/mainboard/sifive/hifive-unleashed/Makefile.inc @@ -11,12 +11,26 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. +bootblock-y += memlayout.ld bootblock-y += flash.c -bootblock-y += bootblock.c +bootblock-y += media.c +romstage-y += memlayout.ld romstage-y += flash.c +romstage-y += media.c romstage-y += romstage.c -bootblock-y += memlayout.ld -romstage-y += memlayout.ld ramstage-y += memlayout.ld +ramstage-y += flash.c +ramstage-y += media.c + + +DTB=build/hifive-unleashed.dtb +DTS=src/mainboard/sifive/hifive-unleashed/hifive-unleashed.dts +$(DTB): $(DTS) + dtc -I dts -O dtb -o $(DTB) $(DTS) + +cbfs-files-y += fallback/DTB +fallback/DTB-file := $(DTB) +fallback/DTB-type := raw + diff --git a/src/mainboard/sifive/hifive-unleashed/bootblock.c b/src/mainboard/sifive/hifive-unleashed/bootblock.c deleted file mode 100644 index 777b2aa..0000000 --- a/src/mainboard/sifive/hifive-unleashed/bootblock.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/addressmap.h> -#include <soc/spi.h> -#include <soc/spi_flash.h> -#include <soc/clock.h> - -extern void flash_init(void); -extern void bootblock_mainboard_init(void); - -void bootblock_mainboard_init(void) -{ - flash_init(); -} diff --git a/src/mainboard/sifive/hifive-unleashed/media.c b/src/mainboard/sifive/hifive-unleashed/media.c new file mode 100644 index 0000000..4a8f463 --- /dev/null +++ b/src/mainboard/sifive/hifive-unleashed/media.c @@ -0,0 +1,123 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boot_device.h> +#include <symbols.h> +#include <cbfs.h> +#include <arch/io.h> +#include <soc/addressmap.h> +#include <soc/spi.h> +#include <soc/sd.h> +#include <soc/clock.h> +#include <console/console.h> +#include <string.h> + +void flash_init(void); +// void boot_device_init(void); +// const struct region_device *boot_device_ro(void); + +/* At 0x20000000: A 256MiB long memory-mapped view of the flash at QSPI0 */ +static struct mem_region_device spi_mdev = + MEM_REGION_DEV_RO_INIT((void *)0x20000000, CONFIG_ROM_SIZE); + +static ssize_t unleashed_sd_readat(const struct region_device *rdev, void *dest, + size_t offset, size_t count) +{ + if (offset / 512 == (offset + count - 1) / 512) { + size_t lba = offset / 512; + size_t o = offset % 512; + size_t l = count; + uint8_t tmp[512]; + if (sd_copy((spi_ctrl*)FU540_QSPI2, tmp, lba, 1) != 0) { + return -1; + } + memcpy(dest, tmp + o, l); + } else { + int has_begin = !!(offset % 512); + int has_end = !!((offset + count) % 512); + size_t first_lba = offset / 512; + size_t last_lba = (offset + count - 1) / 512; + if (has_begin) { + size_t lba = first_lba; + size_t o = offset % 512; + size_t l = 512 - o; + uint8_t tmp[512]; + if (sd_copy((spi_ctrl*)FU540_QSPI2, tmp, lba, 1) != 0) { + return -1; + } + memcpy(dest, tmp + o, l); + } + if (first_lba + has_begin <= last_lba - has_end) { + size_t lba = first_lba + has_begin; + size_t size = (last_lba - has_end) - (first_lba + has_begin) + 1; + size_t o = 512 - offset % 512; + if (sd_copy((spi_ctrl*)FU540_QSPI2, dest + o, lba, size) != 0) { + return -1; + } + } + if (has_end) { + size_t lba = last_lba; + size_t o = 0; + size_t l = (offset + count) % 512; + uint8_t tmp[512]; + if (sd_copy((spi_ctrl*)FU540_QSPI2, tmp, lba, 1) != 0) { + return -1; + } + memcpy(dest + count - l, tmp + o, l); + } + } + return count; +} + +static const struct region_device_ops unleashed_sd_ops = { + .mmap = mmap_helper_rdev_mmap, + .munmap = mmap_helper_rdev_munmap, + .readat = unleashed_sd_readat, +}; + + +static struct mmap_helper_region_device sd_mdev = + MMAP_HELPER_REGION_INIT(&unleashed_sd_ops, 0, CONFIG_ROM_SIZE); + + +const struct region_device *boot_device_ro() +{ + switch(read32((uint32_t *)FU540_MSEL)) { + case 6: + case 10: + case 15: + return &spi_mdev.rdev; + case 11: + return &sd_mdev.rdev; + } + return NULL; +} + +void boot_device_init() +{ + switch(read32((uint32_t *)FU540_MSEL)) { + case 6: + case 10: + case 15: + flash_init(); + break; + case 11: + sd_init((spi_ctrl*)FU540_QSPI2, clock_get_tlclk_khz()); + mmap_helper_device_init(&sd_mdev, _cbfs_cache, _cbfs_cache_size); + break; + default: + die("Wrong configuration of MSEL"); + } +} diff --git a/src/soc/sifive/fu540/Makefile.inc b/src/soc/sifive/fu540/Makefile.inc index 83c7b1c..866267e 100644 --- a/src/soc/sifive/fu540/Makefile.inc +++ b/src/soc/sifive/fu540/Makefile.inc @@ -15,28 +15,31 @@ bootblock-y += uart.c bootblock-y += clint.c -bootblock-y += media.c +# bootblock-y += media.c bootblock-y += bootblock.c bootblock-y += clock.c bootblock-y += spi.c +bootblock-y += sd.c romstage-y += uart.c romstage-y += clint.c -romstage-y += media.c +# romstage-y += media.c romstage-y += sdram.c romstage-y += cbmem.c romstage-y += otp.c romstage-y += clock.c romstage-y += spi.c +romstage-y += sd.c ramstage-y += uart.c ramstage-y += clint.c -ramstage-y += media.c +# ramstage-y += media.c ramstage-y += sdram.c ramstage-y += cbmem.c ramstage-y += otp.c ramstage-y += clock.c ramstage-y += spi.c +ramstage-y += sd.c CPPFLAGS_common += -Isrc/soc/sifive/fu540/include diff --git a/src/soc/sifive/fu540/include/soc/memlayout.ld b/src/soc/sifive/fu540/include/soc/memlayout.ld index b9b9c47..81a7f9b 100644 --- a/src/soc/sifive/fu540/include/soc/memlayout.ld +++ b/src/soc/sifive/fu540/include/soc/memlayout.ld @@ -28,9 +28,11 @@ CAR_STACK(FU540_L2LIM + 64K, 20K) PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 84K, 8K) ROMSTAGE(FU540_L2LIM + 128K, 128K) + PRERAM_CBFS_CACHE(FU540_L2LIM + 256K, 128K) L2LIM_END(FU540_L2LIM + 2M) DRAM_START(FU540_DRAM) RAMSTAGE(FU540_DRAM, 256K) MEM_STACK(FU540_DRAM + 256K, 20K) + POSTRAM_CBFS_CACHE(FU540_DRAM + 512K, 32M - 512K) } diff --git a/src/soc/sifive/fu540/include/soc/sd.h b/src/soc/sifive/fu540/include/soc/sd.h new file mode 100644 index 0000000..679d0f4 --- /dev/null +++ b/src/soc/sifive/fu540/include/soc/sd.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 SiFive, Inc + * Copyright (C) 2019 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _LIBRARIES_SD_H +#define _LIBRARIES_SD_H + +#define SD_INIT_ERROR_CMD0 1 +#define SD_INIT_ERROR_CMD8 2 +#define SD_INIT_ERROR_ACMD41 3 +#define SD_INIT_ERROR_CMD58 4 +#define SD_INIT_ERROR_CMD16 5 + +#define SD_COPY_ERROR_CMD18 1 +#define SD_COPY_ERROR_CMD18_CRC 2 + +#ifndef __ASSEMBLER__ + +#include <stdint.h> +#include <stddef.h> + +int sd_init(spi_ctrl* spi, unsigned int input_clk_hz); +int sd_copy(spi_ctrl* spi, void* dst, uint32_t src_lba, size_t size); + +#endif /* !__ASSEMBLER__ */ + +#endif /* _LIBRARIES_SD_H */ diff --git a/src/soc/sifive/fu540/media.c b/src/soc/sifive/fu540/media.c deleted file mode 100644 index 7b9ccb0..0000000 --- a/src/soc/sifive/fu540/media.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Jonathan Neuschäfer - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <boot_device.h> - -/* At 0x20000000: A 256MiB long memory-mapped view of the flash at QSPI0 */ -static struct mem_region_device mdev = - MEM_REGION_DEV_RO_INIT((void *)0x20000000, CONFIG_ROM_SIZE); - -const struct region_device *boot_device_ro(void) -{ - return &mdev.rdev; -} diff --git a/src/soc/sifive/fu540/sd.c b/src/soc/sifive/fu540/sd.c new file mode 100644 index 0000000..3af26ad --- /dev/null +++ b/src/soc/sifive/fu540/sd.c @@ -0,0 +1,302 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 SiFive, Inc + * Copyright (C) 2019 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mcall.h> +#include <arch/io.h> +#include <soc/spi.h> +#include <soc/sd.h> + + +#define SPI_DIR_RX 0 +#define SPI_DIR_TX 1 + +#define SPI_ENDIAN_MSB 0 +#define SPI_ENDIAN_LSB 1 + +#define SPI_CSMODE_AUTO 0 +#define SPI_CSMODE_HOLD 2 +#define SPI_CSMODE_OFF 3 + +#define SPI_PROTO_S 0 +#define SPI_PROTO_D 1 +#define SPI_PROTO_Q 2 + +#define SD_CMD_GO_IDLE_STATE 0 +#define SD_CMD_SEND_IF_COND 8 +#define SD_CMD_STOP_TRANSMISSION 12 +#define SD_CMD_SET_BLOCKLEN 16 +#define SD_CMD_READ_BLOCK_MULTIPLE 18 +#define SD_CMD_APP_SEND_OP_COND 41 +#define SD_CMD_APP_CMD 55 +#define SD_CMD_READ_OCR 58 +#define SD_RESPONSE_IDLE 0x1 +// Data token for commands 17, 18, 24 +#define SD_DATA_TOKEN 0xfe + + +// SD card initialization must happen at 100-400kHz +#define SD_POWER_ON_FREQ_KHZ 400L +// SD cards normally support reading/writing at 20MHz +#define SD_POST_INIT_CLK_KHZ 20000L + + +// Command frame starts by asserting low and then high for first two clock edges +#define SD_CMD(cmd) (0x40 | (cmd)) + + +/** + * Send dummy byte (all ones). + * + * Used in many cases to read one byte from SD card, since SPI is a full-duplex + * protocol and it is necessary to send a byte in order to read a byte. + */ +static inline uint8_t sd_dummy(spi_ctrl* spi) +{ + return spi_txrx(spi, 0xFF); +} + + +static int sd_cmd(spi_ctrl* spi, uint8_t cmd, uint32_t arg, uint8_t crc) +{ + unsigned long n; + uint8_t r; + + spi->csmode.mode = SPI_CSMODE_HOLD; + sd_dummy(spi); + spi_txrx(spi, cmd); + spi_txrx(spi, arg >> 24); + spi_txrx(spi, arg >> 16); + spi_txrx(spi, arg >> 8); + spi_txrx(spi, arg); + spi_txrx(spi, crc); + + n = 1000; + do { + r = sd_dummy(spi); + if (!(r & 0x80)) { + break; + } + } while (--n > 0); + return r; +} + + +static inline void sd_cmd_end(spi_ctrl* spi) +{ + sd_dummy(spi); + spi->csmode.mode = SPI_CSMODE_AUTO; +} + + +static void sd_poweron(spi_ctrl* spi, unsigned int input_clk_khz) +{ + // Initialize SPI controller + spi->fmt.raw_bits = ((spi_reg_fmt) { + .proto = SPI_PROTO_S, + .dir = SPI_DIR_RX, + .endian = SPI_ENDIAN_MSB, + .len = 8, + }).raw_bits; + spi->csdef |= 0x1; + spi->csid = 0; + + spi->sckdiv = spi_min_clk_divisor(input_clk_khz, SD_POWER_ON_FREQ_KHZ); + spi->csmode.mode = SPI_CSMODE_OFF; + + for (int i = 10; i > 0; i--) { + // Set SD card pin DI high for 74+ cycles + // SD CMD pin is the same pin as SPI DI, so CMD = 0xff means assert DI high + // for 8 cycles. + sd_dummy(spi); + } + + spi->csmode.mode = SPI_CSMODE_AUTO; +} + + +/** + * Reset card. + */ +static int sd_cmd0(spi_ctrl* spi) +{ + int rc; + rc = (sd_cmd(spi, SD_CMD(SD_CMD_GO_IDLE_STATE), 0, 0x95) != SD_RESPONSE_IDLE); + sd_cmd_end(spi); + return rc; +} + + +/** + * Check for SD version and supported voltages. + */ +static int sd_cmd8(spi_ctrl* spi) +{ + // Check for high capacity cards + // Fail if card does not support SDHC + int rc; + rc = (sd_cmd(spi, SD_CMD(SD_CMD_SEND_IF_COND), 0x000001AA, 0x87) != SD_RESPONSE_IDLE); + sd_dummy(spi); /* command version; reserved */ + sd_dummy(spi); /* reserved */ + rc |= ((sd_dummy(spi) & 0xF) != 0x1); /* voltage */ + rc |= (sd_dummy(spi) != 0xAA); /* check pattern */ + sd_cmd_end(spi); + return rc; +} + + +/** + * Send app command. Used as prefix to app commands (ACMD). + */ +static void sd_cmd55(spi_ctrl* spi) +{ + sd_cmd(spi, SD_CMD(SD_CMD_APP_CMD), 0, 0x65); + sd_cmd_end(spi); +} + + +/** + * Start SDC initialization process. + */ +static int sd_acmd41(spi_ctrl* spi) +{ + uint8_t r; + do { + sd_cmd55(spi); + r = sd_cmd(spi, SD_CMD(SD_CMD_APP_SEND_OP_COND), 0x40000000, 0x77); /* HCS = 1 */ + sd_cmd_end(spi); + } while (r == SD_RESPONSE_IDLE); + return (r != 0x00); +} + + +/** + * Read operation conditions register (OCR) to check for availability of block + * addressing mode. + */ +static int sd_cmd58(spi_ctrl* spi) +{ + // HACK: Disabled due to bugs. It is not strictly necessary + // to issue this command if we only support SD cards that support SDHC mode. + return 0; + // int rc; + // rc = (sd_cmd(spi, SD_CMD(SD_CMD_READ_OCR), 0, 0xFD) != 0x00); + // rc |= ((sd_dummy(spi) & 0x80) != 0x80); /* Power up status */ + // sd_dummy(spi); /* Supported voltages */ + // sd_dummy(spi); /* Supported voltages */ + // sd_dummy(spi); /* Supported voltages */ + // sd_cmd_end(spi); + // return rc; +} + + +/** + * Set block addressing mode. + */ +static int sd_cmd16(spi_ctrl* spi) +{ + int rc; + rc = (sd_cmd(spi, SD_CMD(SD_CMD_SET_BLOCKLEN), 0x200, 0x15) != 0x00); + sd_cmd_end(spi); + return rc; +} + + +static uint8_t crc7(uint8_t prev, uint8_t in) +{ + // CRC polynomial 0x89 + uint8_t remainder = prev & in; + remainder ^= (remainder >> 4) ^ (remainder >> 7); + remainder ^= remainder << 4; + return remainder & 0x7f; +} + + +static uint16_t crc16(uint16_t crc, uint8_t data) +{ + // CRC polynomial 0x11021 + crc = (uint8_t)(crc >> 8) | (crc << 8); + crc ^= data; + crc ^= (uint8_t)(crc >> 4) & 0xf; + crc ^= crc << 12; + crc ^= (crc & 0xff) << 5; + return crc; +} + + +//int sd_init(spi_ctrl* spi, unsigned int input_clk_khz, int skip_sd_init_commands) +int sd_init(spi_ctrl* spi, unsigned int input_clk_khz) +{ + sd_poweron(spi, input_clk_khz); + if (sd_cmd0(spi)) + return SD_INIT_ERROR_CMD0; + if (sd_cmd8(spi)) + return SD_INIT_ERROR_CMD8; + if (sd_acmd41(spi)) + return SD_INIT_ERROR_ACMD41; + if (sd_cmd58(spi)) + return SD_INIT_ERROR_CMD58; + if (sd_cmd16(spi)) + return SD_INIT_ERROR_CMD16; + + // Increase clock frequency after initialization for higher performance. + spi->sckdiv = spi_min_clk_divisor(input_clk_khz, SD_POST_INIT_CLK_KHZ); + return 0; +} + + +int sd_copy(spi_ctrl* spi, void* dst, uint32_t src_lba, size_t size) +{ + volatile uint8_t *p = dst; + long i = size; + int rc = 0; + + uint8_t c = 0; + c = crc7(c, SD_CMD(SD_CMD_READ_BLOCK_MULTIPLE)); + c = crc7(c, src_lba >> 24); + c = crc7(c, (src_lba >> 16) & 0xff); + c = crc7(c, (src_lba >> 8) & 0xff); + c = crc7(c, src_lba & 0xff); + c = (c << 1) | 1; + if (sd_cmd(spi, SD_CMD(SD_CMD_READ_BLOCK_MULTIPLE), src_lba, c) != 0x00) { + sd_cmd_end(spi); + return SD_COPY_ERROR_CMD18; + } + do { + uint16_t crc, crc_exp; + long n; + + crc = 0; + n = 512; + while (sd_dummy(spi) != SD_DATA_TOKEN); + do { + uint8_t x = sd_dummy(spi); + *p++ = x; + crc = crc16(crc, x); + } while (--n > 0); + + crc_exp = ((uint16_t)sd_dummy(spi) << 8); + crc_exp |= sd_dummy(spi); + + if (crc != crc_exp) { + rc = SD_COPY_ERROR_CMD18_CRC; + break; + } + } while (--i > 0); + + sd_cmd(spi, SD_CMD(SD_CMD_STOP_TRANSMISSION), 0, 0x01); + sd_cmd_end(spi); + return rc; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/30901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id97d293aee33082191cfaf47844769bdfa3d7a1b Gerrit-Change-Number: 30901 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

4 25

Change in ...coreboot[master]: soc/amd/common: Refactor S3 helpers
by Kyösti Mälkki (Code Review) 16 Aug '19

16 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31490 Change subject: soc/amd/common: Refactor S3 helpers ...................................................................... soc/amd/common: Refactor S3 helpers Change-Id: I1506ee2f7ecf3cb6ec4cce37a030c05f78ec6d59 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/s3_resume.h M src/soc/amd/common/block/pi/agesawrapper.c M src/soc/amd/common/block/s3/Makefile.inc M src/soc/amd/common/block/s3/s3_resume.c 4 files changed, 53 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/31490/1 diff --git a/src/soc/amd/common/block/include/amdblocks/s3_resume.h b/src/soc/amd/common/block/include/amdblocks/s3_resume.h index 13f8010..9323baf 100644 --- a/src/soc/amd/common/block/include/amdblocks/s3_resume.h +++ b/src/soc/amd/common/block/include/amdblocks/s3_resume.h @@ -17,10 +17,10 @@ #define __AMD_S3_RESUME_H__ #include <stdint.h> +#include <agesa_headers.h> -int save_s3_info(void *nv_base, size_t nv_size, - void *vol_base, size_t vol_size); -void get_s3nv_info(void **base, size_t *size); -void get_s3vol_info(void **base, size_t *size); +AGESA_STATUS OemInitResume(S3_DATA_BLOCK *dataBlock); +AGESA_STATUS OemS3LateRestore(S3_DATA_BLOCK *dataBlock); +AGESA_STATUS OemS3Save(S3_DATA_BLOCK *dataBlock); #endif /* __AMD_S3_RESUME_H__ */ diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index e769a45..1579b0b 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -313,10 +313,8 @@ Status = amd_dispatch(RtbParams); timestamp_add_now(TS_AGESA_INIT_RTB_DONE); - if (save_s3_info(RtbParams->S3DataBlock.NvStorage, - RtbParams->S3DataBlock.NvStorageSize, - RtbParams->S3DataBlock.VolatileStorage, - RtbParams->S3DataBlock.VolatileStorageSize)) + Status = OemS3Save(&RtbParams->S3DataBlock); + if (Status != AGESA_SUCCESS) printk(BIOS_ERR, "S3 data not saved, resuming impossible\n"); return Status; @@ -325,10 +323,8 @@ static AGESA_STATUS amd_init_resume(AMD_RESUME_PARAMS *InitResumeParams) { AGESA_STATUS status; - size_t nv_size; - get_s3nv_info(&InitResumeParams->S3DataBlock.NvStorage, &nv_size); - InitResumeParams->S3DataBlock.NvStorageSize = nv_size; + OemInitResume(&InitResumeParams->S3DataBlock); timestamp_add_now(TS_AGESA_INIT_RESUME_START); status = amd_dispatch(InitResumeParams); @@ -340,12 +336,10 @@ static AGESA_STATUS amd_s3late_restore(AMD_S3LATE_PARAMS *S3LateParams) { AGESA_STATUS Status; - size_t vol_size; amd_initcpuio(); - get_s3vol_info(&S3LateParams->S3DataBlock.VolatileStorage, &vol_size); - S3LateParams->S3DataBlock.VolatileStorageSize = vol_size; + OemS3LateRestore(&S3LateParams->S3DataBlock); timestamp_add_now(TS_AGESA_S3_LATE_START); Status = amd_dispatch(S3LateParams); @@ -357,10 +351,8 @@ static AGESA_STATUS amd_s3final_restore(AMD_S3FINAL_PARAMS *S3FinalParams) { AGESA_STATUS Status; - size_t vol_size; - get_s3vol_info(&S3FinalParams->S3DataBlock.VolatileStorage, &vol_size); - S3FinalParams->S3DataBlock.VolatileStorageSize = vol_size; + OemS3LateRestore(&S3FinalParams->S3DataBlock); timestamp_add_now(TS_AGESA_S3_FINAL_START); Status = amd_dispatch(S3FinalParams); diff --git a/src/soc/amd/common/block/s3/Makefile.inc b/src/soc/amd/common/block/s3/Makefile.inc index 7d950b0..9efc6bc 100644 --- a/src/soc/amd/common/block/s3/Makefile.inc +++ b/src/soc/amd/common/block/s3/Makefile.inc @@ -1,6 +1,6 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_S3),y) -romstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c -ramstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c +romstage-y += s3_resume.c +ramstage-y += s3_resume.c endif diff --git a/src/soc/amd/common/block/s3/s3_resume.c b/src/soc/amd/common/block/s3/s3_resume.c index eb0148f..818bde2 100644 --- a/src/soc/amd/common/block/s3/s3_resume.c +++ b/src/soc/amd/common/block/s3/s3_resume.c @@ -31,49 +31,66 @@ board_reset(); } -void get_s3nv_info(void **base, size_t *size) +AGESA_STATUS OemInitResume(S3_DATA_BLOCK *dataBlock) { + void *base; + size_t size; + int i; + uint32_t erased = 0xffffffff; struct region_device rdev; if (mrc_cache_get_current(MRC_TRAINING_DATA, DEFAULT_MRC_VERSION, &rdev)) reboot_from_resume("mrc_cache_get_current error, rebooting.\n"); - *base = rdev_mmap_full(&rdev); - *size = region_device_sz(&rdev); - if (!*base || !*size) + base = rdev_mmap_full(&rdev); + size = region_device_sz(&rdev); + if (!base || !size) reboot_from_resume("Error: S3 NV data not found, rebooting.\n"); /* Read 16 bytes to infer if the NV has been erased from flash. */ - int i; - uint32_t erased = 0xffffffff; for (i = 0; i < 4; i++) - erased &= read32((uint32_t *)*base + i); - + erased &= read32((uint32_t *)base + i); if (erased == 0xffffffff) reboot_from_resume("Error: S3 NV data invalid, rebooting.\n"); - printk(BIOS_SPEW, "S3 NV data @0x%p, 0x%0zx bytes\n", *base, *size); + dataBlock->NvStorage = base; + dataBlock->NvStorageSize = size; + printk(BIOS_SPEW, "S3 NV data @0x%p, 0x%0zx bytes\n", + dataBlock->NvStorage, (size_t)dataBlock->NvStorageSize); + + return AGESA_SUCCESS; } -void get_s3vol_info(void **base, size_t *size) +AGESA_STATUS OemS3LateRestore(S3_DATA_BLOCK *dataBlock) { - stage_cache_get_raw(STAGE_S3_DATA, base, size); - if (!*base || !*size) + void *base; + size_t size; + + stage_cache_get_raw(STAGE_S3_DATA, &base, &size); + if (!base || !size) { printk(BIOS_ERR, "Error: S3 volatile data not found\n"); - else - printk(BIOS_SPEW, "S3 volatile data @0x%p 0x%0zx total bytes\n", - *base, *size); -} - -int save_s3_info(void *nv_base, size_t nv_size, void *vol_base, size_t vol_size) -{ - if (mrc_cache_stash_data(MRC_TRAINING_DATA, DEFAULT_MRC_VERSION, - nv_base, nv_size) < 0) { - printk(BIOS_ERR, "Failed to stash MRC data\n"); - return -1; + return AGESA_FATAL; } - stage_cache_add_raw(STAGE_S3_DATA, vol_base, vol_size); - return 0; + dataBlock->VolatileStorage = base; + dataBlock->VolatileStorageSize = size; + printk(BIOS_SPEW, "S3 volatile data @0x%p, 0x%0zx bytes\n", + dataBlock->VolatileStorage, (size_t)dataBlock->VolatileStorageSize); + + return AGESA_SUCCESS; +} + +AGESA_STATUS OemS3Save(S3_DATA_BLOCK *dataBlock) +{ + if (mrc_cache_stash_data(MRC_TRAINING_DATA, DEFAULT_MRC_VERSION, + dataBlock->NvStorage, dataBlock->NvStorageSize) < 0) { + printk(BIOS_ERR, "Failed to stash MRC data\n"); + return AGESA_CRITICAL; + } + + stage_cache_add_raw(STAGE_S3_DATA, dataBlock->VolatileStorage, + dataBlock->VolatileStorageSize); + + return AGESA_SUCCESS; } -- To view, visit https://review.coreboot.org/c/coreboot/+/31490 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1506ee2f7ecf3cb6ec4cce37a030c05f78ec6d59 Gerrit-Change-Number: 31490 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

8 33

Change in ...coreboot[master]: mediaek/mt8183: add dsi driver for mt8183
by jitao shi (Code Review) 15 Aug '19

15 Aug '19

jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31591 Change subject: mediaek/mt8183: add dsi driver for mt8183 ...................................................................... mediaek/mt8183: add dsi driver for mt8183 BUG=b:80501386,b:117254947 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Ic413f524ca0b36f0b01f723a71fe9745e2710cd2 Signed-off-by: Jitao Shi <jitao.shi(a)mediatek.com> --- M src/soc/mediatek/mt8183/Makefile.inc A src/soc/mediatek/mt8183/dsi.c M src/soc/mediatek/mt8183/include/soc/addressmap.h A src/soc/mediatek/mt8183/include/soc/dsi.h 4 files changed, 957 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/31591/1 diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index b7e2ca4..02eaf6b 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -41,6 +41,7 @@ ramstage-y += auxadc.c ramstage-y += ../common/cbmem.c emi.c ramstage-y += ddp.c +ramstage-y += dsi.c ramstage-y += ../common/gpio.c gpio.c ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c diff --git a/src/soc/mediatek/mt8183/dsi.c b/src/soc/mediatek/mt8183/dsi.c new file mode 100644 index 0000000..f96d847 --- /dev/null +++ b/src/soc/mediatek/mt8183/dsi.c @@ -0,0 +1,470 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <soc/addressmap.h> +#include <soc/dsi.h> +#include <timer.h> + +static void mipi_write32(void *a, uint32_t offset, uint32_t v) +{ + write32(a + offset, v); +} + +static void mipi_clrsetbits_le32(void *a, uint32_t offset, uint32_t m, uint32_t v) +{ + clrsetbits_le32(a + offset, m, v); +} + +static void mipi_clrbits_le32(void *a, uint32_t offset, uint32_t m) +{ + clrbits_le32(a + offset, m); +} + +static void mipi_setbits_le32(void *a, uint32_t offset, uint32_t m) +{ + setbits_le32(a + offset, m); +} + +static void dsi_write32(void *a, uint32_t v) +{ + write32(a, v); +} + +static void dsi_clrsetbits_le32(void *a, uint32_t m, uint32_t v) +{ + clrsetbits_le32(a, m, v); +} + +static void dsi_clrbits_le32(void *a, uint32_t m) +{ + clrbits_le32(a, m); +} + +static void dsi_setbits_le32(void *a, uint32_t m) +{ + setbits_le32(a, m); +} + +static int mtk_dsi_phy_clk_setting(u32 format, u32 lanes, + const struct edid *edid, struct mtk_phy_timing *phy_timing) +{ + unsigned int txdiv, txdiv0, txdiv1; + u64 pcw; + int data_rate; + u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits; + u64 total_bits; + + switch (format) { + case MIPI_DSI_FMT_RGB565: + bit_per_pixel = 16; + break; + case MIPI_DSI_FMT_RGB666: + case MIPI_DSI_FMT_RGB666_PACKED: + bit_per_pixel = 18; + break; + case MIPI_DSI_FMT_RGB888: + default: + bit_per_pixel = 24; + break; + } + + htotal = edid->mode.hbl + edid->mode.ha; + htotal_bits = htotal * bit_per_pixel; + + overhead_cycles = 2 * phy_timing->lpx + phy_timing->da_hs_prepare + + phy_timing->da_hs_zero + phy_timing->da_hs_trail + + phy_timing->da_hs_exit + 1; + + overhead_bits = overhead_cycles * 8U; + total_bits = htotal_bits + overhead_bits; + + data_rate = (u64)(edid->mode.pixel_clock * 1000 * total_bits) / (htotal * lanes); + + printk(BIOS_ERR, "data_rate: %u bps\n", data_rate); + + if (data_rate >= 2000000000) { + txdiv = 1; + txdiv0 = 0; + txdiv1 = 0; + } else if (data_rate >= 1000000000) { + txdiv = 2; + txdiv0 = 1; + txdiv1 = 0; + } else if (data_rate >= 500000000) { + txdiv = 4; + txdiv0 = 2; + txdiv1 = 0; + } else if (data_rate > 250000000) { + txdiv = 8; + txdiv0 = 3; + txdiv1 = 0; + } else if (data_rate >= 125000000) { + txdiv = 16; + txdiv0 = 4; + txdiv1 = 0; + } else { + printk(BIOS_ERR, "data rate (%u) must be >=50. Please check " + "pixel clock (%u), bpp (%u), and number of lanes (%u)\n", + data_rate, edid->mode.pixel_clock, bit_per_pixel, lanes); + return -1; + } + + mipi_clrbits_le32(mipi_tx, MIPITX_PLL_CON4, BIT(11) | BIT(10)); + + mipi_setbits_le32(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON); + udelay(30); + mipi_clrbits_le32(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN); + + pcw = (u64)((data_rate / 1000000) * (1 << txdiv0) * (1 << txdiv1)) << 24; + pcw /= 26; + + mipi_write32(mipi_tx, MIPITX_PLL_CON0, pcw); + mipi_clrsetbits_le32(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV, + txdiv0 << 8); + udelay(30); + mipi_setbits_le32(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_EN); + + /* BG_LPF_EN / BG_CORE_EN */ + mipi_write32(mipi_tx, MIPITX_LANE_CON, 0x3FFF0180); + udelay(40); + mipi_write32(mipi_tx, MIPITX_LANE_CON, 0x3FFF00c0); + + /* Switch OFF each Lane */ + mipi_clrbits_le32(mipi_tx, MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN); + mipi_clrbits_le32(mipi_tx, MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN); + mipi_clrbits_le32(mipi_tx, MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN); + mipi_clrbits_le32(mipi_tx, MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN); + mipi_clrbits_le32(mipi_tx, MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN); + + mipi_setbits_le32(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN); + + return data_rate; +} + +static void mtk_dsi_phy_timconfig(u32 data_rate, struct mtk_phy_timing *phy_timing) +{ + u32 timcon0, timcon1, timcon2, timcon3; + + timcon0 = phy_timing->lpx | phy_timing->da_hs_prepare << 8 | + phy_timing->da_hs_zero << 16 | phy_timing->da_hs_trail << 24; + timcon1 = phy_timing->ta_go | phy_timing->ta_sure << 8 | + phy_timing->ta_get << 16 | phy_timing->da_hs_exit << 24; + timcon2 = 1 << 8 | phy_timing->clk_hs_zero << 16 | + phy_timing->clk_hs_trail << 24; + timcon3 = phy_timing->clk_hs_prepare | phy_timing->clk_hs_post << 8 | + phy_timing->clk_hs_exit << 16; + + dsi_write32(&dsi->dsi_phy_timecon0, timcon0); + dsi_write32(&dsi->dsi_phy_timecon1, timcon1); + dsi_write32(&dsi->dsi_phy_timecon2, timcon2); + dsi_write32(&dsi->dsi_phy_timecon3, timcon3); +} + +static void mtk_dsi_reset(void) +{ + dsi_setbits_le32(&dsi->dsi_con_ctrl, 3); + dsi_clrbits_le32(&dsi->dsi_con_ctrl, 1); +} + +static void mtk_dsi_clk_hs_mode_enable(void) +{ + dsi_setbits_le32(&dsi->dsi_phy_lccon, LC_HS_TX_EN); +} + +static void mtk_dsi_clk_hs_mode_disable(void) +{ + dsi_clrbits_le32(&dsi->dsi_phy_lccon, LC_HS_TX_EN); +} + +static void mtk_dsi_set_mode(u32 mode_flags) +{ + u32 tmp_reg1 = 0; + + if (mode_flags & MIPI_DSI_MODE_VIDEO) { + tmp_reg1 = SYNC_PULSE_MODE; + + if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) + tmp_reg1 = BURST_MODE; + + if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) + tmp_reg1 = SYNC_PULSE_MODE; + } + + dsi_write32(&dsi->dsi_mode_ctrl, tmp_reg1); +} + +static void mtk_dsi_phy_timing_calc(u32 format, u32 lanes, + const struct edid *edid, struct mtk_phy_timing *phy_timing) +{ + u32 ui, cycle_time, data_rate; + u32 bit_per_pixel; + + switch (format) { + case MIPI_DSI_FMT_RGB565: + bit_per_pixel = 16; + break; + case MIPI_DSI_FMT_RGB666: + case MIPI_DSI_FMT_RGB666_PACKED: + bit_per_pixel = 18; + break; + case MIPI_DSI_FMT_RGB888: + default: + bit_per_pixel = 24; + break; + } + + data_rate = edid->mode.pixel_clock * bit_per_pixel / lanes; + + ui = 1000 / (data_rate / 1000) + 1U; + cycle_time = 8000 / (data_rate / 1000) + 1U; + + phy_timing->lpx = DIV_ROUND_UP(0x50, cycle_time); + phy_timing->da_hs_prepare = DIV_ROUND_UP((0x40 + 0x5 * ui), cycle_time); + phy_timing->da_hs_zero = DIV_ROUND_UP((0xc8 + 0x0a * ui), cycle_time); + phy_timing->da_hs_trail = DIV_ROUND_UP(((0x4 * ui) + 0x50), cycle_time); + + if (phy_timing->da_hs_zero > phy_timing->da_hs_prepare) + phy_timing->da_hs_zero -= phy_timing->da_hs_prepare; + + phy_timing->ta_go = 4U * phy_timing->lpx; + phy_timing->ta_sure = 3U * phy_timing->lpx / 2U; + phy_timing->ta_get = 5U * phy_timing->lpx; + phy_timing->da_hs_exit = 2U * phy_timing->lpx; + + phy_timing->clk_hs_zero = DIV_ROUND_UP(0x150U, cycle_time); + phy_timing->clk_hs_trail = DIV_ROUND_UP(0x64U, cycle_time) + 0xaU; + + phy_timing->clk_hs_prepare = DIV_ROUND_UP(0x40U, cycle_time); + phy_timing->clk_hs_post = DIV_ROUND_UP(80U + 52U * ui, cycle_time); + phy_timing->clk_hs_exit = 2U * phy_timing->lpx; +} + +static void mtk_dsi_rxtx_control(u32 mode_flags, u32 lanes) +{ + u32 tmp_reg = 0; + + switch (lanes) { + case 1: + tmp_reg = 1 << 2; + break; + case 2: + tmp_reg = 3 << 2; + break; + case 3: + tmp_reg = 7 << 2; + break; + case 4: + default: + tmp_reg = 0xf << 2; + break; + } + + tmp_reg |= (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6; + tmp_reg |= (mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3; + + dsi_write32(&dsi->dsi_txrx_ctrl, tmp_reg); +} + +static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, + const struct edid *edid) +{ + u32 hsync_active_byte; + u32 hbp_byte; + u32 hfp_byte; + u32 vbp_byte; + u32 vfp_byte; + u32 bpp; + u32 packet_fmt; + u32 hactive; + + if (format == MIPI_DSI_FMT_RGB565) + bpp = 2; + else + bpp = 3; + + vbp_byte = edid->mode.vbl - edid->mode.vso - edid->mode.vspw - + edid->mode.vborder; + vfp_byte = edid->mode.vso - edid->mode.vborder; + + + dsi_write32(&dsi->dsi_vsa_nl, edid->mode.vspw); + dsi_write32(&dsi->dsi_vbp_nl, vbp_byte); + dsi_write32(&dsi->dsi_vfp_nl, vfp_byte); + dsi_write32(&dsi->dsi_vact_nl, edid->mode.va); + + if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) + hbp_byte = (edid->mode.hbl - edid->mode.hso - edid->mode.hspw - + edid->mode.hborder) * bpp - 10; + else + hbp_byte = (edid->mode.hbl - edid->mode.hso - + edid->mode.hborder) * bpp - 10; + + hsync_active_byte = edid->mode.hspw * bpp - 10; + hfp_byte = (edid->mode.hso - edid->mode.hborder) * bpp - 12; + + dsi_write32(&dsi->dsi_hsa_wc, hsync_active_byte); + dsi_write32(&dsi->dsi_hbp_wc, hbp_byte); + dsi_write32(&dsi->dsi_hfp_wc, hfp_byte); + + switch (format) { + case MIPI_DSI_FMT_RGB888: + packet_fmt = PACKED_PS_24BIT_RGB888; + break; + case MIPI_DSI_FMT_RGB666: + packet_fmt = LOOSELY_PS_18BIT_RGB666; + break; + case MIPI_DSI_FMT_RGB666_PACKED: + packet_fmt = PACKED_PS_18BIT_RGB666; + break; + case MIPI_DSI_FMT_RGB565: + packet_fmt = PACKED_PS_16BIT_RGB565; + break; + default: + packet_fmt = PACKED_PS_24BIT_RGB888; + break; + } + + hactive = edid->mode.ha; + packet_fmt |= (hactive * bpp) & DSI_PS_WC; + + dsi_write32(&dsi->dsi_psctrl, 0x2c << 24 | packet_fmt); + dsi_write32(&dsi->dsi_size_con, edid->mode.va << 16 | hactive); +} + +static void mtk_dsi_start(void) +{ + dsi_write32(&dsi->dsi_start, 0); + dsi_write32(&dsi->dsi_start, 1); +} + +static void mtk_dsi_cmdq(u8 *data, u8 len) +{ + struct stopwatch sw; + u8 *tx_buf = data; + u8 cmdq_size; + u32 reg_val, cmdq_mask, i, config, cmdq_off, type, intsta_0; + + switch (len) { + case 0: + return; + + case 1: + type = MIPI_DSI_DCS_SHORT_WRITE; + break; + + case 2: + type = MIPI_DSI_DCS_SHORT_WRITE_PARAM; + break; + + default: + type = MIPI_DSI_DCS_LONG_WRITE; + break; + } + + if (MTK_DSI_HOST_IS_READ(type)) + config = BTA; + else + config = (len > 2) ? LONG_PACKET : SHORT_PACKET; + + if (len > 2) { + cmdq_size = 1 + (len + 3) / 4; + cmdq_off = 4; + cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1; + reg_val = (len << 16) | (type << 8) | config; + } else { + cmdq_size = 1; + cmdq_off = 2; + cmdq_mask = CONFIG | DATA_ID; + reg_val = (type << 8) | config; + } + + for (i = 0; i < len; i++) + dsi_clrsetbits_le32(&dsi->dsi_cmdq0 + ((cmdq_off + i) & (~0x3)), + (0xff << (((i + cmdq_off) & 3) * 8)), + tx_buf[i] << (((i + cmdq_off) & 3) * 8)); + + dsi_clrsetbits_le32(&dsi->dsi_cmdq0, cmdq_mask, reg_val); + dsi_clrsetbits_le32(&dsi->dsi_cmdq_size, CMDQ_SIZE, cmdq_size); + dsi_write32(&dsi->dsi_intsta, 0); + mtk_dsi_start(); + + stopwatch_init_usecs_expire(&sw, 400); + do { + intsta_0 = read32(&dsi->dsi_intsta); + if (intsta_0 & CMD_DONE_INT_FLAG) + break; + udelay(4); + } while (!stopwatch_expired(&sw)); + + if (!(intsta_0 & CMD_DONE_INT_FLAG)) + printk(BIOS_ERR, "dsi DONE INT Timeout\n"); + + dsi_write32(&dsi->dsi_start, 0); +} + +static void push_table(struct lcm_init_table *init_cmd, u32 count) +{ + u32 cmd, i; + + for (i = 0; i < count; i++) { + cmd = init_cmd[i].cmd; + + switch (cmd) { + case DELAY_CMD: + mdelay(init_cmd[i].cmd); + break; + + case END_OF_TABLE: + break; + + case INIT_CMD: + default: + mtk_dsi_cmdq(init_cmd[i].data, init_cmd[i].len); + break; + } + } +} + +int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, bool dual, + const struct edid *edid, struct lcm_init_table *init_cmd, u32 count) +{ + int data_rate; + struct mtk_phy_timing phy_timing; + + mtk_dsi_phy_timing_calc(format, lanes, edid, &phy_timing); + + data_rate = mtk_dsi_phy_clk_setting(format, lanes, edid, &phy_timing); + + if (data_rate < 0) + return -1; + + mtk_dsi_reset(); + dsi_write32(&dsi->dsi_force_commit, 3); + mtk_dsi_phy_timconfig(data_rate, &phy_timing); + mtk_dsi_rxtx_control(mode_flags, lanes); + mtk_dsi_clk_hs_mode_disable(); + mtk_dsi_config_vdo_timing(mode_flags, format, edid); + mtk_dsi_clk_hs_mode_enable(); + mtk_dsi_set_mode(0); + push_table(init_cmd, count); + mtk_dsi_set_mode(mode_flags); + mtk_dsi_start(); + + return 0; +} + diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h index 88653eb..75202dd 100644 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -47,6 +47,7 @@ IOCFG_RT_BASE = IO_PHYS + 0x01C50000, IOCFG_RM_BASE = IO_PHYS + 0x01D20000, IOCFG_RB_BASE = IO_PHYS + 0x01D30000, + MIPITX_BASE = IO_PHYS + 0x01E50000, IOCFG_LB_BASE = IO_PHYS + 0x01E70000, IOCFG_LM_BASE = IO_PHYS + 0x01E80000, IOCFG_BL_BASE = IO_PHYS + 0x01E90000, @@ -64,6 +65,7 @@ DISP_AAL0_BASE = IO_PHYS + 0x04010000, DISP_GAMMA0_BASE = IO_PHYS + 0x04011000, DISP_DITHER0_BASE = IO_PHYS + 0x04012000, + DSI_BASE = IO_PHYS + 0x04014000, DISP_MUTEX_BASE = IO_PHYS + 0x04016000, SMI_LARB0 = IO_PHYS + 0x04017000, SMI_BASE = IO_PHYS + 0x04019000, diff --git a/src/soc/mediatek/mt8183/include/soc/dsi.h b/src/soc/mediatek/mt8183/include/soc/dsi.h new file mode 100644 index 0000000..7b74478 --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/dsi.h @@ -0,0 +1,484 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DSI_REG_H_ +#define _DSI_REG_H_ + +#include <edid.h> +#include <types.h> + +enum mipi_dsi_pixel_format { + MIPI_DSI_FMT_RGB888, + MIPI_DSI_FMT_RGB666, + MIPI_DSI_FMT_RGB666_PACKED, + MIPI_DSI_FMT_RGB565 +}; + +/* video mode */ +enum { + MIPI_DSI_MODE_VIDEO = BIT(0), + /* video burst mode */ + MIPI_DSI_MODE_VIDEO_BURST = BIT(1), + /* video pulse mode */ + MIPI_DSI_MODE_VIDEO_SYNC_PULSE = BIT(2), + /* enable auto vertical count mode */ + MIPI_DSI_MODE_VIDEO_AUTO_VERT = BIT(3), + /* enable hsync-end packets in vsync-pulse and v-porch area */ + MIPI_DSI_MODE_VIDEO_HSE = BIT(4), + /* disable hfront-porch area */ + MIPI_DSI_MODE_VIDEO_HFP = BIT(5), + /* disable hback-porch area */ + MIPI_DSI_MODE_VIDEO_HBP = BIT(6), + /* disable hsync-active area */ + MIPI_DSI_MODE_VIDEO_HSA = BIT(7), + /* flush display FIFO on vsync pulse */ + MIPI_DSI_MODE_VSYNC_FLUSH = BIT(8), + /* disable EoT packets in HS mode */ + MIPI_DSI_MODE_EOT_PACKET = BIT(9), + /* device supports non-continuous clock behavior (DSI spec 5.6.1) */ + MIPI_DSI_CLOCK_NON_CONTINUOUS = BIT(10), + /* transmit data in low power */ + MIPI_DSI_MODE_LPM = BIT(11) +}; + +struct dsi_regs { + u32 dsi_start; + u8 reserved0[4]; + u32 dsi_inten; + u32 dsi_intsta; + u32 dsi_con_ctrl; + u32 dsi_mode_ctrl; + u32 dsi_txrx_ctrl; + u32 dsi_psctrl; + u32 dsi_vsa_nl; + u32 dsi_vbp_nl; + u32 dsi_vfp_nl; + u32 dsi_vact_nl; + u32 dsi_lfr_con; + u32 dsi_lfr_sta; + u32 dsi_size_con; + u32 dsi_vfp_early_stop; + u32 reserved1[4]; + u32 dsi_hsa_wc; + u32 dsi_hbp_wc; + u32 dsi_hfp_wc; + u32 dsi_bllp_wc; + u32 dsi_cmdq_size; + u32 dsi_hstx_cklp_wc; + u8 reserved2[156]; + u32 dsi_phy_lccon; + u32 dsi_phy_ld0con; + u8 reserved3[4]; + u32 dsi_phy_timecon0; + u32 dsi_phy_timecon1; + u32 dsi_phy_timecon2; + u32 dsi_phy_timecon3; + u8 reserved4[16]; + u32 dsi_vm_cmd_con; + u8 reserved5[92]; + u32 dsi_force_commit; + u8 reserved6[108]; + u32 dsi_cmdq0; +}; + +check_member(dsi_regs, dsi_phy_lccon, 0x104); +check_member(dsi_regs, dsi_phy_timecon3, 0x11c); +check_member(dsi_regs, dsi_vm_cmd_con, 0x130); +check_member(dsi_regs, dsi_force_commit, 0x190); +check_member(dsi_regs, dsi_cmdq0, 0x200); +static struct dsi_regs *const dsi = (void *)DSI_BASE; + +#define DELAY_CMD 0 +#define END_OF_TABLE 1 +#define INIT_CMD 2 + +struct lcm_init_table { + u32 cmd; + u32 len; + u8 data[64]; +}; + +struct mtk_phy_timing { + u8 lpx; + u8 da_hs_prepare; + u8 da_hs_zero; + u8 da_hs_trail; + + u8 ta_go; + u8 ta_sure; + u8 ta_get; + u8 da_hs_exit; + + u8 clk_hs_zero; + u8 clk_hs_trail; + + u8 clk_hs_prepare; + u8 clk_hs_post; + u8 clk_hs_exit; +}; + +/* DSI_INTSTA */ +enum { + LPRX_RD_RDY_INT_FLAG = BIT(0), + CMD_DONE_INT_FLAG = BIT(1), + TE_RDY_INT_FLAG = BIT(2), + VM_DONE_INT_FLAG = BIT(3), + EXT_TE_RDY_INT_FLAG = BIT(4), + DSI_BUSY = BIT(31), +}; + +/* DSI_CON_CTRL */ +enum { + DSI_RESET = BIT(0), + DSI_EN = BIT(1), + DSI_DUAL = BIT(4), +}; + +/* DSI_MODE_CTRL */ +enum { + MODE = 3, + CMD_MODE = 0, + SYNC_PULSE_MODE = 1, + SYNC_EVENT_MODE = 2, + BURST_MODE = 3, + FRM_MODE = BIT(16), + MIX_MODE = BIT(17) +}; + +/* DSI_PSCTRL */ +enum { + DSI_PS_WC = 0x3fff, + DSI_PS_SEL = (3 << 16), + PACKED_PS_16BIT_RGB565 = (0 << 16), + LOOSELY_PS_18BIT_RGB666 = (1 << 16), + PACKED_PS_18BIT_RGB666 = (2 << 16), + PACKED_PS_24BIT_RGB888 = (3 << 16) +}; + +/* DSI_CMDQ_SIZE */ +enum { + CMDQ_SIZE = 0x3f, +}; + +/* DSI_PHY_LCCON */ +enum { + LC_HS_TX_EN = BIT(0), + LC_ULPM_EN = BIT(1), + LC_WAKEUP_EN = BIT(2) +}; + +/*DSI_PHY_LD0CON */ +enum { + LD0_RM_TRIG_EN = BIT(0), + LD0_ULPM_EN = BIT(1), + LD0_WAKEUP_EN = BIT(2) +}; + +enum { + LPX = (0xff << 0), + HS_PRPR = (0xff << 8), + HS_ZERO = (0xff << 16), + HS_TRAIL = (0xff << 24) +}; + +enum { + TA_GO = (0xff << 0), + TA_SURE = (0xff << 8), + TA_GET = (0xff << 16), + DA_HS_EXIT = (0xff << 24) +}; + +enum { + CONT_DET = (0xff << 0), + CLK_ZERO = (0xf << 16), + CLK_TRAIL = (0xff << 24) +}; + +enum { + CLK_HS_PRPR = (0xff << 0), + CLK_HS_POST = (0xff << 8), + CLK_HS_EXIT = (0xf << 16) +}; + +/* DSI_VM_CMD_CON */ +enum { + VM_CMD_EN = BIT(0), + TS_VFP_EN = BIT(5), +}; + +/* DSI_CMDQ0 */ +enum { + CONFIG = (0xff << 0), + SHORT_PACKET = 0, + LONG_PACKET = 2, + BTA = BIT(2), + DATA_ID = (0xff << 8), + DATA_0 = (0xff << 16), + DATA_1 = (0xff << 24), +}; + +#define MIPITX_LANE_CON 0x000c +#define MIPITX_PLL_PWR 0x0028 +#define MIPITX_PLL_CON0 0x002c +#define MIPITX_PLL_CON1 0x0030 +#define MIPITX_PLL_CON2 0x0034 +#define MIPITX_PLL_CON3 0x0038 +#define MIPITX_PLL_CON4 0x003c +#define MIPITX_D2_SW_CTL_EN 0x0144 +#define MIPITX_D0_SW_CTL_EN 0x0244 +#define MIPITX_CK_CKMODE_EN 0x0328 +#define DSI_CK_CKMODE_EN BIT(0) +#define MIPITX_CK_SW_CTL_EN 0x0344 +#define MIPITX_D1_SW_CTL_EN 0x0444 +#define MIPITX_D3_SW_CTL_EN 0x0544 +#define DSI_SW_CTL_EN BIT(0) +#define AD_DSI_PLL_SDM_PWR_ON BIT(0) +#define AD_DSI_PLL_SDM_ISO_EN BIT(1) + +#define RG_DSI_PLL_EN BIT(4) +#define RG_DSI_PLL_POSDIV (0x7 << 8) + + +/* MIPITX_REG */ +struct mipi_tx_regs { + u32 dsi_con; + u32 dsi_clock_lane; + u32 dsi_data_lane[4]; + u8 reserved0[40]; + u32 dsi_top_con; + u32 dsi_bg_con; + u8 reserved1[8]; + u32 dsi_pll_con0; + u32 dsi_pll_con1; + u32 dsi_pll_con2; + u32 dsi_pll_con3; + u32 dsi_pll_chg; + u32 dsi_pll_top; + u32 dsi_pll_pwr; + u8 reserved2[4]; + u32 dsi_rgs; + u32 dsi_gpi_en; + u32 dsi_gpi_pull; + u32 dsi_phy_sel; + u32 dsi_sw_ctrl_en; + u32 dsi_sw_ctrl_con0; + u32 dsi_sw_ctrl_con1; + u32 dsi_sw_ctrl_con2; + u32 dsi_dbg_con; + u32 dsi_dbg_out; + u32 dsi_apb_async_sta; +}; + +check_member(mipi_tx_regs, dsi_top_con, 0x40); +check_member(mipi_tx_regs, dsi_pll_pwr, 0x68); + +static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX_BASE; + +/* MIPITX_DSI_CON */ +enum { + RG_DSI_LDOCORE_EN = BIT(0), + RG_DSI_CKG_LDOOUT_EN = BIT(1), + RG_DSI_BCLK_SEL = (3 << 2), + RG_DSI_LD_IDX_SEL = (7 << 4), + RG_DSI_PHYCLK_SEL = (2 << 8), + RG_DSI_DSICLK_FREQ_SEL = BIT(10), + RG_DSI_LPTX_CLMP_EN = BIT(11) +}; + +/* MIPITX_DSI_CLOCK_LANE */ +enum { + LDOOUT_EN = BIT(0), + CKLANE_EN = BIT(1), + IPLUS1 = BIT(2), + LPTX_IPLUS2 = BIT(3), + LPTX_IMINUS = BIT(4), + LPCD_IPLUS = BIT(5), + LPCD_IMLUS = BIT(6), + RT_CODE = (0xf << 8) +}; + +/* MIPITX_DSI_TOP_CON */ +enum { + RG_DSI_LNT_INTR_EN = BIT(0), + RG_DSI_LNT_HS_BIAS_EN = BIT(1), + RG_DSI_LNT_IMP_CAL_EN = BIT(2), + RG_DSI_LNT_TESTMODE_EN = BIT(3), + RG_DSI_LNT_IMP_CAL_CODE = (0xf << 4), + RG_DSI_LNT_AIO_SEL = (7 << 8), + RG_DSI_PAD_TIE_LOW_EN = BIT(11), + RG_DSI_DEBUG_INPUT_EN = BIT(12), + RG_DSI_PRESERVE = (7 << 13) +}; + +/* MIPITX_DSI_BG_CON */ +enum { + RG_DSI_BG_CORE_EN = BIT(0), + RG_DSI_BG_CKEN = BIT(1), + RG_DSI_BG_DIV = (0x3 << 2), + RG_DSI_BG_FAST_CHARGE = BIT(4), + RG_DSI_V12_SEL = (7 << 5), + RG_DSI_V10_SEL = (7 << 8), + RG_DSI_V072_SEL = (7 << 11), + RG_DSI_V04_SEL = (7 << 14), + RG_DSI_V032_SEL = (7 << 17), + RG_DSI_V02_SEL = (7 << 20), + rsv_23 = BIT(23), + RG_DSI_BG_R1_TRIM = (0xf << 24), + RG_DSI_BG_R2_TRIM = (0xf << 28) +}; + +/* MIPITX_DSI_PLL_CON0 */ +enum { + RG_DSI_MPPLL_PLL_EN = BIT(0), + RG_DSI_MPPLL_PREDIV = (3 << 1), + RG_DSI_MPPLL_TXDIV0 = (3 << 3), + RG_DSI_MPPLL_TXDIV1 = (3 << 5), + RG_DSI_MPPLL_POSDIV = (7 << 7), + RG_DSI_MPPLL_MONVC_EN = BIT(10), + RG_DSI_MPPLL_MONREF_EN = BIT(11), + RG_DSI_MPPLL_VOD_EN = BIT(12) +}; + +/* MIPITX_DSI_PLL_CON1 */ +enum { + RG_DSI_MPPLL_SDM_FRA_EN = BIT(0), + RG_DSI_MPPLL_SDM_SSC_PH_INIT = BIT(1), + RG_DSI_MPPLL_SDM_SSC_EN = BIT(2), + RG_DSI_MPPLL_SDM_SSC_PRD = (0xffff << 16) +}; + +/* MIPITX_DSI_PLL_PWR */ +enum { + RG_DSI_MPPLL_SDM_PWR_ON = BIT(0), + RG_DSI_MPPLL_SDM_ISO_EN = BIT(1), + RG_DSI_MPPLL_SDM_PWR_ACK = BIT(8) +}; + +/* MIPI DSI Processor-to-Peripheral transaction types */ +enum { + MIPI_DSI_V_SYNC_START = 0x01, + MIPI_DSI_V_SYNC_END = 0x11, + MIPI_DSI_H_SYNC_START = 0x21, + MIPI_DSI_H_SYNC_END = 0x31, + + MIPI_DSI_COLOR_MODE_OFF = 0x02, + MIPI_DSI_COLOR_MODE_ON = 0x12, + MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22, + MIPI_DSI_TURN_ON_PERIPHERAL = 0x32, + + MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03, + MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13, + MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23, + + MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04, + MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14, + MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24, + + MIPI_DSI_DCS_SHORT_WRITE = 0x05, + MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15, + + MIPI_DSI_DCS_READ = 0x06, + + MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37, + + MIPI_DSI_END_OF_TRANSMISSION = 0x08, + + MIPI_DSI_NULL_PACKET = 0x09, + MIPI_DSI_BLANKING_PACKET = 0x19, + MIPI_DSI_GENERIC_LONG_WRITE = 0x29, + MIPI_DSI_DCS_LONG_WRITE = 0x39, + + MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c, + + MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d, + MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d, + + MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e, + MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e, + MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e, + MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e, +}; + +/* MIPI DSI Peripheral-to-Processor transaction types */ +enum { + MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT = 0x02, + MIPI_DSI_RX_END_OF_TRANSMISSION = 0x08, + MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE = 0x11, + MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE = 0x12, + MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE = 0x1a, + MIPI_DSI_RX_DCS_LONG_READ_RESPONSE = 0x1c, + MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE = 0x21, + MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE = 0x22, +}; + +/* MIPI DCS commands */ +enum { + MIPI_DCS_NOP = 0x00, + MIPI_DCS_SOFT_RESET = 0x01, + MIPI_DCS_GET_DISPLAY_ID = 0x04, + MIPI_DCS_GET_RED_CHANNEL = 0x06, + MIPI_DCS_GET_GREEN_CHANNEL = 0x07, + MIPI_DCS_GET_BLUE_CHANNEL = 0x08, + MIPI_DCS_GET_DISPLAY_STATUS = 0x09, + MIPI_DCS_GET_POWER_MODE = 0x0A, + MIPI_DCS_GET_ADDRESS_MODE = 0x0B, + MIPI_DCS_GET_PIXEL_FORMAT = 0x0C, + MIPI_DCS_GET_DISPLAY_MODE = 0x0D, + MIPI_DCS_GET_SIGNAL_MODE = 0x0E, + MIPI_DCS_GET_DIAGNOSTIC_RESULT = 0x0F, + MIPI_DCS_ENTER_SLEEP_MODE = 0x10, + MIPI_DCS_EXIT_SLEEP_MODE = 0x11, + MIPI_DCS_ENTER_PARTIAL_MODE = 0x12, + MIPI_DCS_ENTER_NORMAL_MODE = 0x13, + MIPI_DCS_EXIT_INVERT_MODE = 0x20, + MIPI_DCS_ENTER_INVERT_MODE = 0x21, + MIPI_DCS_SET_GAMMA_CURVE = 0x26, + MIPI_DCS_SET_DISPLAY_OFF = 0x28, + MIPI_DCS_SET_DISPLAY_ON = 0x29, + MIPI_DCS_SET_COLUMN_ADDRESS = 0x2A, + MIPI_DCS_SET_PAGE_ADDRESS = 0x2B, + MIPI_DCS_WRITE_MEMORY_START = 0x2C, + MIPI_DCS_WRITE_LUT = 0x2D, + MIPI_DCS_READ_MEMORY_START = 0x2E, + MIPI_DCS_SET_PARTIAL_AREA = 0x30, + MIPI_DCS_SET_SCROLL_AREA = 0x33, + MIPI_DCS_SET_TEAR_OFF = 0x34, + MIPI_DCS_SET_TEAR_ON = 0x35, + MIPI_DCS_SET_ADDRESS_MODE = 0x36, + MIPI_DCS_SET_SCROLL_START = 0x37, + MIPI_DCS_EXIT_IDLE_MODE = 0x38, + MIPI_DCS_ENTER_IDLE_MODE = 0x39, + MIPI_DCS_SET_PIXEL_FORMAT = 0x3A, + MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C, + MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E, + MIPI_DCS_SET_TEAR_SCANLINE = 0x44, + MIPI_DCS_GET_SCANLINE = 0x45, + MIPI_DCS_READ_DDB_START = 0xA1, + MIPI_DCS_READ_DDB_CONTINUE = 0xA8, +}; + +#define MTK_DSI_HOST_IS_READ(type) \ + ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \ + (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \ + (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \ + (type == MIPI_DSI_DCS_READ)) + +extern int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, bool dual, + const struct edid *edid, struct lcm_init_table *init_cmd, u32 count); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic413f524ca0b36f0b01f723a71fe9745e2710cd2 Gerrit-Change-Number: 31591 Gerrit-PatchSet: 1 Gerrit-Owner: jitao shi <jitao.shi(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: jitao shi <jitao.shi(a)mediatek.com> Gerrit-MessageType: newchange

7 50

Change in ...coreboot[master]: mediatek/mt8183: Add display driver
by yongqiang niu (Code Review) 09 Aug '19

09 Aug '19

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31478 Change subject: mediatek/mt8183: Add display driver ...................................................................... mediatek/mt8183: Add display driver BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Ic4aecc58d081f14f5d136b9ff8e813e6f40f78eb Signed-off-by: Yongqiang Niu <yongqiang.niu(a)mediatek.com> --- M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/Makefile.inc A src/soc/mediatek/mt8183/ddp.c M src/soc/mediatek/mt8183/include/soc/addressmap.h A src/soc/mediatek/mt8183/include/soc/ddp.h 5 files changed, 602 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/31478/1 diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index e1d8f5f..a089236 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -13,9 +13,14 @@ * GNU General Public License for more details. */ +#include <bootmode.h> +#include <console/console.h> #include <device/device.h> +#include <edid.h> +#include <soc/ddp.h> #include <soc/gpio.h> #include <soc/mmu_operations.h> +#include <soc/mtcmos.h> #include <soc/usb.h> static void configure_emmc(void) @@ -37,8 +42,36 @@ setup_usb_host(); } +static void display_startup(void) +{ + int ret = 0; + struct edid edid; + + edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); + + mtk_ddp_init(); + if (ret < 0) { + printk(BIOS_ERR, "dsi init fail\n"); + return; + } + + mtk_ddp_mode_set(&edid); + + set_vbe_mode_info_valid(&edid, (uintptr_t)0); +} + static void mainboard_init(struct device *dev) { + if (display_init_required()) { + printk(BIOS_INFO, "start display init.\n"); + mtcmos_display_power_on(); + mtcmos_protect_display_bus(); + + display_startup(); + } else { + printk(BIOS_INFO, "Skipping display init.\n"); + } + configure_emmc(); configure_usb(); } diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 5770a83..225a969 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -49,6 +49,7 @@ ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c ramstage-y += ../common/wdt.c +ramstage-y += ddp.c CPPFLAGS_common += -Isrc/soc/mediatek/mt8183/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include diff --git a/src/soc/mediatek/mt8183/ddp.c b/src/soc/mediatek/mt8183/ddp.c new file mode 100644 index 0000000..2e2c0d2 --- /dev/null +++ b/src/soc/mediatek/mt8183/ddp.c @@ -0,0 +1,229 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <edid.h> +#include <stdlib.h> +#include <string.h> +#include <stddef.h> +#include <soc/addressmap.h> +#include <soc/ddp.h> + +#define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16) +#define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16) + +static void disp_config_main_path_connection(void) +{ + write32(&mmsys_cfg->disp_ovl0_mout_en, OVL0_MOUT_EN_OVL0_2L); + + write32(&mmsys_cfg->disp_ovl0_2l_mout_en, OVL0_2L_MOUT_EN_DISP_PATH0); + + write32(&mmsys_cfg->disp_path0_sel_in, DISP_PATH0_SEL_IN_OVL0_2L); + + write32(&mmsys_cfg->disp_rdma0_sout_sel_in, RDMA0_SOUT_SEL_IN_COLOR); + + write32(&mmsys_cfg->disp_dither0_mout_en, DITHER0_MOUT_EN_DISP_DSI0); + + write32(&mmsys_cfg->dsi0_sel_in, DSI0_SEL_IN_DITHER0_MOUT); +} + +static void disp_config_main_path_mutex(void) +{ + write32(&disp_mutex->mutex[0].mod, MUTEX_MOD_MAIN_PATH); + + /* Clock source from DSI0 */ + write32(&disp_mutex->mutex[0].ctl, + MUTEX_SOF_DSI0 | (MUTEX_SOF_DSI0 << 6)); + write32(&disp_mutex->mutex[0].en, BIT(0)); +} + +static void ovl_set_roi(u32 idx, u32 width, u32 height, u32 color) +{ + write32(&disp_ovl[idx]->roi_size, height << 16 | width); + write32(&disp_ovl[idx]->roi_bgclr, color); +} + +static void ovl_layer_enable(u32 idx) +{ + write32(&disp_ovl[idx]->rdma[0].ctrl, BIT(0)); + write32(&disp_ovl[idx]->rdma[0].mem_gmc_setting, RDMA_MEM_GMC); + + setbits_le32(&disp_ovl[idx]->src_con, BIT(0)); +} + +static void ovl_bgclr_in_sel(u32 idx) +{ + setbits_le32(&disp_ovl[idx]->datapath_con, BIT(2)); +} + +static void rdma_start(u32 idx) +{ + setbits_le32(&disp_rdma[idx]->global_con, RDMA_ENGINE_EN); +} + +static void rdma_config(u32 idx, u32 width, u32 height, u32 vrefresh) +{ + u32 threshold; + u32 reg; + u32 fifo_size; + + /* Config width */ + clrsetbits_le32(&disp_rdma[idx]->size_con_0, 0x1FFF, width); + + /* Config height */ + clrsetbits_le32(&disp_rdma[idx]->size_con_1, 0xFFFFF, height); + + /* + * Enable FIFO underflow since DSI and DPI can't be blocked. Keep the + * FIFO pseudo size reset default of 8 KiB. Set the output threshold to + * 6 microseconds with 7/6 overhead to account for blanking, and with a + * pixel depth of 4 bytes: + */ + + fifo_size = RDMA_FIFO_SIZE_0 * KiB; + + threshold = width * height * vrefresh * 4 * 7 / 1000000; + + if (threshold > fifo_size) + threshold = fifo_size; + + reg = RDMA_FIFO_UNDERFLOW_EN | + RDMA_FIFO_PSEUDO_SIZE(fifo_size) | + RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); + + write32(&disp_rdma[idx]->fifo_con, reg); +} + +static void color_start(u32 width, u32 height) +{ + write32(&disp_color->width, width); + write32(&disp_color->height, height); + write32(&disp_color->cfg_main, COLOR_BYPASS_ALL | COLOR_SEQ_SEL); + write32(&disp_color->start, BIT(0)); +} + +static void aal_start(u32 width, u32 height) +{ + write32(&disp_aal->size, height << 16 | width); + write32(&disp_aal->en, PQ_EN); +} + +static void ccorr_start(u32 width, u32 height) +{ + write32(&disp_ccorr->size, height << 16 | width); + write32(&disp_ccorr->cfg, PQ_RELAY_MODE); + write32(&disp_ccorr->en, PQ_EN); +} + +static void dither_start(u32 width, u32 height) +{ + write32(&disp_dither->size, height << 16 | width); + write32(&disp_dither->cfg, PQ_RELAY_MODE); + write32(&disp_dither->en, PQ_EN); +} + +static void gamma_start(u32 width, u32 height) +{ + write32(&disp_gamma->size, height << 16 | width); + write32(&disp_gamma->en, PQ_EN); +} + +static void ovl_layer_config(u32 idx, u32 fmt, u32 bpp, u32 width, u32 height) +{ + write32(&disp_ovl[idx]->layer[0].con, fmt << 12); + write32(&disp_ovl[idx]->layer[0].src_size, height << 16 | width); + write32(&disp_ovl[idx]->layer[0].pitch, (width * bpp) & 0xFFFF); + + ovl_layer_enable(idx); +} + +static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh) +{ + u32 idx = 0; + + /* Setup OVL */ + for (idx = 0; idx < MAIN_PATH_OVL_NR; idx++) { + u32 color = 0; + + if (idx == 0) + color = 0xFF0000FF; + + ovl_set_roi(idx, width, height, color); + } + + /* Setup RDMA0 */ + idx = 0; + rdma_config(idx, width, height, vrefresh); + + /* Setup Color */ + color_start(width, height); + + /* Setup CCORR */ + ccorr_start(width, height); + + /* Setup AAL */ + aal_start(width, height); + + /* Setup GAMMA */ + gamma_start(width, height); + + /* Setup DITHER */ + dither_start(width, height); + + /* Setup main path connection */ + disp_config_main_path_connection(); + + /* Setup main path mutex */ + disp_config_main_path_mutex(); +} + +static void disp_clock_on(void) +{ + clrbits_le32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_DISP_ALL); + + clrbits_le32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DISP_DSI0 | + CG_CON1_DISP_DSI0_INTERFACE); +} + +static void disp_m4u_port_off(void) +{ + write32((void *)(SMI_LARB0 + 0x380), 0); +} + +void mtk_ddp_init(void) +{ + disp_clock_on(); + disp_m4u_port_off(); +} + +void mtk_ddp_mode_set(const struct edid *edid) +{ + u32 fmt = OVL_INFMT_RGBA8888; + u32 bpp = edid->framebuffer_bits_per_pixel / 8; + u32 idx = 0; + u32 width = edid->mode.ha; + u32 height = edid->mode.va; + u32 vrefresh = edid->mode.refresh; + + main_disp_path_setup(width, height, vrefresh); + + rdma_start(idx); + + ovl_layer_config(idx, fmt, bpp, width, height); + + ovl_bgclr_in_sel(idx+1); +} diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h index d41b2b9..88653eb 100644 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -53,6 +53,19 @@ IOCFG_LT_BASE = IO_PHYS + 0x01F20000, IOCFG_TL_BASE = IO_PHYS + 0x01F30000, SSUSB_SIF_BASE = IO_PHYS + 0x01F40300, + MMSYS_BASE = IO_PHYS + 0x04000000, + DISP_OVL0_BASE = IO_PHYS + 0x04008000, + DISP_OVL0_2L_BASE = IO_PHYS + 0x04009000, + DISP_OVL1_2L_BASE = IO_PHYS + 0x0400A000, + DISP_RDMA0_BASE = IO_PHYS + 0x0400B000, + DISP_RDMA1_BASE = IO_PHYS + 0x0400C000, + DISP_COLOR0_BASE = IO_PHYS + 0x0400E000, + DISP_CCORR0_BASE = IO_PHYS + 0x0400F000, + DISP_AAL0_BASE = IO_PHYS + 0x04010000, + DISP_GAMMA0_BASE = IO_PHYS + 0x04011000, + DISP_DITHER0_BASE = IO_PHYS + 0x04012000, + DISP_MUTEX_BASE = IO_PHYS + 0x04016000, + SMI_LARB0 = IO_PHYS + 0x04017000, SMI_BASE = IO_PHYS + 0x04019000, }; diff --git a/src/soc/mediatek/mt8183/include/soc/ddp.h b/src/soc/mediatek/mt8183/include/soc/ddp.h new file mode 100644 index 0000000..38f66e8 --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/ddp.h @@ -0,0 +1,326 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DDP_REG_H_ +#define _DDP_REG_H_ + +#include <soc/addressmap.h> +#include <types.h> + +#define MAIN_PATH_OVL_NR 2 + +struct mmsys_cfg_regs { + u32 reserved_0x000[64]; /* 0x000 */ + u32 mmsys_cg_con0; /* 0x100 */ + u32 mmsys_cg_set0; /* 0x104 */ + u32 mmsys_cg_clr0; /* 0x108 */ + u32 reserved_0x10C; /* 0x10C */ + u32 mmsys_cg_con1; /* 0x110 */ + u32 mmsys_cg_set1; /* 0x114 */ + u32 mmsys_cg_clr1; /* 0x118 */ + u32 reserved_0x11C[889]; /* 0x11C */ + u32 disp_ovl0_mout_en; /* 0xF00 */ + u32 disp_ovl0_2l_mout_en; /* 0xF04 */ + u32 disp_ovl1_2l_mout_en; /* 0xF08 */ + u32 disp_dither0_mout_en; /* 0xF0C */ + u32 reserved_0xF10[5]; /* 0xF10 - 0xF20 */ + u32 disp_path0_sel_in; /* 0xF24 */ + u32 reserved_0xF28; /* 0xF28 */ + u32 dsi0_sel_in; /* 0xF2C */ + u32 dpi0_sel_in; /* 0xF30 */ + u32 reserved_0xF34; /* 0xF34 */ + u32 disp_ovl0_2l_sel_in; /* 0xF38 */ + u32 reserved_0xF3C[5]; /* 0xF3C - 0xF4C */ + u32 disp_rdma0_sout_sel_in; /* 0xF50 */ + u32 disp_rdma1_sout_sel_in; /* 0xF54 */ + u32 reserved_0xF58[3]; /* 0xF58 - 0xF60 */ + u32 dpi0_sel_sout_sel_in; /* 0xF64 */ +}; + +check_member(mmsys_cfg_regs, mmsys_cg_con0, 0x100); +check_member(mmsys_cfg_regs, reserved_0x11C, 0x11C); +check_member(mmsys_cfg_regs, disp_ovl0_mout_en, 0xF00); +check_member(mmsys_cfg_regs, reserved_0xF10, 0xF10); +check_member(mmsys_cfg_regs, disp_path0_sel_in, 0xF24); +check_member(mmsys_cfg_regs, disp_ovl0_2l_sel_in, 0xF38); +check_member(mmsys_cfg_regs, reserved_0xF3C, 0xF3C); +check_member(mmsys_cfg_regs, disp_rdma0_sout_sel_in, 0xF50); +check_member(mmsys_cfg_regs, dpi0_sel_sout_sel_in, 0xF64); +static struct mmsys_cfg_regs *const mmsys_cfg = + (void *)MMSYS_BASE; + + +/* DISP_REG_CONFIG_MMSYS_CG_CON0 + Configures free-run clock gating 0 + 0: Enable clock + 1: Clock gating */ +enum { + CG_CON0_SMI_COMMON = BIT(0), + CG_CON0_SMI_LARB0 = BIT(1), + CG_CON0_GALS_COMMON0 = BIT(3), + CG_CON0_GALS_COMMON1 = BIT(4), + CG_CON0_DISP_OVL0 = BIT(20), + CG_CON0_DISP_OVL0_2L = BIT(21), + CG_CON0_DISP_OVL1_2L = BIT(22), + CG_CON0_DISP_RDMA0 = BIT(23), + CG_CON0_DISP_RDMA1 = BIT(24), + CG_CON0_DISP_WDMA0 = BIT(25), + CG_CON0_DISP_COLOR0 = BIT(26), + CG_CON0_DISP_CCORR0 = BIT(27), + CG_CON0_DISP_AAL0 = BIT(28), + CG_CON0_DISP_GAMMA0 = BIT(29), + CG_CON0_DISP_DITHER0 = BIT(30), + CG_CON0_DISP_ALL = CG_CON0_SMI_COMMON | + CG_CON0_SMI_LARB0 | + CG_CON0_GALS_COMMON0 | + CG_CON0_GALS_COMMON1 | + CG_CON0_DISP_OVL0 | + CG_CON0_DISP_OVL0_2L | + CG_CON0_DISP_RDMA0 | + CG_CON0_DISP_COLOR0 | + CG_CON0_DISP_CCORR0 | + CG_CON0_DISP_AAL0 | + CG_CON0_DISP_DITHER0 | + CG_CON0_DISP_GAMMA0, + CG_CON0_ALL = 0xffffffff +}; + +/* DISP_REG_CONFIG_MMSYS_CG_CON1 + Configures free-run clock gating 1 + 0: Enable clock + 1: Clock gating */ +enum { + CG_CON1_DISP_DSI0 = BIT(0), + CG_CON1_DISP_DSI0_INTERFACE = BIT(1), + CG_CON1_DISP_26M = BIT(7), + + CG_CON1_ALL = 0xffffffff +}; + +enum { + OVL0_MOUT_EN_RDMA0 = BIT(0), + OVL0_MOUT_EN_OVL0_2L = BIT(4), + OVL0_2L_MOUT_EN_DISP_PATH0 = BIT(0), + OVL1_2L_MOUT_EN_DISP_RDMA1 = BIT(4), + DITHER0_MOUT_EN_DISP_DSI0 = BIT(0), +}; + +enum { + DISP_PATH0_SEL_IN_OVL0 = 0, + DISP_PATH0_SEL_IN_OVL0_2L = 1, + DSI0_SEL_IN_DITHER0_MOUT = 0, + DSI0_SEL_IN_RDMA0 = 1, + RDMA0_SOUT_SEL_IN_DSI0 = 0, + RDMA0_SOUT_SEL_IN_COLOR = 1, +}; + +struct disp_mutex_regs { + u32 inten; + u32 intsta; + u32 reserved0[6]; + struct { + u32 en; + u32 dummy; + u32 rst; + u32 ctl; + u32 mod; + u32 reserved[3]; + } mutex[12]; +}; + +static struct disp_mutex_regs *const disp_mutex = (void *)DISP_MUTEX_BASE; + +enum { + MUTEX_MOD_DISP_RDMA0 = BIT(0), + MUTEX_MOD_DISP_RDMA1 = BIT(1), + MUTEX_MOD_DISP_OVL0 = BIT(9), + MUTEX_MOD_DISP_OVL0_2L = BIT(10), + MUTEX_MOD_DISP_OVL1_2L = BIT(11), + MUTEX_MOD_DISP_WDMA0 = BIT(12), + MUTEX_MOD_DISP_COLOR0 = BIT(13), + MUTEX_MOD_DISP_CCORR0 = BIT(14), + MUTEX_MOD_DISP_AAL0 = BIT(15), + MUTEX_MOD_DISP_GAMMA0 = BIT(16), + MUTEX_MOD_DISP_DITHER0 = BIT(17), + MUTEX_MOD_DISP_PWM0 = BIT(28), + MUTEX_MOD_MAIN_PATH = MUTEX_MOD_DISP_OVL0 | MUTEX_MOD_DISP_OVL0_2L | + MUTEX_MOD_DISP_RDMA0 | MUTEX_MOD_DISP_COLOR0 | + MUTEX_MOD_DISP_CCORR0 | MUTEX_MOD_DISP_AAL0 | + MUTEX_MOD_DISP_GAMMA0| MUTEX_MOD_DISP_DITHER0, +}; + +enum { + MUTEX_SOF_SINGLE_MODE = 0, + MUTEX_SOF_DSI0 = 1, + MUTEX_SOF_DPI0 = 2, +}; + +struct disp_ovl_regs { + u32 sta; + u32 inten; + u32 intsta; + u32 en; + u32 trig; + u32 rst; + u32 reserved_0x018[2]; + u32 roi_size; + u32 datapath_con; + u32 roi_bgclr; + u32 src_con; + struct { + u32 con; + u32 srckey; + u32 src_size; + u32 offset; + u32 reserved0; + u32 pitch; + u32 reserved1[2]; + } layer[4]; + u32 reserved_0x0B0[4]; + struct { + u32 ctrl; + u32 reserved0; + u32 mem_gmc_setting; + u32 mem_slow_con; + u32 fifo_ctrl; + u32 reserved1[3]; + } rdma[4]; + u32 reserved_0x140[880]; + u32 reserved_0xF00[16]; + u32 l0_addr; + u32 reserved_0xF44[7]; + u32 l1_addr; + u32 reserved_0xF64[7]; + u32 l2_addr; + u32 reserved_0xF84[7]; + u32 l3_addr; +}; + +check_member(disp_ovl_regs, reserved_0x018, 0x018); +check_member(disp_ovl_regs, roi_size, 0x020); +check_member(disp_ovl_regs, reserved_0x0B0, 0x0B0); +check_member(disp_ovl_regs, reserved_0x140, 0x140); +check_member(disp_ovl_regs, reserved_0xF00, 0xF00); +check_member(disp_ovl_regs, l0_addr, 0xF40); +check_member(disp_ovl_regs, l3_addr, 0xFA0); +static struct disp_ovl_regs *const disp_ovl[2] = { + (void *)DISP_OVL0_BASE, (void *)DISP_OVL0_2L_BASE +}; + +struct disp_rdma_regs { + u32 int_enable; + u32 int_status; + u32 reserved0[2]; + u32 global_con; + u32 size_con_0; + u32 size_con_1; + u32 target_line; + u32 reserved1; + u32 mem_con; + u32 reserved2; + u32 mem_src_pitch; + u32 mem_gmc_setting_0; + u32 mem_gmc_setting_1; + u32 mem_slow_con; + u32 mem_gmc_setting_2; + u32 fifo_con; + u32 reserved3[4]; + u32 cf[3][3]; + u32 cf_pre_add[3]; + u32 cf_post_add[3]; + u32 dummy; + u32 debug_out_sel; +}; + +enum { + RDMA_ENGINE_EN = BIT(0), + RDMA_FIFO_UNDERFLOW_EN = BIT(31), + RDMA_FIFO_SIZE_0 = 5, /* 5K */ + RDMA_VREFRESH = 60, /* vrefresh 60HZ */ + RDMA_MEM_GMC = 0x40402020, +}; + +check_member(disp_rdma_regs, debug_out_sel, 0x94); +static struct disp_rdma_regs *const disp_rdma[2] = { + (void *)DISP_RDMA0_BASE, + (void *)DISP_RDMA1_BASE, +}; + +struct disp_color_regs { + u8 reserved0[1024]; + u32 cfg_main; + u8 reserved1[2044]; + u32 start; + u8 reserved2[76]; + u32 width; + u32 height; +}; + +check_member(disp_color_regs, cfg_main, 0x400); +check_member(disp_color_regs, start, 0xC00); +check_member(disp_color_regs, width, 0xC50); +check_member(disp_color_regs, height, 0xC54); +static struct disp_color_regs *const disp_color = (void *)DISP_COLOR0_BASE; + +enum { + COLOR_BYPASS_ALL = BIT(7), + COLOR_SEQ_SEL = BIT(13), +}; + +struct disp_pq_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 status; + u32 reserved0[3]; + u32 cfg; + u32 reserved1[3]; + u32 size; +}; + +enum { + PQ_EN = BIT(0), + PQ_RELAY_MODE = BIT(0), +}; + +static struct disp_pq_regs *const disp_ccorr = (void *)DISP_CCORR0_BASE; + +static struct disp_pq_regs *const disp_aal = (void *)DISP_AAL0_BASE; + +static struct disp_pq_regs *const disp_gamma = (void *)DISP_GAMMA0_BASE; + +static struct disp_pq_regs *const disp_dither = (void *)DISP_DITHER0_BASE; + +enum OVL_INPUT_FORMAT { + OVL_INFMT_RGB565 = 0, + OVL_INFMT_RGB888 = 1, + OVL_INFMT_RGBA8888 = 2, + OVL_INFMT_ARGB8888 = 3, + OVL_INFMT_UYVY = 4, + OVL_INFMT_YUYV = 5, + OVL_INFMT_UNKNOWN = 16, + + OVL_COLOR_BASE = 30, + OVL_INFMT_BGR565 = OVL_INFMT_RGB565 + OVL_COLOR_BASE, + OVL_INFMT_BGR888 = OVL_INFMT_RGB888 + OVL_COLOR_BASE, + OVL_INFMT_BGRA8888 = OVL_INFMT_RGBA8888 + OVL_COLOR_BASE, + OVL_INFMT_ABGR8888 = OVL_INFMT_ARGB8888 + OVL_COLOR_BASE, +}; + +void mtk_ddp_init(void); +void mtk_ddp_mode_set(const struct edid *edid); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4aecc58d081f14f5d136b9ff8e813e6f40f78eb Gerrit-Change-Number: 31478 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-MessageType: newchange

9 61

Change in ...coreboot[master]: WIP: riscv: Implement FIT for RISC-V
by Philipp Hug (Code Review) 08 Aug '19

08 Aug '19

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31215 Change subject: WIP: riscv: Implement FIT for RISC-V ...................................................................... WIP: riscv: Implement FIT for RISC-V Change-Id: Ic50f14a4f483d904db590ecd53bb1fc5bdeb06d6 --- M payloads/Kconfig M src/arch/riscv/Makefile.inc A src/arch/riscv/fit_payload.c M src/soc/sifive/fu540/Kconfig 4 files changed, 171 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/31215/1 diff --git a/payloads/Kconfig b/payloads/Kconfig index c7a7ba6..0c5ce8f 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -30,7 +30,7 @@ config PAYLOAD_FIT bool "A FIT payload" - depends on ARCH_ARM64 + depends on ARCH_ARM64 || ARCH_RISCV select PAYLOAD_FIT_SUPPORT help Select this option if you have a payload image (a FIT file) which diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index e4c8468..12609d4 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -139,6 +139,7 @@ ramstage-y += tables.c ramstage-y += payload.S ramstage-$(ARCH_RISCV_PMP) += pmp.c +ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c ramstage-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ diff --git a/src/arch/riscv/fit_payload.c b/src/arch/riscv/fit_payload.c new file mode 100644 index 0000000..2176095 --- /dev/null +++ b/src/arch/riscv/fit_payload.c @@ -0,0 +1,166 @@ +/* + * Copyright 2013 Google Inc. + * Copyright 2018 Facebook, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <bootmem.h> +#include <stdlib.h> +#include <program_loading.h> +#include <string.h> +#include <commonlib/compression.h> +#include <commonlib/cbfs_serialized.h> +#include <lib.h> +#include <fit.h> +#include <endian.h> + +#define MAX_KERNEL_SIZE (64*MiB) + +static bool fit_place_kernel(const struct range_entry *r, void *arg) +{ + struct region *region = arg; + resource_t start; + + if (range_entry_tag(r) != BM_MEM_RAM) + return true; + + /** + * The Image must be placed text_offset bytes from a 2MB aligned base + * address anywhere in usable system RAM and called there. The region + * between the 2 MB aligned base address and the start of the image has + * no special significance to the kernel, and may be used for other + * purposes. + * + * If the reserved memory (BL31 for example) is smaller than text_offset + * we can use the 2 MiB base address, otherwise use the next 2 MiB page. + * It's not mandatory, but wastes less memory below the kernel. + */ + start = ALIGN_DOWN(range_entry_base(r), 2 * MiB); + + if (start < range_entry_base(r)) + start += 2 * MiB; + /** + * At least image_size bytes from the start of the image must be free + * for use by the kernel. + */ + if (start + region->size < range_entry_end(r)) { + region->offset = (size_t)start; + return false; + } + + return true; +} + +/** + * Place the region in free memory range. + * + * The caller has to set region->offset to the minimum allowed address. + * The region->offset is usually 0 on kernel >v4.6 and kernel_base + kernel_size + * on kernel <v4.6. + */ +static bool fit_place_mem(const struct range_entry *r, void *arg) +{ + struct region *region = arg; + resource_t start; + + if (range_entry_tag(r) != BM_MEM_RAM) + return true; + + /* Linux 4.15 doesn't like 4KiB alignment. Align to 1 MiB for now. */ + start = ALIGN_UP(MAX(region->offset, range_entry_base(r)), 1 * MiB); + + if (start + region->size < range_entry_end(r)) { + region->offset = (size_t)start; + return false; + } + + return true; +} + +bool fit_payload_arch(struct prog *payload, struct fit_config_node *config, + struct region *kernel, + struct region *fdt, + struct region *initrd) +{ + bool place_anywhere; + void *arg = NULL; + + if (!config->fdt || !fdt) { + printk(BIOS_CRIT, "CRIT: Providing a valid FDT is mandatory to " + "boot an RISCV kernel!\n"); + return false; + } + + /* Update kernel size from image header, if possible */ + kernel->size = 0x2000000; //get_kernel_size(config->kernel_node); + printk(BIOS_DEBUG, "FIT: Using kernel size of 0x%zx bytes\n", + kernel->size); + + + /** + * The code assumes that bootmem_walk provides a sorted list of memory + * regions, starting from the lowest address. + * The order of the calls here doesn't matter, as the placement is + * enforced in the called functions. + * For details check code on top. + */ + + if (!bootmem_walk(fit_place_kernel, kernel)) + return false; + + /* Mark as reserved for future allocations. */ + bootmem_add_range(kernel->offset, kernel->size, BM_MEM_PAYLOAD); + + /** + * NOTE: versions prior to v4.6 cannot make use of memory below the + * physical offset of the Image so it is recommended that the Image be + * placed as close as possible to the start of system RAM. + * + * For kernel <v4.6 the INITRD and FDT can't be placed below the kernel. + * In that case set region offset to an address on top of kernel. + */ + + place_anywhere = false; + printk(BIOS_DEBUG, "FIT: Placing FDT and INITRD %s\n", + place_anywhere ? "anywhere" : "on top of kernel"); + + /* Place INITRD */ + if (config->ramdisk) { + initrd->offset = 0; + + if (!bootmem_walk(fit_place_mem, initrd)) + return false; + /* Mark as reserved for future allocations. */ + bootmem_add_range(initrd->offset, initrd->size, BM_MEM_PAYLOAD); + } + + /* Place FDT */ + if (place_anywhere) + fdt->offset = 0; + else + fdt->offset = kernel->offset + kernel->size; + + if (!bootmem_walk(fit_place_mem, fdt)) + return false; + /* Mark as reserved for future allocations. */ + bootmem_add_range(fdt->offset, fdt->size, BM_MEM_PAYLOAD); + + /* Kernel expects FDT as argument */ + arg = (void *)fdt->offset; + + prog_set_entry(payload, (void *)kernel->offset, arg); + + bootmem_dump_ranges(); + + return true; +} diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig index 6ebde33..20645da 100644 --- a/src/soc/sifive/fu540/Kconfig +++ b/src/soc/sifive/fu540/Kconfig @@ -49,4 +49,7 @@ int default 0 +config HEAP_SIZE + default 0x10000 + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic50f14a4f483d904db590ecd53bb1fc5bdeb06d6 Gerrit-Change-Number: 31215 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-MessageType: newchange

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coreboot-gerrit February 2019