coreboot-gerrit February 2019

coreboot-gerrit@coreboot.org

1 participants
1249 discussions

Change in ...coreboot[master]: [RFC] Initial commit to support SKL SP and OCP Tiogapass platform
by Name of user not set (Code Review) 03 Dec '19

03 Dec '19

Name of user not set #1002246 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31205 Change subject: [RFC] Initial commit to support SKL SP and OCP Tiogapass platform ...................................................................... [RFC] Initial commit to support SKL SP and OCP Tiogapass platform Summary: This commit adds support for SK SP and OCP Tiogapass platform: * Added microcode files. * Added FSP header files. * Updated skylake soc code to accomodate FSP 2.0. * Added tiogapass platform code to accomodate FSP 2.0. With this commit, it is able to build coreboot.rom image. The 3 FSP binaries are added to the coreboot image. It looks okay by examining the coreboot.rom file through ifdtool command. However, when booting with this image, no postcode is observed on port 80, no UART message shows up. Debugging is on-going. This commit is submitted as draft to enable early review feedback. Change-Id: I389355162eb9515b533a8d7f77cc8f03b8beb019 Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> test Change-Id: I033a52bc3f0b86f0ec1db8325b7435d20d194fda --- M src/Kconfig M src/drivers/intel/fsp2_0/include/fsp/api.h A src/mainboard/ocp/tiogapass/Kconfig A src/mainboard/ocp/tiogapass/Kconfig.name A src/mainboard/ocp/tiogapass/Makefile.inc A src/mainboard/ocp/tiogapass/acpi/mainboard.asl A src/mainboard/ocp/tiogapass/board_id.c A src/mainboard/ocp/tiogapass/board_id.h A src/mainboard/ocp/tiogapass/board_info.txt A src/mainboard/ocp/tiogapass/bootblock.c A src/mainboard/ocp/tiogapass/cmos.default A src/mainboard/ocp/tiogapass/cmos.layout A src/mainboard/ocp/tiogapass/devicetree.cb A src/mainboard/ocp/tiogapass/dsdt.asl A src/mainboard/ocp/tiogapass/gpio.h A src/mainboard/ocp/tiogapass/pei_data.c A src/mainboard/ocp/tiogapass/ramstage.c A src/mainboard/ocp/tiogapass/romstage.c A src/mainboard/ocp/tiogapass/spd/Makefile.inc A src/mainboard/ocp/tiogapass/spd/spd.h A src/mainboard/ocp/tiogapass/spd/spd_util.c M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/include/fsp20/soc/ramstage.h M src/soc/intel/skylake/irq.c M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/soc/intel/skylake/vr_config.c M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DebugSupport.h A src/vendorcode/intel/fsp/fsp2_0/skykabylake/FirmwareVersionInfoHob.h A src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h A src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h A src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h A src/vendorcode/intel/fsp/fsp2_0/skykabylake/FsptUpd.h 34 files changed, 1,968 insertions(+), 162 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/31205/1 diff --git a/src/Kconfig b/src/Kconfig index a069f63..7de3335 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -360,6 +360,7 @@ source "src/ec/*/*/Kconfig" # FIXME move to vendorcode source "src/drivers/intel/fsp1_0/Kconfig" +source "src/drivers/intel/fsp2_0/Kconfig" source "src/southbridge/intel/common/firmware/Kconfig" source "src/vendorcode/*/Kconfig" diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 5ed3801..666020a 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -66,9 +66,9 @@ void platform_fsp_notify_status(enum fsp_notify_phase phase); /* Initialize memory margin analysis settings. */ -void setup_mma(FSP_M_CONFIG *memory_cfg); +void setup_mma(FSPM_CONFIG *memory_cfg); /* Update the SOC specific memory config param for mma. */ -void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, +void soc_update_memory_params_for_mma(FSPM_CONFIG *memory_cfg, struct mma_config_param *mma_cfg); /* diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig new file mode 100644 index 0000000..c411b15 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -0,0 +1,58 @@ +if BOARD_OCP_TIOGAPASS + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_32768 + select CONSOLE_SERIAL + select DRIVERS_UART + select GENERIC_SPD_BIN + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select EC_ACPI + select HAVE_OPTION_TABLE + select HAVE_SMI_HANDLER + select SERIRQ_CONTINUOUS_MODE + select SKYLAKE_SOC_PCH_H + select SOC_INTEL_SKYLAKE + select SUPERIO_NUVOTON_NCT6776 + select SUPERIO_NUVOTON_NCT6776_COM_A + select MAINBOARD_USES_FSP2_0 + select HAVE_CMOS_DEFAULT + + +config PLATFORM_USES_FSP2_0 + bool "FSP driver 2.0" + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_DIR + string + default "ocp/tiogapass" + +config MAINBOARD_PART_NUMBER + string + default "Tioga Pass" + +config MAINBOARD_FAMILY + string + default "OCP_TiogaPass" + +config CBFS_SIZE + hex + default 0x1000000 + +config VIRTUAL_ROM_SIZE + hex + default 0x2000000 + +config MAX_CPUS + int + default 8 + +config TPM_PIRQ + hex + default 0x18 # GPP_E0_IRQ + +endif # BOARD_OCP_TIOGAPASS diff --git a/src/mainboard/ocp/tiogapass/Kconfig.name b/src/mainboard/ocp/tiogapass/Kconfig.name new file mode 100644 index 0000000..0c57fd3 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_OCP_TIOGAPASS + bool "Tioga Pass" diff --git a/src/mainboard/ocp/tiogapass/Makefile.inc b/src/mainboard/ocp/tiogapass/Makefile.inc new file mode 100644 index 0000000..77cdb16 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/Makefile.inc @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2016 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +subdirs-y += spd + +bootblock-y += bootblock.c +romstage-y += pei_data.c +romstage-y += board_id.c + +ramstage-y += ramstage.c diff --git a/src/mainboard/ocp/tiogapass/acpi/mainboard.asl b/src/mainboard/ocp/tiogapass/acpi/mainboard.asl new file mode 100644 index 0000000..5174eeb --- /dev/null +++ b/src/mainboard/ocp/tiogapass/acpi/mainboard.asl @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/gpio.h> diff --git a/src/mainboard/ocp/tiogapass/board_id.c b/src/mainboard/ocp/tiogapass/board_id.c new file mode 100644 index 0000000..a362b08 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/board_id.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "board_id.h" +#include <ec/acpi/ec.h> +#include <stdint.h> + +/* + * Get Board ID via EC I/O port write/read + */ +int get_board_id(void) +{ + uint8_t buffer[2]; + uint8_t index; + if (send_ec_command(EC_FAB_ID_CMD) == 0) { + for (index = 0; index < sizeof(buffer); index++) + buffer[index] = recv_ec_data(); + return (buffer[1] << 8) | buffer[0]; + } + return -1; +} diff --git a/src/mainboard/ocp/tiogapass/board_id.h b/src/mainboard/ocp/tiogapass/board_id.h new file mode 100644 index 0000000..881866f --- /dev/null +++ b/src/mainboard/ocp/tiogapass/board_id.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MAINBOARD_BOARD_ID_H_ +#define _MAINBOARD_BOARD_ID_H_ + +/* Mobile Board Id 0x00 - 0xFF */ +#define BOARD_ID_SKL_A0_RVP3 0x04 +#define BOARD_ID_SKL_RVP7 0x0B + +/* 60-6F reserved for KBL RVPs */ +#define BOARD_ID_KBL_LPDDR3_RVP3 0x60 +#define BOARD_ID_KBL_LPDDR3_RVP7 0x64 + +/* Board/FAB ID Command */ +#define EC_FAB_ID_CMD 0x0D + +/* + * Returns board information (board id[15:8] and + * Fab info[7:0]) on success and < 0 on error + */ +int get_board_id(void); + +#endif /* _MAINBOARD_BOARD_ID_H_ */ diff --git a/src/mainboard/ocp/tiogapass/board_info.txt b/src/mainboard/ocp/tiogapass/board_info.txt new file mode 100644 index 0000000..25dac38 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/board_info.txt @@ -0,0 +1,5 @@ +Board name: Tioga Pass +Category: server +ROM protocol: SPI +ROM socketed: yes +Release year: 2017 diff --git a/src/mainboard/ocp/tiogapass/bootblock.c b/src/mainboard/ocp/tiogapass/bootblock.c new file mode 100644 index 0000000..cf9740d --- /dev/null +++ b/src/mainboard/ocp/tiogapass/bootblock.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/gpio.h> +#include "gpio.h" + +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> + +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) + +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't do. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + +void bootblock_mainboard_init(void) +{ + early_config_gpio(); +} + +void bootblock_mainboard_early_init(void) +{ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/ocp/tiogapass/cmos.default b/src/mainboard/ocp/tiogapass/cmos.default new file mode 100644 index 0000000..cd8bd47 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/cmos.default @@ -0,0 +1,4 @@ +boot_option=Fallback +debug_level=Spew +power_on_after_fail=Disable +nmi=Enable diff --git a/src/mainboard/ocp/tiogapass/cmos.layout b/src/mainboard/ocp/tiogapass/cmos.layout new file mode 100644 index 0000000..83a2e05 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/cmos.layout @@ -0,0 +1,117 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2016 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +#401 7 r 0 unused + +# coreboot config options: southbridge +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#544 440 r 0 unused + + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb new file mode 100644 index 0000000..9b23a0e --- /dev/null +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -0,0 +1,293 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # FSP Configuration + register "EnableAzalia" = "1" + register "DspEnable" = "1" + register "IoBufferOwnership" = "3" + register "SmbusEnable" = "1" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "0" + register "Heci3Enabled" = "0" + + register "SaGv" = "3" + register "PmTimerDisabled" = "0" + + # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s + register "PmConfigSlpS3MinAssert" = "0x02" + + # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s + register "PmConfigSlpS4MinAssert" = "0x04" + + # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s + register "PmConfigSlpSusMinAssert" = "0x03" + + # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s + register "PmConfigSlpAMinAssert" = "0x03" + + # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled + register "SerialIrqConfigSirqEnable" = "0x01" + register "SerialIrqConfigSirqMode" = "0x01" + + # VR Settings Configuration for 5 Domains + #+----------------+-------+-------+-------------+-------------+-------+ + #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | + #+----------------+-------+-------+-------------+-------------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------------+-------------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x10, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x1C, \ + .voltage_limit = 0x5F0 \ + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x88, \ + .voltage_limit = 0x5F0 \ + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x8C ,\ + .voltage_limit = 0x5F0 \ + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x8C, \ + .voltage_limit = 0x5F0 \ + }" + + # Skip coreboot MP Init + register "common_soc_config" = "{ + .use_fsp_mp_init = 1, + }" + + # Enable x1 slot + register "PcieRpEnable[7]" = "1" + register "PcieRpClkReqSupport[7]" = "1" + register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3 + + # Enable x4 slot + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4 + + # Enable Root port 6 and 13. + register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[12]" = "1" + + # Enable CLKREQ# + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqSupport[12]" = "1" + + # RP 6 uses SRCCLKREQ1# while RP `3 uses SRCCLKREQ2# + register "PcieRpClkReqNumber[5]" = "0" + register "PcieRpClkReqNumber[12]" = "1" + + register "EnableLan" = "1" + + # USB related + register "SsicPortEnable" = "1" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # OTG + register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Touch Pad + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 BT + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Touch Panel + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Front Panel + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # Front Panel + register "usb2_ports[7]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb) + register "usb2_ports[8]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb) + register "usb2_ports[9]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK + register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK + register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" # Finger print sensor + register "usb2_ports[12]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn + register "usb2_ports[13]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" # OTG + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Flex + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # IVCAM + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn + register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK + + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V + + # Must leave UART0 enabled or SD/eMMC will not work as PCI + + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0a" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x0b" + register "pirqf_routing" = "0x0b" + register "pirqg_routing" = "0x0b" + register "pirqh_routing" = "0x0b" + + register "PmTimerDisabled" = "0" + + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + [2] = 1, \ + [3] = 1, \ + [4] = 1, \ + [5] = 1, \ + [6] = 1, \ + [7] = 1, \ + }" + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoPci, \ + [PchSerialIoIndexI2C1] = PchSerialIoPci, \ + [PchSerialIoIndexI2C2] = PchSerialIoPci, \ + [PchSerialIoIndexI2C3] = PchSerialIoPci, \ + [PchSerialIoIndexI2C4] = PchSerialIoPci, \ + [PchSerialIoIndexI2C5] = PchSerialIoPci, \ + [PchSerialIoIndexSpi0] = PchSerialIoPci, \ + [PchSerialIoIndexSpi1] = PchSerialIoPci, \ + [PchSerialIoIndexUart0] = PchSerialIoPci, \ + [PchSerialIoIndexUart1] = PchSerialIoPci, \ + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ + }" + + # PL2 override 25W + register "tdp_pl2_override" = "25" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Enable/Disable VMX feature + register "VmxEnable" = "0" + # Use default SD card detect GPIO configuration + #register "sdcard_cd_gpio_default" = "GPP_A7" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 19.0 on end # UART #2 + device pci 19.1 on end # I2C #5 + device pci 19.2 on end # I2C #4 + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 on end # UART #0 + device pci 1e.1 on end # UART #1 + device pci 1e.2 on end # GSPI #0 + device pci 1e.3 on end # GSPI #1 + device pci 1e.4 off end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 off end # SDCard + device pci 1f.0 on + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE + end +end diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl new file mode 100644 index 0000000..45d9a85 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <soc/intel/skylake/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + } + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/ocp/tiogapass/gpio.h b/src/mainboard/ocp/tiogapass/gpio.h new file mode 100644 index 0000000..f8db6cd --- /dev/null +++ b/src/mainboard/ocp/tiogapass/gpio.h @@ -0,0 +1,183 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _GPIORVP8_H +#define _GPIORVP8_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* TCA6424A I/O Expander */ +#define IO_EXPANDER_BUS 4 +#define IO_EXPANDER_0_ADDR 0x22 +#define IO_EXPANDER_P0CONF 0x0C /* Port 0 conf offset */ +#define IO_EXPANDER_P0DOUT 0x04 /* Port 0 data offset */ +#define IO_EXPANDER_P1CONF 0x0D +#define IO_EXPANDER_P1DOUT 0x05 +#define IO_EXPANDER_P2CONF 0x0E +#define IO_EXPANDER_P2DOUT 0x06 +#define IO_EXPANDER_1_ADDR 0x23 + +/* GPE_EC_WAKE */ +#define GPE_EC_WAKE GPE0_LAN_WAK +#define EC_SMI_GPI GPP_I3 + +/* + * Gpio based irq for touchpad, 18th index in North Bank + * MAX_DIRECT_IRQ + GPSW_SIZE + 19 + */ +#define KBLRVP_TOUCHPAD_IRQ 33 + +#define KBLRVP_TOUCH_IRQ 31 + +#define BOARD_TOUCHPAD_NAME "touchpad" +#define BOARD_TOUCHPAD_IRQ KBLRVP_TOUCHPAD_IRQ +#define BOARD_TOUCHPAD_I2C_BUS 0 +#define BOARD_TOUCHPAD_I2C_ADDR 0x20 + +#define BOARD_TOUCHSCREEN_NAME "touchscreen" +#define BOARD_TOUCHSCREEN_IRQ KBLRVP_TOUCH_IRQ +#define BOARD_TOUCHSCREEN_I2C_BUS 0 +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4c + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +/* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF3), +/* EC_LPC_IO0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF3), +/* EC_LPC_IO1*/ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF3), +/* EC_LPC_IO2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF3), +/* EC_LPC_IO3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF3), +/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF3), +/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF3), +/* PIRQAB */ PAD_CFG_GPI(GPP_A7, NONE, DEEP), +/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), +/* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF3), +/* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), +/* PMEB */ PAD_CFG_GPI(GPP_A11, NONE, DEEP), +/* SUS_PWR_ACK_R */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), +/* PM_SUS_ESPI_RST */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF3), +/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1), +/* BT_RF_KILL */ PAD_CFG_GPO(GPP_B3, 1, DEEP), +/* EXTTS_SNI_DRV1 */ PAD_CFG_NF(GPP_B4, NONE, DEEP, NF1), +/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), +/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* GPP_B_14_SPKR */ PAD_CFG_NF(GPP_B14, 20K_PD, DEEP, NF1), +/* GSPI0_MISO */ PAD_CFG_GPO(GPP_B17, 1, DEEP), +/* PCHHOTB */ PAD_CFG_NF(GPP_B23, 20K_PD, DEEP, NF2), +/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), +/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), +/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 1, DEEP), +/* SML0_CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), +/* SML0_DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), +/* SML1_CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), +/* SML1_DATA */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), +/* UART0_RTS_N */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), +/* UART0_CTS_N */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), +/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* UART2_RTS_N */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), +/* UART2_CTS_N */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), +/* SSP0_SFRM */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), +/* SSP0_TXD */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), +/* SSP0_RXD */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), +/* SSP0_SCLK */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), +/* SATAE_IFDET */ PAD_CFG_NF(GPP_E0, 20K_PU, DEEP, NF1), +/* SATAE_IFDET */ PAD_CFG_NF(GPP_E1, 20K_PU, DEEP, NF1), +/* CPU_GP0 */ PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1), +/* SSD_SATA_DEVSLP */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), +/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), +/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), +/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), +/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), +/* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), +/* SATAXPCIE_4 */ PAD_CFG_NF(GPP_F1, 20K_PU, DEEP,NF1), +/* SATA_DEVSLP_3 */ PAD_CFG_GPI_ACPI_SCI(GPP_F5, NONE, DEEP, YES), +/* SATA_DEVSLP_4 */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), +/* SATA_SCLOCK */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), +/* SATA_SLOAD */ PAD_CFG_GPI(GPP_F11, NONE, DEEP), +/* SATA_SDATAOUT1 */ PAD_CFG_GPI_APIC(GPP_F12, NONE, DEEP), +/* SATA_SDATAOUT0 */ PAD_CFG_GPI_APIC(GPP_F13, NONE, DEEP), +/* H_SKTOCC_N */ PAD_CFG_GPI_APIC(GPP_F14, NONE, DEEP), +/* USB_OC4_R_N */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), +/* USB_OC5_R_N */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), +/* USB_OC6_R_N */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), +/* USB_OC7_R_N */ PAD_CFG_GPO(GPP_F18, 1, DEEP), +/* GPIO_PEG_RESET */ PAD_CFG_GPO(GPP_F22, 1, DEEP), +/* VCORE_VBOOST_CTRL */ PAD_CFG_GPO(GPP_F23, 0, DEEP), +/* FAN_TACH_0 */ PAD_CFG_GPO(GPP_G0, 1, DEEP), +/* FAN_TACH_1 */ PAD_CFG_GPO(GPP_G1, 1, DEEP), +/* FAN_TACH_2 */ PAD_CFG_GPI_ACPI_SCI(GPP_G2, NONE, DEEP, YES), +/* FAN_TACH_3 */ PAD_CFG_GPI_ACPI_SCI(GPP_G3, NONE, DEEP, YES), +/* FAN_TACH_4 */ PAD_CFG_GPO(GPP_G4, 1, DEEP), +/* FAN_TACH_5 */ PAD_CFG_GPI_APIC(GPP_G5, NONE, DEEP), +/* FAN_TACH_6 */ PAD_CFG_GPI_ACPI_SCI(GPP_G6, NONE, DEEP, YES), +/* FAN_TACH_7 */ PAD_CFG_GPO(GPP_G7, 1, DEEP), +/* GSXDOUT */ PAD_CFG_GPI_ACPI_SCI(GPP_G12, 20K_PD, DEEP, YES), +/* GSXSLOAD */ PAD_CFG_GPO(GPP_G13, 1, DEEP), +/* GSXDIN */ PAD_CFG_GPI_ACPI_SCI(GPP_G14, NONE, DEEP, YES), +/* GSXSRESETB */ PAD_CFG_GPO(GPP_G15, 0, DEEP), +/* GSXCLK */ PAD_CFG_GPO(GPP_G16, 0, DEEP), +/* NMIB */ PAD_CFG_GPI_APIC(GPP_G18, NONE, DEEP), +/* SMIB */ PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), +/* TEST_SETUP_MENU */ PAD_CFG_GPI_APIC(GPP_G20, NONE, DEEP), +/* P_INTF_N */ PAD_CFG_GPI_ACPI_SCI(GPP_G21, NONE, DEEP, YES), +/* PCH_PEGSLOT1 */ PAD_CFG_GPO(GPP_G22, 1, DEEP), +/* IVCAM_DFU_R */ PAD_CFG_GPO(GPP_G23, 1, DEEP), +/* SRCCLKREQB_8 */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), +/* SML2CLK */ PAD_CFG_GPI(GPP_H10, NONE, DEEP), +/* SML2DATA */ PAD_CFG_GPI(GPP_H11, NONE, DEEP), +/* SML3CLK */ PAD_CFG_GPI_APIC(GPP_H13, NONE, DEEP), +/* SML3DATA */ PAD_CFG_GPI_APIC(GPP_H14, NONE, DEEP), +/* SML3ALERTB */ PAD_CFG_GPI_APIC(GPP_H15, NONE, DEEP), +/* SML4DATA */ PAD_CFG_GPO(GPP_H17, 1, DEEP), +/* LED_DRIVE */ PAD_CFG_GPO(GPP_H23, 0, DEEP), +/* DDSP_HPD_0 */ PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), +/* DDSP_HPD_1 */ PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), +/* DDSP_HPD_2 */ PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), +/* DDSP_HPD_1 */ PAD_CFG_GPI_ACPI_SMI(GPP_I3, NONE, DEEP, YES), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_I6, 20K_PD, DEEP, NF1), +/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_I8, 20K_PD, DEEP, NF1), +/* DDPD_CTRLCLK */ PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), +/* DDPD_CTRLDATA */ PAD_CFG_NF(GPP_I10, 20K_PD, DEEP, NF1), +/* EC_PCH_ACPRESENT */ PAD_CFG_GPO(GPD1, 0, DEEP), +/* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), +/* PM_PWRBTN_R_N */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), +/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), +/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), +/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), +/* USB_WAKEOUT_N */ PAD_CFG_NF(GPD7, NONE, DEEP, NF1), +/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), +/* PCH_SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), +/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), + +}; + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), +}; + + +#endif +#endif diff --git a/src/mainboard/ocp/tiogapass/pei_data.c b/src/mainboard/ocp/tiogapass/pei_data.c new file mode 100644 index 0000000..ac4ce95 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/pei_data.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> +#include "spd/spd.h" + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + mainboard_fill_dq_map_data(&pei_data->dq_map); + mainboard_fill_dqs_map_data(&pei_data->dqs_map); + mainboard_fill_rcomp_res_data(&pei_data->RcompResistor); + mainboard_fill_rcomp_strength_data(&pei_data->RcompTarget); +} diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c new file mode 100644 index 0000000..6fef017 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/ramstage.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <console/console.h> +#include <device/i2c_simple.h> +#include <soc/ramstage.h> +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +// params->CdClock = 3; + + /* Enable Virtual Channel 1 */ +// params->PchHdaVcType = 0x1; +} + +static void ioexpander_init(void *unused) +{ + printk(BIOS_DEBUG, "Programming TCA6424A I/O expander\n"); + + /* I/O Expander 1, Port 0 Data */ + i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_0_ADDR, IO_EXPANDER_P0DOUT, + 0xF7); + /* Port 0 Configuration */ + i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_0_ADDR, IO_EXPANDER_P0CONF, + 0xE0); + + /* Port 1 Data */ + i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_0_ADDR, IO_EXPANDER_P1DOUT, + 0x9E); + /* Port 1 Configuration */ + i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_0_ADDR, IO_EXPANDER_P1CONF, + 0x8C); + + /* Port 2 Data */ + i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_0_ADDR, IO_EXPANDER_P2DOUT, + 0xDA); + /* Port 2 Configuration */ + i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_0_ADDR, IO_EXPANDER_P2CONF, + 0x08); + + /* I/O Expander 2, Port 0 Data */ + i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_1_ADDR, IO_EXPANDER_P0DOUT, + 0xFF); + /* Port 0 Configuration */ + i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_1_ADDR, IO_EXPANDER_P0CONF, + 0x00); + +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, ioexpander_init, NULL); diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c new file mode 100644 index 0000000..230cc50 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/romstage.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/byteorder.h> +#include <cbfs.h> +#include <console/console.h> +#include <fsp/api.h> +#include <gpio.h> +#include "gpio.h" +#include <soc/romstage.h> +#include <soc/gpio.h> +#include "spd/spd.h" +#include <string.h> +#include <spd_bin.h> +#include "board_id.h" + + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSPM_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + u8 spd_index = (get_board_id() >> 5) & 0x7; + + printk(BIOS_INFO, "SPD index %d\n", spd_index); +/* + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); +*/ + if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP3)) { + struct region_device spd_rdev; + +// mem_cfg->DqPinsInterleaved = 0; + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found\n"); +// mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); + /* Memory leak is ok since we have memory mapped boot media */ +// mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); + } else { /* CONFIG_BOARD_INTEL_KBLRVP7 and CONFIG_BOARD_INTEL_KBLRVP8 */ + struct spd_block blk = { + .addr_map = { 0x50, 0x51, 0x52, 0x53, }, + }; + +// mem_cfg->DqPinsInterleaved = 1; + get_spd_smbus(&blk); +// mem_cfg->MemorySpdDataLen = blk.len; +// mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; +// mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; + if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8)) { +// mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; +// mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; + } + + } +// mupd->FspmTestConfig.DmiVc1 = 1; +// if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8)) +// mem_cfg->UserBd = BOARD_TYPE_DESKTOP; +} diff --git a/src/mainboard/ocp/tiogapass/spd/Makefile.inc b/src/mainboard/ocp/tiogapass/spd/Makefile.inc new file mode 100644 index 0000000..721736d --- /dev/null +++ b/src/mainboard/ocp/tiogapass/spd/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## Copyright (C) 2015 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += spd_util.c diff --git a/src/mainboard/ocp/tiogapass/spd/spd.h b/src/mainboard/ocp/tiogapass/spd/spd.h new file mode 100644 index 0000000..a5f1af3 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/spd/spd.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#define RCOMP_TARGET_PARAMS 0x5 + +void mainboard_fill_dq_map_data(void *dq_map_ptr); +void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(void *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); + +#endif diff --git a/src/mainboard/ocp/tiogapass/spd/spd_util.c b/src/mainboard/ocp/tiogapass/spd/spd_util.c new file mode 100644 index 0000000..2c26d78 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/spd/spd_util.c @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> +#include "spd.h" + +void mainboard_fill_dq_map_data(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 2, 3, 6, 7 } }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 121, 81, 100 }; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { + 100, 40, 20, 20, 26 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 506a041..f1f03d7 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -20,6 +20,7 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 + select BOOTBLOCK_CONSOLE select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS @@ -28,43 +29,40 @@ select COMMON_FADT select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select C_ENVIRONMENT_BOOTBLOCK - select FSP_M_XIP if MAINBOARD_USES_FSP2_0 - select FSP_T_XIP if FSP_CAR select GENERIC_GPIO_LIB select HAVE_FSP_GOP - select INTEL_DESCRIPTOR_MODE_CAPABLE + select HAVE_INTEL_FIRMWARE select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER - select INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select IOAPIC select MRC_SETTINGS_PROTECT select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP select PARALLEL_MP_AP_WORK + select PCIEXP_ASPM + select PCIEXP_CLK_PM + select PCIEXP_COMMON_CLOCK + select PCIEXP_L1_SUB_STATE select PCIEX_LENGTH_64MB select REG_SCRIPT + select RTC select SA_ENABLE_DPR select SMM_TSEG select SMP - select PMC_GLOBAL_RESET_ENABLE_LOCK select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK - select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT - select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL select SOC_INTEL_COMMON_BLOCK_GSPI - select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SGX select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP - select SOC_INTEL_COMMON_BLOCK_UART select SOC_INTEL_COMMON_BLOCK_VMX select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_NHLT @@ -76,10 +74,6 @@ select TSC_SYNC_MFENCE select UDELAY_TSC -config CPU_INTEL_NUM_FIT_ENTRIES - int - default 10 - config MAINBOARD_USES_FSP2_0 bool default n @@ -88,7 +82,7 @@ def_bool y depends on MAINBOARD_USES_FSP2_0 select PLATFORM_USES_FSP2_0 - select UDK_2015_BINDING + select UDK_2017_BINDING select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select POSTCAR_CONSOLE select POSTCAR_STAGE @@ -98,7 +92,6 @@ depends on !MAINBOARD_USES_FSP2_0 select PLATFORM_USES_FSP1_1 select DISPLAY_FSP_ENTRY_POINTS - select SKIP_FSP_CAR config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC @@ -112,6 +105,10 @@ select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH +config BOOTBLOCK_RESETS + string + default "soc/intel/common/reset.c" + config CBFS_SIZE hex default 0x200000 @@ -124,6 +121,10 @@ hex default 0xfef00000 +config BOOTBLOCK_CPU_INIT + string + default "soc/intel/skylake/bootblock/bootblock.c" + config DCACHE_RAM_SIZE hex default 0x40000 @@ -162,6 +163,10 @@ help This option allows you to select MMIO Base Address of sideband bus. +config SERIAL_CPU_INIT + bool + default n + config SERIRQ_CONTINUOUS_MODE bool default n @@ -181,12 +186,31 @@ string default "8086,0406" +config UART_DEBUG + bool "Enable UART debug port." + default y + select CONSOLE_SERIAL + select DRIVERS_UART_8250MEM_32 + select NO_UART_ON_SUPERIO + +config UART_FOR_CONSOLE + int "Index for LPSS UART port to use for console" + default 2 if DRIVERS_UART_8250MEM + default 0 + help + Index for LPSS UART port to use for console: + 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2 + config SKYLAKE_SOC_PCH_H bool default n help Choose this option if you have a PCH-H chipset. +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "soc/intel/skylake/bootblock/timestamp.inc" + config NHLT_DMIC_2CH bool default n @@ -247,19 +271,37 @@ help Include DSP firmware settings for DA7219 headset codec. -config FSP_HEADER_PATH - string "Location of FSP headers" - depends on MAINBOARD_USES_FSP2_0 - # Use KabylakeFsp for both Skylake and Kabylake as it supports both. - # SkylakeFsp is FSP 1.1 and therefore incompatible. - default "3rdparty/fsp/KabylakeFspBinPkg/Include/" if SOC_INTEL_SKYLAKE - default "3rdparty/fsp/KabylakeFspBinPkg/Include/" if SOC_INTEL_KABYLAKE +choice + prompt "Cache-as-ram implementation" + default USE_SKYLAKE_CAR_NEM_ENHANCED + help + This option allows you to select how cache-as-ram (CAR) is set up. -config FSP_FD_PATH - string - depends on FSP_USE_REPO - default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" if SOC_INTEL_SKYLAKE - default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" if SOC_INTEL_KABYLAKE +config USE_SKYLAKE_CAR_NEM_ENHANCED + bool "Enhanced Non-evict mode" + select SOC_INTEL_COMMON_BLOCK_CAR + select INTEL_CAR_NEM_ENHANCED + help + A current limitation of NEM (Non-Evict mode) is that code and data + sizes are derived from the requirement to not write out any modified + cache line. With NEM, if there is no physical memory behind the + cached area, the modified data will be lost and NEM results will be + inconsistent. ENHANCED NEM guarantees that modified data is always + kept in cache while clean data is replaced. + +config USE_SKYLAKE_FSP_CAR + bool "Use FSP CAR" + select FSP_CAR + help + Use FSP APIs to initialize and tear down the Cache-As-Ram. + +endchoice + +config SKIP_FSP_CAR + bool "Skip cache as RAM setup in FSP" + default y + help + Skip Cache as RAM setup in FSP. config SPI_FLASH_INCLUDE_ALL_DRIVERS bool diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index ee2c928..c5451e6 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -2,7 +2,6 @@ subdirs-y += nhlt subdirs-y += romstage -subdirs-y += ../../../cpu/intel/common subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic @@ -11,7 +10,6 @@ subdirs-y += ../../../cpu/x86/tsc bootblock-y += bootblock/bootblock.c -bootblock-$(CONFIG_FSP_CAR) += fspcar.c bootblock-y += bootblock/cpu.c bootblock-y += i2c.c bootblock-y += bootblock/pch.c @@ -22,13 +20,13 @@ bootblock-y += pmutil.c bootblock-y += spi.c bootblock-y += lpc.c -bootblock-y += uart.c +bootblock-$(CONFIG_UART_DEBUG) += uart.c verstage-y += gspi.c verstage-y += pmutil.c verstage-y += i2c.c verstage-y += spi.c -verstage-y += uart.c +verstage-$(CONFIG_UART_DEBUG) += uart.c romstage-y += gpio.c romstage-y += gspi.c @@ -40,7 +38,7 @@ romstage-y += pmutil.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c romstage-y += spi.c -romstage-y += uart.c +romstage-$(CONFIG_UART_DEBUG) += uart.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += chip.c @@ -67,33 +65,22 @@ ramstage-y += spi.c ramstage-y += systemagent.c ramstage-y += thermal.c -ramstage-y += uart.c -ramstage-y += vr_config.c +ramstage-$(CONFIG_UART_DEBUG) += uart.c +//ramstage-y += vr_config.c smm-y += elog.c smm-y += gpio.c smm-y += p2sb.c smm-y += pmutil.c smm-y += smihandler.c -smm-y += uart.c +smm-$(CONFIG_UART_DEBUG) += uart.c postcar-y += memmap.c postcar-y += gspi.c postcar-y += spi.c -postcar-y += i2c.c -postcar-y += uart.c +postcar-$(CONFIG_UART_DEBUG) += uart.c - -# Skylake D0 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_406ex/microcode.bin -# Skylake H Q0 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_506ex/microcode.bin -# Kabylake H0, Y0 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_806ex/microcode.bin -# Kabylake HB0 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_906ex/microcode.bin -# Missing for Skylake C0 (0x406e2), Kabylake G0 (0x406e8), Kabylake HA0 (0x506e8) -# since those are probably pre-release samples. +# cpu_microcode_bins += ??? CPPFLAGS_common += -I$(src)/soc/intel/skylake CPPFLAGS_common += -I$(src)/soc/intel/skylake/include @@ -103,6 +90,7 @@ CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/skylake else CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp20 +CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/skykabylake endif # Currently used for microcode path. diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 3ade8d7..020dea3 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -20,12 +20,16 @@ #include <fsp/api.h> #include <arch/acpi.h> #include <arch/io.h> +#include <chip.h> +#include <compiler.h> +#include <bootstate.h> #include <console/console.h> #include <device/device.h> +#include <device/pci.h> #include <device/pci_ids.h> +#include <fsp/api.h> #include <fsp/util.h> #include <intelblocks/chip.h> -#include <intelblocks/itss.h> #include <intelblocks/xdci.h> #include <intelpch/lockdown.h> #include <romstage_handoff.h> @@ -34,7 +38,6 @@ #include <soc/interrupt.h> #include <soc/iomap.h> #include <soc/irq.h> -#include <soc/itss.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/systemagent.h> @@ -165,16 +168,8 @@ void soc_init_pre_device(void *chip_info) { - /* Snapshot the current GPIO IRQ polarities. FSP is setting a - * default policy that doesn't honor boards' requirements. */ - itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); - /* Perform silicon specific init. */ fsp_silicon_init(romstage_handoff_is_resume()); - - /* Restore GPIO IRQ polarities back to previous settings. */ - itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); - /* swap enabled PCI ports in device tree if needed */ pcie_override_devicetree_after_silicon_init(); } @@ -227,8 +222,9 @@ /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { - FSP_S_CONFIG *params = &supd->FspsConfig; - FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig; + FSPS_CONFIG *params = &supd->FspsConfig; +#if 0 +// FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig; static struct soc_intel_skylake_config *config; uintptr_t vbt_data = (uintptr_t)vbt_get(); int i; @@ -244,14 +240,14 @@ /* Set PsysPmax if it is available from DT */ if (config->psys_pmax) { /* PsysPmax is in unit of 1/8 Watt */ - tconfig->PsysPmax = config->psys_pmax * 8; - printk(BIOS_DEBUG, "psys_pmax = %d\n", tconfig->PsysPmax); +// tconfig->PsysPmax = config->psys_pmax * 8; +// printk(BIOS_DEBUG, "psys_pmax = %d\n", tconfig->PsysPmax); } - params->GraphicsConfigPtr = (u32) vbt_data; +// params->GraphicsConfigPtr = (u32) vbt_data; for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { - params->PortUsb20Enable[i] = +/* params->PortUsb20Enable[i] = config->usb2_ports[i].enable; params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; @@ -295,6 +291,7 @@ sizeof(params->PcieRpLtrEnable)); memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, sizeof(params->PcieRpHotPlug)); +*/ /* * PcieRpClkSrcNumber UPD is set to clock source number(0-6) for @@ -341,15 +338,6 @@ params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; params->ScsSdCardEnabled = config->ScsSdCardEnabled; - if (!!params->ScsEmmcHs400Enabled && !!config->EmmcHs400DllNeed) { - params->PchScsEmmcHs400DllDataValid = - !!config->EmmcHs400DllNeed; - params->PchScsEmmcHs400RxStrobeDll1 = - config->ScsEmmcHs400RxStrobeDll1; - params->PchScsEmmcHs400TxDataDll = - config->ScsEmmcHs400TxDataDll; - } - /* If ISH is enabled, enable ISH elements */ dev = dev_find_slot(0, PCH_DEVFN_ISH); if (dev) @@ -365,20 +353,18 @@ params->SataMode = config->SataMode; params->SataSpeedLimit = config->SataSpeedLimit; params->SataPwrOptEnable = config->SataPwrOptEnable; - params->EnableTcoTimer = !config->PmTimerDisabled; - tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; - tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; - tconfig->PowerLimit4 = config->PowerLimit4; +// tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; +// tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; /* * To disable HECI, the Psf needs to be left unlocked * by FSP till end of post sequence. Based on the devicetree * setting, we set the appropriate PsfUnlock policy in FSP, * do the changes and then lock it back in coreboot during finalize. */ - tconfig->PchSbAccessUnlock = (config->HeciEnabled == 0) ? 1 : 0; +// tconfig->PchSbAccessUnlock = (config->HeciEnabled == 0) ? 1 : 0; if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { - tconfig->PchLockDownBiosInterface = 0; +// tconfig->PchLockDownBiosInterface = 0; params->PchLockDownBiosLock = 0; params->PchLockDownSpiEiss = 0; /* @@ -390,17 +376,8 @@ */ params->SpiFlashCfgLockDown = 0; } - /* only replacing preexisting subsys ID defaults when non-zero */ - if (CONFIG_SUBSYSTEM_VENDOR_ID != 0) { - params->DefaultSvid = CONFIG_SUBSYSTEM_VENDOR_ID; - params->PchSubSystemVendorId = CONFIG_SUBSYSTEM_VENDOR_ID; - } - - if (CONFIG_SUBSYSTEM_DEVICE_ID != 0) { - params->DefaultSid = CONFIG_SUBSYSTEM_DEVICE_ID; - params->PchSubSystemId = CONFIG_SUBSYSTEM_DEVICE_ID; - } - + params->PchSubSystemVendorId = config->PchConfigSubSystemVendorId; + params->PchSubSystemId = config->PchConfigSubSystemId; params->PchPmWolEnableOverride = config->WakeConfigWolEnableOverride; params->PchPmPcieWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; params->PchPmDeepSxPol = config->PmConfigDeepSxPol; @@ -467,13 +444,13 @@ params->FastPkgCRampDisableSa = config->FastPkgCRampDisableSa; /* Enable PMC XRAM read */ - tconfig->PchPmPmcReadDisable = config->PchPmPmcReadDisable; +// tconfig->PchPmPmcReadDisable = config->PchPmPmcReadDisable; /* Enable/Disable EIST */ - tconfig->Eist = config->eist_enable; +// tconfig->Eist = config->eist_enable; /* Set TccActivationOffset */ - tconfig->TccActivationOffset = config->tcc_offset; +// tconfig->TccActivationOffset = config->tcc_offset; /* Enable VT-d and X2APIC */ if (!config->ignore_vtd && soc_is_vtd_capable()) { @@ -487,12 +464,13 @@ params->PchIoApicDeviceNumber = 31; params->PchIoApicFunctionNumber = 0; } +#endif soc_irq_settings(params); } /* Mainboard GPIO Configuration */ -__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) +__weak void mainboard_silicon_init_params(FSPS_CONFIG *params) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } diff --git a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h index e75b350..820e517 100644 --- a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h +++ b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h @@ -22,10 +22,10 @@ #include <fsp/api.h> #include <fsp/util.h> -#define FSP_SIL_UPD FSP_S_CONFIG -#define FSP_MEM_UPD FSP_M_CONFIG +#define FSP_SIL_UPD FSPS_CONFIG +#define FSP_MEM_UPD FSPM_CONFIG -void mainboard_silicon_init_params(FSP_S_CONFIG *params); +void mainboard_silicon_init_params(FSPS_CONFIG *params); void soc_fsp_load(void); void soc_init_pre_device(void *chip_info); void soc_irq_settings(FSP_SIL_UPD *params); diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c index 7b3e1bd..d26bd84 100644 --- a/src/soc/intel/skylake/irq.c +++ b/src/soc/intel/skylake/irq.c @@ -22,6 +22,7 @@ #include <soc/irq.h> #include <string.h> +#if 0 static const SI_PCH_DEVICE_INTERRUPT_CONFIG devintconfig[] = { /* * cAVS(Audio, Voice, Speech), INTA is default, programmed in @@ -216,23 +217,26 @@ DEVICE_INT_CONFIG(PCH_DEV_SLOT_ISH, PCI_FUNC(PCH_DEVFN_ISH), int_A, ISH_IRQ) }; +#endif void soc_irq_settings(FSP_SIL_UPD *params) { - uint32_t i, intdeventry; + uint32_t i; +// uint32_t i, intdeventry; u8 irq_config[PCH_MAX_IRQ_CONFIG]; - const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); - const struct soc_intel_skylake_config *config = dev->chip_info; +// const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); +// const struct soc_intel_skylake_config *config = dev->chip_info; /* Get Device Int Count */ - intdeventry = ARRAY_SIZE(devintconfig); +// intdeventry = ARRAY_SIZE(devintconfig); /* update irq table */ - memcpy((SI_PCH_DEVICE_INTERRUPT_CONFIG *) +/* memcpy((SI_PCH_DEVICE_INTERRUPT_CONFIG *) (params->DevIntConfigPtr), devintconfig, intdeventry * sizeof(SI_PCH_DEVICE_INTERRUPT_CONFIG)); params->NumOfDevIntConfig = intdeventry; +*/ /* PxRC to IRQ programming */ for (i = 0; i < PCH_MAX_IRQ_CONFIG; i++) { switch (i) { @@ -250,13 +254,15 @@ break; } } - memcpy(params->PxRcConfig, irq_config, PCH_MAX_IRQ_CONFIG); +// memcpy(params->PxRcConfig, irq_config, PCH_MAX_IRQ_CONFIG); /* GPIO IRQ Route The valid values is 14 or 15 */ - if (config->GpioIrqSelect == 0) +/* if (config->GpioIrqSelect == 0) params->GpioIrqRoute = GPIO_IRQ14; else params->GpioIrqRoute = config->GpioIrqSelect; +*/ /* SCI IRQ Select The valid values is 9, 10, 11 and 20 21, 22, 23 */ +#if 0 if (config->SciIrqSelect == 0) params->SciIrqSelect = SCI_IRQ9; else @@ -268,6 +274,7 @@ params->TcoIrqSelect = config->TcoIrqSelect; /* TCO Irq enable/disable */ params->TcoIrqEnable = config->TcoIrqEnable; +#endif } /* diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 2a60158..48f3429 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -18,6 +18,7 @@ #include <arch/io.h> #include <arch/symbols.h> #include <assert.h> +#include <compiler.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cbmem.h> @@ -37,6 +38,7 @@ #include <string.h> #include <timestamp.h> #include <security/vboot/vboot_common.h> +#include <MemInfoHob.h> #define FSP_SMBIOS_MEMORY_INFO_GUID \ { \ @@ -101,18 +103,18 @@ if (src_dimm->Status != DIMM_PRESENT) continue; - switch (memory_info_hob->MemoryType) { + switch(memory_info_hob->MemoryType) { case MRC_DDR_TYPE_DDR4: - ddr_type = MEMORY_TYPE_DDR4; + ddr_type = MEMORY_DEVICE_DDR4; break; case MRC_DDR_TYPE_DDR3: - ddr_type = MEMORY_TYPE_DDR3; + ddr_type = MEMORY_DEVICE_DDR3; break; case MRC_DDR_TYPE_LPDDR3: - ddr_type = MEMORY_TYPE_LPDDR3; + ddr_type = MEMORY_DEVICE_LPDDR3; break; default: - ddr_type = MEMORY_TYPE_UNKNOWN; + ddr_type = MEMORY_DEVICE_UNKNOWN; break; } @@ -190,19 +192,19 @@ run_postcar_phase(&pcf); } -static void cpu_flex_override(FSP_M_CONFIG *m_cfg) +static void cpu_flex_override(FSPM_CONFIG *m_cfg) { msr_t flex_ratio; - m_cfg->CpuRatioOverride = 1; +// m_cfg->CpuRatioOverride = 1; /* * Set cpuratio to that value set in bootblock, This will ensure FSPM * knows the intended flex ratio. */ flex_ratio = rdmsr(MSR_FLEX_RATIO); - m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; +// m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; } -static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, +static void soc_memory_init_params(FSPM_CONFIG *m_cfg, const struct soc_intel_skylake_config *config) { int i; @@ -215,31 +217,30 @@ * With the default stolen size of 32MB(-8MB) there is not enough space * for FBC to work with a high resolution panel. */ - m_cfg->IgdDvmt50PreAlloc = 2; - m_cfg->MmioSize = 0x800; /* 2GB in MB */ - m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; - m_cfg->IedSize = CONFIG_IED_REGION_SIZE; - m_cfg->ProbelessTrace = config->ProbelessTrace; - m_cfg->SaGv = config->SaGv; - m_cfg->UserBd = BOARD_TYPE_ULT_ULX; - m_cfg->RMT = config->Rmt; - m_cfg->CmdTriStateDis = config->CmdTriStateDis; - m_cfg->DdrFreqLimit = config->DdrFreqLimit; - m_cfg->VmxEnable = config->VmxEnable; - m_cfg->PrmrrSize = config->PrmrrSize; +// m_cfg->IgdDvmt50PreAlloc = 2; +// m_cfg->MmioSize = 0x800; /* 2GB in MB */ +// m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; +// m_cfg->IedSize = CONFIG_IED_REGION_SIZE; +// m_cfg->ProbelessTrace = config->ProbelessTrace; +// m_cfg->SaGv = config->SaGv; +// m_cfg->UserBd = BOARD_TYPE_ULT_ULX; +// m_cfg->RMT = config->Rmt; +// m_cfg->DdrFreqLimit = config->DdrFreqLimit; +// m_cfg->VmxEnable = config->VmxEnable; +// m_cfg->PrmrrSize = config->PrmrrSize; for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { if (config->PcieRpEnable[i]) mask |= (1<<i); } - m_cfg->PcieRpEnableMask = mask; +// m_cfg->PcieRpEnableMask = mask; cpu_flex_override(m_cfg); if (!config->ignore_vtd) { - m_cfg->PchHpetBdfValid = 1; - m_cfg->PchHpetBusNumber = 250; - m_cfg->PchHpetDeviceNumber = 15; - m_cfg->PchHpetFunctionNumber = 0; +// m_cfg->PchHpetBdfValid = 1; +// m_cfg->PchHpetBusNumber = 250; +// m_cfg->PchHpetDeviceNumber = 15; +// m_cfg->PchHpetFunctionNumber = 0; } } @@ -247,8 +248,8 @@ { const struct device *dev; const struct soc_intel_skylake_config *config; - FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig; + FSPM_CONFIG *m_cfg = &mupd->FspmConfig; +// FSPM_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig; dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); config = dev->chip_info; @@ -256,43 +257,43 @@ soc_memory_init_params(m_cfg, config); /* Skip creating Management Engine MBP HOB */ - m_t_cfg->SkipMbpHob = 0x01; +// m_t_cfg->SkipMbpHob = 0x01; /* Enable DMI Virtual Channel for ME */ - m_t_cfg->DmiVcm = 0x01; +// m_t_cfg->DmiVcm = 0x01; /* Enable Sending DID to ME */ - m_t_cfg->SendDidMsg = 0x01; - m_t_cfg->DidInitStat = 0x01; +// m_t_cfg->SendDidMsg = 0x01; +// m_t_cfg->DidInitStat = 0x01; /* DCI and TraceHub configs */ - m_t_cfg->PchDciEn = config->PchDciEn; - m_cfg->EnableTraceHub = config->EnableTraceHub; - m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size; - m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size; +// m_t_cfg->PchDciEn = config->PchDciEn; +// m_cfg->EnableTraceHub = config->EnableTraceHub; +// m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size; +// m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size; /* Enable SMBus controller based on config */ - m_cfg->SmbusEnable = config->SmbusEnable; +// m_cfg->SmbusEnable = config->SmbusEnable; mainboard_memory_init_params(mupd); } -void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, +void soc_update_memory_params_for_mma(FSPM_CONFIG *memory_cfg, struct mma_config_param *mma_cfg) { /* Boot media is memory mapped for Skylake and Kabylake (SPI). */ assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); - memory_cfg->MmaTestContentPtr = - (uintptr_t) rdev_mmap_full(&mma_cfg->test_content); - memory_cfg->MmaTestContentSize = - region_device_sz(&mma_cfg->test_content); - memory_cfg->MmaTestConfigPtr = - (uintptr_t) rdev_mmap_full(&mma_cfg->test_param); - memory_cfg->MmaTestConfigSize = - region_device_sz(&mma_cfg->test_param); - memory_cfg->MrcFastBoot = 0x00; - memory_cfg->SaGv = 0x02; +// memory_cfg->MmaTestContentPtr = +// (uintptr_t) rdev_mmap_full(&mma_cfg->test_content); +// memory_cfg->MmaTestContentSize = +// region_device_sz(&mma_cfg->test_content); +// memory_cfg->MmaTestConfigPtr = +// (uintptr_t) rdev_mmap_full(&mma_cfg->test_param); +// memory_cfg->MmaTestConfigSize = +// region_device_sz(&mma_cfg->test_param); +// memory_cfg->MrcFastBoot = 0x00; +// memory_cfg->SaGv = 0x02; } __weak void mainboard_memory_init_params(FSPM_UPD *mupd) diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index 4508fda..9266330 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -56,7 +56,7 @@ * | IccMax(AML-Y) | 4.1A | 28A | 24A | 24A | * +----------------+-------------+---------------+------+-----+ */ - +#if 0 static const struct { uint16_t icc_max[NUM_VR_DOMAINS]; }sku_icc_max_mapping[] = { @@ -167,12 +167,13 @@ .voltage_limit = 1520, }, }; +#endif static uint16_t get_dev_id(struct device *dev) { return pci_read_config16(dev, PCI_DEVICE_ID); } - +#if 0 static int get_kbl_sku(void) { static int sku = -1; @@ -201,7 +202,6 @@ sku = -2; return sku; } - static uint16_t get_sku_icc_max(int domain, uint16_t board_icc_max) { /* If board provided non-zero value, use it. */ @@ -229,7 +229,7 @@ cfg = chip_cfg; else cfg = &default_configs[domain]; - +/* vr_params->VrConfigEnable[domain] = cfg->vr_config_enable; vr_params->Psi1Threshold[domain] = cfg->psi1threshold; vr_params->Psi2Threshold[domain] = cfg->psi2threshold; @@ -240,9 +240,10 @@ vr_params->ImonOffset[domain] = cfg->imon_offset; vr_params->IccMax[domain] = get_sku_icc_max(domain, cfg->icc_max); vr_params->VrVoltageLimit[domain] = cfg->voltage_limit; - +*/ #if IS_ENABLED(CONFIG_PLATFORM_USES_FSP2_0) - vr_params->AcLoadline[domain] = cfg->ac_loadline; - vr_params->DcLoadline[domain] = cfg->dc_loadline; +// vr_params->AcLoadline[domain] = cfg->ac_loadline; +// vr_params->DcLoadline[domain] = cfg->dc_loadline; #endif } +#endif diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DebugSupport.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DebugSupport.h index 6983469..af0950f 100644 --- a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DebugSupport.h +++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DebugSupport.h @@ -605,7 +605,7 @@ UINT64 ELR; // Exception Link Register UINT64 SPSR; // Saved Processor Status Register UINT64 FPSR; // Floating Point Status Register - UINT64 ESR; // Exception syndrome register +// UINT64 ESR; // Exception syndrome register UINT64 FAR; // Fault Address Register } EFI_SYSTEM_CONTEXT_AARCH64; diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FirmwareVersionInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FirmwareVersionInfoHob.h new file mode 100644 index 0000000..fca01e9 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FirmwareVersionInfoHob.h @@ -0,0 +1,67 @@ +/** @file + Header file for Firmware Version Information + + Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved. + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License which accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _FIRMWARE_VERSION_INFO_HOB_H_ +#define _FIRMWARE_VERSION_INFO_HOB_H_ + +#include <Uefi/UefiMultiPhase.h> +#include <Pi/PiBootMode.h> +#include <Pi/PiHob.h> + +#pragma pack(1) +/// +/// Firmware Version Structure +/// +typedef struct { + UINT8 MajorVersion; + UINT8 MinorVersion; + UINT8 Revision; + UINT16 BuildNumber; +} FIRMWARE_VERSION; + +/// +/// Firmware Version Information Structure +/// +typedef struct { + UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name + UINT8 VersionStringIndex; ///< Offset 1 Index of Version String + FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version +} FIRMWARE_VERSION_INFO; + +#ifndef __SMBIOS_STANDARD_H__ +/// +/// The Smbios structure header. +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Handle; +} SMBIOS_STRUCTURE; +#endif + +/// +/// Firmware Version Information HOB Structure +/// +typedef struct { + EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB + SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB + UINT8 Count; ///< Offset 28 Number of FVI elements included. +/// +/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer +/// +} FIRMWARE_VERSION_INFO_HOB; +#pragma pack() + +#endif // _FIRMWARE_VERSION_INFO_HOB_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h new file mode 100644 index 0000000..cf543fe --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h @@ -0,0 +1,48 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#include <FspEas.h> + +#pragma pack(1) + +#define FSPT_UPD_SIGNATURE 0x545F445055434F53 /* 'SOCUPD_T' */ + +#define FSPM_UPD_SIGNATURE 0x4D5F445055434F53 /* 'SOCUPD_M' */ + +#define FSPS_UPD_SIGNATURE 0x535F445055434F53 /* 'SOCUPD_S' */ + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h new file mode 100644 index 0000000..a66b3306 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h @@ -0,0 +1,248 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include <FspUpd.h> + +#pragma pack(1) + + +/** FSP-M Configuration +**/ +typedef struct { + +/** Offset 0x0040 - Tseg Size + Size of SMRAM memory reserved. + 2:2 MB, 4:4 MB, 8:8 MB, 16:16 MB +**/ + UINT8 PcdSmmTsegSize; + +/** Offset 0x0041 - FSP Debug Print Level + Select the FSP debug message print level. + 0:NO DEBUG, 1:MIN DEBUG, 2:MED DEBUG, 3:VERBOSE DEBUG +**/ + UINT8 PcdFspDebugPrintErrorLevel; + +/** Offset 0x0042 - Channel 0 DIMM 0 SPD SMBus Address + SPD SMBus Address of each DIMM slot. +**/ + UINT8 PcdSpdSmbusAddress_0_0; + +/** Offset 0x0043 - Channel 0 DIMM 1 SPD SMBus Address + SPD SMBus Address of each DIMM slot. +**/ + UINT8 PcdSpdSmbusAddress_0_1; + +/** Offset 0x0044 - Channel 1 DIMM 0 SPD SMBus Address + SPD SMBus Address of each DIMM slot. +**/ + UINT8 PcdSpdSmbusAddress_1_0; + +/** Offset 0x0045 - Channel 1 DIMM 1 SPD SMBus Address + SPD SMBus Address of each DIMM slot. +**/ + UINT8 PcdSpdSmbusAddress_1_1; + +/** Offset 0x0046 - Enable Rank Margin Tool + Enable/disable Rank Margin Tool. + $EN_DIS +**/ + UINT8 PcdMrcRmtSupport; + +/** Offset 0x0047 - RMT CPGC exp_loop_cnt + Set the CPGC exp_loop_cnt field for RMT execution 2^(exp_loop_cnt -1). + 1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15 +**/ + UINT8 PcdMrcRmtCpgcExpLoopCntValue; + +/** Offset 0x0048 - RMT CPGC num_bursts + Set the CPGC num_bursts field for RMT execution 2^(num_bursts -1). + 1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15 +**/ + UINT8 PcdMrcRmtCpgcNumBursts; + +/** Offset 0x0049 - Preserve Memory Across Reset + Enable/disable memory preservation across reset. + $EN_DIS +**/ + UINT8 PcdMemoryPreservation; + +/** Offset 0x004A - Fast Boot + Enable/disable Fast Boot function. Once enabled, all following boots will use the + presaved MRC data to improve the boot performance. + $EN_DIS +**/ + UINT8 PcdFastBoot; + +/** Offset 0x004B - ECC Support + Enable/disable ECC Support. + $EN_DIS +**/ + UINT8 PcdEccSupport; + +/** Offset 0x004C - HSUART Device + Select the PCI High Speed UART Device for Serial Port. + 0:HSUART0, 1:HSUART1, 2:HSUART2 +**/ + UINT8 PcdHsuartDevice; + +/** Offset 0x004D - Memory Down + Enable/disable Memory Down function. + $EN_DIS +**/ + UINT8 PcdMemoryDown; + +/** Offset 0x004E +**/ + UINT32 PcdMemoryDownConfigPtr; + +/** Offset 0x0052 - SATA Controller 0 + Enable/disable SATA Controller 0. + $EN_DIS +**/ + UINT8 PcdEnableSATA0; + +/** Offset 0x0053 - SATA Controller 1 + Enable/disable SATA Controller 1. + $EN_DIS +**/ + UINT8 PcdEnableSATA1; + +/** Offset 0x0054 - Intel Quick Assist Technology + Enable/disable Intel Quick Assist Technology. + $EN_DIS +**/ + UINT8 PcdEnableIQAT; + +/** Offset 0x0055 - SPD Write Disable + Select SMBus SPD Write Enable State (Default: 0 = [FORCE_ENABLE], 1 = [FORCE_DISABLE]) + 0:Force Enable, 1:Force Disable +**/ + UINT8 PcdSmbusSpdWriteDisable; + +/** Offset 0x0056 - ME_SHUTDOWN Message + Enable/Disable sending ME_SHUTDOWN message to ME, refer to FSP Integration Guide + for details. + $EN_DIS +**/ + UINT8 PcdEnableMeShutdown; + +/** Offset 0x0057 - XHCI Controller + Enable / Disable XHCI controller + $EN_DIS +**/ + UINT8 PcdEnableXhci; + +/** Offset 0x0058 - Memory Frequency + Set DDR Memory Frequency, refer to FSP Integration Guide for details.. + 15:Auto, 3:1600, 4:1866, 5:2133, 6:2400 +**/ + UINT8 PcdDdrFreq; + +/** Offset 0x0059 - MMIO Size + Set memory mapped IO space size + 0:2048M, 1:1024M, 2:3072M +**/ + UINT8 PcdMmioSize; + +/** Offset 0x005A +**/ + UINT8 UnusedUpdSpace0[6]; + +/** Offset 0x0060 - Customer Revision + The Customer can set this revision string for their own purpose. +**/ + UINT8 PcdCustomerRevision[32]; + +/** Offset 0x0080 - 32-Bit bus mode + Enable/Disable 32-Bit bus memory mode. + $EN_DIS +**/ + UINT8 PcdHalfWidthEnable; + +/** Offset 0x0081 - TCL Performance + Enable/Disable Tcl timing for performance. + $EN_DIS +**/ + UINT8 PcdTclIdle; + +/** Offset 0x0082 - Interleave Mode + Select Interleave Mode + 0:DISABLED, 1:MODE0, 2:MODE1, 3:MODE2 +**/ + UINT8 PcdInterleaveMode; + +/** Offset 0x0083 - Memory Thermal Throttling + Enable/disable Memory Thermal Throttling management mode + $EN_DIS +**/ + UINT8 PcdMemoryThermalThrottling; + +/** Offset 0x0084 +**/ + UINT8 UnusedUpdSpace1[348]; + +/** Offset 0x01E0 +**/ + UINT8 ReservedMemoryInitUpd[16]; +} FSPM_CONFIG; + +/** Fsp M UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPM_ARCH_UPD FspmArchUpd; + +/** Offset 0x0040 +**/ + FSPM_CONFIG FspmConfig; + +/** Offset 0x01F0 +**/ + UINT8 UnusedUpdSpace2[14]; + +/** Offset 0x01FE +**/ + UINT16 UpdTerminator; +} FSPM_UPD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h new file mode 100644 index 0000000..5d0b793 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h @@ -0,0 +1,192 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include <FspUpd.h> + +#pragma pack(1) + + +/** FSP-S Configuration +**/ +typedef struct { + +/** Offset 0x0020 - PCIe Controller 0 Bifurcation + Configure PCI Express controller 0 bifurcation. + 0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8 +**/ + UINT8 PcdBifurcationPcie0; + +/** Offset 0x0021 - PCIe Controller 1 Bifurcation + Configure PCI Express controller 1 bifurcation. + 0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8 +**/ + UINT8 PcdBifurcationPcie1; + +/** Offset 0x0022 - Active Core Count + Select # of Active Cores (Default: 0, 0:ALL, 1..15 = 1..15 Cores) + 0:ALL, 1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, + 14:14, 15:15 +**/ + UINT8 PcdActiveCoreCount; + +/** Offset 0x0023 +**/ + UINT32 PcdCpuMicrocodePatchBase; + +/** Offset 0x0027 +**/ + UINT32 PcdCpuMicrocodePatchSize; + +/** Offset 0x002B - PCIe Controller 0 + Enable / Disable PCI Express controller 0 + $EN_DIS +**/ + UINT8 PcdEnablePcie0; + +/** Offset 0x002C - PCIe Controller 1 + Enable / Disable PCI Express controller 1 + $EN_DIS +**/ + UINT8 PcdEnablePcie1; + +/** Offset 0x002D - Embedded Multi-Media Controller (eMMC) + Enable / Disable Embedded Multi-Media controller + $EN_DIS +**/ + UINT8 PcdEnableEmmc; + +/** Offset 0x002E - LAN Controllers + Enable / Disable LAN controllers, refer to FSP Integration Guide for details. + 0:Disable LAN 0 & LAN 1, 1:Enable LAN 0 & LAN 1, 2:Disable LAN 1 only +**/ + UINT8 PcdEnableGbE; + +/** Offset 0x002F +**/ + UINT32 PcdFiaMuxConfigRequestPtr; + +/** Offset 0x0033 +**/ + UINT8 UnusedUpdSpace0[4]; + +/** Offset 0x0037 - PCIe Root Port 0 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcdPcieRootPort0DeEmphasis; + +/** Offset 0x0038 - PCIe Root Port 1 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcdPcieRootPort1DeEmphasis; + +/** Offset 0x0039 - PCIe Root Port 2 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcdPcieRootPort2DeEmphasis; + +/** Offset 0x003A - PCIe Root Port 3 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcdPcieRootPort3DeEmphasis; + +/** Offset 0x003B - PCIe Root Port 4 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcdPcieRootPort4DeEmphasis; + +/** Offset 0x003C - PCIe Root Port 5 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcdPcieRootPort5DeEmphasis; + +/** Offset 0x003D - PCIe Root Port 6 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcdPcieRootPort6DeEmphasis; + +/** Offset 0x003E - PCIe Root Port 7 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcdPcieRootPort7DeEmphasis; + +/** Offset 0x003F +**/ + UINT8 UnusedUpdSpace1; + +/** Offset 0x0040 +**/ + UINT32 PcdEMMCDLLConfigPtr; + +/** Offset 0x0044 +**/ + UINT8 UnusedUpdSpace2[156]; + +/** Offset 0x00E0 +**/ + UINT8 ReservedSiliconInitUpd[16]; +} FSPS_CONFIG; + +/** Fsp S UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPS_CONFIG FspsConfig; + +/** Offset 0x00F0 +**/ + UINT8 UnusedUpdSpace3[14]; + +/** Offset 0x00FE +**/ + UINT16 UpdTerminator; +} FSPS_UPD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FsptUpd.h new file mode 100644 index 0000000..340f144 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FsptUpd.h @@ -0,0 +1,109 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPTUPD_H__ +#define __FSPTUPD_H__ + +#include <FspUpd.h> + +#pragma pack(1) + + +/** FSP-T Core UPD +**/ +typedef struct { + +/** Offset 0x0020 +**/ + UINT32 MicrocodeRegionBase; + +/** Offset 0x0024 +**/ + UINT32 MicrocodeRegionLength; + +/** Offset 0x0028 +**/ + UINT32 CodeRegionBase; + +/** Offset 0x002C +**/ + UINT32 CodeRegionLength; + +/** Offset 0x0030 +**/ + UINT8 Reserved1[16]; +} FSPT_CORE_UPD; + +/** FSP-T Configuration +**/ +typedef struct { + +/** Offset 0x0040 - Disable Port80 output in FSP-T + Select Port80 Control in FSP-T (0:VPD-Style, 1:Enable Port80 Output, 2:Disable Port80 + Output, refer to FSP Integration Guide for details + 0:VPD-Style, 1:Enable Port80 Output[Default], 2:Disable Port80 Output +**/ + UINT8 PcdFsptPort80RouteDisable; + +/** Offset 0x0041 +**/ + UINT8 ReservedTempRamInitUpd[31]; +} FSPT_CONFIG; + +/** Fsp T UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPT_CORE_UPD FsptCoreUpd; + +/** Offset 0x0040 +**/ + FSPT_CONFIG FsptConfig; + +/** Offset 0x0060 +**/ + UINT8 UnusedUpdSpace0[30]; + +/** Offset 0x007E +**/ + UINT16 UpdTerminator; +} FSPT_UPD; + +#pragma pack() + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I033a52bc3f0b86f0ec1db8325b7435d20d194fda Gerrit-Change-Number: 31205 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002246 Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: drivers/smmstore: Fix some issues
by Arthur Heymans (Code Review) 29 Nov '19

29 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30432 Change subject: drivers/smmstore: Fix some issues ...................................................................... drivers/smmstore: Fix some issues This fixes the following: - Make the API ARCH independent (no dependency on size_t) - clean up the code a little Change-Id: I629be25d2a9b65796ae8f7a700b6bdab57b91b22 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/smmstore/store.c M src/include/smmstore.h M src/soc/intel/common/block/smm/smihandler.c 3 files changed, 86 insertions(+), 67 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/30432/1 diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c index 409949a..0a62b3c 100644 --- a/src/drivers/smmstore/store.c +++ b/src/drivers/smmstore/store.c @@ -62,8 +62,8 @@ if (cbfs_locate_file_in_region(&file, CONFIG_SMMSTORE_REGION, CONFIG_SMMSTORE_FILENAME, NULL) < 0) { - printk(BIOS_WARNING, "smm store: " - "Unable to find SMM store file in region '%s'\n", + printk(BIOS_WARNING, + "smm store: Unable to find SMM store file in region '%s'\n", CONFIG_SMMSTORE_REGION); return -1; } @@ -87,14 +87,13 @@ * returns 0 on success, -1 on failure * writes up to `*bufsize` bytes into `buf` and updates `*bufsize` */ -int smmstore_read_region(void *buf, ssize_t *bufsize) +int smmstore_read_region(void *buf, uint32_t *bufsize) { struct region_device store; if (bufsize == NULL) return -1; - *bufsize = 0; if (lookup_store(&store) < 0) { printk(BIOS_WARNING, "reading region failed\n"); return -1; @@ -109,6 +108,66 @@ return 0; } +static enum cb_err scan_end(ssize_t *end) +{ + struct region_device store; + + if (lookup_store(&store) < 0) { + printk(BIOS_WARNING, "reading region failed\n"); + return CB_ERR; + } + ssize_t data_sz = region_device_sz(&store); + + /* scan for end */ + *end = 0; + uint32_t k_sz, v_sz; + while (*end < data_sz) { + /* make odd corner cases identifiable, eg. invalid v_sz */ + k_sz = 0; + + if (rdev_readat(&store, &k_sz, *end, sizeof(k_sz)) < 0) { + printk(BIOS_WARNING, "failed reading key size\n"); + return CB_ERR; + } + + /* found the end */ + if (k_sz == 0xffffffff) + break; + + /* something is fishy here: + * Avoid wrapping (since data_size < MAX_UINT32_T / 2) while + * other problems are covered by the loop condition + */ + if (k_sz > data_sz) { + printk(BIOS_WARNING, "key size out of bounds\n"); + return CB_ERR; + } + + if (rdev_readat(&store, &v_sz, *end + 4, sizeof(v_sz)) < 0) { + printk(BIOS_WARNING, "failed reading value size\n"); + return CB_ERR; + } + + if (v_sz > data_sz) { + printk(BIOS_WARNING, "value size out of bounds\n"); + return CB_ERR; + } + + *end += sizeof(k_sz) + sizeof(v_sz) + k_sz + v_sz + 1; + *end = ALIGN_UP(*end, sizeof(uint32_t)); + } + + printk(BIOS_WARNING, "used smm store size might be 0x%zx bytes\n", *end); + + if (k_sz != 0xffffffff) { + printk(BIOS_WARNING, + "eof of data marker looks invalid: 0x%x\n", k_sz); + return CB_ERR; + } + + return CB_SUCCESS; + +} /* * Append data to region * @@ -124,78 +183,38 @@ return -1; } - ssize_t data_sz = region_device_sz(&store); - - /* scan for end */ - ssize_t end = 0; - uint32_t k_sz, v_sz; - while (end < data_sz) { - /* make odd corner cases identifiable, eg. invalid v_sz */ - k_sz = 0; - - if (rdev_readat(&store, &k_sz, end, sizeof(k_sz)) < 0) { - printk(BIOS_WARNING, "failed reading key size\n"); - return -1; - } - - /* found the end */ - if (k_sz == 0xffffffff) - break; - - /* something is fishy here: - * Avoid wrapping (since data_size < MAX_UINT32_T / 2) while - * other problems are covered by the loop condition - */ - if (k_sz > data_sz) { - printk(BIOS_WARNING, "key size out of bounds\n"); - return -1; - } - - if (rdev_readat(&store, &v_sz, end + 4, sizeof(v_sz)) < 0) { - printk(BIOS_WARNING, "failed reading value size\n"); - return -1; - } - - if (v_sz > data_sz) { - printk(BIOS_WARNING, "value size out of bounds\n"); - return -1; - } - - end += 8 + k_sz + v_sz + 1; - end = ALIGN_UP(end, sizeof(uint32_t)); - } - - printk(BIOS_WARNING, "used smm store size might be 0x%zx bytes\n", end); - - if (k_sz != 0xffffffff) { - printk(BIOS_WARNING, - "eof of data marker looks invalid: 0x%x\n", k_sz); + ssize_t end; + if (scan_end(&end) == CB_ERR) return -1; - } printk(BIOS_WARNING, "used size looks legit\n"); printk(BIOS_WARNING, "open (%zx, %zx) for writing\n", region_device_offset(&store), region_device_sz(&store)); - if (boot_device_rw_subregion(&store.region, &store) < 0) { + if (boot_device_rw_subregion(region_device_region(&store), &store) < 0) { printk(BIOS_WARNING, "couldn't open store for writing\n"); return -1; } - uint32_t record_sz = 8 + key_sz + value_sz + 1; - if (end + record_sz >= data_sz) { + struct region subregion = + { + .offset = end, + .size = sizeof(key_sz) + sizeof(value_sz) + key_sz + value_sz + 1, + }; + + if (region_is_subregion(region_device_region(&store), &subregion)) { printk(BIOS_WARNING, "not enough space for new data\n"); return -1; } - if (rdev_writeat(&store, &key_sz, end, 4) != 4) { + if (rdev_writeat(&store, &key_sz, end, sizeof(key_sz) != sizeof(key_sz))) { printk(BIOS_WARNING, "failed writing key size\n"); } - end += 4; - if (rdev_writeat(&store, &value_sz, end, 4) != 4) { + end += sizeof(key_sz); + if (rdev_writeat(&store, &value_sz, end, sizeof(value_sz) != sizeof(key_sz))) { printk(BIOS_WARNING, "failed writing value size\n"); } - end += 4; + end += sizeof(value_sz); if (rdev_writeat(&store, key, end, key_sz) != key_sz) { printk(BIOS_WARNING, "failed writing key data\n"); } @@ -205,7 +224,7 @@ } end += value_sz; uint8_t nul = 0; - if (rdev_writeat(&store, &nul, end, 1) != 1) { + if (rdev_writeat(&store, &nul, end, sizeof(nul)) != sizeof(nul)) { printk(BIOS_WARNING, "failed writing termination\n"); } diff --git a/src/include/smmstore.h b/src/include/smmstore.h index a535c5b..30a8191 100644 --- a/src/include/smmstore.h +++ b/src/include/smmstore.h @@ -28,22 +28,22 @@ #define SMMSTORE_CMD_APPEND 3 struct smmstore_params_read { - void *buf; - ssize_t bufsize; + uint32_t *buf; + uint32_t bufsize; }; struct smmstore_params_append { - void *key; - size_t keysize; - void *val; - size_t valsize; + uint32_t *key; + uint32_t keysize; + uint32_t *val; + uint32_t valsize; }; /* SMM responder */ uint32_t smmstore_exec(uint8_t command, void *param); /* implementation */ -int smmstore_read_region(void *buf, ssize_t *bufsize); +int smmstore_read_region(void *buf, uint32_t *bufsize); int smmstore_append_data(void *key, uint32_t key_sz, void *value, uint32_t value_sz); int smmstore_clear_region(void); diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 2ffc00f..c125c0c 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -311,7 +311,7 @@ reg_ebx = save_state_ops->get_reg(io_smi, RBX); /* drivers/smmstore/smi.c */ - ret = smmstore_exec(sub_command, (void *)reg_ebx); + ret = smmstore_exec(sub_command, (uintptr_t *)reg_ebx); save_state_ops->set_reg(io_smi, RAX, ret); } -- To view, visit https://review.coreboot.org/c/coreboot/+/30432 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I629be25d2a9b65796ae8f7a700b6bdab57b91b22 Gerrit-Change-Number: 30432 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

6 35

Change in ...coreboot[master]: [WIP] soc/amd/common: Use static allocation for params
by Kyösti Mälkki (Code Review) 15 Nov '19

15 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31489 Change subject: [WIP] soc/amd/common: Use static allocation for params ...................................................................... [WIP] soc/amd/common: Use static allocation for params Lifetime of the structure is the duration of call to AGESA. There is no need to allocate and release these from AGESA's internal heap for every single call. Change-Id: Ibef6ca8481f926d4e18e1aef5136e69f5834feb1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/pi/agesawrapper.c 1 file changed, 22 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/31489/1 diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 821535d..e769a45 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -410,6 +410,26 @@ } +union AMD_MAX_ALLOC_PARAMS { + AMD_INTERFACE_PARAMS p1; + AMD_RESET_PARAMS p2; + AMD_EARLY_PARAMS p3; + AMD_POST_PARAMS p4; + AMD_RESUME_PARAMS p5; + AMD_ENV_PARAMS p6; + AMD_MID_PARAMS p7; + AMD_LATE_PARAMS p8; +#if 1 + AMD_RTB_PARAMS p9; +#else + AMD_S3SAVE_PARAMS p10; +#endif + AMD_S3LATE_PARAMS p11; + AMD_S3FINAL_PARAMS p12; +}; + +static union AMD_MAX_ALLOC_PARAMS sp; + AGESA_STATUS agesa_execute_state(AGESA_STRUCT_NAME func) { AGESA_STATUS status = AGESA_UNSUPPORTED; @@ -417,19 +437,9 @@ AMD_CONFIG_PARAMS *StdHeader = &template; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS *aip = &AmdParamStruct; - union { - AMD_RESET_PARAMS ResetParams; - AMD_S3LATE_PARAMS S3LateParams; - AMD_S3FINAL_PARAMS S3FinalParams; - } sp; - if ((func == AMD_INIT_RESET) || (func == AMD_S3LATE_RESTORE) || - (func == AMD_S3FINAL_RESTORE)) { - memset(&sp, 0, sizeof(sp)); - amd_create_struct(aip, func, &sp, sizeof(sp)); - } else { - amd_create_struct(aip, func, NULL, 0); - } + memset(&sp, 0, sizeof(sp)); + amd_create_struct(aip, func, &sp, sizeof(sp)); StdHeader = aip->NewStructPtr; StdHeader->Func = func; -- To view, visit https://review.coreboot.org/c/coreboot/+/31489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibef6ca8481f926d4e18e1aef5136e69f5834feb1 Gerrit-Change-Number: 31489 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 6

Change in ...coreboot[master]: device/hypertransport: Drop dev_find_slot() debugging
by Kyösti Mälkki (Code Review) 15 Nov '19

15 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30704 Change subject: device/hypertransport: Drop dev_find_slot() debugging ...................................................................... device/hypertransport: Drop dev_find_slot() debugging Change-Id: I810ca9cfc72de9ea532d53cabdaf8845be837432 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/device/device.c M src/device/device_const.c M src/include/device/device.h 3 files changed, 5 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/30704/1 diff --git a/src/device/device.c b/src/device/device.c index 20a4077..7836af1 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -1253,7 +1253,4 @@ final_link(link); printk(BIOS_INFO, "Devices finalized\n"); - - if (IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT)) - ht_report_devtree_sanity(); } diff --git a/src/device/device_const.c b/src/device/device_const.c index 480ac76..cdae33d 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -177,15 +177,6 @@ * Work around the devicetree topology being manipulated on-the-fly * on systems with HyperTransport Support. */ - -static int ht_tree_needs_fixing, ht_tree_fixup_failed; - -void ht_report_devtree_sanity(void) -{ - printk(BIOS_INFO, "HT fixup counters %d / %d (rqrd/failed)\n", - ht_tree_needs_fixing, ht_tree_fixup_failed); -} - static const struct bus *ht_bus_reloc(const struct bus *parent, pci_devfn_t devfn) { @@ -222,34 +213,20 @@ DEVTREE_CONST struct device *pcidev_path_on_root(pci_devfn_t devfn) { - DEVTREE_CONST struct device *dev; DEVTREE_CONST struct device *pci_domain; + const struct bus *root; pci_domain = dev_find_path(NULL, DEVICE_PATH_DOMAIN); if (!pci_domain) return NULL; - dev = pcidev_path_behind(pci_domain->link_list, devfn); + root = pci_domain->link_list; /* Static devicetree with HyperTransport has whacky topology. */ - if (!IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT)) - return dev; + if (IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT)) + root = ht_bus_reloc(root, devfn); - DEVTREE_CONST struct device *dev_fixup, *dev_old_method; - - const struct bus *root = ht_bus_reloc(pci_domain->link_list, devfn); - dev_fixup = pcidev_path_behind(root, devfn); - dev_old_method = dev_find_slot(0, devfn); - - if (ENV_RAMSTAGE) { - if (dev != dev_old_method) - ht_tree_needs_fixing++; - - if (dev_fixup != dev_old_method) - ht_tree_fixup_failed++; - } - - return dev_old_method; + return pcidev_path_behind(root, devfn); } DEVTREE_CONST struct device *pcidev_on_root(uint8_t dev, uint8_t fn) diff --git a/src/include/device/device.h b/src/include/device/device.h index 40a0f58..540b7e3 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -227,7 +227,6 @@ void show_one_resource(int debug_level, struct device *dev, struct resource *resource, const char *comment); void show_all_devs_resources(int debug_level, const char *msg); -void ht_report_devtree_sanity(void); /* Rounding for boundaries. * Due to some chip bugs, go ahead and round IO to 16 -- To view, visit https://review.coreboot.org/c/coreboot/+/30704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I810ca9cfc72de9ea532d53cabdaf8845be837432 Gerrit-Change-Number: 30704 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: device/hypertransport: Fix regression on dev_find_slot() removal
by Kyösti Mälkki (Code Review) 15 Nov '19

15 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30703 Change subject: device/hypertransport: Fix regression on dev_find_slot() removal ...................................................................... device/hypertransport: Fix regression on dev_find_slot() removal The regression is with the implementation of the functions introduced in commit ad7674e device: Introduce pcidev_on_root() and friends For these platforms, the first PCI node on devicetree is not the root of PCI bus hierarchy, and the topology (bus->children and dev->sibling links) are being manipulated during HyperTransport enumeration. This workaround reverts to old method of using dev_find_slot() while keeping track of whether the new method would give equivalent result. Change-Id: I05a54de542f97159266a1c127da32665957f58f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M Makefile.inc M src/device/device.c M src/device/device_const.c M src/device/hypertransport.c M src/include/device/device.h M src/include/device/pci.h 6 files changed, 87 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/30703/1 diff --git a/Makefile.inc b/Makefile.inc index 2741b19..24b5164 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -577,7 +577,10 @@ verstage-y+=$(DEVICETREE_STATIC_C) bootblock-y+=$(DEVICETREE_STATIC_C) postcar-y+=$(DEVICETREE_STATIC_C) + +ifneq ($(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT),y) smm-y+=$(DEVICETREE_STATIC_C) +endif ####################################################################### # Clean up rules diff --git a/src/device/device.c b/src/device/device.c index 7836af1..20a4077 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -1253,4 +1253,7 @@ final_link(link); printk(BIOS_INFO, "Devices finalized\n"); + + if (IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT)) + ht_report_devtree_sanity(); } diff --git a/src/device/device_const.c b/src/device/device_const.c index ec128e8..480ac76 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -173,6 +173,43 @@ return child; } +/*** + * Work around the devicetree topology being manipulated on-the-fly + * on systems with HyperTransport Support. + */ + +static int ht_tree_needs_fixing, ht_tree_fixup_failed; + +void ht_report_devtree_sanity(void) +{ + printk(BIOS_INFO, "HT fixup counters %d / %d (rqrd/failed)\n", + ht_tree_needs_fixing, ht_tree_fixup_failed); +} + +static const struct bus *ht_bus_reloc(const struct bus *parent, + pci_devfn_t devfn) +{ + DEVTREE_CONST struct device *dev; + DEVTREE_CONST struct bus *bus; + + /* HyperTransport enumeration fixes up the whacky + * topology present in static devicetree. + */ + if (ENV_RAMSTAGE && (SCAN_COMPLETE == ht_scanning_status())) + return parent; + + if (devfn >= PCI_DEVFN(0x18, 0)) + return parent; + + /* One of the links is bus for devices 0:00.x to 0:17.x. */ + dev = pcidev_path_behind(parent, PCI_DEVFN(0x18, 0)); + for (bus = dev->link_list; bus; bus = bus->next) + if (bus->children) + return bus; + + return NULL; +} + DEVTREE_CONST struct device *pcidev_path_behind( const struct bus *parent, pci_devfn_t devfn) { @@ -185,12 +222,34 @@ DEVTREE_CONST struct device *pcidev_path_on_root(pci_devfn_t devfn) { + DEVTREE_CONST struct device *dev; DEVTREE_CONST struct device *pci_domain; pci_domain = dev_find_path(NULL, DEVICE_PATH_DOMAIN); if (!pci_domain) return NULL; - return pcidev_path_behind(pci_domain->link_list, devfn); + + dev = pcidev_path_behind(pci_domain->link_list, devfn); + + /* Static devicetree with HyperTransport has whacky topology. */ + if (!IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT)) + return dev; + + DEVTREE_CONST struct device *dev_fixup, *dev_old_method; + + const struct bus *root = ht_bus_reloc(pci_domain->link_list, devfn); + dev_fixup = pcidev_path_behind(root, devfn); + dev_old_method = dev_find_slot(0, devfn); + + if (ENV_RAMSTAGE) { + if (dev != dev_old_method) + ht_tree_needs_fixing++; + + if (dev_fixup != dev_old_method) + ht_tree_fixup_failed++; + } + + return dev_old_method; } DEVTREE_CONST struct device *pcidev_on_root(uint8_t dev, uint8_t fn) diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c index ed6b2dd..fd4961e 100644 --- a/src/device/hypertransport.c +++ b/src/device/hypertransport.c @@ -244,6 +244,13 @@ } } +static int ht_scan_chain_process = SCAN_NOT_STARTED; + +int ht_scanning_status(void) +{ + return ht_scan_chain_process; +} + static unsigned int do_hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned *ht_unitid_base, @@ -276,6 +283,9 @@ /* Restore the hypertransport chain to it's uninitialized state. */ ht_collapse_early_enumeration(bus, offset_unitid); + if (bus->secondary == 0) + ht_scan_chain_process = SCAN_IN_PROGRESS; + /* See which static device nodes I have. */ old_devices = bus->children; bus->children = 0; @@ -472,6 +482,9 @@ last_func->sibling = old_devices; } + if (bus->secondary == 0) + ht_scan_chain_process = SCAN_COMPLETE; + return next_unitid; } diff --git a/src/include/device/device.h b/src/include/device/device.h index 540b7e3..40a0f58 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -227,6 +227,7 @@ void show_one_resource(int debug_level, struct device *dev, struct resource *resource, const char *comment); void show_all_devs_resources(int debug_level, const char *msg); +void ht_report_devtree_sanity(void); /* Rounding for boundaries. * Due to some chip bugs, go ahead and round IO to 16 diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 7cf7e06..41ad281 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -122,6 +122,13 @@ int pci_msix_table_bar(struct device *dev, u32 *offset, u8 *idx); struct msix_entry *pci_msix_get_table(struct device *dev); +enum { + SCAN_NOT_STARTED = 0, + SCAN_IN_PROGRESS, + SCAN_COMPLETE +}; +int ht_scanning_status(void); + #define PCI_IO_BRIDGE_ALIGN 4096 #define PCI_MEM_BRIDGE_ALIGN (1024*1024) -- To view, visit https://review.coreboot.org/c/coreboot/+/30703 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05a54de542f97159266a1c127da32665957f58f9 Gerrit-Change-Number: 30703 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: [WIP]mb/asus/p5ql-em: Add mainboard
by Arthur Heymans (Code Review) 09 Nov '19

09 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31323 Change subject: [WIP]mb/asus/p5ql-em: Add mainboard ...................................................................... [WIP]mb/asus/p5ql-em: Add mainboard Tested, working: - First dimm slot of each channel - USB, SATA - CPU FSB at 1067MHz - Libgfxinit on DVI and VGA slot - PCI slot - Realtek NIC (configure macaddress in Kconfig) - PEG slot Tested, not working: - second dimm slot for each channel. Those are hooked up to the second rank of the channel, instead of rank 3 and 4. The raminit does not support such setups. Untested: - PCIe x1 slot, likely works fine - HDMI TODO: - BSEL superio pins Tested using SeaBIOS 1.12, Linux 4.19. Change-Id: I88fe9c66dae079cd7eedcc9736c5922defbc0e5a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/mainboard/asus/p5ql-em/Kconfig A src/mainboard/asus/p5ql-em/Kconfig.name A src/mainboard/asus/p5ql-em/Makefile.inc A src/mainboard/asus/p5ql-em/acpi/ec.asl A src/mainboard/asus/p5ql-em/acpi/ich10_pci_irqs.asl A src/mainboard/asus/p5ql-em/acpi/platform.asl A src/mainboard/asus/p5ql-em/acpi/superio.asl A src/mainboard/asus/p5ql-em/acpi_tables.c A src/mainboard/asus/p5ql-em/board_info.txt A src/mainboard/asus/p5ql-em/cmos.default A src/mainboard/asus/p5ql-em/cmos.layout A src/mainboard/asus/p5ql-em/cstates.c A src/mainboard/asus/p5ql-em/data.vbt A src/mainboard/asus/p5ql-em/devicetree.cb A src/mainboard/asus/p5ql-em/dsdt.asl A src/mainboard/asus/p5ql-em/gma-mainboard.ads A src/mainboard/asus/p5ql-em/gpio.c A src/mainboard/asus/p5ql-em/hda_verb.c A src/mainboard/asus/p5ql-em/romstage.c 19 files changed, 811 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/31323/1 diff --git a/src/mainboard/asus/p5ql-em/Kconfig b/src/mainboard/asus/p5ql-em/Kconfig new file mode 100644 index 0000000..07af627 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/Kconfig @@ -0,0 +1,47 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> +# Copyright (C) 2018 Arthur Heymans <arthur(a)aheymans.xyz> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_ASUS_P5QL_EM + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA775 + select NORTHBRIDGE_INTEL_X4X + select SOUTHBRIDGE_INTEL_I82801JX + select SUPERIO_WINBOND_W83627DHG + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_1024 + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select REALTEK_8168_RESET + +config MAINBOARD_DIR + string + default "asus/p5ql-em" + +config MAINBOARD_PART_NUMBER + string + default "P5QL EM" + +config MAX_CPUS + int + default 4 + +endif # BOARD_ASUS_P5QL_EM diff --git a/src/mainboard/asus/p5ql-em/Kconfig.name b/src/mainboard/asus/p5ql-em/Kconfig.name new file mode 100644 index 0000000..92ead65 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_P5QL_EM + bool "P5QL EM" diff --git a/src/mainboard/asus/p5ql-em/Makefile.inc b/src/mainboard/asus/p5ql-em/Makefile.inc new file mode 100644 index 0000000..6b3d94a --- /dev/null +++ b/src/mainboard/asus/p5ql-em/Makefile.inc @@ -0,0 +1,17 @@ +# +# This file is part of the coreboot project. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +ramstage-y += cstates.c +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/p5ql-em/acpi/ec.asl b/src/mainboard/asus/p5ql-em/acpi/ec.asl new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/acpi/ec.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/asus/p5ql-em/acpi/ich10_pci_irqs.asl b/src/mainboard/asus/p5ql-em/acpi/ich10_pci_irqs.asl new file mode 100644 index 0000000..861561a --- /dev/null +++ b/src/mainboard/asus/p5ql-em/acpi/ich10_pci_irqs.asl @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: + * IRQ routing for the 0:1e.0 PCI bridge of the ICH10 + */ + +If (PICM) { + Return (Package() { + /* PCI slot */ + Package() { 0x0000ffff, 0, 0, 0x10}, + Package() { 0x0000ffff, 1, 0, 0x11}, + Package() { 0x0000ffff, 2, 0, 0x12}, + Package() { 0x0000ffff, 3, 0, 0x13}, + }) +} Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0}, + }) +} diff --git a/src/mainboard/asus/p5ql-em/acpi/platform.asl b/src/mainboard/asus/p5ql-em/acpi/platform.asl new file mode 100644 index 0000000..6c92a4e --- /dev/null +++ b/src/mainboard/asus/p5ql-em/acpi/platform.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store(Arg0, PICM) +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) /* SMI Function */ + Store (0, TRP0) /* Generate trap */ + Return (SMIF) /* Return value of SMI handler */ +} diff --git a/src/mainboard/asus/p5ql-em/acpi/superio.asl b/src/mainboard/asus/p5ql-em/acpi/superio.asl new file mode 100644 index 0000000..8f414f5 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/acpi/superio.asl @@ -0,0 +1 @@ +/* TODO */ diff --git a/src/mainboard/asus/p5ql-em/acpi_tables.c b/src/mainboard/asus/p5ql-em/acpi_tables.c new file mode 100644 index 0000000..d609a0e --- /dev/null +++ b/src/mainboard/asus/p5ql-em/acpi_tables.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <southbridge/intel/i82801jx/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + + gnvs->pwrs = 1; /* Power state (AC = 1) */ + gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ + gnvs->apic = 1; /* Enable APIC */ + gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->cmap = 0x01; /* Enable COM 1 port */ +} diff --git a/src/mainboard/asus/p5ql-em/board_info.txt b/src/mainboard/asus/p5ql-em/board_info.txt new file mode 100644 index 0000000..42d4812 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: https://www.asus.com/Motherboards/P5QC/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/asus/p5ql-em/cmos.default b/src/mainboard/asus/p5ql-em/cmos.default new file mode 100644 index 0000000..ad822d5 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/cmos.default @@ -0,0 +1,5 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable +sata_mode=AHCI diff --git a/src/mainboard/asus/p5ql-em/cmos.layout b/src/mainboard/asus/p5ql-em/cmos.layout new file mode 100644 index 0000000..09ba5c5 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/cmos.layout @@ -0,0 +1,104 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 5 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# coreboot config options: southbridge +408 1 e 10 sata_mode +409 2 e 7 power_on_after_fail +411 1 e 1 nmi + +# coreboot config options: cpu +#424 8 r 0 unused + +# coreboot config options: northbridge +432 4 e 11 gfx_uma_size +#436 548 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +10 0 AHCI +10 1 Compatible +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/asus/p5ql-em/cstates.c b/src/mainboard/asus/p5ql-em/cstates.c new file mode 100644 index 0000000..aa7214d --- /dev/null +++ b/src/mainboard/asus/p5ql-em/cstates.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpigen.h> +#include <device/device.h> +#include <southbridge/intel/i82801jx/i82801jx.h> + +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} diff --git a/src/mainboard/asus/p5ql-em/data.vbt b/src/mainboard/asus/p5ql-em/data.vbt new file mode 100644 index 0000000..5dd1803 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/data.vbt Binary files differ diff --git a/src/mainboard/asus/p5ql-em/devicetree.cb b/src/mainboard/asus/p5ql-em/devicetree.cb new file mode 100644 index 0000000..e13d59b --- /dev/null +++ b/src/mainboard/asus/p5ql-em/devicetree.cb @@ -0,0 +1,169 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> +# Copyright (C) 2018 Angel Pons <th3fanbus(a)gmail.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +chip northbridge/intel/x4x # Northbridge + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + chip cpu/intel/model_1067x # CPU + device lapic 0xACAC off end + end + end + device domain 0 on # PCI domain + device pci 0.0 on # Host Bridge + subsystemid 0x1043 0x8336 + end + device pci 1.0 on # PEG + subsystemid 0x1043 0x8336 + end + device pci 2.0 on # Integrated graphics controller + subsystemid 0x1043 0x8336 + end + device pci 2.1 on # Integrated graphics controller 2 + subsystemid 0x1043 0x8336 + end + device pci 3.0 off end # ME + device pci 3.1 off end # ME + device pci 3.2 off end # ME + device pci 3.3 off end # ME + device pci 6.0 off end # PEG 2 + chip southbridge/intel/i82801jx # Southbridge + register "gpe0_en" = "0x40" + + # Set AHCI mode. + register "sata_port_map" = "0x3f" + register "sata_clock_request" = "0" + register "sata_traffic_monitor" = "0" + + # Enable PCIe ports 0,2,3 as slots. + register "pcie_slot_implemented" = "0x31" + + device pci 19.0 off end # GBE + device pci 1a.0 on # USB + subsystemid 0x1043 0x82d4 + end + device pci 1a.1 on # USB + subsystemid 0x1043 0x82d4 + end + device pci 1a.2 on # USB + subsystemid 0x1043 0x82d4 + end + device pci 1a.7 on # USB + subsystemid 0x1043 0x82d4 + end + device pci 1b.0 on # Audio + subsystemid 0x1043 0x82fe + end + device pci 1c.0 on end # PCIe 1 PCIe x1 Slot #1 + device pci 1c.1 off end # PCIe 2 + device pci 1c.2 off end # PCIe 3 + device pci 1c.3 on # PCIe 4 1394 controller + device pci 0.0 on + subsystemid 0x1043 0x8313 + end + end + device pci 1c.4 on # PCIe 5 Marvell IDE + device pci 0.0 on + subsystemid 0x1043 0x82a2 + end + end + device pci 1c.5 on # PCIe 6 Realtek LAN + device pci 0.0 on + subsystemid 0x1043 0x82c6 + end + end + device pci 1d.0 on # USB + subsystemid 0x1043 0x82d4 + end + device pci 1d.1 on # USB + subsystemid 0x1043 0x82d4 + end + device pci 1d.2 on # USB + subsystemid 0x1043 0x82d4 + end + device pci 1d.7 on # USB + subsystemid 0x1043 0x82d4 + end + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # LPC bridge + subsystemid 0x1043 0x82d4 + chip superio/winbond/w83627dhg + device pnp 2e.0 on # Floppy + # global + irq 0x2c = 0x92 + #floppy + io 0x60 = 0x3f0 + irq 0x70 = 0x06 + drq 0x74 = 0x02 + end + device pnp 2e.1 on # Parallel port + # parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # COM2, IR + device pnp 2e.5 on # Keyboard, mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # SPI + device pnp 2e.7 on end # GPIO6 (all input) + device pnp 2e.8 off end # WDT0#, PLED + device pnp 2e.9 off end # GPIO2 + device pnp 2e.109 on # GPIO3 + irq 0xf0 = 0xf3 + irq 0xf1 = 0x0c + end + device pnp 2e.209 on # GPIO4 + irq 0xf4 = 0x06 + irq 0xf5 = 0x06 + end + device pnp 2e.309 on # GPIO5 + irq 0xe0 = 0xdf + irq 0xf3 = 0x09 # RSVD SUSLED settings + end + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HWM, front pannel LED + io 0x60 = 0x290 + irq 0x70 = 0 + end + device pnp 2e.c off end # PECI, SST + end + end + device pci 1f.1 off end # PATA/IDE + device pci 1f.2 on # SATA + subsystemid 0x1043 0x82d4 + end + device pci 1f.3 on # SMbus + subsystemid 0x1043 0x82d4 + end + device pci 1f.4 off end + device pci 1f.5 on # IDE + subsystemid 0x1043 0x82d4 + end + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asus/p5ql-em/dsdt.asl b/src/mainboard/asus/p5ql-em/dsdt.asl new file mode 100644 index 0000000..d7ce26e --- /dev/null +++ b/src/mainboard/asus/p5ql-em/dsdt.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/i82801jx/i82801jx.h> + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00000001 // OEM revision +) +{ + // global NVS and variables + #include "acpi/platform.asl" + #include <southbridge/intel/i82801jx/acpi/globalnvs.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/x4x/acpi/x4x.asl> + #include <southbridge/intel/i82801jx/acpi/ich10.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801jx/acpi/sleepstates.asl> +} diff --git a/src/mainboard/asus/p5ql-em/gma-mainboard.ads b/src/mainboard/asus/p5ql-em/gma-mainboard.ads new file mode 100644 index 0000000..43a7d89 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/gma-mainboard.ads @@ -0,0 +1,29 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + HDMI2, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/p5ql-em/gpio.c b/src/mainboard/asus/p5ql-em/gpio.c new file mode 100644 index 0000000..7bc8b9b --- /dev/null +++ b/src/mainboard/asus/p5ql-em/gpio.c @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio12 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio7 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/asus/p5ql-em/hda_verb.c b/src/mainboard/asus/p5ql-em/hda_verb.c new file mode 100644 index 0000000..9e54df6 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/hda_verb.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0888, + 0x104382fe, // Subsystem ID + 13, // Number of entries + + /* Pin Widget Verb Table */ + + AZALIA_PIN_CFG(0, 0x11, 0x99430130), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x01012014), + AZALIA_PIN_CFG(0, 0x18, 0x01a19840), + AZALIA_PIN_CFG(0, 0x19, 0x02a19c50), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0, 0x1c, 0x593301f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4015e601), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + + 0x80862803, + 0x80860101, + 1, + + AZALIA_PIN_CFG(1, 0x03, 0x18560010), +}; + +const u32 pc_beep_verbs[0] = {}; + +const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs); +const u32 cim_verb_data_size = ARRAY_SIZE(cim_verb_data); diff --git a/src/mainboard/asus/p5ql-em/romstage.c b/src/mainboard/asus/p5ql-em/romstage.c new file mode 100644 index 0000000..da822ac --- /dev/null +++ b/src/mainboard/asus/p5ql-em/romstage.c @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <southbridge/intel/i82801jx/i82801jx.h> +#include <southbridge/intel/common/gpio.h> +#include <northbridge/intel/x4x/x4x.h> +#include <cpu/x86/bist.h> +#include <cpu/intel/romstage.h> +#include <superio/winbond/w83627dhg/w83627dhg.h> +#include <superio/winbond/common/winbond.h> +#include <northbridge/intel/x4x/iomap.h> + +#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) +#define LPC_DEV PCI_DEV(0, 0x1f, 0) + +/* Early mainboard specific GPIO setup. + * We should use standard gpio.h eventually + */ + +static void mb_gpio_init(void) +{ + /* Set the value for GPIO base address register and enable GPIO. */ + pci_write_config32(LPC_DEV, D31F0_GPIO_BASE, (DEFAULT_GPIOBASE | 1)); + pci_write_config8(LPC_DEV, D31F0_GPIO_CNTL, 0x10); + + setup_pch_gpios(&mainboard_gpio_map); + + /* Enable IOAPIC */ + RCBA8(0x31ff) = 0x03; + RCBA8(0x31ff); +} + +static void ich10_enable_lpc(void) +{ + /* Configure serial IRQs.*/ + pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010); + pci_write_config16(LPC_DEV, D31F0_LPC_EN, CNF1_LPC_EN | KBC_LPC_EN + | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN + | COMA_LPC_EN); + /* HW EC */ + pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x00000295); + /* TODO: FSB BSEL pins... */ +} + +void mainboard_romstage_entry(unsigned long bist) +{ + /* This board has first dimm slot of each channel hooked up to + rank0 and rank1, while the second dimm slot is only connected + to rank1. The raminit does not support such setups + const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 }; */ + const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; + u8 boot_path = 0; + u8 s3_resume; + + /* Set southbridge and Super I/O GPIOs. */ + ich10_enable_lpc(); + mb_gpio_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + console_init(); + + report_bist_failure(bist); + enable_smbus(); + + x4x_early_init(); + + s3_resume = southbridge_detect_s3_resume(); + if (s3_resume) + boot_path = BOOT_PATH_RESUME; + if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) + boot_path = BOOT_PATH_WARM_RESET; + + sdram_initialize(boot_path, spd_addrmap); + + x4x_late_init(s3_resume); + + printk(BIOS_DEBUG, "x4x late init complete\n"); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88fe9c66dae079cd7eedcc9736c5922defbc0e5a Gerrit-Change-Number: 31323 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 40

Change in ...coreboot[master]: cpu/intel/car/core2: Update microcode in CAR setup
by Arthur Heymans (Code Review) 07 Nov '19

07 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30775 Change subject: cpu/intel/car/core2: Update microcode in CAR setup ...................................................................... cpu/intel/car/core2: Update microcode in CAR setup This updates the BSP microcode during CAR setup. Change-Id: I8ecd1b99e18c7e73ae47f850fdc4870751dc6e8c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/core2/cache_as_ram.S 1 file changed, 28 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/30775/1 diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 981b12d..4fb8c66 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -111,6 +111,17 @@ movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr + /* Cache the whole rom to fetch microcode updates */ + movl $MTRR_PHYS_BASE(1), %ecx + xorl %edx, %edx + movl $CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax + wrmsr + + movl $MTRR_PHYS_MASK(1), %ecx + rdmsr + movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + wrmsr + post_code(0x25) /* Enable MTRR. */ @@ -131,15 +142,17 @@ invd movl %eax, %cr0 - /* Clear the cache memory region. This will also fill up the cache. */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE >> 2), %ecx - xorl %eax, %eax - rep stosl +#if IS_ENABLED(CONFIG_MICROCODE_UPDATE_PRE_RAM) +update_microcode: + /* put the return address in %esp */ + movl $end_microcode_update, %esp + jmp update_bsp_microcode +end_microcode_update: +#endif +cache_xip: post_code(0x26) - /* Enable Cache-as-RAM mode by disabling cache. */ + /* Disable caching to set final MTRRs for speeding up XIP. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax movl %eax, %cr0 @@ -165,8 +178,16 @@ /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax + invd movl %eax, %cr0 + /* Clear the cache memory region. This will also fill up the cache. */ + movl $CACHE_AS_RAM_BASE, %esi + movl %esi, %edi + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx + xorl %eax, %eax + rep stosl + /* Setup the stack. */ mov $_car_stack_end, %esp -- To view, visit https://review.coreboot.org/c/coreboot/+/30775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ecd1b99e18c7e73ae47f850fdc4870751dc6e8c Gerrit-Change-Number: 30775 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 9

Change in ...coreboot[master]: util/autoport: Make dsdt.asl prettier
by Angel Pons (Code Review) 03 Nov '19

03 Nov '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30971 Change subject: util/autoport: Make dsdt.asl prettier ...................................................................... util/autoport: Make dsdt.asl prettier Small cosmetic changes which fix OCD-inducing aesthetic inaccuracies. Change-Id: I8fef4bbe12b283cee2ab8d078de950171757bbfe Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/autoport/main.go 1 file changed, 7 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/30971/1 diff --git a/util/autoport/main.go b/util/autoport/main.go index ee26966..5d660d1 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -842,13 +842,14 @@ for _, define := range DSDTDefines { if define.Comment != "" { - fmt.Fprintf(dsdt, "\t/* %s. */\n", define.Comment) + fmt.Fprintf(dsdt, "\t/* %s. */\n", define.Comment) } dsdt.WriteString("#define " + define.Key + " " + define.Value + "\n") } dsdt.WriteString( - `#include <arch/acpi.h> + ` +#include <arch/acpi.h> DefinitionBlock( "dsdt.aml", "DSDT", @@ -858,7 +859,7 @@ 0x20141018 // OEM revision ) { - // Some generic macros + /* Some generic macros */ #include "acpi/platform.asl" `) @@ -870,9 +871,8 @@ } dsdt.WriteString(` - Scope (\_SB) { - Device (PCI0) - { + Device (\_SB.PCI0) + { `) for _, x := range DSDTPCI0Includes { if x.Comment != "" { @@ -881,8 +881,7 @@ fmt.Fprintf(dsdt, "\t\t#include <%s>\n", x.File) } dsdt.WriteString( - ` } - } + ` } } `) -- To view, visit https://review.coreboot.org/c/coreboot/+/30971 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8fef4bbe12b283cee2ab8d078de950171757bbfe Gerrit-Change-Number: 30971 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 8

Change in ...coreboot[master]: [WIP] Reduce (void **) pointer usage
by Arthur Heymans (Code Review) 02 Nov '19

02 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30684 Change subject: [WIP] Reduce (void **) pointer usage ...................................................................... [WIP] Reduce (void **) pointer usage Use uintptr_t * instead. Change-Id: I8ef5d9fad0298c79806fd94ca053027822022ac2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/haswell/stage_cache.c M src/cpu/intel/model_206ax/stage_cache.c M src/drivers/intel/fsp1_1/include/fsp/memmap.h M src/drivers/intel/fsp1_1/raminit.c M src/drivers/intel/fsp1_1/ramstage.c M src/drivers/intel/fsp1_1/stack.c M src/drivers/intel/fsp1_1/stage_cache.c M src/drivers/intel/fsp2_0/include/fsp/memmap.h M src/drivers/intel/fsp2_0/stage_cache.c M src/include/stage_cache.h M src/lib/ext_stage_cache.c M src/soc/amd/stoneyridge/cpu.c M src/soc/amd/stoneyridge/include/soc/northbridge.h M src/soc/amd/stoneyridge/ramtop.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/apollolake/memmap.c M src/soc/intel/baytrail/stage_cache.c M src/soc/intel/braswell/cpu.c M src/soc/intel/braswell/memmap.c M src/soc/intel/braswell/northcluster.c M src/soc/intel/broadwell/stage_cache.c M src/soc/intel/cannonlake/memmap.c M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/common/block/include/intelblocks/smm.h M src/soc/intel/common/block/smm/smm.c M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/denverton_ns/include/soc/smm.h M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/icelake/memmap.c M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/skylake/memmap.c M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/soc/intel/skylake/smmrelocate.c 35 files changed, 102 insertions(+), 124 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/30684/1 diff --git a/src/cpu/intel/haswell/stage_cache.c b/src/cpu/intel/haswell/stage_cache.c index 009cc09..fb4a6c3 100644 --- a/src/cpu/intel/haswell/stage_cache.c +++ b/src/cpu/intel/haswell/stage_cache.c @@ -17,10 +17,10 @@ #include <stage_cache.h> #include "haswell.h" -void stage_cache_external_region(void **base, size_t *size) +void stage_cache_external_region(uintptr_t *base, size_t *size) { /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. * The top of RAM is defined to be the TSEG base address. */ *size = RESERVED_SMM_SIZE; - *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); + *base = cbmem_top() + RESERVED_SMM_OFFSET; } diff --git a/src/cpu/intel/model_206ax/stage_cache.c b/src/cpu/intel/model_206ax/stage_cache.c index 26dc5e0..a0aaba5 100644 --- a/src/cpu/intel/model_206ax/stage_cache.c +++ b/src/cpu/intel/model_206ax/stage_cache.c @@ -17,12 +17,12 @@ #include <stage_cache.h> #include "model_206ax.h" -void stage_cache_external_region(void **base, size_t *size) +void stage_cache_external_region(uintptr_t *base, size_t *size) { /* * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. * The top of RAM is defined to be the TSEG base address. */ *size = RESERVED_SMM_SIZE; - *base = (void *)((uintptr_t)cbmem_top() + RESERVED_SMM_OFFSET); + *base = cbmem_top() + RESERVED_SMM_OFFSET; } diff --git a/src/drivers/intel/fsp1_1/include/fsp/memmap.h b/src/drivers/intel/fsp1_1/include/fsp/memmap.h index 965bce6..49bd019 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/memmap.h +++ b/src/drivers/intel/fsp1_1/include/fsp/memmap.h @@ -27,7 +27,7 @@ /* Fills in the arguments for the entire SMM region covered by chipset * protections. e.g. TSEG. */ -void smm_region(void **start, size_t *size); +void smm_region(uintptr_t *start, size_t *size); enum { /* SMM handler area. */ @@ -42,6 +42,6 @@ /* Fills in the start and size for the requested SMM subregion. Returns * 0 on susccess, < 0 on failure. */ -int smm_subregion(int sub, void **start, size_t *size); +int smm_subregion(int sub, uintptr_t *start, size_t *size); #endif /* _COMMON_MEMMAP_H_ */ diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 7fed2a1..ad9e9dd 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -147,12 +147,12 @@ /* Display SMM area */ #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) - char *smm_base; + uintptr_t smm_base; size_t smm_size; - smm_region((void **)&smm_base, &smm_size); + smm_region(&smm_base, &smm_size); printk(BIOS_DEBUG, "0x%08x: smm_size\n", (unsigned int)smm_size); - printk(BIOS_DEBUG, "0x%p: smm_base\n", smm_base); + printk(BIOS_DEBUG, "0x%08x: smm_base\n", (unsigned int)smm_base); #endif /* Migrate CAR data */ diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 864ab45..41d5437 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -33,19 +33,19 @@ /* Display SMM memory map */ static void smm_memory_map(void) { - void *base; + uintptr_t base; size_t size; int i; printk(BIOS_SPEW, "SMM Memory Map\n"); smm_region(&base, &size); - printk(BIOS_SPEW, "SMRAM : %p 0x%zx\n", base, size); + printk(BIOS_SPEW, "SMRAM : 0x%08x 0x%zx\n", (unsigned int)base, size); for (i = 0; i < SMM_SUBREGION_NUM; i++) { if (smm_subregion(i, &base, &size)) continue; - printk(BIOS_SPEW, " Subregion %d: %p 0x%zx\n", i, base, size); + printk(BIOS_SPEW, " Subregion %d: 0x%08x 0x%zx\n", i, (unsigned int)base, size); } } diff --git a/src/drivers/intel/fsp1_1/stack.c b/src/drivers/intel/fsp1_1/stack.c index eb2a637..1b748aa 100644 --- a/src/drivers/intel/fsp1_1/stack.c +++ b/src/drivers/intel/fsp1_1/stack.c @@ -117,9 +117,8 @@ num_mtrrs++; #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) - void *smm_base; + uintptr_t smm_base; size_t smm_size; - uint32_t tseg_base; /* * Cache the TSEG region at the top of ram. This region is not @@ -128,11 +127,10 @@ * the SMM handler as well as using the TSEG region for other purposes. */ smm_region(&smm_base, &smm_size); - tseg_base = (uint32_t)smm_base; slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ slot = stack_push32(slot, ~(alignment - 1) | MTRR_PHYS_MASK_VALID); slot = stack_push32(slot, 0); /* upper base */ - slot = stack_push32(slot, tseg_base | MTRR_TYPE_WRBACK); + slot = stack_push32(slot, (uint32_t)smm_base | MTRR_TYPE_WRBACK); num_mtrrs++; #endif diff --git a/src/drivers/intel/fsp1_1/stage_cache.c b/src/drivers/intel/fsp1_1/stage_cache.c index 2d594e6..4895340 100644 --- a/src/drivers/intel/fsp1_1/stage_cache.c +++ b/src/drivers/intel/fsp1_1/stage_cache.c @@ -18,11 +18,11 @@ #include <fsp/memmap.h> #include <stage_cache.h> -void stage_cache_external_region(void **base, size_t *size) +void stage_cache_external_region(uintptr_t *base, size_t *size) { if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); - *base = NULL; + *base = 0; *size = 0; } } diff --git a/src/drivers/intel/fsp2_0/include/fsp/memmap.h b/src/drivers/intel/fsp2_0/include/fsp/memmap.h index 965bce6..49bd019 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/memmap.h +++ b/src/drivers/intel/fsp2_0/include/fsp/memmap.h @@ -27,7 +27,7 @@ /* Fills in the arguments for the entire SMM region covered by chipset * protections. e.g. TSEG. */ -void smm_region(void **start, size_t *size); +void smm_region(uintptr_t *start, size_t *size); enum { /* SMM handler area. */ @@ -42,6 +42,6 @@ /* Fills in the start and size for the requested SMM subregion. Returns * 0 on susccess, < 0 on failure. */ -int smm_subregion(int sub, void **start, size_t *size); +int smm_subregion(int sub, uintptr_t *start, size_t *size); #endif /* _COMMON_MEMMAP_H_ */ diff --git a/src/drivers/intel/fsp2_0/stage_cache.c b/src/drivers/intel/fsp2_0/stage_cache.c index 434eae9..2ea6656 100644 --- a/src/drivers/intel/fsp2_0/stage_cache.c +++ b/src/drivers/intel/fsp2_0/stage_cache.c @@ -20,11 +20,11 @@ #include <reset.h> #include <program_loading.h> -void stage_cache_external_region(void **base, size_t *size) +void stage_cache_external_region(uintptr_t *base, size_t *size) { if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); - *base = NULL; + *base = 0; *size = 0; } } diff --git a/src/include/stage_cache.h b/src/include/stage_cache.h index 28cb859..2a6c3bc 100644 --- a/src/include/stage_cache.h +++ b/src/include/stage_cache.h @@ -41,7 +41,7 @@ /* Load the cached stage at given location returning the stage entry point. */ void stage_cache_load_stage(int stage_id, struct prog *stage); /* Fill in parameters for the external stage cache, if utilized. */ -void stage_cache_external_region(void **base, size_t *size); +void stage_cache_external_region(uintptr_t *base, size_t *size); /* Metadata associated with each stage. */ struct stage_cache { diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index c3d4aee..35bcce4 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -32,12 +32,12 @@ static void stage_cache_create_empty(void) { struct imd *imd; - void *base; + uintptr_t base; size_t size; imd = imd_get(); stage_cache_external_region(&base, &size); - imd_handle_init(imd, (void *)(size + (uintptr_t)base)); + imd_handle_init(imd, (void *)(size + base)); printk(BIOS_DEBUG, "External stage cache:\n"); imd_create_tiered_empty(imd, 4096, 4096, 1024, 32); @@ -48,12 +48,12 @@ static void stage_cache_recover(void) { struct imd *imd; - void *base; + uintptr_t base; size_t size; imd = imd_get(); stage_cache_external_region(&base, &size); - imd_handle_init(imd, (void *)(size + (uintptr_t)base)); + imd_handle_init(imd, (void *)(size + base)); if (imd_recover(imd)) printk(BIOS_DEBUG, "Unable to recover external stage cache.\n"); } diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 1d9804d..e5b8bea 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -62,21 +62,21 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - void *smm_base; + uintptr_t smm_base; size_t smm_size; - void *handler_base; + uintptr_t handler_base; size_t handler_size; /* Initialize global tracking state. */ smm_region_info(&smm_base, &smm_size); smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); - relo_attrs.smbase = (uint32_t)smm_base; + relo_attrs.smbase = smm_base; relo_attrs.tseg_base = relo_attrs.smbase; relo_attrs.tseg_mask = ALIGN_DOWN(~(smm_size - 1), 128 * KiB); relo_attrs.tseg_mask |= SMM_TSEG_WB; - *perm_smbase = (uintptr_t)handler_base; + *perm_smbase = handler_base; *perm_smsize = handler_size; *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); } diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index d62c791..82be938 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -114,12 +114,12 @@ * Fills in the arguments for the entire SMM region covered by chipset * protections. e.g. TSEG. */ -void smm_region_info(void **start, size_t *size); +void smm_region_info(uintptr_t *start, size_t *size); /* * Fills in the start and size for the requested SMM subregion. Returns * 0 on success, < 0 on failure. */ -int smm_subregion(int sub, void **start, size_t *size); +int smm_subregion(int sub, uintptr_t *start, size_t *size); void domain_enable_resources(struct device *dev); void domain_read_resources(struct device *dev); void domain_set_resources(struct device *dev); diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c index 15968ab..ea3bd8b 100644 --- a/src/soc/amd/stoneyridge/ramtop.c +++ b/src/soc/amd/stoneyridge/ramtop.c @@ -80,18 +80,18 @@ return CONFIG_SMM_TSEG_SIZE; } -void stage_cache_external_region(void **base, size_t *size) +void stage_cache_external_region(uintptr_t *base, size_t *size) { if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); - *base = NULL; + *base = 0; *size = 0; } } -void smm_region_info(void **start, size_t *size) +void smm_region_info(uintptr_t *start, size_t *size) { - *start = (void *)smm_region_start(); + *start = smm_region_start(); *size = smm_region_size(); } @@ -117,7 +117,7 @@ wrmsr(SMM_MASK_MSR, mask); } -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { uintptr_t sub_base; size_t sub_size; @@ -143,7 +143,7 @@ return -1; } - *start = (void *)sub_base; + *start = sub_base; *size = sub_size; return 0; diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 9314488..e89f9e6 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -82,7 +82,7 @@ { struct postcar_frame pcf; uintptr_t top_of_ram; - void *smm_base; + uintptr_t smm_base; size_t smm_size; uintptr_t tseg_base; msr_t base, mask; diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index bcec28e..89faa85 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -196,9 +196,9 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - void *smm_base; + uintptr_t smm_base; size_t smm_size; - void *handler_base; + uintptr_t handler_base; size_t handler_size; /* All range registers are aligned to 4KiB */ diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index be15e16..50ececa 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -48,7 +48,7 @@ return tolum; } -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { uintptr_t sub_base; size_t sub_size; @@ -56,7 +56,6 @@ const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; smm_region_info(&smm_base, &sub_size); - sub_base = (uintptr_t)smm_base; assert(sub_size > CONFIG_SMM_RESERVED_SIZE); @@ -74,7 +73,7 @@ return -1; } - *start = (void *)sub_base; + *start = smm_base; *size = sub_size; return 0; diff --git a/src/soc/intel/baytrail/stage_cache.c b/src/soc/intel/baytrail/stage_cache.c index 4c2a976..8e8c67f 100644 --- a/src/soc/intel/baytrail/stage_cache.c +++ b/src/soc/intel/baytrail/stage_cache.c @@ -17,7 +17,7 @@ #include <stage_cache.h> #include <soc/smm.h> -void stage_cache_external_region(void **base, size_t *size) +void stage_cache_external_region(uintptr_t *base, size_t *size) { char *smm_base; /* 1MiB cache size */ @@ -27,5 +27,5 @@ * cbmem_top(). */ smm_base = cbmem_top(); *size = cache_size; - *base = &smm_base[smm_region_size() - cache_size]; + *base = smm_base + smm_region_size() - cache_size; } diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 12f34fb..b4face2 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -147,7 +147,7 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - void *smm_base; + uintptr_t smm_base; size_t smm_size; /* All range registers are aligned to 4KiB */ diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index d7c9952..89c3ab0 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -29,9 +29,9 @@ return smm_size; } -void smm_region(void **start, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - *start = (void *)((iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20); + *start = (iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20; *size = smm_region_size(); } @@ -51,15 +51,13 @@ * | (TSEG) | * +-------------------------+ BUNIT_SMRRL */ -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { uintptr_t sub_base; - void *sub_ptr; size_t sub_size; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; - smm_region(&sub_ptr, &sub_size); - sub_base = (uintptr_t)sub_ptr; + smm_region(&sub_base, &sub_size); switch (sub) { case SMM_SUBREGION_HANDLER: @@ -75,7 +73,7 @@ return -1; } - *start = (void *)sub_base; + *start = sub_base; *size = sub_size; return 0; @@ -83,7 +81,7 @@ void *cbmem_top(void) { - char *smm_base; + uintptr_t smm_base; size_t smm_size; /* @@ -114,6 +112,6 @@ * +-------------------------+ */ - smm_region((void **)&smm_base, &smm_size); + smm_region(&smm_base, &smm_size); return (void *)smm_base; } diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index 6e148b9..36b4377 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -87,7 +87,7 @@ unsigned long mmconf; unsigned long bmbound_k; unsigned long bmbound_hi; - void *smm_base; + uintptr_t smm_base; size_t smm_size; unsigned long tseg_base_k; unsigned long tseg_top_k; diff --git a/src/soc/intel/broadwell/stage_cache.c b/src/soc/intel/broadwell/stage_cache.c index dc59ab7..b812ced 100644 --- a/src/soc/intel/broadwell/stage_cache.c +++ b/src/soc/intel/broadwell/stage_cache.c @@ -18,7 +18,7 @@ #include <stage_cache.h> #include <stdint.h> -void stage_cache_external_region(void **base, size_t *size) +void stage_cache_external_region(uintptr_t *base, size_t *size) { /* The ramstage cache lives in the TSEG region. * The top of RAM is defined to be the TSEG base address. */ @@ -26,6 +26,6 @@ offset -= CONFIG_IED_REGION_SIZE; offset -= CONFIG_SMM_RESERVED_SIZE; - *base = (void *)(cbmem_top() + offset); + *base = cbmem_top() + offset; *size = CONFIG_SMM_RESERVED_SIZE; } diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 64e07be..8aeabac 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -29,9 +29,9 @@ #include <soc/systemagent.h> #include <stdlib.h> -void smm_region(void **start, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - *start = (void *)sa_get_tseg_base(); + *start = sa_get_tseg_base(); *size = sa_get_tseg_size(); } @@ -46,16 +46,14 @@ * | (TSEG) | * +-------------------------+ TSEG */ -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { uintptr_t sub_base; size_t sub_size; - void *smm_base; const size_t ied_size = CONFIG_IED_REGION_SIZE; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; - smm_region(&smm_base, &sub_size); - sub_base = (uintptr_t)smm_base; + smm_region(&sub_base, &sub_size); switch (sub) { case SMM_SUBREGION_HANDLER: @@ -77,7 +75,7 @@ return -1; } - *start = (void *)sub_base; + *start = sub_base; *size = sub_size; return 0; diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index e688592..59ae790 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -173,11 +173,11 @@ static void fill_in_relocation_params(struct device *dev, struct smm_relocation_params *params) { - void *handler_base; + uintptr_t handler_base; size_t handler_size; - void *ied_base; + uintptr_t *ied_base; size_t ied_size; - void *tseg_base; + uintptr_t tseg_base; size_t tseg_size; u32 emrr_base; u32 emrr_size; @@ -196,9 +196,9 @@ smm_subregion(SMM_SUBREGION_CHIPSET, &ied_base, &ied_size); params->smram_size = handler_size; - params->smram_base = (uintptr_t)handler_base; + params->smram_base = handler_base; - params->ied_base = (uintptr_t)ied_base; + params->ied_base = ied_base; params->ied_size = ied_size; /* SMRR has 32-bits of valid address aligned to 4KiB. */ @@ -232,24 +232,21 @@ static void setup_ied_area(struct smm_relocation_params *params) { - char *ied_base; - struct ied_header ied = { .signature = "INTEL RSVD", .size = params->ied_size, .reserved = {0}, }; - ied_base = (void *)params->ied_base; printk(BIOS_DEBUG, "IED base = 0x%08x\n", params->ied_base); printk(BIOS_DEBUG, "IED size = 0x%08x\n", params->ied_size); /* Place IED header at IEDBASE. */ - memcpy(ied_base, &ied, sizeof(ied)); + memcpy(params->ied_base, &ied, sizeof(ied)); /* Zero out 32KiB at IEDBASE + 1MiB */ - memset(ied_base + 1 * MiB, 0, 32 * KiB); + memset(params->ied_base + 1 * MiB, 0, 32 * KiB); } void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, diff --git a/src/soc/intel/common/block/include/intelblocks/smm.h b/src/soc/intel/common/block/include/intelblocks/smm.h index c04ec46..e2d38fd 100644 --- a/src/soc/intel/common/block/include/intelblocks/smm.h +++ b/src/soc/intel/common/block/include/intelblocks/smm.h @@ -33,6 +33,6 @@ void smm_southbridge_clear_state(void); void smm_southbridge_enable(uint16_t pm1_events); /* API to get SMM region start and size based on Host Bridge register */ -void smm_region_info(void **start, size_t *size); +void smm_region_info(uintptr_t *start, size_t *size); #endif diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c index d929975..d9b5645 100644 --- a/src/soc/intel/common/block/smm/smm.c +++ b/src/soc/intel/common/block/smm/smm.c @@ -89,9 +89,9 @@ ); } -void smm_region_info(void **start, size_t *size) +void smm_region_info(uintptr_t *start, size_t *size) { - *start = (void *)sa_get_tseg_base(); + *start = sa_get_tseg_base(); *size = sa_get_tseg_size(); } diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 676fab7..683af8e 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -91,9 +91,9 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - void *smm_base; + uintptr_t smm_base; size_t smm_size; - void *handler_base; + uintptr_t handler_base; size_t handler_size; /* All range registers are aligned to 4KiB */ @@ -108,7 +108,7 @@ relo_attrs.smrr_mask = ~(smm_size - 1) & rmask; relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; - *perm_smbase = (uintptr_t)handler_base; + *perm_smbase = handler_base; *perm_smsize = handler_size; *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); } diff --git a/src/soc/intel/denverton_ns/include/soc/smm.h b/src/soc/intel/denverton_ns/include/soc/smm.h index 771c3d8..e597e9d 100644 --- a/src/soc/intel/denverton_ns/include/soc/smm.h +++ b/src/soc/intel/denverton_ns/include/soc/smm.h @@ -33,7 +33,7 @@ /* Fills in the arguments for the entire SMM region covered by chipset * protections. e.g. TSEG. */ -void smm_region(void **start, size_t *size); +void smm_region(uintptr_t *start, size_t *size); enum { /* SMM handler area. */ @@ -48,7 +48,7 @@ /* Fills in the start and size for the requested SMM subregion. Returns * 0 on success, < 0 on failure. */ -int smm_subregion(int sub, void **start, size_t *size); +int smm_subregion(int sub, uintptr_t *start, size_t *size); #if !defined(__PRE_RAM__) && !defined(__SMM___) #include <stdint.h> diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index a42d861..b4812ab 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -71,13 +71,13 @@ return system_agent_region_base(TOLUD) - smm_region_start(); } -void smm_region(void **start, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - *start = (void *)smm_region_start(); + *start = smm_region_start(); *size = smm_region_size(); } -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { uintptr_t sub_base; size_t sub_size; @@ -102,7 +102,7 @@ return -1; } - *start = (void *)sub_base; + *start = sub_base; *size = sub_size; return 0; diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 617b64a..712ec83 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -147,9 +147,8 @@ uintptr_t top_of_ram; #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) - void *smm_base; + uintptr_t smm_base; size_t smm_size; - uintptr_t tseg_base; #endif console_init(); @@ -190,8 +189,7 @@ * region for other purposes. */ smm_region(&smm_base, &smm_size); - tseg_base = (uintptr_t)smm_base; - postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); #endif run_postcar_phase(&pcf); diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index 027b8b0..20ae6e8 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -28,9 +28,9 @@ #include <soc/systemagent.h> #include <stdlib.h> -void smm_region(void **start, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - *start = (void *)sa_get_tseg_base(); + *start = sa_get_tseg_base(); *size = sa_get_tseg_size(); } @@ -45,16 +45,14 @@ * | (TSEG) | * +-------------------------+ TSEG */ -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { - uintptr_t sub_base; size_t sub_size; - void *smm_base; + uintptr_t smm_base; const size_t ied_size = CONFIG_IED_REGION_SIZE; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; smm_region(&smm_base, &sub_size); - sub_base = (uintptr_t)smm_base; switch (sub) { case SMM_SUBREGION_HANDLER: @@ -76,7 +74,7 @@ return -1; } - *start = (void *)sub_base; + *start = smm_base; *size = sub_size; return 0; diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index 57a366a..bb81799 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -172,11 +172,11 @@ static void fill_in_relocation_params(struct device *dev, struct smm_relocation_params *params) { - void *handler_base; + uintptr_t handler_base; size_t handler_size; - void *ied_base; + uintptr_t ied_base; size_t ied_size; - void *tseg_base; + uintptr_t tseg_base; size_t tseg_size; u32 emrr_base; u32 emrr_size; @@ -195,9 +195,9 @@ smm_subregion(SMM_SUBREGION_CHIPSET, &ied_base, &ied_size); params->smram_size = handler_size; - params->smram_base = (uintptr_t)handler_base; + params->smram_base = handler_base; - params->ied_base = (uintptr_t)ied_base; + params->ied_base = ied_base; params->ied_size = ied_size; /* SMRR has 32-bits of valid address aligned to 4KiB. */ @@ -231,24 +231,21 @@ static void setup_ied_area(struct smm_relocation_params *params) { - char *ied_base; - struct ied_header ied = { .signature = "INTEL RSVD", .size = params->ied_size, .reserved = {0}, }; - ied_base = (void *)params->ied_base; printk(BIOS_DEBUG, "IED base = 0x%08x\n", params->ied_base); printk(BIOS_DEBUG, "IED size = 0x%08x\n", params->ied_size); /* Place IED header at IEDBASE. */ - memcpy(ied_base, &ied, sizeof(ied)); + memcpy(params->ied_base, &ied, sizeof(ied)); /* Zero out 32KiB at IEDBASE + 1MiB */ - memset(ied_base + 1 * MiB, 0, 32 * KiB); + memset(params->ied_base + 1 * MiB, 0, 32 * KiB); } void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index f0ccb1d..c33787a 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -40,9 +40,9 @@ return 8*MiB; } -void smm_region(void **start, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - *start = (void *)sa_get_tseg_base(); + *start = sa_get_tseg_base(); *size = sa_get_tseg_size(); } @@ -57,16 +57,14 @@ * | (TSEG) | * +-------------------------+ TSEG */ -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { - uintptr_t sub_base; size_t sub_size; - void *smm_base; + uintptr_t smm_base; const size_t ied_size = CONFIG_IED_REGION_SIZE; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; smm_region(&smm_base, &sub_size); - sub_base = (uintptr_t)smm_base; switch (sub) { case SMM_SUBREGION_HANDLER: @@ -88,7 +86,7 @@ return -1; } - *start = (void *)sub_base; + *start = smm_base; *size = sub_size; return 0; diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 2a60158..248f50f 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -167,7 +167,7 @@ postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { - void *smm_base; + uintptr_t *smm_base; size_t smm_size; uintptr_t tseg_base; @@ -179,7 +179,7 @@ * region for other purposes. */ smm_region(&smm_base, &smm_size); - tseg_base = (uintptr_t)smm_base; + tseg_base = smm_base; postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); } diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index cb4e23f..82aacd4 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -241,24 +241,21 @@ static void setup_ied_area(struct smm_relocation_params *params) { - char *ied_base; - struct ied_header ied = { .signature = "INTEL RSVD", .size = params->ied_size, .reserved = {0}, }; - ied_base = (void *)params->ied_base; printk(BIOS_DEBUG, "IED base = 0x%08x\n", params->ied_base); printk(BIOS_DEBUG, "IED size = 0x%08x\n", params->ied_size); /* Place IED header at IEDBASE. */ - memcpy(ied_base, &ied, sizeof(ied)); + memcpy(params->ied_base, &ied, sizeof(ied)); /* Zero out 32KiB at IEDBASE + 1MiB */ - memset(ied_base + (1 << 20), 0, (32 << 10)); + memset(params->ied_base + 1 * MiB, 0, 32 * KiB); } void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, -- To view, visit https://review.coreboot.org/c/coreboot/+/30684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ef5d9fad0298c79806fd94ca053027822022ac2 Gerrit-Change-Number: 30684 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

7 19

Change in ...coreboot[master]: lib/prog_loaders.c: Add prog_locate_hook() for measured and verified ...
by Frans Hendriks (Code Review) 28 Oct '19

28 Oct '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30811 Change subject: lib/prog_loaders.c: Add prog_locate_hook() for measured and verified boot. ...................................................................... lib/prog_loaders.c: Add prog_locate_hook() for measured and verified boot. Before images are loaded from cbfs it needs to be measured and/or verified. prog_locate_hook() is added and can be used to start measured/verified boot. BUG=N/A TEST=Created verified binary and verify logging on Facebook FBG-1701 Change-Id: I12207fc8f2e9ca45d048cf8c8d9c057f53e5c2c7 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/include/program_loading.h M src/lib/prog_loaders.c 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/30811/1 diff --git a/src/include/program_loading.h b/src/include/program_loading.h index 468f0b3..a382daf 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -3,6 +3,7 @@ * * Copyright 2015 Google Inc. * Copyright (C) 2014 Imagination Technologies + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -136,6 +137,7 @@ /* Locate the identified program to run. Return 0 on success. < 0 on error. */ int prog_locate(struct prog *prog); +int prog_locate_hook(struct prog *prog); /* Run the program described by prog. */ void prog_run(struct prog *prog); diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index b763417..4fa9a03 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright 2015 Google Inc. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -39,6 +40,9 @@ { struct cbfsf file; + if (prog_locate_hook(prog)) + return -1; + cbfs_prepare_program_locate(); if (cbfs_boot_locate(&file, prog_name(prog), NULL)) @@ -74,6 +78,7 @@ halt(); } +int __weak prog_locate_hook(struct prog *prog) {return 0; } void __weak stage_cache_add(int stage_id, const struct prog *stage) {} void __weak stage_cache_load_stage(int stage_id, -- To view, visit https://review.coreboot.org/c/coreboot/+/30811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12207fc8f2e9ca45d048cf8c8d9c057f53e5c2c7 Gerrit-Change-Number: 30811 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

9 45

← Newer
1
...
6
7
8
9
10
11
12
...
125
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2019