coreboot-gerrit December 2019

coreboot-gerrit@coreboot.org

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1761 discussions

Change in coreboot[master]: mb/google/hatch: Enable PchPmSlpS0Vm075VSupport for hatch
by Kane Chen (Code Review) 02 Dec '19

02 Dec '19

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35596 ) Change subject: mb/google/hatch: Enable PchPmSlpS0Vm075VSupport for hatch ...................................................................... mb/google/hatch: Enable PchPmSlpS0Vm075VSupport for hatch On hatch and variant HW designs supports VCCPRIM_CORE Low Voltage Mode. VCCPRIM_CORE can be down to 0.75v when slp_s0 is asserted. This commit enables PchPmSlpS0Vm075VSupport UPD so that FSP can program related setttings to save power. BUG=b:134092071 TEST=Run suspend_stress_test on kohaku and pass 100 cycles Change-Id: Ia02ff8823883489b36349457213409496f082f36 Signed-off-by: Kane Chen <kane.chen(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/35596/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 7382209..a2831e1 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -58,6 +58,8 @@ register "PmTimerDisabled" = "1" + register "PchPmSlpS0Vm075VSupport" = "1" + # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | -- To view, visit https://review.coreboot.org/c/coreboot/+/35596 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia02ff8823883489b36349457213409496f082f36 Gerrit-Change-Number: 35596 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cannonlake: Ensure bootblock disable GPIO PM configuration
by Subrata Banik (Code Review) 02 Dec '19

02 Dec '19

Hello Patrick Rudolph, EricR Lai, Selma Bensaid, Bora Guvendik, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/37319 to look at the new patch set (#4). Change subject: soc/intel/cannonlake: Ensure bootblock disable GPIO PM configuration ...................................................................... soc/intel/cannonlake: Ensure bootblock disable GPIO PM configuration This patch performs below operations: 1. Rename soc_fill_gpio_pm_configuration to soc_gpio_pm_configuration 2. Avoid redundent definitions of soc_fill_gpio_pm_configuration 3. Calling from bootblock and after FSP-S to ensure GPIO PM configuration is disable even with platform reset. BUG=b:144002424 TEST=coreboot disable all MISCCFG.bit 0-5 local clock gating. Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/cannonlake/chip.c A src/soc/intel/cannonlake/gpio_common.c M src/soc/intel/cannonlake/include/soc/gpio.h 5 files changed, 56 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/37319/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/37319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250 Gerrit-Change-Number: 37319 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/cannonlake: Ensure bootblock disable GPIO PM configuration
by Subrata Banik (Code Review) 02 Dec '19

02 Dec '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37319 ) Change subject: soc/intel/cannonlake: Ensure bootblock disable GPIO PM configuration ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/37319/2/src/soc/intel/cannonlake/b… File src/soc/intel/cannonlake/bootblock/pch.c: https://review.coreboot.org/c/coreboot/+/37319/2/src/soc/intel/cannonlake/b… PS2, Line 186: soc_fill_gpio_pm_configuration > Agree with Furquan, this is why I said we should invoke this right after FSP-S.... Done -- To view, visit https://review.coreboot.org/c/coreboot/+/37319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250 Gerrit-Change-Number: 37319 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Dec 2019 06:21:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Ensure bootblock disable GPIO PM configuration
by Subrata Banik (Code Review) 02 Dec '19

02 Dec '19

Hello Patrick Rudolph, EricR Lai, Selma Bensaid, Bora Guvendik, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/37319 to look at the new patch set (#3). Change subject: soc/intel/cannonlake: Ensure bootblock disable GPIO PM configuration ...................................................................... soc/intel/cannonlake: Ensure bootblock disable GPIO PM configuration This patch performs below operations: 1. Rename soc_fill_gpio_pm_configuration to soc_gpio_pm_configuration 2. Avoid redundent definitions of soc_fill_gpio_pm_configuration 3. Calling from bootblock and after FSP-S to ensure GPIO PM configuration is disable even with platform reset. BUG=b:144002424 TEST=coreboot disable all MISCCFG.bit 0-5 local clock gating. Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/cannonlake/chip.c M src/soc/intel/cannonlake/gpio.c M src/soc/intel/cannonlake/include/soc/gpio.h 4 files changed, 36 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/37319/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/37319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250 Gerrit-Change-Number: 37319 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/cannonlake: Ensure bootblock disable GPIO PM configuration
by EricR Lai (Code Review) 02 Dec '19

02 Dec '19

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37319 ) Change subject: soc/intel/cannonlake: Ensure bootblock disable GPIO PM configuration ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/37319/2/src/soc/intel/cannonlake/b… File src/soc/intel/cannonlake/bootblock/pch.c: https://review.coreboot.org/c/coreboot/+/37319/2/src/soc/intel/cannonlake/b… PS2, Line 186: soc_fill_gpio_pm_configuration > valid point, let me address this Agree with Furquan, this is why I said we should invoke this right after FSP-S.... -- To view, visit https://review.coreboot.org/c/coreboot/+/37319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250 Gerrit-Change-Number: 37319 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Dec 2019 05:39:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Ensure bootblock disable GPIO PM configuration
by Subrata Banik (Code Review) 02 Dec '19

02 Dec '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37319 ) Change subject: soc/intel/cannonlake: Ensure bootblock disable GPIO PM configuration ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/37319/2/src/soc/intel/cannonlake/b… File src/soc/intel/cannonlake/bootblock/pch.c: https://review.coreboot.org/c/coreboot/+/37319/2/src/soc/intel/cannonlake/b… PS2, Line 186: soc_fill_gpio_pm_configuration > I don't think we need to duplicate this function: https://review.coreboot.org/cgit/coreboot. […] valid point, let me address this -- To view, visit https://review.coreboot.org/c/coreboot/+/37319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250 Gerrit-Change-Number: 37319 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Dec 2019 04:59:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Ensure bootblock disable GPIO PM configuration
by Furquan Shaikh (Code Review) 02 Dec '19

02 Dec '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37319 ) Change subject: soc/intel/cannonlake: Ensure bootblock disable GPIO PM configuration ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/37319/2/src/soc/intel/cannonlake/b… File src/soc/intel/cannonlake/bootblock/pch.c: https://review.coreboot.org/c/coreboot/+/37319/2/src/soc/intel/cannonlake/b… PS2, Line 186: soc_fill_gpio_pm_configuration I don't think we need to duplicate this function: https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/cannonlake… Can this instead be added to a file that can be used by either stage? Also, I think we should name this function differently -- it is not just filling GPIO PM configuration, but actually performing GPIO PM configuration. -- To view, visit https://review.coreboot.org/c/coreboot/+/37319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250 Gerrit-Change-Number: 37319 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Dec 2019 04:49:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in em100[master]: WIP: Add preliminary network update functionality
by Stefan Reinauer (Code Review) 02 Dec '19

02 Dec '19

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/37072 ) Change subject: WIP: Add preliminary network update functionality ...................................................................... WIP: Add preliminary network update functionality DO NOT MERGE. Incomplete. Only for your amusement. Update chip database and firmware images over the network. Change-Id: I5c378754da4ce06b63f317eb22fa237d7a616fd8 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M Makefile M em100.c M em100.h M tar.c 4 files changed, 13 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/72/37072/1 diff --git a/Makefile b/Makefile index ef1bd01..c4c33b4 100644 --- a/Makefile +++ b/Makefile @@ -36,7 +36,7 @@ XZ = xz/xz_crc32.c xz/xz_crc64.c xz/xz_dec_bcj.c xz/xz_dec_lzma2.c xz/xz_dec_stream.c SOURCES = em100.c firmware.c fpga.c hexdump.c sdram.c spi.c system.c trace.c usb.c -SOURCES += tar.c $(XZ) +SOURCES += curl.c tar.c $(XZ) OBJECTS = $(SOURCES:.c=.o) diff --git a/em100.c b/em100.c index d075711..30a518c 100644 --- a/em100.c +++ b/em100.c @@ -690,6 +690,7 @@ {"firmware-write", 1, 0, 'g'}, {"device", 1, 0, 'x'}, {"list-devices", 0, 0, 'l'}, + {"update-files", 0, 0, 'U'}, {"terminal",0 ,0, 'T'}, {NULL, 0, 0, 0} }; @@ -718,6 +719,7 @@ " -x|--device BUS:DEV use EM100pro on USB bus/device\n" " -x|--device DPxxxxxx use EM100pro with serial no DPxxxxxx\n" " -l|--list-devices list all connected EM100pro devices\n" + " -U|--update-files update device (chip) and firmware database\n" " -D|--debug: print debug information.\n" " -h|--help: this help text\n\n", name); @@ -742,9 +744,7 @@ unsigned long spi_start_address = 0; const char *voltage = NULL; - test_tar(); - - while ((opt = getopt_long(argc, argv, "c:d:a:u:rsvtO:F:f:g:S:V:p:Dx:lhT", + while ((opt = getopt_long(argc, argv, "c:d:a:u:rsvtO:F:f:g:S:V:p:Dx:lUhT", longopts, &idx)) != -1) { switch (opt) { case 'c': @@ -812,6 +812,9 @@ case 'l': em100_list(); return 0; + case 'U': + update_all_files(); + return 0; default: case 'h': usage(argv[0]); diff --git a/em100.h b/em100.h index 0f5d51d..dd01204 100644 --- a/em100.h +++ b/em100.h @@ -171,6 +171,10 @@ unsigned char *tar_load_compressed(char *filename, long *length); int test_tar(void); +/* Network */ +void download(char *name, char *id); +int update_all_files(void); + /* Misc. */ #define MB * 1024 * 1024 diff --git a/tar.c b/tar.c index 23e4486..aceaf29 100644 --- a/tar.c +++ b/tar.c @@ -235,6 +235,7 @@ return fw; } +#if 0 int test_tar(void) { int ret; @@ -270,4 +271,4 @@ free(fw); return 0; } - +#endif -- To view, visit https://review.coreboot.org/c/em100/+/37072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I5c378754da4ce06b63f317eb22fa237d7a616fd8 Gerrit-Change-Number: 37072 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [DO NOT SUBMIT] Dump full calibration params
by Yu-Ping Wu (Code Review) 02 Dec '19

02 Dec '19

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35618 ) Change subject: [DO NOT SUBMIT] Dump full calibration params ...................................................................... [DO NOT SUBMIT] Dump full calibration params This patch is only for debugging. Change-Id: I04ec044776f2168a149a21a199b0adb0aa68e46f Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/mainboard/google/kukui/romstage.c M src/soc/mediatek/mt8183/Kconfig M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/emi.h 4 files changed, 54 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/35618/1 diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c old mode 100644 new mode 100755 index 2fbc789..0359887 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -108,6 +108,9 @@ if (err == 0) { printk(BIOS_INFO, "successfully load dram_blob and " "run DRAM calibration\n"); + just_for_test_dump_coreboot_params(&freq_params[DRAM_DFS_SHUFFLE_1]); + just_for_test_dump_coreboot_params(&freq_params[DRAM_DFS_SHUFFLE_2]); + just_for_test_dump_coreboot_params(&freq_params[DRAM_DFS_SHUFFLE_3]); write_calibration_data_to_flash(freq_params); return; } diff --git a/src/soc/mediatek/mt8183/Kconfig b/src/soc/mediatek/mt8183/Kconfig old mode 100644 new mode 100755 index 576f2d5..ba65aa5 --- a/src/soc/mediatek/mt8183/Kconfig +++ b/src/soc/mediatek/mt8183/Kconfig @@ -19,7 +19,7 @@ config DEBUG_DRAM bool "Output verbose DRAM related debug messages" - default n + default y help This option enables additional DRAM related debug messages. diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c old mode 100644 new mode 100755 index dfd59b1..1b0c120 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -65,6 +65,9 @@ bool have_calibration_params(const struct sdram_params *params) { + dramc_show("calibration_result_start:%#x, calibration_result_end:%#x\n", + params->calibration_result_start, + params->calibration_result_end); return (params->calibration_result_start == PARAM_START_PATTERN && params->calibration_result_end == PARAM_END_PATTERN); } @@ -477,6 +480,48 @@ } #endif +void just_for_test_dump_coreboot_params(const struct sdram_params *params) +{ + dramc_show("%s dump params calibration_result_start\n", __func__); + dramc_show("calibration_result_start = 0x%x\n", params->calibration_result_start); + + dramc_show("dump params frequency:%d\n", params->frequency); + + dramc_show("\n dump params write leveling\n"); + for (u8 chn = 0; chn < 2; chn++) + for (u8 rk = 0; rk < 2; rk++) + for (u8 dqs = 0; dqs < 2; dqs++) + dramc_show("write leveling[%d][%d][%d] = 0x%x\n", + chn, rk, dqs, params->wr_level[chn][rk][dqs]); + + dramc_show("dump params cbt_cs\n"); + for (u8 chn = 0; chn < 2; chn++) + for (u8 rk = 0; rk < 2; rk++) + dramc_show("cbt_cs[%d][%d] = 0x%x\n", + chn, rk, params->cbt_cs_dly[chn][rk]); + + dramc_show("dump params cbt_mr12\n"); + for (u8 chn = 0; chn < 2; chn++) + for (u8 rk = 0; rk < 2; rk++) + dramc_show("cbt_mr12[%d][%d] = 0x%x\n", + chn, rk, params->cbt_final_vref[chn][rk]); + + dramc_show("dump params clk_delay\n"); + for (u8 chn = 0; chn < 2; chn++) + dramc_show("clk_delay[%d] = %d\n", chn, params->duty_clk_delay[chn]); + + dramc_show("dump params dqs_delay\n"); + for (u8 chn = 0; chn < 2; chn++) + for (u8 dqs = 0; dqs < 2; dqs++) + dramc_show("dqs_delay[%d][%d] = %d\n", + chn, dqs, params->duty_dqs_delay[chn][dqs]); + + dramc_show("dump params delay_cell_unit\n"); + dramc_show("delay_cell_unit = %d\n", params->delay_cell_unit); + dramc_show("calibration_result_end = 0x%x\n", params->calibration_result_end); + +} + void mt_set_emi(const struct sdram_params *freq_params) { int freq_shuffle = DRAM_DFS_SHUFFLE_1; @@ -489,6 +534,8 @@ u8 current_freqsel = freq_tbl[freq_shuffle]; params = &freq_params[freq_shuffle]; + just_for_test_dump_coreboot_params(params); + init_dram(params, current_freqsel); do_calib(params, current_freqsel); diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h old mode 100644 new mode 100755 index cdaadbc..55a2b0e --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -88,4 +88,7 @@ bool have_calibration_params(const struct sdram_params *params); void clean_calibration_data(void); +void just_for_test_dump_coreboot_params(const struct sdram_params *params); + + #endif /* SOC_MEDIATEK_MT8183_EMI_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04ec044776f2168a149a21a199b0adb0aa68e46f Gerrit-Change-Number: 35618 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/spi/flashconsole: Re-add NULL checks
by Patrick Georgi (Code Review) 01 Dec '19

01 Dec '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37375 ) Change subject: drivers/spi/flashconsole: Re-add NULL checks ...................................................................... drivers/spi/flashconsole: Re-add NULL checks Change-Id: I5a90ea9aa3dd510beb6941b000d081944d5a2b95 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/drivers/spi/flashconsole.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/37375/1 diff --git a/src/drivers/spi/flashconsole.c b/src/drivers/spi/flashconsole.c index afe3492..98f3cb4 100644 --- a/src/drivers/spi/flashconsole.c +++ b/src/drivers/spi/flashconsole.c @@ -81,6 +81,9 @@ void flashconsole_tx_byte(unsigned char c) { + if (!rdev_ptr) + return; + size_t region_size = region_device_sz(rdev_ptr); line_buffer[line_offset++] = c; @@ -104,6 +107,9 @@ if (busy) return; + if (!rdev_ptr) + return; + busy = 1; region_size = region_device_sz(rdev_ptr); if (offset + len >= region_size) -- To view, visit https://review.coreboot.org/c/coreboot/+/37375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a90ea9aa3dd510beb6941b000d081944d5a2b95 Gerrit-Change-Number: 37375 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit December 2019