coreboot-gerrit December 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: Add ipc-300 devicetree and hsio. lapic 0
by Дмитрий Понаморев (Code Review) 10 Dec '19

10 Dec '19

Дмитрий Понаморев has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37632 ) Change subject: Add ipc-300 devicetree and hsio. lapic 0 ...................................................................... Patch Set 1: This our second motherboard on denverton_ns with vga ASPEED AST2510. Intel i211-AT non work on FreeBSD... -- To view, visit https://review.coreboot.org/c/coreboot/+/37632 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib230dba7cea898a9bc4792990ac469aec57643d0 Gerrit-Change-Number: 37632 Gerrit-PatchSet: 1 Gerrit-Owner: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-Comment-Date: Tue, 10 Dec 2019 12:28:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Changes of Intel Harcuvar CRB sources for Atom C3538 Teleplatforms Ze...
by Дмитрий Понаморев (Code Review) 10 Dec '19

10 Dec '19

Дмитрий Понаморев has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36411 ) Change subject: Changes of Intel Harcuvar CRB sources for Atom C3538 Teleplatforms Zero board ...................................................................... Patch Set 2: This for our first motherboard with intel FM10400 (Zero) -- To view, visit https://review.coreboot.org/c/coreboot/+/36411 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43735b376bafb1fd995fde50bc4e7d7ace915a03 Gerrit-Change-Number: 36411 Gerrit-PatchSet: 2 Gerrit-Owner: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-Comment-Date: Tue, 10 Dec 2019 12:26:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp1_1: Configure UART after memory init
by Paul Menzel (Code Review) 10 Dec '19

10 Dec '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28464 ) Change subject: drivers/intel/fsp1_1: Configure UART after memory init ...................................................................... Patch Set 4: Code-Review+1 (2 comments) https://review.coreboot.org/c/coreboot/+/28464/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/28464/4//COMMIT_MSG@9 PS4, Line 9: FSP code will default enable the onboard serial port. , and does not allow to configure it. https://review.coreboot.org/c/coreboot/+/28464/4//COMMIT_MSG@9 PS4, Line 9: default by default -- To view, visit https://review.coreboot.org/c/coreboot/+/28464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d Gerrit-Change-Number: 28464 Gerrit-PatchSet: 4 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Tue, 10 Dec 2019 11:23:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/daisy: Move 'PMIC_BUS' to Kconfig
by HAOUAS Elyes (Code Review) 10 Dec '19

10 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37580 ) Change subject: mb/google/daisy: Move 'PMIC_BUS' to Kconfig ...................................................................... mb/google/daisy: Move 'PMIC_BUS' to Kconfig Change-Id: If40fa38e5b249452a6dacf4a4045b6bd00c27cfa Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/daisy/Kconfig M src/mainboard/google/daisy/romstage.c 2 files changed, 14 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/37580/1 diff --git a/src/mainboard/google/daisy/Kconfig b/src/mainboard/google/daisy/Kconfig index f15bd9b..61bb80b 100644 --- a/src/mainboard/google/daisy/Kconfig +++ b/src/mainboard/google/daisy/Kconfig @@ -58,4 +58,8 @@ int default 3 +config PMIC_BUS + int + default 0 + endif # BOARD_GOOGLE_DAISY diff --git a/src/mainboard/google/daisy/romstage.c b/src/mainboard/google/daisy/romstage.c index 838a6c7..0857024 100644 --- a/src/mainboard/google/daisy/romstage.c +++ b/src/mainboard/google/daisy/romstage.c @@ -36,8 +36,6 @@ #include "exynos5250.h" -#define PMIC_BUS 0 - static void setup_power(int is_resume) { int error = 0; @@ -63,26 +61,26 @@ * * Disable Coin BATT Charging */ - error = max77686_disable_backup_batt(PMIC_BUS); + error = max77686_disable_backup_batt(CONFIG_PMIC_BUS); - error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK2, VDD_ARM_MV, + error |= max77686_volsetting(CONFIG_PMIC_BUS, PMIC_BUCK2, VDD_ARM_MV, REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK3, VDD_INT_UV, + error |= max77686_volsetting(CONFIG_PMIC_BUS, PMIC_BUCK3, VDD_INT_UV, REG_ENABLE, MAX77686_UV); - error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK1, VDD_MIF_MV, + error |= max77686_volsetting(CONFIG_PMIC_BUS, PMIC_BUCK1, VDD_MIF_MV, REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK4, VDD_G3D_MV, + error |= max77686_volsetting(CONFIG_PMIC_BUS, PMIC_BUCK4, VDD_G3D_MV, REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUS, PMIC_LDO2, VDD_LDO2_MV, + error |= max77686_volsetting(CONFIG_PMIC_BUS, PMIC_LDO2, VDD_LDO2_MV, REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUS, PMIC_LDO3, VDD_LDO3_MV, + error |= max77686_volsetting(CONFIG_PMIC_BUS, PMIC_LDO3, VDD_LDO3_MV, REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUS, PMIC_LDO5, VDD_LDO5_MV, + error |= max77686_volsetting(CONFIG_PMIC_BUS, PMIC_LDO5, VDD_LDO5_MV, REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUS, PMIC_LDO10, VDD_LDO10_MV, + error |= max77686_volsetting(CONFIG_PMIC_BUS, PMIC_LDO10, VDD_LDO10_MV, REG_ENABLE, MAX77686_MV); - error |= max77686_enable_32khz_cp(PMIC_BUS); + error |= max77686_enable_32khz_cp(CONFIG_PMIC_BUS); if (error) { printk(BIOS_CRIT, "%s: PMIC error: %#x\n", __func__, error); -- To view, visit https://review.coreboot.org/c/coreboot/+/37580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If40fa38e5b249452a6dacf4a4045b6bd00c27cfa Gerrit-Change-Number: 37580 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: vboot: remove old vboot_fill_handoff function header
by Joel Kitching (Code Review) 10 Dec '19

10 Dec '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37588 ) Change subject: vboot: remove old vboot_fill_handoff function header ...................................................................... vboot: remove old vboot_fill_handoff function header This function was removed in CB:33535. BUG=b:124141368 TEST=make clean && make runtests BRANCH=none Change-Id: Ifded75319c92dcbb4befbb3fbecc1cd2df8a9ad0 Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/security/vboot/misc.h 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/37588/1 diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index d03e76e..1fda8b4 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -53,11 +53,6 @@ struct region_device *fw); /* - * Source: security/vboot/vboot_handoff.c - */ -void vboot_fill_handoff(void); - -/* * Source: security/vboot/bootmode.c */ void vboot_save_recovery_reason_vbnv(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/37588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifded75319c92dcbb4befbb3fbecc1cd2df8a9ad0 Gerrit-Change-Number: 37588 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/{facebook/portwell}: Remove ITE8258_CMD_PORT
by Wim Vervoorn (Code Review) 10 Dec '19

10 Dec '19

Hello Frans Hendriks, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37609 to review the following change. Change subject: mb/{facebook/portwell}: Remove ITE8258_CMD_PORT ...................................................................... mb/{facebook/portwell}: Remove ITE8258_CMD_PORT ITE8258_CMD_PORT is used in com_init.c only. Replace ITE8258_CMD_PORT by fixed value in the c file. ITE8258_DATA_PORT is removed as this isn't used. BUG=N/A TEST=build Change-Id: I401da3f127db9e65763fd8d115eb274fbadbefbe Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/mainboard/facebook/fbg1701/com_init.c M src/mainboard/facebook/fbg1701/onboard.h M src/mainboard/portwell/m107/com_init.c M src/mainboard/portwell/m107/onboard.h 4 files changed, 2 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/37609/1 diff --git a/src/mainboard/facebook/fbg1701/com_init.c b/src/mainboard/facebook/fbg1701/com_init.c index f19aba3..fc640dd 100644 --- a/src/mainboard/facebook/fbg1701/com_init.c +++ b/src/mainboard/facebook/fbg1701/com_init.c @@ -17,9 +17,8 @@ #include <bootblock_common.h> #include <device/pnp_ops.h> -#include "onboard.h" -#define SERIAL_DEV PNP_DEV(ITE8528_CMD_PORT, 1) /* ITE8528 UART1 */ +#define SERIAL_DEV PNP_DEV(0x6E, 1) /* ITE8528 UART1 */ void bootblock_mainboard_early_init(void) { diff --git a/src/mainboard/facebook/fbg1701/onboard.h b/src/mainboard/facebook/fbg1701/onboard.h index c22a63a..6e094ab 100644 --- a/src/mainboard/facebook/fbg1701/onboard.h +++ b/src/mainboard/facebook/fbg1701/onboard.h @@ -21,9 +21,6 @@ /* SD CARD gpio */ #define SDCARD_CD 81 /* Not used */ -#define ITE8528_CMD_PORT 0x6E -#define ITE8528_DATA_PORT 0x6F - /* Define the items to be measured or verified */ #define FSP (const char *)"fsp.bin" #define CMOS_LAYOUT (const char *)"cmos_layout.bin" diff --git a/src/mainboard/portwell/m107/com_init.c b/src/mainboard/portwell/m107/com_init.c index f19aba3..fc640dd 100644 --- a/src/mainboard/portwell/m107/com_init.c +++ b/src/mainboard/portwell/m107/com_init.c @@ -17,9 +17,8 @@ #include <bootblock_common.h> #include <device/pnp_ops.h> -#include "onboard.h" -#define SERIAL_DEV PNP_DEV(ITE8528_CMD_PORT, 1) /* ITE8528 UART1 */ +#define SERIAL_DEV PNP_DEV(0x6E, 1) /* ITE8528 UART1 */ void bootblock_mainboard_early_init(void) { diff --git a/src/mainboard/portwell/m107/onboard.h b/src/mainboard/portwell/m107/onboard.h index fd4e4d6..3a5dee2 100644 --- a/src/mainboard/portwell/m107/onboard.h +++ b/src/mainboard/portwell/m107/onboard.h @@ -21,6 +21,4 @@ /* SD CARD gpio */ #define SDCARD_CD 81 /* Not used */ -#define ITE8528_CMD_PORT 0x6E -#define ITE8528_DATA_PORT 0x6F #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/37609 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I401da3f127db9e65763fd8d115eb274fbadbefbe Gerrit-Change-Number: 37609 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Add Jasperlake Device IDs
by Patrick Georgi (Code Review) 10 Dec '19

10 Dec '19

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37434 ) Change subject: soc/intel/common: Add Jasperlake Device IDs ...................................................................... soc/intel/common: Add Jasperlake Device IDs Add Jasperlake SA and PCH IDs Change-Id: I2c9ec1ee4236184b986d99250f263172c80f7117 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37434 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Reviewed-by: Aamir Bohra <aamir.bohra(a)intel.com> Reviewed-by: V Sowmya <v.sowmya(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/scs/sd.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/tigerlake/bootblock/report_platform.c 18 files changed, 76 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Aamir Bohra: Looks good to me, approved V Sowmya: Looks good to me, approved Lean Sheng Tan: Looks good to me, but someone else must approve diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 9324141..43752f8 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2809,6 +2809,8 @@ #define PCI_DEVICE_ID_INTEL_TGP_ESPI_24 0xA09D #define PCI_DEVICE_ID_INTEL_TGP_ESPI_25 0xA09E #define PCI_DEVICE_ID_INTEL_TGP_ESPI_26 0xA09F +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_1 0x3887 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_2 0x4d80 /* Intel PCIE device ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10 @@ -3004,6 +3006,15 @@ #define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP15 0x02b6 #define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP16 0x02b7 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP1 0x38b8 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP2 0x38b9 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP3 0x38ba +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP4 0x38bb +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP5 0x38bc +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP6 0x38bd +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP7 0x38be +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP8 0x38bf + /* Intel SATA device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_U_SATA 0x9d03 #define PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA 0x9d07 @@ -3035,6 +3046,7 @@ #define PCI_DEVICE_ID_INTEL_TGP_SATA 0xa0d5 #define PCI_DEVICE_ID_INTEL_TGP_PREMIUM_SATA 0xa0d7 #define PCI_DEVICE_ID_INTEL_TGP_COMPAT_SATA 0x282a +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SATA 0x38d3 /* Intel PMC device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PMC 0x9d21 @@ -3049,6 +3061,7 @@ #define PCI_DEVICE_ID_INTEL_ICP_PMC 0x34a1 #define PCI_DEVICE_ID_INTEL_CMP_PMC 0x02a1 #define PCI_DEVICE_ID_INTEL_TGP_PMC 0xa0a1 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PMC 0x38a1 /* Intel I2C device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_I2C0 0x9d60 @@ -3108,6 +3121,13 @@ #define PCI_DEVICE_ID_INTEL_TGP_I2C6 0xa0d8 #define PCI_DEVICE_ID_INTEL_TGP_I2C7 0xa0d9 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C0 0x38e8 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C1 0x38e9 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C2 0x38ea +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C3 0x38eb +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C4 0x38c5 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C5 0x38c6 + /* Intel UART device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_UART0 0x9d27 #define PCI_DEVICE_ID_INTEL_SPT_UART1 0x9d28 @@ -3142,6 +3162,10 @@ #define PCI_DEVICE_ID_INTEL_TGP_UART1 0xa0a9 #define PCI_DEVICE_ID_INTEL_TGP_UART2 0xa0c7 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART0 0x38a8 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART1 0x38a9 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART2 0x38c7 + /* Intel SPI device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_SPI1 0x9d24 #define PCI_DEVICE_ID_INTEL_SPT_SPI2 0x9d29 @@ -3180,6 +3204,11 @@ #define PCI_DEVICE_ID_INTEL_TGP_GSPI5 0xa0de #define PCI_DEVICE_ID_INTEL_TGP_GSPI6 0xa0df +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI0 0x38aa +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI1 0x38ab +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI2 0x38fb +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_HWSEQ_SPI 0x38a4 + /* Intel IGD device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_GT1F_DT2 0x1902 #define PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM 0x1906 @@ -3283,6 +3312,7 @@ #define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT 0x9A49 #define PCI_DEVICE_ID_INTEL_TGL_GT3_ULT 0x9A52 #define PCI_DEVICE_ID_INTEL_TGL_GT2_ULX 0x9A40 +#define PCI_DEVICE_ID_INTEL_JSL_PRE_PROD_GT0 0x4569 /* Intel Northbridge Ids */ #define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 @@ -3338,6 +3368,7 @@ #define PCI_DEVICE_ID_INTEL_TGL_ID_U 0x9A14 #define PCI_DEVICE_ID_INTEL_TGL_ID_U_1 0x9A12 #define PCI_DEVICE_ID_INTEL_TGL_ID_Y 0x9A10 +#define PCI_DEVICE_ID_INTEL_JSL_PRE_PROD 0x4e2a /* Intel SMBUS device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23 @@ -3349,6 +3380,7 @@ #define PCI_DEVICE_ID_INTEL_ICP_LP_SMBUS 0x34a3 #define PCI_DEVICE_ID_INTEL_CMP_SMBUS 0x02a3 #define PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS 0xa0a3 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SMBUS 0x38a3 /* Intel XHCI device Ids */ #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 @@ -3363,6 +3395,7 @@ #define PCI_DEVICE_ID_INTEL_ICP_LP_XHCI 0x34ed #define PCI_DEVICE_ID_INTEL_CMP_LP_XHCI 0x02ed #define PCI_DEVICE_ID_INTEL_TGP_LP_XHCI 0xa0ed +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_XHCI 0x38ed /* Intel P2SB device Ids */ #define PCI_DEVICE_ID_INTEL_APL_P2SB 0x5a92 @@ -3377,6 +3410,7 @@ #define PCI_DEVICE_ID_INTEL_ICL_P2SB 0x34a0 #define PCI_DEVICE_ID_INTEL_CMP_P2SB 0x02a0 #define PCI_DEVICE_ID_INTEL_TGL_P2SB 0xa0a0 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_P2SB 0x38a0 /* Intel SRAM device Ids */ #define PCI_DEVICE_ID_INTEL_APL_SRAM 0x5aec @@ -3386,6 +3420,7 @@ #define PCI_DEVICE_ID_INTEL_ICL_SRAM 0x34ef #define PCI_DEVICE_ID_INTEL_CMP_SRAM 0x02ef #define PCI_DEVICE_ID_INTEL_TGL_SRAM 0xa0ef +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SRAM 0x38ef /* Intel AUDIO device Ids */ #define PCI_DEVICE_ID_INTEL_APL_AUDIO 0x5a98 @@ -3401,6 +3436,7 @@ #define PCI_DEVICE_ID_INTEL_CMP_AUDIO 0x02c8 #define PCI_DEVICE_ID_INTEL_BSW_AUDIO 0x2284 #define PCI_DEVICE_ID_INTEL_TGL_AUDIO 0xa0c8 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_AUDIO 0x38c8 /* Intel HECI/ME device Ids */ #define PCI_DEVICE_ID_INTEL_APL_CSE0 0x5a9a @@ -3417,6 +3453,7 @@ #define PCI_DEVICE_ID_INTEL_ICL_CSE0 0x34e0 #define PCI_DEVICE_ID_INTEL_CMP_CSE0 0x02e0 #define PCI_DEVICE_ID_INTEL_TGL_CSE0 0xa0e0 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_CSE0 0x38e0 /* Intel XDCI device Ids */ #define PCI_DEVICE_ID_INTEL_APL_XDCI 0x5aaa @@ -3436,6 +3473,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_SD 0xa375 #define PCI_DEVICE_ID_INTEL_ICL_SD 0x34f8 #define PCI_DEVICE_ID_INTEL_CMP_SD 0x02f5 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SD 0x38f8 /* Intel EMMC device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_EMMC 0x9d2b @@ -3514,7 +3552,6 @@ #define PCI_DEVICE_ID_ADAPTEC_7887 0x8778 #define PCI_DEVICE_ID_ADAPTEC_7888 0x8878 #define PCI_DEVICE_ID_ADAPTEC_1030 0x8b78 - #define PCI_VENDOR_ID_ADAPTEC2 0x9005 #define PCI_DEVICE_ID_ADAPTEC2_2940U2 0x0010 #define PCI_DEVICE_ID_ADAPTEC2_2930U2 0x0011 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 011916d..6aaba40 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -755,6 +755,7 @@ PCI_DEVICE_ID_INTEL_ICL_CSE0, PCI_DEVICE_ID_INTEL_CMP_CSE0, PCI_DEVICE_ID_INTEL_TGL_CSE0, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_CSE0, 0, }; diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index 947c002..6c00ed1 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -35,6 +35,7 @@ PCI_DEVICE_ID_INTEL_CMP_AUDIO, PCI_DEVICE_ID_INTEL_ICL_AUDIO, PCI_DEVICE_ID_INTEL_TGL_AUDIO, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_AUDIO, 0, }; diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 4b418cc..cbe189c 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -213,6 +213,7 @@ PCI_DEVICE_ID_INTEL_TGL_GT2_ULT, PCI_DEVICE_ID_INTEL_TGL_GT2_ULX, PCI_DEVICE_ID_INTEL_TGL_GT3_ULT, + PCI_DEVICE_ID_INTEL_JSL_PRE_PROD_GT0, 0, }; diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index 1749bf5..bc692d3 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -243,6 +243,12 @@ PCI_DEVICE_ID_INTEL_TGP_I2C5, PCI_DEVICE_ID_INTEL_TGP_I2C6, PCI_DEVICE_ID_INTEL_TGP_I2C7, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C0, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C1, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C2, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C3, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C4, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C5, 0, }; diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 249e6d6..258975c 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -222,6 +222,8 @@ PCI_DEVICE_ID_INTEL_TGP_ESPI_24, PCI_DEVICE_ID_INTEL_TGP_ESPI_25, PCI_DEVICE_ID_INTEL_TGP_ESPI_26, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_1, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_2, 0 }; diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 981ad07..75c74f2 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -180,6 +180,7 @@ PCI_DEVICE_ID_INTEL_ICL_P2SB, PCI_DEVICE_ID_INTEL_CMP_P2SB, PCI_DEVICE_ID_INTEL_TGL_P2SB, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_P2SB, 0, }; diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index 406a227..ecc1fcb 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -266,6 +266,14 @@ PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP14, PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP15, PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP16, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP1, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP2, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP3, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP4, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP5, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP6, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP7, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP8, 0 }; diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 1d2aa61..1645070 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -134,6 +134,7 @@ PCI_DEVICE_ID_INTEL_ICP_PMC, PCI_DEVICE_ID_INTEL_CMP_PMC, PCI_DEVICE_ID_INTEL_TGP_PMC, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PMC, 0 }; diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index 13ac32e..0f26262 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -100,6 +100,7 @@ PCI_DEVICE_ID_INTEL_TGP_SATA, PCI_DEVICE_ID_INTEL_TGP_PREMIUM_SATA, PCI_DEVICE_ID_INTEL_TGP_COMPAT_SATA, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SATA, 0 }; diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c index 2794a3b..e94e4e9 100644 --- a/src/soc/intel/common/block/scs/sd.c +++ b/src/soc/intel/common/block/scs/sd.c @@ -73,6 +73,7 @@ PCI_DEVICE_ID_INTEL_CNP_H_SD, PCI_DEVICE_ID_INTEL_ICL_SD, PCI_DEVICE_ID_INTEL_CMP_SD, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SD, 0 }; diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index d7114e4..c9a6b17 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -96,6 +96,7 @@ PCI_DEVICE_ID_INTEL_ICP_LP_SMBUS, PCI_DEVICE_ID_INTEL_CMP_SMBUS, PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SMBUS, 0 }; diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 3c77cc4..eedde75 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -89,6 +89,10 @@ PCI_DEVICE_ID_INTEL_TGP_GSPI4, PCI_DEVICE_ID_INTEL_TGP_GSPI5, PCI_DEVICE_ID_INTEL_TGP_GSPI6, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI0, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI1, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI2, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_HWSEQ_SPI, 0 }; diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c index 47ba28f..9e44fa3 100644 --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -52,6 +52,7 @@ PCI_DEVICE_ID_INTEL_ICL_SRAM, PCI_DEVICE_ID_INTEL_CMP_SRAM, PCI_DEVICE_ID_INTEL_TGL_SRAM, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SRAM, 0, }; diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index b365706..2019ef6 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -367,6 +367,7 @@ PCI_DEVICE_ID_INTEL_TGL_ID_U, PCI_DEVICE_ID_INTEL_TGL_ID_U_1, PCI_DEVICE_ID_INTEL_TGL_ID_Y, + PCI_DEVICE_ID_INTEL_JSL_PRE_PROD, 0 }; diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 718eaca..4053516 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -278,6 +278,9 @@ PCI_DEVICE_ID_INTEL_TGP_UART0, PCI_DEVICE_ID_INTEL_TGP_UART1, PCI_DEVICE_ID_INTEL_TGP_UART2, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART0, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART1, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART2, 0, }; diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index 5930e23..af4d132 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -132,6 +132,7 @@ PCI_DEVICE_ID_INTEL_ICP_LP_XHCI, PCI_DEVICE_ID_INTEL_CMP_LP_XHCI, PCI_DEVICE_ID_INTEL_TGP_LP_XHCI, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_XHCI, 0 }; diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c index 41061ee..3d856a5 100644 --- a/src/soc/intel/tigerlake/bootblock/report_platform.c +++ b/src/soc/intel/tigerlake/bootblock/report_platform.c @@ -47,6 +47,7 @@ { PCI_DEVICE_ID_INTEL_TGL_ID_U, "Tigerlake-U-4-2" }, { PCI_DEVICE_ID_INTEL_TGL_ID_U_1, "Tigerlake-U-4-3e" }, { PCI_DEVICE_ID_INTEL_TGL_ID_Y, "Tigerlake-Y-4-2" }, + { PCI_DEVICE_ID_INTEL_JSL_PRE_PROD, "Jasperlake Pre Prod" }, }; static struct { @@ -85,6 +86,8 @@ { PCI_DEVICE_ID_INTEL_TGP_ESPI_24, "Tigerlake-Base SKU" }, { PCI_DEVICE_ID_INTEL_TGP_ESPI_25, "Tigerlake-Base SKU" }, { PCI_DEVICE_ID_INTEL_TGP_ESPI_26, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_1, "Jasperlake Pre Prod" }, + { PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_2, "Jasperlake Pre Prod" }, }; static struct { @@ -95,6 +98,7 @@ { PCI_DEVICE_ID_INTEL_TGL_GT2_ULT, "Tigerlake U GT2" }, { PCI_DEVICE_ID_INTEL_TGL_GT2_ULX, "Tigerlake Y GT2" }, { PCI_DEVICE_ID_INTEL_TGL_GT3_ULT, "Tigerlake U GT3" }, + { PCI_DEVICE_ID_INTEL_JSL_PRE_PROD_GT0, "Jasperlake Pre Prod GT0" }, }; static inline uint8_t get_dev_revision(pci_devfn_t dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/37434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c9ec1ee4236184b986d99250f263172c80f7117 Gerrit-Change-Number: 37434 Gerrit-PatchSet: 6 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: amdblocks/pci: add common implementation of MMCONF enabling
by Michał Żygowski (Code Review) 10 Dec '19

10 Dec '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37552 ) Change subject: amdblocks/pci: add common implementation of MMCONF enabling ...................................................................... amdblocks/pci: add common implementation of MMCONF enabling Add common function to enable PCI MMCONF base address. Use the common function in stoneyridge bootblock. Enable the common implementation for other AMD southbridges for use in C bootblock. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I1bb8b22b282584c421a9fffa3322b2a8e406d037 --- A src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h M src/soc/amd/common/block/pci/Kconfig M src/soc/amd/common/block/pci/Makefile.inc A src/soc/amd/common/block/pci/amd_pci_mmconf.c M src/soc/amd/stoneyridge/bootblock/bootblock.c M src/southbridge/amd/agesa/hudson/Kconfig M src/southbridge/amd/cimx/sb800/Kconfig M src/southbridge/amd/pi/hudson/Kconfig 8 files changed, 62 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/37552/1 diff --git a/src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h new file mode 100644 index 0000000..4b65ad0 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMDBLOCKS_PCI_MMCONF_H__ +#define __AMDBLOCKS_PCI_MMCONF_H__ + +void enable_pci_mmconf(void); + +#endif diff --git a/src/soc/amd/common/block/pci/Kconfig b/src/soc/amd/common/block/pci/Kconfig index 74ea697..d4efe00 100644 --- a/src/soc/amd/common/block/pci/Kconfig +++ b/src/soc/amd/common/block/pci/Kconfig @@ -4,3 +4,10 @@ help This option builds functions used to program PCI interrupt routing, both PIC and APIC modes. + +config SOC_AMD_COMMON_BLOCK_PCI_MMCONF + bool + default n + help + This option builds function used to program PCI MMIO configuration + base address. diff --git a/src/soc/amd/common/block/pci/Makefile.inc b/src/soc/amd/common/block/pci/Makefile.inc index fc40c9d..b20da88 100644 --- a/src/soc/amd/common/block/pci/Makefile.inc +++ b/src/soc/amd/common/block/pci/Makefile.inc @@ -1,5 +1,6 @@ -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PCI),y) -ramstage-y += amd_pci_util.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCI) += amd_pci_util.c -endif +bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCI_MMCONF) += amd_pci_mmconf.c +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCI_MMCONF) += amd_pci_mmconf.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCI_MMCONF) += amd_pci_mmconf.c diff --git a/src/soc/amd/common/block/pci/amd_pci_mmconf.c b/src/soc/amd/common/block/pci/amd_pci_mmconf.c new file mode 100644 index 0000000..1aed51b --- /dev/null +++ b/src/soc/amd/common/block/pci/amd_pci_mmconf.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <amdblocks/amd_pci_mmconf.h> +#include <cpu/amd/msr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> + +void enable_pci_mmconf(void) +{ + msr_t mmconf; + + mmconf.hi = 0; + mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN + | fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT; + wrmsr(MMIO_CONF_BASE, mmconf); +} diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index d92535a..9920aff 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -24,6 +24,7 @@ #include <bootblock_common.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/agesawrapper_call.h> +#include <amdblocks/amd_pci_mmconf.h> #include <amdblocks/biosram.h> #include <soc/pci_devs.h> #include <soc/cpu.h> @@ -42,15 +43,9 @@ /* Set the MMIO Configuration Base Address, Bus Range, and misc MTRRs. */ static void amd_initmmio(void) { - msr_t mmconf; msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); int mtrr; - mmconf.hi = 0; - mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN - | fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT; - wrmsr(MMIO_CONF_BASE, mmconf); - /* * todo: AGESA currently writes variable MTRRs. Once that is * corrected, un-hardcode this MTRR. @@ -75,6 +70,7 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { + enable_pci_mmconf(); amd_initmmio(); /* * Call lib/bootblock.c main with BSP, shortcut for APs diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 93db1a9..4fe770d 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -30,6 +30,7 @@ select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_PCI_MMCONF config BOOTBLOCK_SOUTHBRIDGE_INIT string diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 0b790b0..23a6c4a 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -24,6 +24,7 @@ select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_PCI_MMCONF if SOUTHBRIDGE_AMD_CIMX_SB800 config BOOTBLOCK_SOUTHBRIDGE_INIT diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index 01f3937..8a52b64 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -33,6 +33,7 @@ select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_PCI_MMCONF config BOOTBLOCK_SOUTHBRIDGE_INIT string -- To view, visit https://review.coreboot.org/c/coreboot/+/37552 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1bb8b22b282584c421a9fffa3322b2a8e406d037 Gerrit-Change-Number: 37552 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: Explicitly enable LPC controller
by Kyösti Mälkki (Code Review) 10 Dec '19

10 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37595 ) Change subject: sb/amd/{agesa,pi}/hudson: Explicitly enable LPC controller ...................................................................... sb/amd/{agesa,pi}/hudson: Explicitly enable LPC controller Location in hudson_lpc_port80() was called conditionally. Also move hudson_lpc_decode() call after enable_acpimmio_decode_pmXX() due the change from IO to MMIO using pm_read/write. Change-Id: I38e94e4b04f0a493052cfd3ffdd0a9c2ac0d07fc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/amd/agesa/hudson/bootblock.c M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/pi/hudson/bootblock.c M src/southbridge/amd/pi/hudson/early_setup.c 4 files changed, 10 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/37595/1 diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c index 6925393..4da030b 100644 --- a/src/southbridge/amd/agesa/hudson/bootblock.c +++ b/src/southbridge/amd/agesa/hudson/bootblock.c @@ -74,8 +74,8 @@ u32 data; bootblock_southbridge_init(); - hudson_lpc_decode(); enable_acpimmio_decode_pm24(); + hudson_lpc_decode(); if (CONFIG(POST_DEVICE_PCI_PCIE)) hudson_pci_port80(); diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index d85cb2b..84c4299 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -20,6 +20,7 @@ #include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> +#include <amdblocks/acpimmio.h> #include "hudson.h" @@ -73,13 +74,6 @@ u8 byte; pci_devfn_t dev; - /* Enable LPC controller */ - outb(0xEC, 0xCD6); - byte = inb(0xCD7); - byte |= 1; - outb(0xEC, 0xCD6); - outb(byte, 0xCD7); - /* Enable port 80 LPC decode in pci function 3 configuration space. */ dev = PCI_DEV(0, 0x14, 3); byte = pci_read_config8(dev, 0x4a); @@ -92,6 +86,9 @@ pci_devfn_t dev; u32 tmp; + /* Enable LPC controller */ + pm_write8(0xec, pm_read8(0xec) | 0x01); + dev = PCI_DEV(0, 0x14, 3); /* Serial port numeration on Hudson: * PORT0 - 0x3f8 diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c index ec8663d..d16aecc 100644 --- a/src/southbridge/amd/pi/hudson/bootblock.c +++ b/src/southbridge/amd/pi/hudson/bootblock.c @@ -73,11 +73,11 @@ u32 data; bootblock_southbridge_init(); - hudson_lpc_decode(); if (CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON)) enable_acpimmio_decode_pm24(); else enable_acpimmio_decode_pm04(); + hudson_lpc_decode(); if (CONFIG(POST_DEVICE_PCI_PCIE)) hudson_pci_port80(); diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 56b894c..0e3646b 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -22,6 +22,7 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <console/console.h> +#include <amdblocks/acpimmio.h> #include "hudson.h" #include "pci_devs.h" @@ -106,13 +107,6 @@ u8 byte; pci_devfn_t dev; - /* Enable LPC controller */ - outb(0xEC, 0xCD6); - byte = inb(0xCD7); - byte |= 1; - outb(0xEC, 0xCD6); - outb(byte, 0xCD7); - /* Enable port 80 LPC decode in pci function 3 configuration space. */ dev = PCI_DEV(0, 0x14, 3); byte = pci_read_config8(dev, 0x4a); @@ -125,6 +119,9 @@ pci_devfn_t dev; u32 tmp; + /* Enable LPC controller */ + pm_write8(0xec, pm_read8(0xec) | 0x01); + dev = PCI_DEV(0, 0x14, 3); /* Serial port numeration on Hudson: * PORT0 - 0x3f8 -- To view, visit https://review.coreboot.org/c/coreboot/+/37595 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38e94e4b04f0a493052cfd3ffdd0a9c2ac0d07fc Gerrit-Change-Number: 37595 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/kohaku: Update TCC offset setting
by shkim (Code Review) 10 Dec '19

10 Dec '19

Hello Seunghwan Kim, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37587 to review the following change. Change subject: mb/google/kohaku: Update TCC offset setting ...................................................................... mb/google/kohaku: Update TCC offset setting This change sets TCC offset to 10 for kohaku. BUG=b:144532818 BRANCH=firmware-hatch-12672.B TEST=Checked thermal and performance efficiency internally (b:144532818) Change-Id: Ia4b53de3a53bc39c1cd0f7626ae23d4c11a7a3db Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.com> --- M src/mainboard/google/hatch/variants/kohaku/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/37587/1 diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 55ac071..84d3cf2a0 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -2,7 +2,7 @@ register "tdp_pl1_override" = "8" register "tdp_pl2_override" = "51" - register "tcc_offset" = "35" # TCC of 65C + register "tcc_offset" = "10" # TCC of 90C register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, -- To view, visit https://review.coreboot.org/c/coreboot/+/37587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4b53de3a53bc39c1cd0f7626ae23d4c11a7a3db Gerrit-Change-Number: 37587 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-MessageType: newchange

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