coreboot-gerrit December 2019

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Change in coreboot[master]: mainboard/google: Fix Hatch baseboard/gpio.c default mux
by Edward O'Callaghan (Code Review) 07 Aug '23

07 Aug '23

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36988 ) Change subject: mainboard/google: Fix Hatch baseboard/gpio.c default mux ...................................................................... mainboard/google: Fix Hatch baseboard/gpio.c default mux The schematics seem to suggest F20,F21,F11,F22 are all NC. BUG=b:144809606 Change-Id: Ide74ab6361f48f0e9c967b9e4318537f605bee2d Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/36988/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 598600b..d8625b9 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -301,12 +301,12 @@ PAD_NC(GPP_F18, NONE), /* F19 : GPP_F19 ==> NC */ PAD_NC(GPP_F19, NONE), - /* F20 : PCH_MEM_STRAP0 */ - PAD_CFG_GPI(GPP_F20, NONE, PLTRST), - /* F21 : PCH_MEM_STRAP1 */ - PAD_CFG_GPI(GPP_F21, NONE, PLTRST), - /* F22 : PCH_MEM_STRAP3 */ - PAD_CFG_GPI(GPP_F22, NONE, PLTRST), + /* F20 : GPP_F20 ==> NC */ + PAD_NC(GPP_F20, NONE), + /* F21 : GPP_F21 ==> NC */ + PAD_NC(GPP_F21, NONE), + /* F22 : GPP_F22 ==> NC */ + PAD_NC(GPP_F22, NONE), /* F23 : GPP_F23 ==> NC */ PAD_NC(GPP_F23, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/36988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide74ab6361f48f0e9c967b9e4318537f605bee2d Gerrit-Change-Number: 36988 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: arch/riscv: Add error detection for supports_extension
by Xiang Wang (Code Review) 07 Aug '23

07 Aug '23

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37130 ) Change subject: arch/riscv: Add error detection for supports_extension ...................................................................... arch/riscv: Add error detection for supports_extension Change-Id: I5df3d82b9a9b4968beea6040b86628b58fd8a45d Signed-off-by: Xiang Wang <merle(a)hardenedlinux.org> --- M src/arch/riscv/include/arch/cpu.h 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/37130/1 diff --git a/src/arch/riscv/include/arch/cpu.h b/src/arch/riscv/include/arch/cpu.h index 72a8a69..dd70af7 100644 --- a/src/arch/riscv/include/arch/cpu.h +++ b/src/arch/riscv/include/arch/cpu.h @@ -49,7 +49,7 @@ * */ int soc_supports_extension(char ext); -static inline int supports_extension(char ext) +static inline int supports_extension_imp(char ext) { uintptr_t isa = read_csr(misa); if (isa) @@ -58,6 +58,13 @@ return soc_supports_extension(ext); } +#define supports_extension(c)\ +({\ + _Static_assert(((c >= 'A') && (c <= 'Z')),\ + "The parameter of supports_extension must be [A-Z]");\ + supports_extension_imp(c);\ +}) + /* If the SOC does not implement misa, the read misa will be zero. * Such SOC requires a non-standard mechanism to detect machine XLEN. * If the soc does not implement misa, implement this function. -- To view, visit https://review.coreboot.org/c/coreboot/+/37130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5df3d82b9a9b4968beea6040b86628b58fd8a45d Gerrit-Change-Number: 37130 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: sb/intel/bd82x6x: Use common AHCI
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37138 ) Change subject: sb/intel/bd82x6x: Use common AHCI ...................................................................... sb/intel/bd82x6x: Use common AHCI Untested. Change-Id: I180c7f11bccfcd50340ba27cd926107765713e04 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/bd82x6x/sata.c 2 files changed, 4 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/37138/1 diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 1c7e9b7..0c6b348 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -24,6 +24,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select SOUTHBRIDGE_INTEL_COMMON_AHCI select SOUTHBRIDGE_INTEL_COMMON_FINALIZE select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_SMBUS diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 3ec065f..06c0f3f 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -23,6 +23,7 @@ #include <pc80/mc146818rtc.h> #include <acpi/sata.h> #include <types.h> +#include <southbridge/intel/common/ahci.h> #include "chip.h" #include "pch.h" @@ -67,8 +68,6 @@ /* AHCI */ if (sata_mode == 0) { - u8 *abar; - printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); /* Set Interrupt Line */ @@ -101,32 +100,8 @@ ((config->sata_port_map ^ 0x3f) << 24) | 0x183); /* Initialize AHCI memory-mapped space */ - abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "ABAR: %p\n", abar); - /* CAP (HBA Capabilities) : enable power management */ - reg32 = read32(abar + 0x00); - reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS - reg32 &= ~0x00020060; // clear SXS+EMS+PMS - /* Set ISS, if available */ - if (config->sata_interface_speed_support) - { - reg32 &= ~0x00f00000; - reg32 |= (config->sata_interface_speed_support & 0x03) - << 20; - } - write32(abar + 0x00, reg32); - /* PI (Ports implemented) */ - write32(abar + 0x0c, config->sata_port_map); - (void) read32(abar + 0x0c); /* Read back 1 */ - (void) read32(abar + 0x0c); /* Read back 2 */ - /* CAP2 (HBA Capabilities Extended)*/ - reg32 = read32(abar + 0x24); - reg32 &= ~0x00000002; - write32(abar + 0x24, reg32); - /* VSP (Vendor Specific Register */ - reg32 = read32(abar + 0xa0); - reg32 &= ~0x00000005; - write32(abar + 0xa0, reg32); + sb_ahci_init(dev, config->sata_port_map, false, false, + config->sata_interface_speed_support, false, 5); } else { /* IDE */ printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/37138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I180c7f11bccfcd50340ba27cd926107765713e04 Gerrit-Change-Number: 37138 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: sb/intel/lynxpoint: Use common AHCI
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37139 ) Change subject: sb/intel/lynxpoint: Use common AHCI ...................................................................... sb/intel/lynxpoint: Use common AHCI Untested. Change-Id: I9c46e85084996b430b077f4bc683a96df42bf41a Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/lynxpoint/Kconfig M src/southbridge/intel/lynxpoint/sata.c 2 files changed, 5 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/37139/1 diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index ef071f2..03b9bbb 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -21,6 +21,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select SOUTHBRIDGE_INTEL_COMMON_AHCI select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 75bfbde..911575b 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -21,6 +21,8 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <delay.h> +#include <southbridge/intel/common/ahci.h> + #include "chip.h" #include "pch.h" @@ -94,8 +96,6 @@ pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); } else if (config->sata_ahci) { - u32 *abar; - printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); /* Set Interrupt Line */ @@ -154,31 +154,8 @@ pci_write_config32(dev, 0x94, reg32); /* Initialize AHCI memory-mapped space */ - abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "ABAR: %p\n", abar); - /* CAP (HBA Capabilities) : enable power management */ - reg32 = read32(abar + 0x00); - reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS - reg32 &= ~0x00020060; // clear SXS+EMS+PMS - if (pch_is_lp()) - reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY - write32(abar + 0x00, reg32); - /* PI (Ports implemented) */ - write32(abar + 0x03, config->sata_port_map); - (void) read32(abar + 0x03); /* Read back 1 */ - (void) read32(abar + 0x03); /* Read back 2 */ - /* CAP2 (HBA Capabilities Extended)*/ - reg32 = read32(abar + 0x09); - /* Enable DEVSLP */ - if (pch_is_lp()) { - if (config->sata_devslp_disable) - reg32 &= ~(1 << 3); - else - reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); - } else { - reg32 &= ~0x00000002; - } - write32(abar + 0x09, reg32); + sb_ahci_init(dev, config->sata_port_map, pch_is_lp(), false, 0, + pch_is_lp() && !config->sata_devslp_disable, 0); } else { printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/37139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c46e85084996b430b077f4bc683a96df42bf41a Gerrit-Change-Number: 37139 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: sb/intel/ibexpeak: Use common AHCI
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37140 ) Change subject: sb/intel/ibexpeak: Use common AHCI ...................................................................... sb/intel/ibexpeak: Use common AHCI Untested. Change-Id: I772e69fe4400d921bea12806a0ab159b7cf5fbe1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/ibexpeak/sata.c 2 files changed, 4 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/37140/1 diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index f9723fb..c923714 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -26,6 +26,7 @@ select USE_WATCHDOG_ON_BOOT select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK + select SOUTHBRIDGE_INTEL_COMMON_AHCI select SOUTHBRIDGE_INTEL_COMMON_FINALIZE select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_SMBUS diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 2d9412a..aa39a54 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -24,6 +24,7 @@ #include <pc80/mc146818rtc.h> #include <acpi/sata.h> #include <types.h> +#include <southbridge/intel/common/ahci.h> #include "chip.h" #include "pch.h" @@ -68,8 +69,6 @@ if (sata_mode == 0) { /* AHCI */ - u32 *abar; - printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); /* Set Interrupt Line */ @@ -104,31 +103,8 @@ pci_write_config32(dev, 0x98, 0x00590200); /* Initialize AHCI memory-mapped space */ - abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "ABAR: %p\n", abar); - /* CAP (HBA Capabilities) : enable power management */ - reg32 = read32(abar + 0x00); - reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS - reg32 &= ~0x00020060; // clear SXS+EMS+PMS - /* Set ISS, if available */ - if (config->sata_interface_speed_support) { - reg32 &= ~0x00f00000; - reg32 |= (config->sata_interface_speed_support & 0x03) - << 20; - } - write32(abar + 0x00, reg32); - /* PI (Ports implemented) */ - write32(abar + 0x03, config->sata_port_map); - (void)read32(abar + 0x03); /* Read back 1 */ - (void)read32(abar + 0x03); /* Read back 2 */ - /* CAP2 (HBA Capabilities Extended) */ - reg32 = read32(abar + 0x09); - reg32 &= ~0x00000002; - write32(abar + 0x09, reg32); - /* VSP (Vendor Specific Register */ - reg32 = read32(abar + 0x28); - reg32 &= ~0x00000005; - write32(abar + 0x28, reg32); + sb_ahci_init(dev, config->sata_port_map, false, false, + config->sata_interface_speed_support, false, 5); } else { /* IDE */ printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/37140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I772e69fe4400d921bea12806a0ab159b7cf5fbe1 Gerrit-Change-Number: 37140 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: sb/intel/i82801ix: Use common AHCI
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37141 ) Change subject: sb/intel/i82801ix: Use common AHCI ...................................................................... sb/intel/i82801ix: Use common AHCI Untested. Change-Id: I4ef0d152ef17a237c0604a3d1f78fcd97a016cf7 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801ix/sata.c 2 files changed, 12 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/37141/1 diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 8363978..9ef680b 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -16,6 +16,7 @@ config SOUTHBRIDGE_INTEL_I82801IX bool + select SOUTHBRIDGE_INTEL_COMMON_AHCI select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI if !BOARD_EMULATION_QEMU_X86_Q35 select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index fa6c1df..7143fa2 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -24,60 +24,13 @@ #include <device/pci_ids.h> #include <pc80/mc146818rtc.h> #include <types.h> +#include <southbridge/intel/common/ahci.h> #include "chip.h" #include "i82801ix.h" typedef struct southbridge_intel_i82801ix_config config_t; -static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map, - const int is_mobile) -{ - int i; - u32 reg32; - struct resource *res; - - /* Initialize AHCI memory-mapped space */ - res = find_resource(dev, PCI_BASE_ADDRESS_5); - if (!res) - return; - - u8 *abar = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "ABAR: %p\n", abar); - - /* Set AHCI access mode. - No other ABAR registers should be accessed before this. */ - reg32 = read32(abar + 0x04); - reg32 |= 1 << 31; - write32(abar + 0x04, reg32); - - /* CAP (HBA Capabilities) : enable power management */ - reg32 = read32(abar + 0x00); - /* CCCS must be set. */ - reg32 |= 0x0c006080; /* set CCCS+PSC+SSC+SALP+SSS */ - reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */ - write32(abar + 0x00, reg32); - - /* PI (Ports implemented) */ - write32(abar + 0x0c, port_map); - /* PCH code reads back twice, do we need it, too? */ - (void) read32(abar + 0x0c); /* Read back 1 */ - (void) read32(abar + 0x0c); /* Read back 2 */ - - /* VSP (Vendor Specific Register) */ - reg32 = read32(abar + 0xa0); - reg32 &= ~0x00000001; /* clear SLPD */ - write32(abar + 0xa0, reg32); - - /* Lock R/WO bits in Port command registers. */ - for (i = 0; i < 6; ++i) { - if (((i == 2) || (i == 3)) && is_mobile) - continue; - u8 *addr = abar + 0x118 + (i * 0x80); - write32(addr, read32(addr)); - } -} - static void sata_program_indexed(struct device *const dev, const int is_mobile) { u32 reg32; @@ -228,8 +181,16 @@ } } - if (sata_mode == 0) - sata_enable_ahci_mmap(dev, config->sata_port_map, is_mobile); + if (sata_mode == 0) { + u32 port_map; + + port_map = config->sata_port_map; + if (is_mobile) + port_map &= ~(3 << 2); + + /* Initialize AHCI memory-mapped space */ + sb_ahci_init(dev, port_map, false, true, 0, false, 1); + } sata_program_indexed(dev, is_mobile); } -- To view, visit https://review.coreboot.org/c/coreboot/+/37141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ef0d152ef17a237c0604a3d1f78fcd97a016cf7 Gerrit-Change-Number: 37141 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: sb/intel/i82801gx: Use common AHCI
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37142 ) Change subject: sb/intel/i82801gx: Use common AHCI ...................................................................... sb/intel/i82801gx: Use common AHCI Untested. Change-Id: I836b43b515545b57eec88bf330da08fdca2902c4 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801gx/sata.c 2 files changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/37142/1 diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 2d95fc2..b8f8731 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -20,6 +20,7 @@ select USE_WATCHDOG_ON_BOOT select HAVE_SMI_HANDLER select COMMON_FADT + select SOUTHBRIDGE_INTEL_COMMON_AHCI select SOUTHBRIDGE_INTEL_COMMON_GPIO select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI if BOOT_DEVICE_SPI_FLASH diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index 47c35ba..f902013 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -20,6 +20,8 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <device/pci_ids.h> +#include <southbridge/intel/common/ahci.h> + #include "chip.h" #include "i82801gx.h" #include "sata.h" @@ -154,11 +156,7 @@ /* Interrupt Pin is set by D31IP.PIP */ pci_write_config8(dev, INTR_LN, 0x0a); - struct resource *ahci_res = find_resource(dev, PCI_BASE_ADDRESS_5); - if (ahci_res != NULL) - /* write AHCI GHC_PI register */ - write32(res2mmio(ahci_res, 0xc, 0), - config->sata_ports_implemented); + sb_ahci_init(dev, config->sata_ports_implemented, false, false, 0, false, 0); break; default: case SATA_MODE_IDE_PLAIN: -- To view, visit https://review.coreboot.org/c/coreboot/+/37142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I836b43b515545b57eec88bf330da08fdca2902c4 Gerrit-Change-Number: 37142 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: sb/intel/i82801jx: Use common AHCI
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37143 ) Change subject: sb/intel/i82801jx: Use common AHCI ...................................................................... sb/intel/i82801jx: Use common AHCI Untested. Change-Id: I87d6e83170025ee69768d83e9a4f68bbde51cac1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/i82801jx/sata.c 2 files changed, 12 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/37143/1 diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 161290f..81da68f 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -16,6 +16,7 @@ config SOUTHBRIDGE_INTEL_I82801JX bool + select SOUTHBRIDGE_INTEL_COMMON_AHCI select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c index e6e08a3..b18f465 100644 --- a/src/southbridge/intel/i82801jx/sata.c +++ b/src/southbridge/intel/i82801jx/sata.c @@ -24,55 +24,13 @@ #include <device/pci_ids.h> #include <pc80/mc146818rtc.h> #include <types.h> +#include <southbridge/intel/common/ahci.h> #include "chip.h" #include "i82801jx.h" typedef struct southbridge_intel_i82801jx_config config_t; -static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map, - const int is_mobile) -{ - int i; - u32 reg32; - - /* Initialize AHCI memory-mapped space */ - u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "ABAR: %p\n", abar); - - /* Set AHCI access mode. - No other ABAR registers should be accessed before this. */ - reg32 = read32(abar + 0x04); - reg32 |= 1 << 31; - write32(abar + 0x04, reg32); - - /* CAP (HBA Capabilities) : enable power management */ - reg32 = read32(abar + 0x00); - /* CCCS must be set. */ - reg32 |= 0x0c006080; /* set CCCS+PSC+SSC+SALP+SSS */ - reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */ - write32(abar + 0x00, reg32); - - /* PI (Ports implemented) */ - write32(abar + 0x0c, port_map); - /* PCH code reads back twice, do we need it, too? */ - (void) read32(abar + 0x0c); /* Read back 1 */ - (void) read32(abar + 0x0c); /* Read back 2 */ - - /* VSP (Vendor Specific Register) */ - reg32 = read32(abar + 0xa0); - reg32 &= ~0x00000001; /* clear SLPD */ - write32(abar + 0xa0, reg32); - - /* Lock R/WO bits in Port command registers. */ - for (i = 0; i < 6; ++i) { - if (((i == 2) || (i == 3)) && is_mobile) - continue; - u8 *addr = abar + 0x118 + (i * 0x80); - write32(addr, read32(addr)); - } -} - static void sata_program_indexed(struct device *const dev, const int is_mobile) { u32 reg32; @@ -223,8 +181,16 @@ } } - if (sata_mode == 0) - sata_enable_ahci_mmap(dev, config->sata_port_map, is_mobile); + if (sata_mode == 0) { + u32 port_map; + + port_map = config->sata_port_map; + if (is_mobile) + port_map &= ~(3 << 2); + + /* Initialize AHCI memory-mapped space */ + sb_ahci_init(dev, port_map, false, true, 0, false, 1); + } sata_program_indexed(dev, is_mobile); } -- To view, visit https://review.coreboot.org/c/coreboot/+/37143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87d6e83170025ee69768d83e9a4f68bbde51cac1 Gerrit-Change-Number: 37143 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lenovo/x131e: remove non-applicable options from CMOS
by James (Code Review) 07 Aug '23

07 Aug '23

James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37146 ) Change subject: mb/lenovo/x131e: remove non-applicable options from CMOS ...................................................................... mb/lenovo/x131e: remove non-applicable options from CMOS These options do not work in the same way as on the Lenovo H8 EC. Since they don't work correctly, drop them from the CMOS settings. Change-Id: Iebc55afd5cc621df562fd7aa9557207147a8199b Signed-off-by: James Ye <jye836(a)gmail.com> --- M src/mainboard/lenovo/x131e/cmos.default M src/mainboard/lenovo/x131e/cmos.layout 2 files changed, 2 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/37146/1 diff --git a/src/mainboard/lenovo/x131e/cmos.default b/src/mainboard/lenovo/x131e/cmos.default index b01978a..ca10a85 100644 --- a/src/mainboard/lenovo/x131e/cmos.default +++ b/src/mainboard/lenovo/x131e/cmos.default @@ -3,12 +3,7 @@ power_on_after_fail=Disable nmi=Enable volume=0x3 -bluetooth=Enable wwan=Enable -wlan=Enable -touchpad=Enable sata_mode=AHCI -fn_ctrl_swap=Disable sticky_fn=Disable -trackpoint=Enable usb_always_on=Disable diff --git a/src/mainboard/lenovo/x131e/cmos.layout b/src/mainboard/lenovo/x131e/cmos.layout index 93c74fb..7696046 100644 --- a/src/mainboard/lenovo/x131e/cmos.layout +++ b/src/mainboard/lenovo/x131e/cmos.layout @@ -60,12 +60,9 @@ 411 1 e 8 sata_mode # coreboot config options: EC -412 1 e 1 bluetooth +#412 1 r 0 unused 413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap +#414 4 r 0 unused 418 1 e 1 sticky_fn 419 2 e 12 usb_always_on #421 3 r 0 unused -- To view, visit https://review.coreboot.org/c/coreboot/+/37146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebc55afd5cc621df562fd7aa9557207147a8199b Gerrit-Change-Number: 37146 Gerrit-PatchSet: 1 Gerrit-Owner: James <jye836(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: James <jye836(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lenovo/t430: [NOTFORMERGE] Add support for MRC raminit
by Petr K (Code Review) 07 Aug '23

07 Aug '23

Petr K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37153 ) Change subject: mb/lenovo/t430: [NOTFORMERGE] Add support for MRC raminit ...................................................................... mb/lenovo/t430: [NOTFORMERGE] Add support for MRC raminit Add support for MRC raminit and fill PEI data to make ports work. Based on ideas from 32500 Change-Id: Ifab1292cbb489331f53ed17008c74f6ad22b2b83 --- M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430/early_init.c 3 files changed, 32 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/37153/1 diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig index 7137b5e..7e52967 100644 --- a/src/mainboard/lenovo/t430/Kconfig +++ b/src/mainboard/lenovo/t430/Kconfig @@ -19,7 +19,6 @@ select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP - select USE_NATIVE_RAMINIT select DRIVERS_LENOVO_HYBRID_GRAPHICS select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_INTERNAL_IS_LVDS diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index f7e0436..2770937 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -30,6 +30,28 @@ end end + # PEI data + register "spd_addresses" = "{ 0xa0, 0x00, 0xa2, 0x00 }" + register "ts_addresses" = "{ 0x00, 0x00, 0x00, 0x00 }" + register "max_mem_clock_mhz" = "800" # DDR3-1600 + + register "usb_port_config" = "{ + { 1, 1, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 2, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 0, 0x0040 }, + { 0, 0, 0x0040 }, + { 1, 2, 0x0040 }, + { 1, 0, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 0, 0x0040 }, + { 1, 0, 0x0040 }, + { 1, 3, 0x0040 }, + { 1, 1, 0x0040 }, + }" + device domain 0x0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" diff --git a/src/mainboard/lenovo/t430/early_init.c b/src/mainboard/lenovo/t430/early_init.c index 74c8b60..d30a621 100644 --- a/src/mainboard/lenovo/t430/early_init.c +++ b/src/mainboard/lenovo/t430/early_init.c @@ -20,6 +20,7 @@ #include <ec/lenovo/pmh7/pmh7.h> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> #include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> #include <device/device.h> #include <device/pci.h> @@ -77,3 +78,12 @@ read_spd(&spd[0], 0x50, id_only); read_spd(&spd[2], 0x51, id_only); } + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ +} + +int mainboard_should_reset_usb(int s3resume) +{ + return !s3resume; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/37153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifab1292cbb489331f53ed17008c74f6ad22b2b83 Gerrit-Change-Number: 37153 Gerrit-PatchSet: 1 Gerrit-Owner: Petr K Gerrit-MessageType: newchange

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