coreboot-gerrit November 2019

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Change in coreboot[master]: drivers/fsp2_0: drop support for FSP-T
by Arthur Heymans (Code Review) 08 Nov '19

08 Nov '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36622 ) Change subject: drivers/fsp2_0: drop support for FSP-T ...................................................................... Patch Set 4: > Patch Set 4: > > > Patch Set 4: > > > > > Patch Set 4: > > > > > > > Patch Set 4: > > > > > > > > > Patch Set 4: > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > > > > > > > > > > > > > Patch Set 4: Code-Review-1 > > > > > > > > > > > > > > > > > > > > > > > > > > FSP-T already set as optional. Some of our customers are using FSP-T, it has to be there. > > > > > > > > > > > > > > > > > > > > > > > > Could you please state why? What does FSP-T do that coreboot cannot? > > > > > > > > > > > > > > > > > > > > > > I understand the concern Arthur. > > > > > > > > > > > > > > > > > > > > > > There are some customer who still like to make use of FSP-T due to various reason. > > > > > > > > > > > > > > > > > > > > > > 1. native CAR implementation majorly focusing on NEM enhance > > > > > > > > > > > 2. Some customers like to use FSP-T with intel boot guard solution, where else native CAR what we implemented is not applicable with bootguard > > > > > > > > > > > > > > > > > > > > Can you give more details on that NEM part, please? > > > > > > > > > > > > > > > > here you go > > > > > > > > https://software.intel.com/en-us/articles/introduction-to-cache-allocation-… > > > > > > > > > > > > > > > > > > On 2: is there any chance, Intel can release more details here so we can (maybe) add support for it? > > > > > > > > > > > > > > So this is supported by fsp-t but not cb native, yet? Is it just writing some registers/msrs or is more needed to get CAT working? > > > > > > > > > > > > Ah, looks like just MSRs. But what exactly does FSP-T have to do with that? > > > > > > > > > > let me explain it little better. > > > > > FSP-T doesn't support CAT where Coreboot is supporting CAT. Current CAT implementation won't work with bootguard enable. As all FSP-T consumers are also willing to use bootguard solution hence they are not keen to use native CB CAR logic. And for current coreboot usage (frok google) doesn't bother to use bootguard hence we are good with CAT/NEM enhanced implementation. > > > > > > > > So it's just a matter of using NEM instead of NEM enhanced? coreboot has that too. > > > > > > sorry if it sounds otherwise. NEM enhance = CAT and both can't work with bootguard enable > > > > No I meant that coreboot has code to do CAR without NEM enhance, but with just NEM. Would that satisfy the bootguard requirements? > > NEM mode won't work with latest coreboot RO and RW design where romstage in RW. We will see hang during verstage if you not selecting NEM enhance and just select NEM mode. But that is something not specific to coreboot NEM implementation but NEM in general so also the implementation in FSP-T? It's weird that it would hang after verstage. The CAR itself is not evicted and if cachelines are full the romstage in RW just gets XIP uncached in that case. Another option is not cache the whole ROM, run verstage and setup XIP cache for the romstage. See how CB:35994 does that. -- To view, visit https://review.coreboot.org/c/coreboot/+/36622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib791b30b621730f4b7c0a5f668a3b6559245daf5 Gerrit-Change-Number: 36622 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 08 Nov 2019 15:05:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/fsp2_0: drop support for FSP-T
by Subrata Banik (Code Review) 08 Nov '19

08 Nov '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36622 ) Change subject: drivers/fsp2_0: drop support for FSP-T ...................................................................... Patch Set 4: > Patch Set 4: > > > Patch Set 4: > > > > > Patch Set 4: > > > > > > > Patch Set 4: > > > > > > > > > Patch Set 4: > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > > > > > > > > > > > Patch Set 4: Code-Review-1 > > > > > > > > > > > > > > > > > > > > > > > > FSP-T already set as optional. Some of our customers are using FSP-T, it has to be there. > > > > > > > > > > > > > > > > > > > > > > Could you please state why? What does FSP-T do that coreboot cannot? > > > > > > > > > > > > > > > > > > > > I understand the concern Arthur. > > > > > > > > > > > > > > > > > > > > There are some customer who still like to make use of FSP-T due to various reason. > > > > > > > > > > > > > > > > > > > > 1. native CAR implementation majorly focusing on NEM enhance > > > > > > > > > > 2. Some customers like to use FSP-T with intel boot guard solution, where else native CAR what we implemented is not applicable with bootguard > > > > > > > > > > > > > > > > > > Can you give more details on that NEM part, please? > > > > > > > > > > > > > > here you go > > > > > > > https://software.intel.com/en-us/articles/introduction-to-cache-allocation-… > > > > > > > > > > > > > > > > On 2: is there any chance, Intel can release more details here so we can (maybe) add support for it? > > > > > > > > > > > > So this is supported by fsp-t but not cb native, yet? Is it just writing some registers/msrs or is more needed to get CAT working? > > > > > > > > > > Ah, looks like just MSRs. But what exactly does FSP-T have to do with that? > > > > > > > > let me explain it little better. > > > > FSP-T doesn't support CAT where Coreboot is supporting CAT. Current CAT implementation won't work with bootguard enable. As all FSP-T consumers are also willing to use bootguard solution hence they are not keen to use native CB CAR logic. And for current coreboot usage (frok google) doesn't bother to use bootguard hence we are good with CAT/NEM enhanced implementation. > > > > > > So it's just a matter of using NEM instead of NEM enhanced? coreboot has that too. > > > > sorry if it sounds otherwise. NEM enhance = CAT and both can't work with bootguard enable > > No I meant that coreboot has code to do CAR without NEM enhance, but with just NEM. Would that satisfy the bootguard requirements? NEM mode won't work with latest coreboot RO and RW design where romstage in RW. We will see hang during verstage if you not selecting NEM enhance and just select NEM mode. -- To view, visit https://review.coreboot.org/c/coreboot/+/36622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib791b30b621730f4b7c0a5f668a3b6559245daf5 Gerrit-Change-Number: 36622 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 08 Nov 2019 15:00:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/fsp2_0: drop support for FSP-T
by Michael Niewöhner (Code Review) 08 Nov '19

08 Nov '19

1 0

Change in coreboot[master]: drivers/fsp2_0: drop support for FSP-T
by Arthur Heymans (Code Review) 08 Nov '19

08 Nov '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36622 ) Change subject: drivers/fsp2_0: drop support for FSP-T ...................................................................... Patch Set 4: > Patch Set 4: > > > Patch Set 4: > > > > > Patch Set 4: > > > > > > > Patch Set 4: > > > > > > > > > Patch Set 4: > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > > > > > > > > > > > > > Patch Set 4: Code-Review-1 > > > > > > > > > > > > > > > > > > > > > > > > > > FSP-T already set as optional. Some of our customers are using FSP-T, it has to be there. > > > > > > > > > > > > > > > > > > > > > > > > Could you please state why? What does FSP-T do that coreboot cannot? > > > > > > > > > > > > > > > > > > > > > > I understand the concern Arthur. > > > > > > > > > > > > > > > > > > > > > > There are some customer who still like to make use of FSP-T due to various reason. > > > > > > > > > > > > > > > > > > > > > > 1. native CAR implementation majorly focusing on NEM enhance > > > > > > > > > > > 2. Some customers like to use FSP-T with intel boot guard solution, where else native CAR what we implemented is not applicable with bootguard > > > > > > > > > > > > > > > > > > > > Can you give more details on that NEM part, please? > > > > > > > > > > > > > > > > here you go > > > > > > > > https://software.intel.com/en-us/articles/introduction-to-cache-allocation-… > > > > > > > > > > > > > > > > > > On 2: is there any chance, Intel can release more details here so we can (maybe) add support for it? > > > > > > > > > > > > > > So this is supported by fsp-t but not cb native, yet? Is it just writing some registers/msrs or is more needed to get CAT working? > > > > > > > > > > > > Ah, looks like just MSRs. But what exactly does FSP-T have to do with that? > > > > > > > > > > let me explain it little better. > > > > > FSP-T doesn't support CAT where Coreboot is supporting CAT. Current CAT implementation won't work with bootguard enable. As all FSP-T consumers are also willing to use bootguard solution hence they are not keen to use native CB CAR logic. And for current coreboot usage (frok google) doesn't bother to use bootguard hence we are good with CAT/NEM enhanced implementation. > > > > > > > > So it's just a matter of using NEM instead of NEM enhanced? coreboot has that too. > > > > > > sorry if it sounds otherwise. NEM enhance = CAT and both can't work with bootguard enable > > > > No I meant that coreboot has code to do CAR without NEM enhance, but with just NEM. Would that satisfy the bootguard requirements? > > Well, the current default is to alsways stick to NEM ehance, isn't it? (had just a short look at Kconfig) That is correct, NEM mode is not an option on skylake, cannonlake, icelake but it's a few Kconfig lines away from enabling that. @Subrata would that satisfy the bootguard requirements? Also arent't ACM's run *before* bootblock? Why would the CAR setup matter? -- To view, visit https://review.coreboot.org/c/coreboot/+/36622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib791b30b621730f4b7c0a5f668a3b6559245daf5 Gerrit-Change-Number: 36622 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 08 Nov 2019 14:59:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/fsp2_0: drop support for FSP-T
by Michael Niewöhner (Code Review) 08 Nov '19

08 Nov '19

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36622 ) Change subject: drivers/fsp2_0: drop support for FSP-T ...................................................................... Patch Set 4: > Patch Set 4: > > > Patch Set 4: > > > > > Patch Set 4: > > > > > > > Patch Set 4: > > > > > > > > > Patch Set 4: > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > > > > > > > > > > > Patch Set 4: Code-Review-1 > > > > > > > > > > > > > > > > > > > > > > > > FSP-T already set as optional. Some of our customers are using FSP-T, it has to be there. > > > > > > > > > > > > > > > > > > > > > > Could you please state why? What does FSP-T do that coreboot cannot? > > > > > > > > > > > > > > > > > > > > I understand the concern Arthur. > > > > > > > > > > > > > > > > > > > > There are some customer who still like to make use of FSP-T due to various reason. > > > > > > > > > > > > > > > > > > > > 1. native CAR implementation majorly focusing on NEM enhance > > > > > > > > > > 2. Some customers like to use FSP-T with intel boot guard solution, where else native CAR what we implemented is not applicable with bootguard > > > > > > > > > > > > > > > > > > Can you give more details on that NEM part, please? > > > > > > > > > > > > > > here you go > > > > > > > https://software.intel.com/en-us/articles/introduction-to-cache-allocation-… > > > > > > > > > > > > > > > > On 2: is there any chance, Intel can release more details here so we can (maybe) add support for it? > > > > > > > > > > > > So this is supported by fsp-t but not cb native, yet? Is it just writing some registers/msrs or is more needed to get CAT working? > > > > > > > > > > Ah, looks like just MSRs. But what exactly does FSP-T have to do with that? > > > > > > > > let me explain it little better. > > > > FSP-T doesn't support CAT where Coreboot is supporting CAT. Current CAT implementation won't work with bootguard enable. As all FSP-T consumers are also willing to use bootguard solution hence they are not keen to use native CB CAR logic. And for current coreboot usage (frok google) doesn't bother to use bootguard hence we are good with CAT/NEM enhanced implementation. > > > > > > So it's just a matter of using NEM instead of NEM enhanced? coreboot has that too. > > > > sorry if it sounds otherwise. NEM enhance = CAT and both can't work with bootguard enable > > No I meant that coreboot has code to do CAR without NEM enhance, but with just NEM. Would that satisfy the bootguard requirements? Well, the current default is to alsways stick to NEM ehance, isn't it? (had just a short look at Kconfig) -- To view, visit https://review.coreboot.org/c/coreboot/+/36622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib791b30b621730f4b7c0a5f668a3b6559245daf5 Gerrit-Change-Number: 36622 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 08 Nov 2019 14:54:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/fsp2_0: drop support for FSP-T
by Arthur Heymans (Code Review) 08 Nov '19

08 Nov '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36622 ) Change subject: drivers/fsp2_0: drop support for FSP-T ...................................................................... Patch Set 4: > Patch Set 4: > > > Patch Set 4: > > > > > Patch Set 4: > > > > > > > Patch Set 4: > > > > > > > > > Patch Set 4: > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > > > > > > > > > Patch Set 4: Code-Review-1 > > > > > > > > > > > > > > > > > > > > > > FSP-T already set as optional. Some of our customers are using FSP-T, it has to be there. > > > > > > > > > > > > > > > > > > > > Could you please state why? What does FSP-T do that coreboot cannot? > > > > > > > > > > > > > > > > > > I understand the concern Arthur. > > > > > > > > > > > > > > > > > > There are some customer who still like to make use of FSP-T due to various reason. > > > > > > > > > > > > > > > > > > 1. native CAR implementation majorly focusing on NEM enhance > > > > > > > > > 2. Some customers like to use FSP-T with intel boot guard solution, where else native CAR what we implemented is not applicable with bootguard > > > > > > > > > > > > > > > > Can you give more details on that NEM part, please? > > > > > > > > > > > > here you go > > > > > > https://software.intel.com/en-us/articles/introduction-to-cache-allocation-… > > > > > > > > > > > > > > On 2: is there any chance, Intel can release more details here so we can (maybe) add support for it? > > > > > > > > > > So this is supported by fsp-t but not cb native, yet? Is it just writing some registers/msrs or is more needed to get CAT working? > > > > > > > > Ah, looks like just MSRs. But what exactly does FSP-T have to do with that? > > > > > > let me explain it little better. > > > FSP-T doesn't support CAT where Coreboot is supporting CAT. Current CAT implementation won't work with bootguard enable. As all FSP-T consumers are also willing to use bootguard solution hence they are not keen to use native CB CAR logic. And for current coreboot usage (frok google) doesn't bother to use bootguard hence we are good with CAT/NEM enhanced implementation. > > > > So it's just a matter of using NEM instead of NEM enhanced? coreboot has that too. > > sorry if it sounds otherwise. NEM enhance = CAT and both can't work with bootguard enable No I meant that coreboot has code to do CAR without NEM enhance, but with just NEM. Would that satisfy the bootguard requirements? -- To view, visit https://review.coreboot.org/c/coreboot/+/36622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib791b30b621730f4b7c0a5f668a3b6559245daf5 Gerrit-Change-Number: 36622 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 08 Nov 2019 14:43:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/fsp2_0: drop support for FSP-T
by Subrata Banik (Code Review) 08 Nov '19

08 Nov '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36622 ) Change subject: drivers/fsp2_0: drop support for FSP-T ...................................................................... Patch Set 4: > Patch Set 4: > > > Patch Set 4: > > > > > Patch Set 4: > > > > > > > Patch Set 4: > > > > > > > > > Patch Set 4: > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > > > > > > > Patch Set 4: Code-Review-1 > > > > > > > > > > > > > > > > > > > > FSP-T already set as optional. Some of our customers are using FSP-T, it has to be there. > > > > > > > > > > > > > > > > > > Could you please state why? What does FSP-T do that coreboot cannot? > > > > > > > > > > > > > > > > I understand the concern Arthur. > > > > > > > > > > > > > > > > There are some customer who still like to make use of FSP-T due to various reason. > > > > > > > > > > > > > > > > 1. native CAR implementation majorly focusing on NEM enhance > > > > > > > > 2. Some customers like to use FSP-T with intel boot guard solution, where else native CAR what we implemented is not applicable with bootguard > > > > > > > > > > > > > > Can you give more details on that NEM part, please? > > > > > > > > > > here you go > > > > > https://software.intel.com/en-us/articles/introduction-to-cache-allocation-… > > > > > > > > > > > > On 2: is there any chance, Intel can release more details here so we can (maybe) add support for it? > > > > > > > > So this is supported by fsp-t but not cb native, yet? Is it just writing some registers/msrs or is more needed to get CAT working? > > > > > > Ah, looks like just MSRs. But what exactly does FSP-T have to do with that? > > > > let me explain it little better. > > FSP-T doesn't support CAT where Coreboot is supporting CAT. Current CAT implementation won't work with bootguard enable. As all FSP-T consumers are also willing to use bootguard solution hence they are not keen to use native CB CAR logic. And for current coreboot usage (frok google) doesn't bother to use bootguard hence we are good with CAT/NEM enhanced implementation. > > So it's just a matter of using NEM instead of NEM enhanced? coreboot has that too. sorry if it sounds otherwise. NEM enhance = CAT and both can't work with bootguard enable -- To view, visit https://review.coreboot.org/c/coreboot/+/36622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib791b30b621730f4b7c0a5f668a3b6559245daf5 Gerrit-Change-Number: 36622 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 08 Nov 2019 14:42:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/fsp2_0: drop support for FSP-T
by Arthur Heymans (Code Review) 08 Nov '19

08 Nov '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36622 ) Change subject: drivers/fsp2_0: drop support for FSP-T ...................................................................... Patch Set 4: > Patch Set 4: > > > Patch Set 4: > > > > > Patch Set 4: > > > > > > > Patch Set 4: > > > > > > > > > Patch Set 4: > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > > > > > Patch Set 4: Code-Review-1 > > > > > > > > > > > > > > > > > > FSP-T already set as optional. Some of our customers are using FSP-T, it has to be there. > > > > > > > > > > > > > > > > Could you please state why? What does FSP-T do that coreboot cannot? > > > > > > > > > > > > > > I understand the concern Arthur. > > > > > > > > > > > > > > There are some customer who still like to make use of FSP-T due to various reason. > > > > > > > > > > > > > > 1. native CAR implementation majorly focusing on NEM enhance > > > > > > > 2. Some customers like to use FSP-T with intel boot guard solution, where else native CAR what we implemented is not applicable with bootguard > > > > > > > > > > > > Can you give more details on that NEM part, please? > > > > > > > > here you go > > > > https://software.intel.com/en-us/articles/introduction-to-cache-allocation-… > > > > > > > > > > On 2: is there any chance, Intel can release more details here so we can (maybe) add support for it? > > > > > > So this is supported by fsp-t but not cb native, yet? Is it just writing some registers/msrs or is more needed to get CAT working? > > > > Ah, looks like just MSRs. But what exactly does FSP-T have to do with that? > > let me explain it little better. > FSP-T doesn't support CAT where Coreboot is supporting CAT. Current CAT implementation won't work with bootguard enable. As all FSP-T consumers are also willing to use bootguard solution hence they are not keen to use native CB CAR logic. And for current coreboot usage (frok google) doesn't bother to use bootguard hence we are good with CAT/NEM enhanced implementation. So it's just a matter of using NEM instead of NEM enhanced? coreboot has that too. -- To view, visit https://review.coreboot.org/c/coreboot/+/36622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib791b30b621730f4b7c0a5f668a3b6559245daf5 Gerrit-Change-Number: 36622 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 08 Nov 2019 14:37:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/fsp2_0: drop support for FSP-T
by Subrata Banik (Code Review) 08 Nov '19

08 Nov '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36622 ) Change subject: drivers/fsp2_0: drop support for FSP-T ...................................................................... Patch Set 4: > Patch Set 4: > > > Patch Set 4: > > > > > Patch Set 4: > > > > > > > Patch Set 4: > > > > > > > > > Patch Set 4: > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > > > > Patch Set 4: Code-Review-1 > > > > > > > > > > > > > > > > FSP-T already set as optional. Some of our customers are using FSP-T, it has to be there. > > > > > > > > > > > > > > Could you please state why? What does FSP-T do that coreboot cannot? > > > > > > > > > > > > I understand the concern Arthur. > > > > > > > > > > > > There are some customer who still like to make use of FSP-T due to various reason. > > > > > > > > > > > > 1. native CAR implementation majorly focusing on NEM enhance > > > > > > 2. Some customers like to use FSP-T with intel boot guard solution, where else native CAR what we implemented is not applicable with bootguard > > > > > > > > > > Can you give more details on that NEM part, please? > > > > > > here you go > > > https://software.intel.com/en-us/articles/introduction-to-cache-allocation-… > > > > > > > > On 2: is there any chance, Intel can release more details here so we can (maybe) add support for it? > > > > So this is supported by fsp-t but not cb native, yet? Is it just writing some registers/msrs or is more needed to get CAT working? > > Ah, looks like just MSRs. But what exactly does FSP-T have to do with that? let me explain it little better. FSP-T doesn't support CAT where Coreboot is supporting CAT. Current CAT implementation won't work with bootguard enable. As all FSP-T consumers are also willing to use bootguard solution hence they are not keen to use native CB CAR logic. And for current coreboot usage (frok google) doesn't bother to use bootguard hence we are good with CAT/NEM enhanced implementation. -- To view, visit https://review.coreboot.org/c/coreboot/+/36622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib791b30b621730f4b7c0a5f668a3b6559245daf5 Gerrit-Change-Number: 36622 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 08 Nov 2019 14:34:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/fsp2_0: drop support for FSP-T
by Michael Niewöhner (Code Review) 08 Nov '19

08 Nov '19

1 0

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