coreboot-gerrit November 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/common/basecode: Implement CSE update flow
by build bot (Jenkins) (Code Review) 22 Nov '19

22 Nov '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35403 ) Change subject: soc/intel/common/basecode: Implement CSE update flow ...................................................................... Patch Set 19: (5 comments) https://review.coreboot.org/c/coreboot/+/35403/19/src/soc/intel/common/base… File src/soc/intel/common/basecode/fw_update/cse_update.c: https://review.coreboot.org/c/coreboot/+/35403/19/src/soc/intel/common/base… PS19, Line 120: /* If CSE boots from BP1, then CSE ready for HMRFPO mode, but not in HMRFPO mode */ code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/35403/19/src/soc/intel/common/base… PS19, Line 121: if(current_bp != BP1) { space required before the open parenthesis '(' https://review.coreboot.org/c/coreboot/+/35403/19/src/soc/intel/common/base… PS19, Line 251: if(!cse_check_rw_state(me_rw_bp_status)) { suspect code indent for conditional statements (8, 17) https://review.coreboot.org/c/coreboot/+/35403/19/src/soc/intel/common/base… PS19, Line 251: if(!cse_check_rw_state(me_rw_bp_status)) { space required before the open parenthesis '(' https://review.coreboot.org/c/coreboot/+/35403/19/src/soc/intel/common/base… PS19, Line 253: return -1; Statements should start on a tabstop -- To view, visit https://review.coreboot.org/c/coreboot/+/35403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Gerrit-Change-Number: 35403 Gerrit-PatchSet: 19 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 22 Nov 2019 18:53:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/basecode: Implement CSE update flow
by Sridhar Siricilla (Code Review) 22 Nov '19

22 Nov '19

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Aamir Bohra, Rizwan Qureshi, V Sowmya, build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35403 to look at the new patch set (#19). Change subject: soc/intel/common/basecode: Implement CSE update flow ...................................................................... soc/intel/common/basecode: Implement CSE update flow This is the core patch that implement CSE FW update flow. To enable the FW update flow the following are required: * Descriptor change to accommodate a larger CSME region The CSME size is 6MB for the POC. * FMAP changes to accommodate ME update binary in RW CBFSes. Due to the increased CSME binary size and to accommodate the extra CSME RW binaries (which are ~2.5 MB) in RW CBFSes, the board FMAP has to be modified. * The new CSE binary with new partitions and respective RW area binaries. The following changes have been done in this patch: * Implement Update flow Get the partition info containing version of ME RW using GET_BOOT_PARTITION_INFO HECI command Get the me_rw.version from the currently selected RW slot. If the version from the above 2 locations don't match start the update Set the CSE's next boot partition to RO using SET_BOOT_PARTITION HECI command. Send global reset command to reset only the CSME Wait for CSME to enter SOFT_TEMP_DISABLE operation mode (indicated by HFSTS1 register bit 19:16) Enable HMRFPO (Host ME Region Flash Protection Override) using the HMRFPO_ENABLE HECI command Erase and Copy the CBFS ME RW to ME RW partition Set the CSE's next boot partition to RW using SET_BOOT_PARTITION HECI command Trigger global reset The system should boot with the Updated ME Verified that the basic update flows are working on Cometlake RVP and hatch. Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- A src/soc/intel/common/basecode/fw_update/Kconfig A src/soc/intel/common/basecode/fw_update/Makefile.inc A src/soc/intel/common/basecode/fw_update/cse_update.c A src/soc/intel/common/basecode/include/intelbasecode/cse_update.h 4 files changed, 439 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/35403/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/35403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Gerrit-Change-Number: 35403 Gerrit-PatchSet: 19 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Sridhar Siricilla (Code Review) 22 Nov '19

22 Nov '19

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Aamir Bohra, Rizwan Qureshi, V Sowmya, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35402 to look at the new patch set (#29). Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... soc/intel/common/block/cse: Add boot partition related APIs The CSE region is logically divided into 3 boot partitions when redundancy is enabled. These boot partitions are represented by BP1, BP2 and BP3. In chrome, CSE can boot from either BP1 or BP2. The CSE image layout appears as below.. ------------- ------------------ -------------------------- |CSE REGION | => | RO | RW | DATA | => | BP1 | BP2 + BP3 | DATA | ------------- ------------------ -------------------------- In order to support CSE FW update to RW region, below APIs help coreboot to get info about the boot partitions, and allows the coreboot to set CSE to boot from required boot partition(either BP1(RO) or BP2). GET_BOOT_PARTITION_INFO - provides info on available partitions in the CSE region. The API provides info on boot partitions like start/end offsets of a partition within CSE region, and their version and partition status. SET_BOOT_PARTITION_INFO - Sets the next boot partition to boot for CSE. With the HECI API, firmware can notify CSE to boot from BP1 or BP2 on next boot. Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cse/Makefile.inc A src/soc/intel/common/block/cse/cse_bp.c M src/soc/intel/common/block/include/intelblocks/cse.h 3 files changed, 491 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35402/29 -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 29 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Nico Huber (Code Review) 22 Nov '19

22 Nov '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35402 ) Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... Patch Set 28: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 28 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 22 Nov 2019 18:50:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/lenovo/t430: Add support for MRC raminit
by Petr K (Code Review) 22 Nov '19

22 Nov '19

Petr K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33539 Change subject: mb/lenovo/t430: Add support for MRC raminit ...................................................................... mb/lenovo/t430: Add support for MRC raminit Add support for MRC raminit and fill PEI data to make ports work. Based on 32500 Signed-off-by: Petr K <piotrkloc94(a)hotmail.com> Change-Id: I3e097f7bb6b1de55b9e6a84efa4f9c630cee0745 --- M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430/romstage.c 3 files changed, 43 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/33539/1 diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig index 7137b5e..7e52967 100644 --- a/src/mainboard/lenovo/t430/Kconfig +++ b/src/mainboard/lenovo/t430/Kconfig @@ -19,7 +19,6 @@ select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP - select USE_NATIVE_RAMINIT select DRIVERS_LENOVO_HYBRID_GRAPHICS select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_INTERNAL_IS_LVDS diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 2731b69..a992377 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -30,6 +30,32 @@ end end + # PEI data + + register "spd_addresses" = "{ 0xa0, 0x00, 0xa2, 0x00 }" + register "ts_addresses" = "{ 0x00, 0x00, 0x00, 0x00 }" + + register "max_mem_clock_mhz" = "800" # DDR3-1600 + + register "usb_port_config" = "{ + + { 1, 1, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 2, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 0, 0x0040 }, + { 0, 0, 0x0040 }, + { 1, 2, 0x0040 }, + { 1, 0, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 0, 0x0040 }, + { 1, 0, 0x0040 }, + { 1, 3, 0x0040 }, + { 1, 1, 0x0040 }, + + }" + device domain 0x0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" diff --git a/src/mainboard/lenovo/t430/romstage.c b/src/mainboard/lenovo/t430/romstage.c index db50bb3..fa46dc3 100644 --- a/src/mainboard/lenovo/t430/romstage.c +++ b/src/mainboard/lenovo/t430/romstage.c @@ -20,6 +20,7 @@ #include <ec/lenovo/pmh7/pmh7.h> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> #include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> #include <device/device.h> #include <device/pci.h> @@ -96,3 +97,19 @@ read_spd(&spd[0], 0x50, id_only); read_spd(&spd[2], 0x51, id_only); } + + +void mainboard_fill_pei_data(struct pei_data *pei_data) + +{ + +} + + +int mainboard_should_reset_usb(int s3resume) + +{ + + return !s3resume; + +} -- To view, visit https://review.coreboot.org/c/coreboot/+/33539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e097f7bb6b1de55b9e6a84efa4f9c630cee0745 Gerrit-Change-Number: 33539 Gerrit-PatchSet: 1 Gerrit-Owner: Petr K Gerrit-MessageType: newchange

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Change in em100[master]: Makefile: Move libs to the end
by Stefan Reinauer (Code Review) 22 Nov '19

22 Nov '19

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/37081 ) Change subject: Makefile: Move libs to the end ...................................................................... Makefile: Move libs to the end Move LDFLAGS to the end of the linker call. This fixes a linking issue on Ubuntu 19.10 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: If15ca42b8f046e68a232d282bec5fa130340b2f4 --- M Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/81/37081/1 diff --git a/Makefile b/Makefile index 515db64..efba410 100644 --- a/Makefile +++ b/Makefile @@ -45,7 +45,7 @@ em100: $(OBJECTS) printf " LD em100\n" - $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $(OBJECTS) + $(CC) $(CFLAGS) -o $@ $(OBJECTS) $(LDFLAGS) em100pro_chips.h: makechips.sh printf " CREATE em100pro_chips.sh & firmware images\n" -- To view, visit https://review.coreboot.org/c/em100/+/37081 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: If15ca42b8f046e68a232d282bec5fa130340b2f4 Gerrit-Change-Number: 37081 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in em100[master]: Cosmetic Makefile fixes
by Stefan Reinauer (Code Review) 22 Nov '19

22 Nov '19

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/37133 ) Change subject: Cosmetic Makefile fixes ...................................................................... Cosmetic Makefile fixes Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I3919f2ea87950aeb92c412778e875b4df8d19188 --- M Makefile 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/33/37133/1 diff --git a/Makefile b/Makefile index 41b5281..164a934 100644 --- a/Makefile +++ b/Makefile @@ -23,23 +23,23 @@ endif endif -CFLAGS ?=-O2 -g -fomit-frame-pointer +CFLAGS ?= -O2 -g -fomit-frame-pointer CFLAGS += $(shell $(PKG_CONFIG) --cflags libusb-1.0) CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS += -Wwrite-strings -Wredundant-decls -Wstrict-aliasing -Wshadow -Wextra CFLAGS += -Wno-unused-but-set-variable # Remove after fixing -CFLAGS +=-Wno-sign-compare -Wno-discarded-qualifiers +CFLAGS += -Wno-sign-compare -Wno-discarded-qualifiers LDFLAGS ?= LDFLAGS += $(shell $(PKG_CONFIG) --libs libusb-1.0) -CC?=gcc -PKG_CONFIG?=pkg-config +CC ?= gcc +PKG_CONFIG ?= pkg-config -SOURCES=em100.c firmware.c fpga.c hexdump.c sdram.c spi.c system.c trace.c usb.c -OBJECTS=$(SOURCES:.c=.o) +SOURCES = em100.c firmware.c fpga.c hexdump.c sdram.c spi.c system.c trace.c usb.c +OBJECTS = $(SOURCES:.c=.o) all: dep em100 -- To view, visit https://review.coreboot.org/c/em100/+/37133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I3919f2ea87950aeb92c412778e875b4df8d19188 Gerrit-Change-Number: 37133 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in em100[master]: Fix compiler warnings
by Stefan Reinauer (Code Review) 22 Nov '19

22 Nov '19

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/37071 ) Change subject: Fix compiler warnings ...................................................................... Fix compiler warnings The signal handler is not used outside of em100.c and it's not using its argument. For convenience, add __packed and __unused to em100.h Change-Id: I981104ac95d648a341bce8348f01bd7eead1da9e Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M em100.c M em100.h M firmware.c 3 files changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/71/37071/1 diff --git a/em100.c b/em100.c index 07099aa..97ff22c 100644 --- a/em100.c +++ b/em100.c @@ -29,7 +29,8 @@ volatile int do_exit_flag = 0; -void exit_handler(int sig) { +static void exit_handler(int sig __unused) +{ do_exit_flag = 1; } diff --git a/em100.h b/em100.h index 9ebcb13..72518d1 100644 --- a/em100.h +++ b/em100.h @@ -20,6 +20,9 @@ #include <libusb.h> +#define __unused __attribute__((unused)) +#define __packed __attribute__((packed)) + struct em100 { libusb_device_handle *dev; libusb_context *ctx; diff --git a/firmware.c b/firmware.c index 6e2ff36..dd1a173 100644 --- a/firmware.c +++ b/firmware.c @@ -184,7 +184,7 @@ } fclose(fw); -#if DEBUG +#ifdef DEBUG hexdump(data, rom_size); #endif free(data); -- To view, visit https://review.coreboot.org/c/em100/+/37071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I981104ac95d648a341bce8348f01bd7eead1da9e Gerrit-Change-Number: 37071 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in em100[master]: Add dependency tracking to Makefile
by Stefan Reinauer (Code Review) 22 Nov '19

22 Nov '19

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/37070 ) Change subject: Add dependency tracking to Makefile ...................................................................... Add dependency tracking to Makefile Reworking Makefile to show more warnings in the code. Create dependencies and compile files separately. Change-Id: I03d4c656a0c4529473adadc3db7bfb9141094021 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M .gitignore M Makefile 2 files changed, 33 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/70/37070/1 diff --git a/.gitignore b/.gitignore index f6eb53d..62b9d8e 100644 --- a/.gitignore +++ b/.gitignore @@ -4,3 +4,4 @@ /makechips /makedpfw /EM100Pro.msi +*.o diff --git a/Makefile b/Makefile index 0518c6f..e56d380 100644 --- a/Makefile +++ b/Makefile @@ -17,36 +17,56 @@ .SILENT: -CFLAGS?=-O2 -g -CFLAGS+=-Wall -Werror +CFLAGS ?=-O2 -g -fomit-frame-pointer +CFLAGS += $(shell $(PKG_CONFIG) --cflags libusb-1.0) + +CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes +CFLAGS += -Wwrite-strings -Wredundant-decls -Wstrict-aliasing -Wshadow -Wextra +CFLAGS += -Wno-unused-but-set-variable +# Remove after fixing +CFLAGS +=-Wno-sign-compare -Wno-discarded-qualifiers + +LDFLAGS ?= +LDFLAGS += $(shell $(PKG_CONFIG) --libs libusb-1.0) + CC?=gcc PKG_CONFIG?=pkg-config SOURCES=em100.c firmware.c fpga.c hexdump.c sdram.c spi.c system.c trace.c usb.c -INCLUDES=em100pro_chips.h em100.h +OBJECTS=$(SOURCES:.c=.o) -all: em100 +all: dep em100 -em100: $(SOURCES) $(INCLUDES) - printf " CC em100\n" - $(CC) $(CFLAGS) $(CPPFLAGS) $(LDFLAGS) -o $@ $(SOURCES) \ - $(shell $(PKG_CONFIG) --cflags --libs libusb-1.0) +em100: $(OBJECTS) + printf " LD em100\n" + $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $(OBJECTS) em100pro_chips.h: makechips.sh printf " CREATE em100pro_chips.sh & firmware images\n" LANG=C ./makechips.sh -makechips.sh: makedpfw makechips - %: %.c - printf " CC $@\n" + printf " CC+LD $@\n" $(CC) $(CFLAGS) $(CPPFLAGS) $(LDFLAGS) -o $@ $< +%.o: %.c + printf " CC $@\n" + $(CC) $(CFLAGS) $(CPPFLAGS) -o $@ -c $< + +dep: $(SOURCES) em100pro_chips.h + $(CC) $(CFLAGS) $(INCLUDES) -MM $(SOURCES) > .dependencies + +makechips.sh: makedpfw makechips + clean: rm -f em100 makedpfw makechips + rm -f $(OBJECTS) # $(SOURCES:.c=.d) rm -rf configs firmware + rm -f .dependencies distclean: clean - rm em100pro_chips.h + rm -f em100pro_chips.h + +-include .dependencies .PHONY: clean distclean -- To view, visit https://review.coreboot.org/c/em100/+/37070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I03d4c656a0c4529473adadc3db7bfb9141094021 Gerrit-Change-Number: 37070 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/i945: Programm CxODT value for each channel
by HAOUAS Elyes (Code Review) 22 Nov '19

22 Nov '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/18548 ) Change subject: nb/intel/i945: Programm CxODT value for each channel ...................................................................... Patch Set 26: > Patch Set 26: > > Does this improve things in any visible way? I don't know. Actually, the main problem for current board, is 'sdram_rcomp_buffer_strength_and_slew()' function (i945/raminit.c) -- To view, visit https://review.coreboot.org/c/coreboot/+/18548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aec35f45250da554ddc5a68f5add157c313399c Gerrit-Change-Number: 18548 Gerrit-PatchSet: 26 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Fri, 22 Nov 2019 16:41:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2019