coreboot-gerrit November 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/(i945): Remove redundant pci_mmio_size
by HAOUAS Elyes (Code Review) 22 Nov '19

22 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36927 ) Change subject: mb/(i945): Remove redundant pci_mmio_size ...................................................................... mb/(i945): Remove redundant pci_mmio_size i945/raminit.c will set pci_mmio_size to DEFAULT_PCI_MMIO_SIZE if the value isless than 768 (see line #1223) Change-Id: I50bf833383e8d06f73e05113cb92fdbbf39fdad6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/apple/macbook21/devicetree.cb M src/mainboard/getac/p470/devicetree.cb M src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb M src/mainboard/ibase/mb899/devicetree.cb M src/mainboard/intel/d945gclf/devicetree.cb M src/mainboard/kontron/986lcd-m/devicetree.cb M src/mainboard/lenovo/t60/devicetree.cb M src/mainboard/lenovo/x60/devicetree.cb M src/mainboard/roda/rk886ex/devicetree.cb 9 files changed, 0 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/36927/1 diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index 137c8fc..3e3ca38 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -35,8 +35,6 @@ end end - register "pci_mmio_size" = "768" - device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x8086 0x7270 diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index e2001d9..0620416 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -25,8 +25,6 @@ end end - register "pci_mmio_size" = "768" - device domain 0 on device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb index ff5d57b..7ecaf28 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb @@ -25,8 +25,6 @@ end end - register "pci_mmio_size" = "768" - device domain 0 on device pci 00.0 on # host bridge subsystemid 0x1458 0x5000 diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb index 78743bd..1f0c76b 100644 --- a/src/mainboard/ibase/mb899/devicetree.cb +++ b/src/mainboard/ibase/mb899/devicetree.cb @@ -9,8 +9,6 @@ end end - register "pci_mmio_size" = "768" - device domain 0 on device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index 7114a29..23723c7 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -21,8 +21,6 @@ end end - register "pci_mmio_size" = "768" - device domain 0 on subsystemid 0x8086 0x464c inherit device pci 00.0 on end # host bridge diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb index 741c47b..377d496 100644 --- a/src/mainboard/kontron/986lcd-m/devicetree.cb +++ b/src/mainboard/kontron/986lcd-m/devicetree.cb @@ -9,8 +9,6 @@ end end - register "pci_mmio_size" = "768" - device domain 0 on device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index ada50f3..2c80dc2 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -35,8 +35,6 @@ end end - register "pci_mmio_size" = "768" - device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2015 diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 1a914fd..54c4e81 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -35,8 +35,6 @@ end end - register "pci_mmio_size" = "768" - device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2017 diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index 5bce304..91601d2 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -25,8 +25,6 @@ end end - register "pci_mmio_size" = "768" - device domain 0 on subsystemid 0x4352 0x6886 inherit device pci 00.0 on end # host bridge -- To view, visit https://review.coreboot.org/c/coreboot/+/36927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50bf833383e8d06f73e05113cb92fdbbf39fdad6 Gerrit-Change-Number: 36927 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/console: Bring back support for printf'ing 64bit ints
by Patrick Georgi (Code Review) 22 Nov '19

22 Nov '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37113 ) Change subject: src/console: Bring back support for printf'ing 64bit ints ...................................................................... src/console: Bring back support for printf'ing 64bit ints commit f96d9051c2 (Remove MIPS Architecture) accidentally enabled a MIPS special case to not support 64bit integers in printf for all platforms. This removes that MIPS-only special case entirely. Change-Id: I5245bb32b45f9bd37bd012a7b15a64fba24a4cb7 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/console/vtxprintf.c 1 file changed, 0 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/37113/1 diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index b9e4369..104f4ea 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -36,20 +36,8 @@ const char *digits = "0123456789abcdef"; int i; int count = 0; -#ifdef SUPPORT_64BIT_INTS unsigned long long num = inum; long long snum = num; -#else - unsigned long num = (unsigned long)inum; - long snum = (long)num; - - if (num != inum) { - /* Alert user to an incorrect result by printing #^!. */ - call_tx('#'); - call_tx('^'); - call_tx('!'); - } -#endif if (type & LARGE) digits = "0123456789ABCDEF"; -- To view, visit https://review.coreboot.org/c/coreboot/+/37113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5245bb32b45f9bd37bd012a7b15a64fba24a4cb7 Gerrit-Change-Number: 37113 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in em100[master]: Really fix the chip detection
by Patrick Georgi (Code Review) 22 Nov '19

22 Nov '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/37147 ) Change subject: Really fix the chip detection ...................................................................... Really fix the chip detection if (!chip) is still always wrong (because it comes from an array) Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Change-Id: Idf472003e5d0ab65c8e1c5acb61b416720cd317f --- M em100.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/47/37147/1 diff --git a/em100.c b/em100.c index 50b04b4..c806413 100644 --- a/em100.c +++ b/em100.c @@ -626,7 +626,7 @@ break; } - if (!chip) + if (!chip->name) return 1; *out = chip; -- To view, visit https://review.coreboot.org/c/em100/+/37147 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: Idf472003e5d0ab65c8e1c5acb61b416720cd317f Gerrit-Change-Number: 37147 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/i945: Programm CxODT value for each channel
by Angel Pons (Code Review) 22 Nov '19

22 Nov '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/18548 ) Change subject: nb/intel/i945: Programm CxODT value for each channel ...................................................................... Patch Set 26: Does this improve things in any visible way? -- To view, visit https://review.coreboot.org/c/coreboot/+/18548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aec35f45250da554ddc5a68f5add157c313399c Gerrit-Change-Number: 18548 Gerrit-PatchSet: 26 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Fri, 22 Nov 2019 15:00:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sb/lynxpoint: Use macros instead of hard-coded IDs
by Felix Singer (Code Review) 22 Nov '19

22 Nov '19

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36706 ) Change subject: sb/lynxpoint: Use macros instead of hard-coded IDs ...................................................................... Patch Set 4: > Patch Set 4: Code-Review+1 I will fix the characters count in a follow up patch by shortening all the PCI macro names. -- To view, visit https://review.coreboot.org/c/coreboot/+/36706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7d0f7122e461b78526692b78f79edcafafd3286 Gerrit-Change-Number: 36706 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 22 Nov 2019 14:13:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/ibexpeak: Decode more LPC IO ranges
by Arthur Heymans (Code Review) 22 Nov '19

22 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36994 ) Change subject: sb/intel/ibexpeak: Decode more LPC IO ranges ...................................................................... sb/intel/ibexpeak: Decode more LPC IO ranges This fixes Thinkpad X201T which uses IO 0x200 for wacom digitizer. Change-Id: Ie569d567a65010aa5372323f8610a1b8b5d2599d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/ibexpeak/bootblock.c 1 file changed, 15 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/36994/1 diff --git a/src/southbridge/intel/ibexpeak/bootblock.c b/src/southbridge/intel/ibexpeak/bootblock.c index 599e182..c8b1d6e 100644 --- a/src/southbridge/intel/ibexpeak/bootblock.c +++ b/src/southbridge/intel/ibexpeak/bootblock.c @@ -62,15 +62,21 @@ const struct device *dev = pcidev_on_root(0x1f, 0); const struct southbridge_intel_ibexpeak_config *config = NULL; - /* Add some default decode ranges: - - 0x2e/2f, 0x4e/0x4f - - EC/Mouse/KBC 60/64, 62/66 - - 0x3f8 COMA - If more are needed, update in mainboard_lpc_init hook - */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN); + /* + * Enable some common LPC IO ranges: + * - 0x2e/0x2f, 0x4e/0x4f often SuperIO + * - 0x60/0x64, 0x62/0x66 often KBC/EC + * - 0x3f0-0x3f5/0x3f7 FDD + * - 0x378-0x37f and 0x778-0x77f LPT + * - 0x2f8-0x2ff COMB + * - 0x3f8-0x3ff COMA + * - 0x208-0x20f GAMEH + * - 0x200-0x207 GAMEL + */ + pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN + | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN + | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN + | COMB_LPC_EN | COMA_LPC_EN); pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); /* Clear PWR_FLR */ -- To view, visit https://review.coreboot.org/c/coreboot/+/36994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie569d567a65010aa5372323f8610a1b8b5d2599d Gerrit-Change-Number: 36994 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/lynxpoint: Use macros instead of hard-coded IDs
by HAOUAS Elyes (Code Review) 22 Nov '19

22 Nov '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36706 ) Change subject: sb/lynxpoint: Use macros instead of hard-coded IDs ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/36706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7d0f7122e461b78526692b78f79edcafafd3286 Gerrit-Change-Number: 36706 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 22 Nov 2019 12:03:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sb/lynxpoint: Use macros instead of hard-coded IDs
by HAOUAS Elyes (Code Review) 22 Nov '19

22 Nov '19

HAOUAS Elyes has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/36706 ) Change subject: sb/lynxpoint: Use macros instead of hard-coded IDs ...................................................................... Removed Code-Review+2 by HAOUAS Elyes <ehaouas(a)noos.fr> -- To view, visit https://review.coreboot.org/c/coreboot/+/36706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7d0f7122e461b78526692b78f79edcafafd3286 Gerrit-Change-Number: 36706 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: deleteVote

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Change in coreboot[master]: sc7180: Add QUPv3 FW load & config
by Roja Rani Yarubandi (Code Review) 22 Nov '19

22 Nov '19

Roja Rani Yarubandi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35499 ) Change subject: sc7180: Add QUPv3 FW load & config ...................................................................... Patch Set 16: > Patch Set 16: Code-Review-1 > > (3 comments) Done, shared patch with Mike -- To view, visit https://review.coreboot.org/c/coreboot/+/35499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d91dd10488931247f81a87b0bdcc598f4bceb31 Gerrit-Change-Number: 35499 Gerrit-PatchSet: 16 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Douglas Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-CC: Stephen Boyd <swboyd(a)chromium.org> Gerrit-Comment-Date: Fri, 22 Nov 2019 11:42:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Drop SOC_INTEL_COFFEELAKE symbol
by Arthur Heymans (Code Review) 22 Nov '19

22 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37145 ) Change subject: soc/intel/cannonlake: Drop SOC_INTEL_COFFEELAKE symbol ...................................................................... soc/intel/cannonlake: Drop SOC_INTEL_COFFEELAKE symbol This Kconfig is unused even in the coffeelake_rvp mainboard. Change-Id: I633b0649bcb4874ea0ad28fac5d1525bf146501c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/gma/Kconfig M src/soc/intel/cannonlake/Kconfig 3 files changed, 6 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/37145/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 1fd4b0c..b8fbdaf 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -69,8 +69,7 @@ bool "Use the IntelFSP based binaries" depends on ADD_FSP_BINARIES depends on SOC_INTEL_APOLLOLAKE || SOC_INTEL_SKYLAKE || \ - SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE || \ - SOC_INTEL_WHISKEYLAKE + SOC_INTEL_KABYLAKE || SOC_INTEL_WHISKEYLAKE help When selecting this option, the SoC must set FSP_HEADER_PATH and FSP_FD_PATH correctly so FSP splitting works. diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 2071351..3850f18 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -69,8 +69,7 @@ || NORTHBRIDGE_INTEL_NEHALEM || NORTHBRIDGE_INTEL_SANDYBRIDGE \ || NORTHBRIDGE_INTEL_HASWELL \ || SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || SOC_INTEL_APOLLOLAKE \ - || SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE \ - || SOC_INTEL_WHISKEYLAKE + || SOC_INTEL_KABYLAKE || SOC_INTEL_WHISKEYLAKE depends on MAINBOARD_USE_LIBGFXINIT || INTEL_GMA_LIBGFXINIT_EDID select RAMSTAGE_LIBHWBASE @@ -97,7 +96,7 @@ string default "Broxton" if SOC_INTEL_APOLLOLAKE default "Skylake" if SOC_INTEL_SKYLAKE || SOC_INTEL_KABYLAKE || \ - SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE + SOC_INTEL_WHISKEYLAKE default "Haswell" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL default "Ironlake" if NORTHBRIDGE_INTEL_NEHALEM || NORTHBRIDGE_INTEL_SANDYBRIDGE default "G45" if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 5731cff..64f4718 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -20,12 +20,6 @@ help Intel Cannonlake support -config SOC_INTEL_COFFEELAKE - bool - select SOC_INTEL_CANNONLAKE_BASE - help - Intel Coffeelake support - config SOC_INTEL_WHISKEYLAKE bool select SOC_INTEL_CANNONLAKE_BASE @@ -106,7 +100,7 @@ select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO select FSP_T_XIP if FSP_CAR - select HECI_DISABLE_USING_SMM if !SOC_INTEL_COFFEELAKE && !SOC_INTEL_WHISKEYLAKE && !SOC_INTEL_COMETLAKE + select HECI_DISABLE_USING_SMM if !SOC_INTEL_WHISKEYLAKE && !SOC_INTEL_COMETLAKE config DCACHE_RAM_BASE default 0xfef00000 @@ -304,14 +298,14 @@ config FSP_HEADER_PATH string "Location of FSP headers" - default "3rdparty/fsp/CoffeeLakeFspBinPkg/Include/" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE + default "3rdparty/fsp/CoffeeLakeFspBinPkg/Include/" if SOC_INTEL_WHISKEYLAKE default "src/vendorcode/intel/fsp/fsp2_0/cometlake/" if SOC_INTEL_COMETLAKE default "src/vendorcode/intel/fsp/fsp2_0/cannonlake/" if SOC_INTEL_CANNONLAKE config FSP_FD_PATH string depends on FSP_USE_REPO - default "3rdparty/fsp/CoffeeLakeFspBinPkg/FSP.fd" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE + default "3rdparty/fsp/CoffeeLakeFspBinPkg/FSP.fd" if SOC_INTEL_WHISKEYLAKE config SOC_INTEL_CANNONLAKE_DEBUG_CONSENT int "Debug Consent for CNL" -- To view, visit https://review.coreboot.org/c/coreboot/+/37145 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I633b0649bcb4874ea0ad28fac5d1525bf146501c Gerrit-Change-Number: 37145 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit November 2019