Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36444 )
Change subject: device/Kconfig: hide display menu when NO_GFX_INIT is selected
......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36444/1/src/device/Kconfig
File src/device/Kconfig:
https://review.coreboot.org/c/coreboot/+/36444/1/src/device/Kconfig@a255
PS1, Line 255: depends on HAVE_VGA_TEXT_FRAMEBUFFER || HAVE_LINEAR_FRAMEBUFFER
> But it's the users choice to enable the driver. And if they don't, we […]
I've commented on CB:35726, hope that helps.
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36444 )
Change subject: device/Kconfig: hide display menu when NO_GFX_INIT is selected
......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36444/1/src/device/Kconfig
File src/device/Kconfig:
https://review.coreboot.org/c/coreboot/+/36444/1/src/device/Kconfig@a255
PS1, Line 255: depends on HAVE_VGA_TEXT_FRAMEBUFFER || HAVE_LINEAR_FRAMEBUFFER
> Huh? HAVE_* are selected by the drivers, not by the user
But it's the users choice to enable the driver. And if they don't, we
won't have a framebuffer.
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27369 )
Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT
......................................................................
Patch Set 49:
(1 comment)
https://review.coreboot.org/c/coreboot/+/27369/49//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/27369/49//COMMIT_MSG@52
PS49, Line 52: single MCU
> I believe microcode_blob.bin can be generated by stitching multiple MCUs together. Wouldn't that still work fine?
Since the size of the microcode is not fixed you cannot put more than one version in the update region as FIT has to point to them. having multiple MCU in the microcode_blob.bin cbfs file should still work fine ofc.
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36087 )
Change subject: soc/intel/tigerlake: Do initial SoC commit
......................................................................
Patch Set 8:
> Patch Set 8:
>
> Sorry, but all companies and developers have to go through the process of submitting quality software stated in the coreboot trademark license agreement as well. Be prepared that this code only goes into the tree if the common code stuff is done before.
Already based on existing feedback on this CL we have started cleaning some existing ICL code and move into possible common code
1. https://review.coreboot.org/q/topic:%22ICL_CLEAN_UP_FOR_TGL_UPSTREAM%22+(st…
2. Common report platform code is also going on from Bora/Usha
i'm hoping to do more in common front in coming weeks but i don't think entire common code can be achieved right now before TGL PO timeline what we have in hand. Expected your cooperation to let TGL 1st copy patch to land based on #1 above. If you think we can't land TGL code before complete common code then we will be in trouble.
Will wait to hear from Aaron/Duncan on that note about plan to host the TGL code for PO
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Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36087 )
Change subject: soc/intel/tigerlake: Do initial SoC commit
......................................................................
Patch Set 8:
Sorry, but all companies and developers have to go through the process of submitting quality software stated in the coreboot trademark license agreement as well. Be prepared that this code only goes into the tree if the common code stuff is done before.
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36087 )
Change subject: soc/intel/tigerlake: Do initial SoC commit
......................................................................
Patch Set 8:
> Patch Set 8: Code-Review-2
>
> If there is so much code that is identical. Just move it to the common code base and do a fresh implementation. This also helps to find dead code etc...
yes, indeed, we are looking for common code method but that has to be logical like based on some generation like gen10 based or gen8 based. we are working on that design but that something should be independent of hosting TGL latest code in open source right. Google like to use tgl soc from cb.org and we don't have that much time to complete common code first and then land TGL. A common code effort need good understanding what we are moving into common else it will defeat the purpose.
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35886 )
Change subject: [TESTME]soc/intel/icelake: Properly select PCIEX_LENGTH_64MB
......................................................................
Patch Set 2:
> Patch Set 2:
>
> Arthur,
>
> In ICL and CNL we are having CONFIG_SA_PCIEX_LENGTH=0x10000000 (256MB)
>
> this is as per CNL programming guide we need to set PCIEX to 256MB
Ok thank you, I will fix it.
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