Subrata Banik has uploaded a new patch set (#10) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/36087 )
Change subject: soc/intel/tigerlake: Do initial SoC commit
......................................................................
soc/intel/tigerlake: Do initial SoC commit
Clone entirely from Icelake
TOT commit: 7d9d63b79f331d6a9c613bce03d6e09ef8745bbe
List of changes on top off initial icelake clone
1. Replace "Icelake" with "Tigerlake"
2. Replace "icl" with "tgl"
3. Replace "icp" with "tgp"
4. Rename structure based on Icelake with Tigerlake
5. Remove and clean below files
5.a Clean up upd override in fsp_params.c,
will be added once FSP available.
Tiger Lake specific changes will follow in subsequent patches.
"The External Design Specification (EDS) is not published yet. It comes
from an authoritative internal source.
The patch has been tested on real hardware."
Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com>
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
A src/soc/intel/tigerlake/Kconfig
A src/soc/intel/tigerlake/Makefile.inc
A src/soc/intel/tigerlake/acpi.c
A src/soc/intel/tigerlake/acpi/gpio.asl
A src/soc/intel/tigerlake/acpi/northbridge.asl
A src/soc/intel/tigerlake/acpi/pch_glan.asl
A src/soc/intel/tigerlake/acpi/pch_hda.asl
A src/soc/intel/tigerlake/acpi/pci_irqs.asl
A src/soc/intel/tigerlake/acpi/pcie.asl
A src/soc/intel/tigerlake/acpi/platform.asl
A src/soc/intel/tigerlake/acpi/scs.asl
A src/soc/intel/tigerlake/acpi/serialio.asl
A src/soc/intel/tigerlake/acpi/smbus.asl
A src/soc/intel/tigerlake/acpi/southbridge.asl
A src/soc/intel/tigerlake/acpi/xhci.asl
A src/soc/intel/tigerlake/bootblock/bootblock.c
A src/soc/intel/tigerlake/bootblock/cpu.c
A src/soc/intel/tigerlake/bootblock/pch.c
A src/soc/intel/tigerlake/bootblock/report_platform.c
A src/soc/intel/tigerlake/chip.c
A src/soc/intel/tigerlake/chip.h
A src/soc/intel/tigerlake/cpu.c
A src/soc/intel/tigerlake/elog.c
A src/soc/intel/tigerlake/espi.c
A src/soc/intel/tigerlake/finalize.c
A src/soc/intel/tigerlake/fsp_params.c
A src/soc/intel/tigerlake/gpio.c
A src/soc/intel/tigerlake/graphics.c
A src/soc/intel/tigerlake/gspi.c
A src/soc/intel/tigerlake/i2c.c
A src/soc/intel/tigerlake/include/soc/bootblock.h
A src/soc/intel/tigerlake/include/soc/cpu.h
A src/soc/intel/tigerlake/include/soc/ebda.h
A src/soc/intel/tigerlake/include/soc/espi.h
A src/soc/intel/tigerlake/include/soc/gpe.h
A src/soc/intel/tigerlake/include/soc/gpio.h
A src/soc/intel/tigerlake/include/soc/gpio_defs.h
A src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h
A src/soc/intel/tigerlake/include/soc/iomap.h
A src/soc/intel/tigerlake/include/soc/irq.h
A src/soc/intel/tigerlake/include/soc/itss.h
A src/soc/intel/tigerlake/include/soc/msr.h
A src/soc/intel/tigerlake/include/soc/nvs.h
A src/soc/intel/tigerlake/include/soc/p2sb.h
A src/soc/intel/tigerlake/include/soc/pch.h
A src/soc/intel/tigerlake/include/soc/pci_devs.h
A src/soc/intel/tigerlake/include/soc/pcr_ids.h
A src/soc/intel/tigerlake/include/soc/pm.h
A src/soc/intel/tigerlake/include/soc/pmc.h
A src/soc/intel/tigerlake/include/soc/ramstage.h
A src/soc/intel/tigerlake/include/soc/romstage.h
A src/soc/intel/tigerlake/include/soc/serialio.h
A src/soc/intel/tigerlake/include/soc/smbus.h
A src/soc/intel/tigerlake/include/soc/smm.h
A src/soc/intel/tigerlake/include/soc/soc_chip.h
A src/soc/intel/tigerlake/include/soc/systemagent.h
A src/soc/intel/tigerlake/include/soc/usb.h
A src/soc/intel/tigerlake/lockdown.c
A src/soc/intel/tigerlake/memmap.c
A src/soc/intel/tigerlake/p2sb.c
A src/soc/intel/tigerlake/pmc.c
A src/soc/intel/tigerlake/pmutil.c
A src/soc/intel/tigerlake/reset.c
A src/soc/intel/tigerlake/romstage/Makefile.inc
A src/soc/intel/tigerlake/romstage/fsp_params.c
A src/soc/intel/tigerlake/romstage/romstage.c
A src/soc/intel/tigerlake/romstage/systemagent.c
A src/soc/intel/tigerlake/sd.c
A src/soc/intel/tigerlake/smihandler.c
A src/soc/intel/tigerlake/smmrelocate.c
A src/soc/intel/tigerlake/spi.c
A src/soc/intel/tigerlake/systemagent.c
A src/soc/intel/tigerlake/uart.c
73 files changed, 7,932 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/36087/10
--
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Gerrit-PatchSet: 10
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Gerrit-MessageType: newpatchset
Subrata Banik has uploaded a new patch set (#9) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/36087 )
Change subject: soc/intel/tigerlake: Do initial SoC commit
......................................................................
soc/intel/tigerlake: Do initial SoC commit
Clone entirely from Icelake
TOT commit: 04b5123aed8983bb9002402545f2cc62b9ffd148 when copied.
List of changes on top off initial icelake clone
1. Replace "Icelake" with "Tigerlake"
2. Replace "icl" with "tgl"
3. Replace "icp" with "tgp"
4. Rename structure based on Icelake with Tigerlake
5. Remove and clean below files
5.a Clean up upd override in fsp_params.c,
will be added once FSP available.
Tiger Lake specific changes will follow in subsequent patches.
Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com>
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
A src/soc/intel/tigerlake/Kconfig
A src/soc/intel/tigerlake/Makefile.inc
A src/soc/intel/tigerlake/acpi.c
A src/soc/intel/tigerlake/acpi/gpio.asl
A src/soc/intel/tigerlake/acpi/northbridge.asl
A src/soc/intel/tigerlake/acpi/pch_glan.asl
A src/soc/intel/tigerlake/acpi/pch_hda.asl
A src/soc/intel/tigerlake/acpi/pci_irqs.asl
A src/soc/intel/tigerlake/acpi/pcie.asl
A src/soc/intel/tigerlake/acpi/platform.asl
A src/soc/intel/tigerlake/acpi/scs.asl
A src/soc/intel/tigerlake/acpi/serialio.asl
A src/soc/intel/tigerlake/acpi/smbus.asl
A src/soc/intel/tigerlake/acpi/southbridge.asl
A src/soc/intel/tigerlake/acpi/xhci.asl
A src/soc/intel/tigerlake/bootblock/bootblock.c
A src/soc/intel/tigerlake/bootblock/cpu.c
A src/soc/intel/tigerlake/bootblock/pch.c
A src/soc/intel/tigerlake/bootblock/report_platform.c
A src/soc/intel/tigerlake/chip.c
A src/soc/intel/tigerlake/chip.h
A src/soc/intel/tigerlake/cpu.c
A src/soc/intel/tigerlake/elog.c
A src/soc/intel/tigerlake/espi.c
A src/soc/intel/tigerlake/finalize.c
A src/soc/intel/tigerlake/fsp_params.c
A src/soc/intel/tigerlake/gpio.c
A src/soc/intel/tigerlake/graphics.c
A src/soc/intel/tigerlake/gspi.c
A src/soc/intel/tigerlake/i2c.c
A src/soc/intel/tigerlake/include/soc/bootblock.h
A src/soc/intel/tigerlake/include/soc/cpu.h
A src/soc/intel/tigerlake/include/soc/ebda.h
A src/soc/intel/tigerlake/include/soc/espi.h
A src/soc/intel/tigerlake/include/soc/gpe.h
A src/soc/intel/tigerlake/include/soc/gpio.h
A src/soc/intel/tigerlake/include/soc/gpio_defs.h
A src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h
A src/soc/intel/tigerlake/include/soc/iomap.h
A src/soc/intel/tigerlake/include/soc/irq.h
A src/soc/intel/tigerlake/include/soc/itss.h
A src/soc/intel/tigerlake/include/soc/msr.h
A src/soc/intel/tigerlake/include/soc/nvs.h
A src/soc/intel/tigerlake/include/soc/p2sb.h
A src/soc/intel/tigerlake/include/soc/pch.h
A src/soc/intel/tigerlake/include/soc/pci_devs.h
A src/soc/intel/tigerlake/include/soc/pcr_ids.h
A src/soc/intel/tigerlake/include/soc/pm.h
A src/soc/intel/tigerlake/include/soc/pmc.h
A src/soc/intel/tigerlake/include/soc/ramstage.h
A src/soc/intel/tigerlake/include/soc/romstage.h
A src/soc/intel/tigerlake/include/soc/serialio.h
A src/soc/intel/tigerlake/include/soc/smbus.h
A src/soc/intel/tigerlake/include/soc/smm.h
A src/soc/intel/tigerlake/include/soc/soc_chip.h
A src/soc/intel/tigerlake/include/soc/systemagent.h
A src/soc/intel/tigerlake/include/soc/usb.h
A src/soc/intel/tigerlake/lockdown.c
A src/soc/intel/tigerlake/memmap.c
A src/soc/intel/tigerlake/p2sb.c
A src/soc/intel/tigerlake/pmc.c
A src/soc/intel/tigerlake/pmutil.c
A src/soc/intel/tigerlake/reset.c
A src/soc/intel/tigerlake/romstage/Makefile.inc
A src/soc/intel/tigerlake/romstage/fsp_params.c
A src/soc/intel/tigerlake/romstage/romstage.c
A src/soc/intel/tigerlake/romstage/systemagent.c
A src/soc/intel/tigerlake/sd.c
A src/soc/intel/tigerlake/smihandler.c
A src/soc/intel/tigerlake/smmrelocate.c
A src/soc/intel/tigerlake/spi.c
A src/soc/intel/tigerlake/systemagent.c
A src/soc/intel/tigerlake/uart.c
73 files changed, 7,935 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/36087/9
--
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Gerrit-Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb
Gerrit-Change-Number: 36087
Gerrit-PatchSet: 9
Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
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Gerrit-MessageType: newpatchset
EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36224 )
Change subject: mb/google/drallion: Turn off HDMI power when enter s0ix
......................................................................
mb/google/drallion: Turn off HDMI power when enter s0ix
Turn off HDMI power when enter s0ix.
BUG=b:143057255
BRANCH=N/A
TEST=Measure the power on GPP_E16 under s0ix
Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com>
Change-Id: I580e6094d48663d5c208fd82c7744485d899bcc1
---
M src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl
1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/36224/1
diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl
index 41121d2..544aaa0 100644
--- a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl
+++ b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl
@@ -15,6 +15,7 @@
#define CAM_EN GPP_B11 /* Active low */
#define TS_PD GPP_E7
+#define HDMI_PD GPP_E16
/* Method called from LPIT prior to enter s0ix state */
Method (MS0X, 1)
@@ -22,9 +23,13 @@
If (Arg0) {
/* Turn off camera power */
\_SB.PCI0.STXS (CAM_EN)
+ /* Turn off HDMI power */
+ \_SB.PCI0.CTXS (HDMI_PD)
} Else {
/* Turn on camera power */
\_SB.PCI0.CTXS (CAM_EN)
+ /* Turn on HDMI power */
+ \_SB.PCI0.STXS (HDMI_PD)
}
}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I580e6094d48663d5c208fd82c7744485d899bcc1
Gerrit-Change-Number: 36224
Gerrit-PatchSet: 1
Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com>
Gerrit-MessageType: newchange
Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36376 )
Change subject: mb/asrock/h110m: configure SuperIO Deep Sleep
......................................................................
mb/asrock/h110m: configure SuperIO Deep Sleep
Change-Id: I10766ffda67bdc830ab01436ebd0578c79f1ec70
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
---
M src/mainboard/asrock/h110m/devicetree.cb
1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/36376/1
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb
index 9898d01..4323028 100644
--- a/src/mainboard/asrock/h110m/devicetree.cb
+++ b/src/mainboard/asrock/h110m/devicetree.cb
@@ -415,10 +415,10 @@
device pnp 2e.14 off end # SVID, Port 80 UART
device pnp 2e.16 off end # DS5
device pnp 2e.116 off end # DS3
- device pnp 2e.316 off end # PCHDSW
+ device pnp 2e.316 on end # PCHDSW
device pnp 2e.416 off end # DSWWOPT
- device pnp 2e.516 off end # DS3OPT
- device pnp 2e.616 off end # DSDSS
+ device pnp 2e.516 on end # DS3OPT
+ device pnp 2e.616 on end # DSDSS
device pnp 2e.716 off end # DSPU
end # superio/nuvoton/nct6791d
chip drivers/pc80/tpm
--
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Gerrit-Branch: master
Gerrit-Change-Id: I10766ffda67bdc830ab01436ebd0578c79f1ec70
Gerrit-Change-Number: 36376
Gerrit-PatchSet: 1
Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com>
Gerrit-MessageType: newchange
Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36375 )
Change subject: mb/asrock/h110m: fix gpe0_dw0 option in device tree
......................................................................
mb/asrock/h110m: fix gpe0_dw0 option in device tree
Sets the same value as the vendor’s firmware.
Change-Id: Idd80f6df081d79a158dd56e7e699572554a4ee5e
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
---
M src/mainboard/asrock/h110m/devicetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/36375/1
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb
index acb2a9e..9898d01 100644
--- a/src/mainboard/asrock/h110m/devicetree.cb
+++ b/src/mainboard/asrock/h110m/devicetree.cb
@@ -29,7 +29,7 @@
# Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE
# offset bits also need to be changed.
- register "gpe0_dw0" = "GPP_B"
+ register "gpe0_dw0" = "GPP_C"
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
--
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Gerrit-Change-Number: 36375
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Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com>
Gerrit-MessageType: newchange