Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35886 )
Change subject: [TESTME]soc/intel/icelake: Properly select PCIEX_LENGTH_64MB
......................................................................
Patch Set 2:
Arthur,
In ICL and CNL we are having CONFIG_SA_PCIEX_LENGTH=0x10000000 (256MB)
this is as per CNL programming guide we need to set PCIEX to 256MB
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Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36275 )
Change subject: arch/arm64: Pass cbmem_top to ramstage via calling argument
......................................................................
Patch Set 20:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36275/20/src/arch/arm64/Kconfig
File src/arch/arm64/Kconfig:
https://review.coreboot.org/c/coreboot/+/36275/20/src/arch/arm64/Kconfig@20
PS20, Line 20: select RAMSTAGE_CBMEM_TOP_ARG if !SOC_NVIDIA_TEGRA210
> Yeah, hmm, looks like it is. […]
That seems like a doable approach.
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36242 )
Change subject: util/ifdtool: Add Tigerlake platform support under IFDv2
......................................................................
Patch Set 4:
HI Ravi,
Can you please just rebase this patch alone, i guess we can let this CL merge without any trouble ?
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35878 )
Change subject: soc/intel/broadwell_de: Define and use MMCONF_BUS_NUMBER
......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35878/5/src/soc/intel/fsp_broadwel…
File src/soc/intel/fsp_broadwell_de/acpi.c:
https://review.coreboot.org/c/coreboot/+/35878/5/src/soc/intel/fsp_broadwel…
PS5, Line 150: MCFG_BASE_ADDRESS, 0, 0,
code indent should use tabs where possible
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Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35877
to look at the new patch set (#5).
Change subject: soc/intel: Use common Kconfig symbols for PCIE config space size
......................................................................
soc/intel: Use common Kconfig symbols for PCIE config space size
PCIe mmconf is not INTEL_SA specific, therefore use the common
CONFIG_MMCONF_BUS_NUMBER.
Change-Id: I179e6c4e84664c7a7581e6103cfc079eb5c449f5
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/apollolake/systemagent.c
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/systemagent.c
M src/soc/intel/common/block/acpi/acpi.c
M src/soc/intel/common/block/systemagent/Kconfig
M src/soc/intel/common/block/systemagent/systemagent_early.c
M src/soc/intel/icelake/Kconfig
M src/soc/intel/icelake/systemagent.c
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/acpi.c
M src/soc/intel/skylake/systemagent.c
12 files changed, 32 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/35877/5
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36275 )
Change subject: arch/arm64: Pass cbmem_top to ramstage via calling argument
......................................................................
Patch Set 20:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36275/20/src/arch/arm64/Kconfig
File src/arch/arm64/Kconfig:
https://review.coreboot.org/c/coreboot/+/36275/20/src/arch/arm64/Kconfig@20
PS20, Line 20: select RAMSTAGE_CBMEM_TOP_ARG if !SOC_NVIDIA_TEGRA210
> Is this the only chipset that cannot switch to the new scheme? Otherwise (if we need to have excepti […]
Yeah, hmm, looks like it is.
Another really simple solution would be to just call
_cbmem_top_ptr = cbmem_top_chipset();
near the end of ramstage_entry(). That's not parameter passing, but the platform doesn't really need that to work because its cbmem_top_chipset() works fine in both stages.
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36275 )
Change subject: arch/arm64: Pass cbmem_top to ramstage via calling argument
......................................................................
Patch Set 20: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/36275/20/src/arch/arm64/Kconfig
File src/arch/arm64/Kconfig:
https://review.coreboot.org/c/coreboot/+/36275/20/src/arch/arm64/Kconfig@20
PS20, Line 20: select RAMSTAGE_CBMEM_TOP_ARG if !SOC_NVIDIA_TEGRA210
> > We need a way to pass arguments to this one. Otherwise it'll be a constant sore thumb. […]
Is this the only chipset that cannot switch to the new scheme? Otherwise (if we need to have exceptions anyway), I don't think this is really worth solving.
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36444 )
Change subject: device/Kconfig: hide display menu when NO_GFX_INIT is selected
......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36444/1/src/device/Kconfig
File src/device/Kconfig:
https://review.coreboot.org/c/coreboot/+/36444/1/src/device/Kconfig@a255
PS1, Line 255: depends on HAVE_VGA_TEXT_FRAMEBUFFER || HAVE_LINEAR_FRAMEBUFFER
> These should already imply !NO_GFX_INIT. I guess you could move the […]
Huh? HAVE_* are selected by the drivers, not by the user
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Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36440 )
Change subject: Makefile.inc: Consolidate submodule comments
......................................................................
Makefile.inc: Consolidate submodule comments
Reduce duplicated comments explaining that submodules' settings in
.gitmodules are update=none, and that --checkout is required. This
prepares for another submodule, and makes adding a third set of
comments unnecessary.
Change-Id: I7721333a61122284ed9975ecd2adc3271a879728
Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
---
M Makefile.inc
1 file changed, 2 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/36440/1
diff --git a/Makefile.inc b/Makefile.inc
index f7f3708..79fc256 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -193,13 +193,11 @@
# try to fetch non-optional submodules if the source is under git
forgetthis:=$(if $(GIT),$(shell git submodule update --init))
ifeq ($(CONFIG_USE_BLOBS),y)
-# this is necessary because 3rdparty/{blobs,intel-microcode} is update=none, and so is ignored
-# unless explicitly requested and enabled through --checkout
+# These items are necessary because each has update=none in .gitmodules. They are ignored
+# until expressly requested and enabled with --checkout
forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/blobs))
forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/intel-microcode))
ifeq ($(CONFIG_PLATFORM_USES_FSP1_0)$(CONFIG_PLATFORM_USES_FSP1_1)$(CONFIG_PLATFORM_USES_FSP2_0),y)
-# this is necessary because 3rdparty/fsp is update=none, and so is ignored
-# unless explicitly requested and enabled through --checkout
forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/fsp))
endif
endif
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