coreboot-gerrit October 2019

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Change in coreboot[master]: soc/intel/tigerlake: Do initial SoC commit
by Arthur Heymans (Code Review) 31 Oct '19

31 Oct '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36087 ) Change subject: soc/intel/tigerlake: Do initial SoC commit ...................................................................... Patch Set 10: (17 comments) I appreciate the effort to fix some issues in other intel/soc targets before moving forward with TGL. It might be a bit easier to track changes if this commit was split up in smaller changes. e.g. split ACPI, bootblock, romstage, ramstage callbacks / PCI drivers, ... There is no mainboard target here so for buildtests it's mostly fine to have one mainboard on top of the soc CL. If one smaller change is ready it can get +2 and get merged independently from other changes. Also coreboot is a moving target so if something changes only a smaller CL needs updating on a rebase vs the big all in one change. https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/K… File src/soc/intel/tigerlake/Kconfig: https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/K… PS10, Line 73: FSP_USES_CB_STACK PLATFORM_USES_FSP2_1 indirectly selects this. You might want to drop the dependency. https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/K… PS10, Line 215: ENABLE_DISPLAY_OVER_EXT_PCIE_GFX This seems to (partially) reinvent CONFIG_ONBOARD_VGA_IS_PRIMARY. Could you get rid of it? https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/M… File src/soc/intel/tigerlake/Makefile.inc: https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/M… PS10, Line 1: feq ($(CONFIG_SOC_INTEL_TIGERLAKE),y) There is now an 'all' class to link code in bootblock,verstage,romstage,postcar,ramstage. It could reduce some lines here. https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/b… File src/soc/intel/tigerlake/bootblock/report_platform.c: https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/b… PS10, Line 29: : static struct { : u32 cpuid; : const char *name; : } cpu_table[] = { : { CPUID_ICELAKE_A0, "Icelake A0" }, : { CPUID_ICELAKE_B0, "Icelake B0" }, : }; : : static struct { : u16 mchid; : const char *name; : } mch_table[] = { : { PCI_DEVICE_ID_INTEL_ICL_ID_U, "Icelake-U" }, : { PCI_DEVICE_ID_INTEL_ICL_ID_U_2_2, "Icelake-U-2-2" }, : { PCI_DEVICE_ID_INTEL_ICL_ID_Y, "Icelake-Y" }, : { PCI_DEVICE_ID_INTEL_ICL_ID_Y_2, "Icelake-Y-2" }, : }; : : static struct { : u16 espiid; : const char *name; : } pch_table[] = { : { PCI_DEVICE_ID_INTEL_ICL_BASE_U_ESPI, "Icelake-U Base" }, : { PCI_DEVICE_ID_INTEL_ICL_BASE_Y_ESPI, "Icelake-Y Base" }, : { PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_ESPI, "Icelake-U Premium" }, : { PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI, "Icelake-U Super" }, : { PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI_REV0, "Icelake-U Super REV0" }, : { PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_ESPI, "Icelake-Y Super" }, : { PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_ESPI, "Icelake-Y Premium" }, : }; : : static struct { : u16 igdid; : const char *name; : } igd_table[] = { : { PCI_DEVICE_ID_INTEL_ICL_GT0_ULT, "Icelake ULT GT0" }, : { PCI_DEVICE_ID_INTEL_ICL_GT0_5_ULT, "Icelake ULT GT0.5" }, : { PCI_DEVICE_ID_INTEL_ICL_GT1_ULT, "Icelake U GT1" }, : { PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_0, "Icelake Y GT2" }, : { PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_1, "Icelake Y GT2_1" }, : { PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_1, "Icelake U GT2_1" }, : { PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_2, "Icelake Y GT2_2" }, : { PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_2, "Icelake U GT2_2" }, : { PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_3, "Icelake Y GT2_3" }, : { PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_3, "Icelake U GT2_3" }, : { PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_4, "Icelake Y GT2_4" }, : { PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_4, "Icelake U GT2_4" }, : { PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_5, "Icelake Y GT2_5" }, : { PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_5, "Icelake U GT2_5" }, : { PCI_DEVICE_ID_INTEL_ICL_GT3_ULT, "Icelake U GT3" }, Does this need updating? https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/b… PS10, Line 96: cpu_string[50], This seems to be only changed in the case that cpuidr.eax < 0x80000004. Change this to const char cpu_not_found = "Platform info not available" and update cpu_name accordingly. https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/b… PS10, Line 121: cpu_name[0] == ' ' Check for bounds. https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/f… File src/soc/intel/tigerlake/finalize.c: https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/f… PS10, Line 118: : BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL); : BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL); Any reason to not make this a '.final' op somewhere? The BOOT_STATE_ macro's should not be used too much. https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/f… File src/soc/intel/tigerlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/f… PS10, Line 42: __weak I'd not make this callback weak. You this to fail at compiletime if not implemented in the mainboard. https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/g… File src/soc/intel/tigerlake/graphics.c: https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/g… PS10, Line 53: /* : * GFX PEIM module inside FSP binary is taking care of graphics : * initialization based on INTEL_GMA_ADD_VBT Kconfig : * option and input VBT file. Hence no need to load/execute legacy VGA : * OpROM in order to initialize GFX. : * : * In case of non-FSP solution, SoC need to select VGA_ROM_RUN : * Kconfig to perform GFX initialization through VGA OpRom. : */ : if (CONFIG(INTEL_GMA_ADD_VBT)) : return; This seems like a bad idea to use a Kconfig option to do something that it is not meant for. Please guard this differently. Don't assume that adding VBT automatically means running the GFX PEIM inside FSP. https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/i… File src/soc/intel/tigerlake/include/soc/bootblock.h: https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/i… PS10, Line 18: : #include <intelblocks/systemagent.h> Don't include it here but in the file implementing the callbacks below. https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/i… File src/soc/intel/tigerlake/include/soc/cpu.h: https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/i… PS10, Line 18: : #include <device/device.h> : #include <intelblocks/msr.h> unused here. Include this in the file defining the function. https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/i… PS10, Line 21: : /* Latency times in units of 32768ns */ : #define C_STATE_LATENCY_CONTROL_0_LIMIT 0x9d : #define C_STATE_LATENCY_CONTROL_1_LIMIT 0x9d : #define C_STATE_LATENCY_CONTROL_2_LIMIT 0x9d : #define C_STATE_LATENCY_CONTROL_3_LIMIT 0x9d : #define C_STATE_LATENCY_CONTROL_4_LIMIT 0x9d : #define C_STATE_LATENCY_CONTROL_5_LIMIT 0x9d : : /* Power in units of mW */ : #define C1_POWER 0x3e8 : #define C6_POWER 0x15e : #define C7_POWER 0xc8 : #define C8_POWER 0xc8 : #define C9_POWER 0xc8 : #define C10_POWER 0xc8 : : /* Common Timer Copy (CTC) frequency - 38.4MHz. */ : #define CTC_FREQ 38400000 : : #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ : (((1 << ((base)*5)) * (limit)) / 1000) : #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ : C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ : (IRTL_1024_NS >> 10)) Is this used in multiple files? If not better move this inside the compilation unit defining the function. https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/i… File src/soc/intel/tigerlake/include/soc/ebda.h: https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/i… PS10, Line 21: struct ebda_config { : uint32_t signature; /* 0x00 - EBDA signature */ : uint32_t tolum_base; /* 0x04 - coreboot memory start */ : uint32_t reserved_mem_size; /* 0x08 - chipset reserved memory size */ : }; note: we might get rid of this soon: CB:36362 https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/i… File src/soc/intel/tigerlake/include/soc/espi.h: https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/i… PS10, Line 19: #include <stdint.h> not needed here? https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/i… File src/soc/intel/tigerlake/include/soc/gpio.h: https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/i… PS10, Line 19: #include <soc/gpio_defs.h> : #include <intelblocks/gpio.h> : : #define CROS_GPIO_DEVICE_NAME "INT3455:00" Is this file needed? Can headers be included directly? https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/r… File src/soc/intel/tigerlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/r… PS10, Line 26: __weak Try to avoid __weak functions like that. It is often more valuable for builds to fail than to have something that is necessarily wrong build. https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/s… File src/soc/intel/tigerlake/smmrelocate.c: https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/s… PS10, Line 180: tseg_base You should check here that TSEG_BASE is aligned to TSEG_SIZE. It often causes weird problems if that is not the case. -- To view, visit https://review.coreboot.org/c/coreboot/+/36087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb Gerrit-Change-Number: 36087 Gerrit-PatchSet: 10 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 31 Oct 2019 13:09:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/tsc: Replace TSC_CONSTANT_RATE with UNKNOWN_TSC_RATE
by Kyösti Mälkki (Code Review) 31 Oct '19

31 Oct '19

Hello Patrick Rudolph, Vanny E, Huang Jin, Philipp Deppenwiese, build bot (Jenkins), David Guckian, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/33928 to look at the new patch set (#11). Change subject: cpu/x86/tsc: Replace TSC_CONSTANT_RATE with UNKNOWN_TSC_RATE ...................................................................... cpu/x86/tsc: Replace TSC_CONSTANT_RATE with UNKNOWN_TSC_RATE Implementations with LAPIC_MONOTONIC_TIMER typically will not have tsc_freq_mhz() implemented and default to UNKNOWN_TSC_RATE. Implementations of tsc_freq_mhz() already cache the value in .bss. Change-Id: I1690cb80295d6b006b75ed69edea28899b674b68 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/cpu.c M src/arch/x86/timestamp.c M src/cpu/intel/fsp_model_406dx/Kconfig M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_1067x/Kconfig M src/cpu/intel/model_106cx/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_6ex/Kconfig M src/cpu/intel/model_6fx/Kconfig M src/cpu/intel/socket_mPGA604/Kconfig M src/cpu/qemu-x86/Kconfig M src/cpu/via/nano/Kconfig M src/cpu/x86/Kconfig M src/cpu/x86/tsc/Makefile.inc M src/cpu/x86/tsc/delay_tsc.c M src/drivers/pc80/pc/i8254.c M src/include/cpu/x86/tsc.h M src/soc/amd/picasso/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/fsp_baytrail/Kconfig M src/soc/intel/fsp_broadwell_de/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/quark/Kconfig M src/soc/intel/skylake/Kconfig 30 files changed, 42 insertions(+), 53 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/33928/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/33928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1690cb80295d6b006b75ed69edea28899b674b68 Gerrit-Change-Number: 33928 Gerrit-PatchSet: 11 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/x86/tsc: Replace TSC_CONSTANT_RATE with UNKNOWN_TSC_RATE
by Kyösti Mälkki (Code Review) 31 Oct '19

31 Oct '19

Hello Patrick Rudolph, Vanny E, Huang Jin, Philipp Deppenwiese, build bot (Jenkins), David Guckian, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/33928 to look at the new patch set (#10). Change subject: cpu/x86/tsc: Replace TSC_CONSTANT_RATE with UNKNOWN_TSC_RATE ...................................................................... cpu/x86/tsc: Replace TSC_CONSTANT_RATE with UNKNOWN_TSC_RATE Implementations of tsc_freq_mhz() already cache the value in .bss. Change-Id: I1690cb80295d6b006b75ed69edea28899b674b68 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/cpu.c M src/arch/x86/timestamp.c M src/cpu/intel/fsp_model_406dx/Kconfig M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_1067x/Kconfig M src/cpu/intel/model_106cx/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_6ex/Kconfig M src/cpu/intel/model_6fx/Kconfig M src/cpu/intel/socket_mPGA604/Kconfig M src/cpu/x86/Kconfig M src/cpu/x86/tsc/Makefile.inc M src/cpu/x86/tsc/delay_tsc.c M src/drivers/pc80/pc/i8254.c M src/include/cpu/x86/tsc.h M src/soc/amd/picasso/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/fsp_baytrail/Kconfig M src/soc/intel/fsp_broadwell_de/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/quark/Kconfig M src/soc/intel/skylake/Kconfig 28 files changed, 40 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/33928/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/33928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1690cb80295d6b006b75ed69edea28899b674b68 Gerrit-Change-Number: 33928 Gerrit-PatchSet: 10 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Makefile, Kconfig: Add AMD dependency for amd_blobs repo
by Marshall Dawson (Code Review) 31 Oct '19

31 Oct '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36416 ) Change subject: Makefile, Kconfig: Add AMD dependency for amd_blobs repo ...................................................................... Makefile, Kconfig: Add AMD dependency for amd_blobs repo Add Kconfig options and a target for cloning and updating the amd_blobs repo. Users should only download the repo after implicitely agreeing to AMD's License text. No formal documented agreement is required. Users may opt to clone the repo, as well as select the git reference to use. The default is origin/master although any may be used, e.g. to support a development effort or a git bisect. All makefile targets and dependencies are if'ed with CONFIG_USE_AMD_BLOBS to prevent accidental cloning. Change-Id: I4ae807659db16756453dc3db2c51848291c681b8 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M Makefile.inc M src/Kconfig 2 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/36416/1 diff --git a/Makefile.inc b/Makefile.inc index f7f3708..48f31ff 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -207,6 +207,29 @@ COREBOOT_EXPORTS += UPDATED_SUBMODULES endif +#ifeq ($(CONFIG_USE_AMD_BLOBS),y) +amd_blobs_name=amd_blobs +amd_blobs_dir=3rdparty/$(amd_blobs_name) +amd_blobs_repo=https://review.coreboot.org/amd_blobs.git + +$(amd_blobs_dir): + $(warning start cd now for clone $(amd_blobs_dir)) + @echo " Cloning $(amd_blobs_name) from Git" + @git clone $(amd_blobs_repo) $(amd_blobs_dir) + +use_amd_blobs: $(amd_blobs_dir) + # if origin/master, always fetch, else fetch only if commit isn't present + if [ "$(CONFIG_AMDBLOBS_REVISION)" = "origin/master" ]; then \ + echo " Fetching new commits from the $(amd_blobs_name) Git repo"; \ + git -C $(amd_blobs_dir) fetch 2>/dev/null; \ + else \ + git -C $(amd_blobs_dir) cat-file -e $(CONFIG_AMDBLOBS_REVISION) || \ + git -C $(amd_blobs_dir) fetch 2>/dev/null; fi + @git -C $(amd_blobs_dir) checkout $(CONFIG_AMDBLOBS_REVISION) 2>/dev/null; + +PHONY+=use_amd_blobs +#endif + postcar-c-deps:=$$(OPTION_TABLE_H) ramstage-c-deps:=$$(OPTION_TABLE_H) romstage-c-deps:=$$(OPTION_TABLE_H) diff --git a/src/Kconfig b/src/Kconfig index 4c71f28..18d35b3 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -235,6 +235,26 @@ might be required for some chipsets or boards. This flag ensures that a "Free" option remains available for users. +config USE_AMD_BLOBS + bool "Allow AMD blobs repository (with license agreement)" + help + This draws in the amd_blobs repository, which contains binary files + distributed by AMD, including VBIOS, PSP bootloaders, SMU firmwares, + etc. Selecting this item to download or clone the repo implies your + agreement to the AMD license agreement. A copy of the license text + may be reviewed by reading Documentation/soc/amd/amdblobs_license.md, + and your copy of the license is present in the repo once downloaded. + + Note that for some products, omitting PSP, SMU images, or other items + may result in a nonbooting coreboot.rom. + +config AMDBLOBS_REVISION + string "AMD blobs repo Git reference" + depends on USE_AMD_BLOBS + default "origin/master" + help + The specific commit's SHA-1 or branch name to use. + config COVERAGE bool "Code coverage support" depends on COMPILER_GCC -- To view, visit https://review.coreboot.org/c/coreboot/+/36416 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ae807659db16756453dc3db2c51848291c681b8 Gerrit-Change-Number: 36416 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: submodules: Add 3rdparty/amd_blobs
by Marshall Dawson (Code Review) 31 Oct '19

31 Oct '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36441 ) Change subject: submodules: Add 3rdparty/amd_blobs ...................................................................... submodules: Add 3rdparty/amd_blobs This is currently an empty repo. The intention for amd_blobs may be found in Documentation/soc/amd/amdblobs_license.md. A subsequent patch will make the repo's init and checkout optional based on a Kconfig symbol. Change-Id: Ia93fb2711beaea4cb1c8e5d71dc3a9e0facc5485 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M .gitmodules A 3rdparty/amd_blobs 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/36441/1 diff --git a/.gitmodules b/.gitmodules index deb3cf0..d90d29b 100644 --- a/.gitmodules +++ b/.gitmodules @@ -37,3 +37,8 @@ [submodule "3rdparty/ffs"] path = 3rdparty/ffs url = ../ffs.git +[submodule "3rdparty/amd_blobs"] + path = 3rdparty/amd_blobs + url = https://review.coreboot.org/amd_blobs + update = none + ignore = dirty diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs new file mode 160000 index 0000000..cf22731 --- /dev/null +++ b/3rdparty/amd_blobs @@ -0,0 +1 @@ +Subproject commit cf227316b0fbd3995854ce21e81a63270b29bfb5 -- To view, visit https://review.coreboot.org/c/coreboot/+/36441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia93fb2711beaea4cb1c8e5d71dc3a9e0facc5485 Gerrit-Change-Number: 36441 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Do initial SoC commit
by Nico Huber (Code Review) 31 Oct '19

31 Oct '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36087 ) Change subject: soc/intel/tigerlake: Do initial SoC commit ...................................................................... Patch Set 9: > Sorry, but all companies and developers have to go through the process of submitting quality software stated in the coreboot trademark license agreement as well. Be prepared that this code only goes into the tree if the common code stuff is done before. I have to side with Intel on the matter of common code. While I totally agree that we shouldn't duplicate too much code, we never made maximizing common code a requirement for new platforms. And it seems harsh to arbitrarily add that requirement when people feel time pressure. That doesn't mean we shouldn't review the Tiger Lake addition. And I think we all agreed already that a 8k LOC patch isn't reviewable. And of course, if we had more common code already, it would be much easier... and we would have a better code base if 3ee54bb hadn't slipped in. Let's not repeat that error. -- To view, visit https://review.coreboot.org/c/coreboot/+/36087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb Gerrit-Change-Number: 36087 Gerrit-PatchSet: 9 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 31 Oct 2019 11:48:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Do initial SoC commit
by Patrick Rudolph (Code Review) 31 Oct '19

31 Oct '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36087 ) Change subject: soc/intel/tigerlake: Do initial SoC commit ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/lo… File src/soc/intel/tigerlake/lockdown.c: https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/lo… PS8, Line 20: > > which datasheet(s) was/were consultated to create this? […] You can still reference the document number and chapter, even if it's not published yet. Applies to all files and functions. -- To view, visit https://review.coreboot.org/c/coreboot/+/36087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb Gerrit-Change-Number: 36087 Gerrit-PatchSet: 10 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 31 Oct 2019 11:48:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: device/Kconfig: hide display menu when NO_GFX_INIT is selected
by Michael Niewöhner (Code Review) 31 Oct '19

31 Oct '19

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36444 ) Change subject: device/Kconfig: hide display menu when NO_GFX_INIT is selected ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/36444/1/src/device/Kconfig File src/device/Kconfig: https://review.coreboot.org/c/coreboot/+/36444/1/src/device/Kconfig@a255 PS1, Line 255: depends on HAVE_VGA_TEXT_FRAMEBUFFER || HAVE_LINEAR_FRAMEBUFFER > I've commented on CB:35726, hope that helps. hmm, I am not sure if that's correct. HAVE_VGA_TEXT_FRAMEBUFFER can be selected for AST2400 graphics for example; that would not be possible when HAVE_VGA_TEXT_FRAMEBUFFER depends on !NO_GFX_INIT -- To view, visit https://review.coreboot.org/c/coreboot/+/36444 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec5a47f84b8c776a45edc6f4b31a03b9ac714b4e Gerrit-Change-Number: 36444 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 31 Oct 2019 11:47:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Do initial SoC commit
by build bot (Jenkins) (Code Review) 31 Oct '19

31 Oct '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36087 ) Change subject: soc/intel/tigerlake: Do initial SoC commit ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/i… File src/soc/intel/tigerlake/include/soc/romstage.h: https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/i… PS10, Line 21: void mainboard_memory_init_params(FSPM_UPD *mupd); need consistent spacing around '*' (ctx:WxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/36087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb Gerrit-Change-Number: 36087 Gerrit-PatchSet: 10 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 31 Oct 2019 11:35:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Do initial SoC commit
by Subrata Banik (Code Review) 31 Oct '19

31 Oct '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36087 ) Change subject: soc/intel/tigerlake: Do initial SoC commit ...................................................................... Patch Set 10: I have re based TGL code based on ICL clean up and common code that we have based as baseline. Kindly help to review this TGL copy patch. Can we make this copy CL land to host TGL code ? -- To view, visit https://review.coreboot.org/c/coreboot/+/36087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb Gerrit-Change-Number: 36087 Gerrit-PatchSet: 10 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 31 Oct 2019 11:35:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2019