Sathyanarayana Nujella has uploaded this change for review. ( https://review.coreboot.org/27167
Change subject: mb/google/poppy/variants/nocturne: Update Slave Addresses of Max98373 Amp's
......................................................................
mb/google/poppy/variants/nocturne: Update Slave Addresses of Max98373 Amp's
When played Left Only Audio and Right Only Audio, we observed that Audio
got swapped. Left Data played on Right Speaker and Viceversa.
This patch fixes the above issue.
BUG=b:73635449
TEST=Play Left only & Right only Audio and cross check Audio.
Change-Id: Ie9c417ad0634a76fc8a4126ee75886603f1b3da0
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com>
---
M src/mainboard/google/poppy/variants/nocturne/devicetree.cb
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/27167/1
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index f746c08..36dc18e6 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -316,7 +316,7 @@
register "uid" = "0"
register "desc" = ""RIGHT SPEAKER AMP""
register "name" = ""MAXR""
- device i2c 31 on end
+ device i2c 32 on end
end
chip drivers/i2c/max98373
register "vmon_slot_no" = "6"
@@ -324,7 +324,7 @@
register "uid" = "1"
register "desc" = ""LEFT SPEAKER AMP""
register "name" = ""MAXL""
- device i2c 32 on end
+ device i2c 31 on end
end
end # I2C #4 - Audio
device pci 1c.0 on
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ie9c417ad0634a76fc8a4126ee75886603f1b3da0
Gerrit-Change-Number: 27167
Gerrit-PatchSet: 1
Gerrit-Owner: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com>
Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/23071 )
Change subject: payloads: Add LinuxBoot payload in u-root mode
......................................................................
payloads: Add LinuxBoot payload in u-root mode
* Add LinuxBoot support
* Add u-root mode
* Download kernel and u-root from upstream sources.
* Add customization options
* Clean kernel only if directory exists
Change-Id: I3a25ff6812e046acc688cbbb203cf262ad751659
Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org>
Reviewed-on: https://review.coreboot.org/23071
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M payloads/Kconfig
M payloads/Makefile.inc
A payloads/external/LinuxBoot/Kconfig
A payloads/external/LinuxBoot/Kconfig.name
A payloads/external/LinuxBoot/Makefile
A payloads/external/LinuxBoot/targets/u-root.mk
M payloads/external/Makefile.inc
M util/abuild/abuild
8 files changed, 319 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Ronald G. Minnich: Looks good to me, approved
diff --git a/payloads/Kconfig b/payloads/Kconfig
index 782f3e0..6b10a0d 100644
--- a/payloads/Kconfig
+++ b/payloads/Kconfig
@@ -64,7 +64,7 @@
choice
prompt "Payload compression algorithm"
default COMPRESSED_PAYLOAD_LZMA
- depends on !PAYLOAD_NONE && !PAYLOAD_LINUX
+ depends on !PAYLOAD_NONE && !PAYLOAD_LINUX && !PAYLOAD_LINUXBOOT
help
Choose the compression algorithm for the chosen payloads.
You can choose between LZMA and LZ4.
diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc
index d894dec..0d142d6 100644
--- a/payloads/Makefile.inc
+++ b/payloads/Makefile.inc
@@ -35,6 +35,7 @@
payloads/external/tint \
payloads/external/tianocore \
payloads/external/GRUB2 \
+payloads/external/LinuxBoot \
payloads/coreinfo/build/coreinfo.elf coreinfo:
$(MAKE) -C payloads/coreinfo defaultbuild
diff --git a/payloads/external/LinuxBoot/Kconfig b/payloads/external/LinuxBoot/Kconfig
new file mode 100644
index 0000000..74e6c94
--- /dev/null
+++ b/payloads/external/LinuxBoot/Kconfig
@@ -0,0 +1,113 @@
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2017 Facebook Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+if PAYLOAD_LINUXBOOT
+
+choice
+ prompt "Architecture"
+ default LINUXBOOT_X86_64
+
+config LINUXBOOT_X86_64
+ bool "x86_64"
+ help
+ AMD64 kernel and initramfs
+
+config LINUXBOOT_X86
+ bool "x86"
+ help
+ X86 kernel and initramfs
+endchoice
+
+config LINUXBOOT_ARCH
+ string
+ default "amd64" if LINUXBOOT_X86_64
+ default "386" if LINUXBOOT_X86
+
+choice
+ prompt "Kernel version"
+ default LINUXBOOT_KERNEL_STABLE
+
+config LINUXBOOT_KERNEL_STABLE
+ bool "4.15.3"
+ help
+ Stable kernel version
+endchoice
+
+config LINUXBOOT_KERNEL_VERSION
+ string
+ default "4.15.3" if LINUXBOOT_KERNEL_STABLE
+
+config LINUXBOOT_KERNEL_CONFIGFILE
+ string "Kernel config file"
+ default ""
+ help
+ Add your own kernel configuration file. Otherwise a default
+ minimal defconfig is used.
+
+config LINUXBOOT_KERNEL_COMMANDLINE
+ string "Kernel command-line"
+ default ""
+ help
+ Add your own kernel command-line arguments.
+
+config PAYLOAD_FILE
+ default "payloads/external/LinuxBoot/linuxboot/kernel-image"
+
+choice
+ prompt "Payload Mode"
+ default LINUXBOOT_UROOT
+
+config LINUXBOOT_UROOT
+ bool "u-root"
+ help
+ Enable u-root linuxboot mode.
+ See http://u-root.tk/ for more information.
+endchoice
+
+if LINUXBOOT_UROOT
+
+choice
+ prompt "U-root version"
+ default LINUXBOOT_UROOT_MASTER
+
+config LINUXBOOT_UROOT_MASTER
+ bool "master"
+ help
+ Latest u-root version
+endchoice
+
+config LINUXBOOT_UROOT_VERSION
+ string
+ default "master" if LINUXBOOT_UROOT_MASTER
+
+config LINUXBOOT_UROOT_COMMANDS
+ string "Select u-root commands"
+ default ""
+ help
+ Comma separated list of additional modules to include. Otherwise all modules
+ of u-root are included.
+
+config LINUXBOOT_UROOT_FILES
+ string "Add files to u-root base"
+ default ""
+ help
+ Path to directory containing root structure for embedding into the
+ initramfs.
+
+config PAYLOAD_USERSPACE
+ string ""
+ default "payloads/external/LinuxBoot/linuxboot/initramfs.cpio.xz"
+
+endif
+endif
diff --git a/payloads/external/LinuxBoot/Kconfig.name b/payloads/external/LinuxBoot/Kconfig.name
new file mode 100644
index 0000000..b7b1085
--- /dev/null
+++ b/payloads/external/LinuxBoot/Kconfig.name
@@ -0,0 +1,23 @@
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2017 Facebook Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config PAYLOAD_LINUXBOOT
+ bool "LinuxBoot"
+ depends on ARCH_X86
+ help
+ Select this option if you want to build a coreboot image
+ with a LinuxBoot payload. If you don't know what this is
+ about, just leave it enabled.
+
+ See https://coreboot.org/Payloads for more information.
diff --git a/payloads/external/LinuxBoot/Makefile b/payloads/external/LinuxBoot/Makefile
new file mode 100644
index 0000000..10ad0c3
--- /dev/null
+++ b/payloads/external/LinuxBoot/Makefile
@@ -0,0 +1,63 @@
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2017 Facebook Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+kernel_tarball=https://cdn.kernel.org/pub/linux/kernel/v4.x/linux-$(CONFIG_LINUXBOOT_KERNEL_VERSION).tar.xz
+project_dir=linuxboot
+kernel_dir=$(project_dir)/kernel
+
+unexport $(COREBOOT_EXPORTS)
+
+all: payload
+
+$(kernel_dir)/.config:
+ echo " WWW Download Linux $(CONFIG_LINUXBOOT_KERNEL_VERSION)"
+ mkdir -p $(kernel_dir)
+ifeq ("$(wildcard $(kernel_dir)/README)","")
+ wget -qO- $(kernel_tarball) | tar xJ -C $(kernel_dir) --strip 1
+endif
+
+config: $(kernel_dir)/.config
+ echo " CONFIG Linux $(CONFIG_LINUXBOOT_KERNEL_VERSION)"
+ifneq ($(CONFIG_LINUXBOOT_KERNEL_CONFIGFILE),)
+ cp $(CONFIG_LINUXBOOT_KERNEL_CONFIGFILE) $(kernel_dir)/.config
+endif
+ifeq ($(CONFIG_LINUXBOOT_ARCH),386)
+ cp x86/defconfig $(kernel_dir)/.config
+else ifeq ($(CONFIG_LINUXBOOT_ARCH),amd64)
+ cp x86_64/defconfig $(kernel_dir)/.config
+endif
+
+$(project_dir)/kernel-image: config
+ echo " MAKE Kernel $(CONFIG_LINUXBOOT_KERNEL_VERSION)"
+ $(MAKE) -C $(kernel_dir) olddefconfig
+ $(MAKE) -C $(kernel_dir) -j $(CPUS)
+ifeq ($(CONFIG_LINUXBOOT_ARCH),386)
+ cp $(kernel_dir)/arch/x86/boot/bzImage $(project_dir)/kernel-image
+else ifeq ($(CONFIG_LINUXBOOT_ARCH),amd64)
+ cp $(kernel_dir)/arch/x86/boot/bzImage $(project_dir)/kernel-image
+endif
+
+payload: $(project_dir)/kernel-image
+ifeq ($(CONFIG_LINUXBOOT_UROOT),y)
+ $(MAKE) -f targets/u-root.mk
+endif
+
+clean:
+ if [ -d "$(kernel_dir)" ]; then make -C $(kernel_dir) clean; fi
+ rm -f $(project_dir)/initramfs.cpio.xz
+
+distclean:
+ rm -rf $(project_dir)
+
+.PHONY: config patch payload clean distclean clone fetch all
diff --git a/payloads/external/LinuxBoot/targets/u-root.mk b/payloads/external/LinuxBoot/targets/u-root.mk
new file mode 100644
index 0000000..9b0e568
--- /dev/null
+++ b/payloads/external/LinuxBoot/targets/u-root.mk
@@ -0,0 +1,80 @@
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2017 Facebook Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+uroot_git_repo=https://github.com/u-root/u-root.git
+uroot_dir=$(project_dir)/go/src/github.com/u-root/u-root
+go_check=$(shell command -v go 1>/dev/null 2>&1 && echo go)
+project_dir=$(shell pwd)/linuxboot
+project_name=u-root
+go_path_dir=$(shell pwd)/linuxboot/go
+
+all: build
+
+check:
+ifneq ($(go_check),go)
+ printf "\n<<Please install Golang >= 1.9 for u-root mode>>\n\n"
+ exit 1
+endif
+ mkdir -p $(project_dir)/go/src/github.com/u-root
+
+$(uroot_dir)/.git:
+ echo " Git Cloning u-root $(CONFIG_LINUXBOOT_UROOT_VERSION)"
+ git clone $(uroot_git_repo) $(uroot_dir)
+
+fetch: check $(uroot_dir)/.git
+ -cd "$(uroot_dir)" && git fetch origin
+
+checkout: fetch
+ cd "$(uroot_dir)" && \
+ if ! git diff --quiet _cb_checkout "$(CONFIG_LINUXBOOT_UROOT_VERSION)" -- 2>/dev/null; \
+ then \
+ printf " CHECKOUT $(project_name) [$(CONFIG_LINUXBOOT_UROOT_VERSION)]\n"; \
+ git checkout $$(git rev-parse HEAD) >/dev/null 2>&1; \
+ git branch -f _cb_checkout "$(CONFIG_LINUXBOOT_UROOT_VERSION)" && \
+ git checkout _cb_checkout && \
+ $(if $(project_patches), \
+ for patch in $(project_patches); do \
+ printf " PATCH $$patch\n"; \
+ git am --keep-cr "$$patch" || \
+ ( printf "Error when applying patches.\n"; \
+ git am --abort; exit 1; ); \
+ done;,true;) \
+ fi
+
+$(project_dir)/initramfs.cpio.xz: checkout
+ cd $(uroot_dir); GOARCH=$(CONFIG_LINUXBOOT_ARCH) GOPATH=$(go_path_dir) go build u-root.go
+ echo " MAKE u-root $(CONFIG_LINUXBOOT_UROOT_VERSION)"
+ifneq ($(CONFIG_LINUXBOOT_UROOT_COMMANDS),)
+ifneq ($(CONFIG_LINUXBOOT_UROOT_FILES),)
+ cd $(uroot_dir); GOARCH=$(CONFIG_LINUXBOOT_ARCH) GOPATH=$(go_path_dir) ./u-root \
+ -build=bb -files $(CONFIG_LINUXBOOT_UROOT_FILES) -o $(project_dir)/initramfs.cpio \
+ ./cmds/{$(CONFIG_LINUXBOOT_UROOT_COMMANDS)}
+else
+ cd $(uroot_dir); GOARCH=$(CONFIG_LINUXBOOT_ARCH) GOPATH=$(go_path_dir) ./u-root \
+ -build=bb -o $(project_dir)/initramfs.cpio ./cmds/{$(CONFIG_LINUXBOOT_UROOT_COMMANDS)}
+endif
+else
+ifneq ($(CONFIG_LINUXBOOT_UROOT_FILES),)
+ cd $(uroot_dir); GOARCH=$(CONFIG_LINUXBOOT_ARCH) GOPATH=$(go_path_dir) ./u-root \
+ -build=bb -files $(CONFIG_LINUXBOOT_UROOT_FILES) -o $(project_dir)/initramfs.cpio
+else
+ cd $(uroot_dir); GOARCH=$(CONFIG_LINUXBOOT_ARCH) GOPATH=$(go_path_dir) ./u-root \
+ -build=bb -o $(project_dir)/initramfs.cpio
+endif
+endif
+ xz -f --check=crc32 -9 --lzma2=dict=1MiB --threads=$(CPUS) $(project_dir)/initramfs.cpio
+
+build: $(project_dir)/initramfs.cpio.xz
+
+.PHONY: build checkout fetch all check
diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc
index ec7d9a8..3943db9 100644
--- a/payloads/external/Makefile.inc
+++ b/payloads/external/Makefile.inc
@@ -4,6 +4,7 @@
##
## Copyright (C) 2009-2010 coresystems GmbH
## Copyright (C) 2015 Google Inc.
+## Copyright (C) 2017 Facebook Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
@@ -31,6 +32,13 @@
#TODO: Figure out version
endif
+ifeq ($(CONFIG_PAYLOAD_LINUXBOOT),y)
+ifneq ($(strip $(call strip_quotes,$(CONFIG_LINUXBOOT_KERNEL_COMMANDLINE))),)
+ ADDITIONAL_PAYLOAD_CONFIG+=-C $(CONFIG_LINUXBOOT_KERNEL_COMMANDLINE)
+endif
+ADDITIONAL_PAYLOAD_CONFIG+=-I $(CONFIG_PAYLOAD_USERSPACE)
+endif
+
ifeq ($(CONFIG_PAYLOAD_LINUX),y)
ifneq ($(strip $(call strip_quotes,$(CONFIG_LINUX_COMMAND_LINE))),)
ADDITIONAL_PAYLOAD_CONFIG+=-C $(CONFIG_LINUX_COMMAND_LINE)
@@ -240,3 +248,32 @@
IPXE_UART=$(IPXE_UART) \
CONFIG_TTYS0_BAUD=$(CONFIG_TTYS0_BAUD) \
MFLAGS= MAKEFLAGS=
+
+# LinuxBoot
+
+linuxboot:
+ $(MAKE) -C payloads/external/LinuxBoot \
+ HOSTCC="$(HOSTCC)" \
+ CC="$(HOSTCC)" \
+ GCC_CC_x86_32=$(GCC_CC_x86_32) \
+ GCC_CC_x86_64=$(GCC_CC_x86_64) \
+ GCC_CC_arm=$(GCC_CC_arm) \
+ GCC_CC_arm64=$(GCC_CC_arm64) \
+ OBJCOPY_x86_32=$(OBJCOPY_x86_32) \
+ OBJCOPY_x86_64=$(OBJCOPY_x86_64) \
+ OBJCOPY_arm=$(OBJCOPY_arm) \
+ OBJCOPY_arm64=$(OBJCOPY_arm64) \
+ CPUS=$(CPUS) \
+ CONFIG_LINUXBOOT_KERNEL_VERSION=$(CONFIG_LINUXBOOT_KERNEL_VERSION) \
+ CONFIG_LINUXBOOT_KERNEL_CONFIGFILE=$(CONFIG_LINUXBOOT_KERNEL_CONFIGFILE) \
+ CONFIG_LINUXBOOT_KERNEL_COMMANDLINE=$(CONFIG_LINUXBOOT_KERNEL_COMMANDLINE) \
+ CONFIG_LINUXBOOT_UROOT_VERSION=$(CONFIG_LINUXBOOT_UROOT_VERSION) \
+ CONFIG_LINUXBOOT_UROOT_COMMANDS="$(CONFIG_LINUXBOOT_UROOT_COMMANDS)" \
+ CONFIG_LINUXBOOT_ARCH=$(CONFIG_LINUXBOOT_ARCH) \
+ CONFIG_LINUXBOOT_UROOT=$(CONFIG_LINUXBOOT_UROOT) \
+ CONFIG_LINUXBOOT_UROOT_FILES=$(CONFIG_LINUXBOOT_UROOT_FILES)
+
+payloads/external/LinuxBoot/linuxboot/kernel-image: linuxboot
+payloads/external/LinuxBoot/linuxboot/initramfs.cpio.xz: linuxboot
+payloads/external/LinuxBoot/linuxboot/kernel/.config: linuxboot
+payloads/external/LinuxBoot/linuxboot/go/src/github.com/u-root/u-root/.git: linuxboot
diff --git a/util/abuild/abuild b/util/abuild/abuild
index d8f4882..50ac8c7 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -267,6 +267,7 @@
echo "# CONFIG_PAYLOAD_GRUB2 is not set"
echo "# CONFIG_PAYLOAD_OPENBIOS is not set"
echo "# CONFIG_PAYLOAD_DEPTHCHARGE is not set"
+ echo "# CONFIG_PAYLOAD_LINUXBOOT is not set"
echo "# CONFIG_PAYLOAD_UBOOT is not set"
echo "# CONFIG_PAYLOAD_TIANOCORE is not set"
echo "# CONFIG_PXE is not set"
--
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Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/23071 )
Change subject: payloads: Add LinuxBoot payload in u-root mode
......................................................................
Patch Set 29:
After some ages let's get it merged. Any improvements can be done in follow ups
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Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/23071 )
Change subject: payloads: Add LinuxBoot payload in u-root mode
......................................................................
Patch Set 29: -Code-Review
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Change subject: payloads: Add LinuxBoot payload in u-root mode
......................................................................
Patch Set 29: Code-Review+2
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Change subject: payloads: Add LinuxBoot payload in u-root mode
......................................................................
Patch Set 29: Verified+1
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Change subject: payloads: Add LinuxBoot payload in u-root mode
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Change subject: lib: Add FIT payload support
......................................................................
Patch Set 36: Code-Review+2
Looks good to me. Julius already approved with +2
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Change subject: Documentation: Add cavium SoC and mainboard
......................................................................
Documentation: Add cavium SoC and mainboard
* Add documentation for CN81XX SoC
* Add documentation for CN81XX EVB SFF mainboard
* Add documentation for BDK
* Add documentation for BOOTROM and BOOTBLOCK behaviour
* Alphabetically sort vendors
Change-Id: Ibfcd42788e31f684baed658dc3c4dfe1b8e4f354
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Reviewed-on: https://review.coreboot.org/27150
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: David Hendricks <david.hendricks(a)gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
---
M Documentation/index.md
A Documentation/mainboard/cavium/cavium_cn81xx_sff_evb.jpg
A Documentation/mainboard/cavium/cn8100_sff_evb.md
M Documentation/mainboard/index.md
A Documentation/soc/cavium/bootflow.md
A Documentation/soc/cavium/cavium_bootflow.png
A Documentation/soc/cavium/cn81xx/index.md
A Documentation/soc/cavium/index.md
M Documentation/soc/index.md
A Documentation/vendorcode/cavium/bdk.md
A Documentation/vendorcode/cavium/index.md
A Documentation/vendorcode/index.md
12 files changed, 275 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
David Hendricks: Looks good to me, approved
Philipp Deppenwiese: Looks good to me, approved
diff --git a/Documentation/index.md b/Documentation/index.md
index 4ec4550..cf22dca 100644
--- a/Documentation/index.md
+++ b/Documentation/index.md
@@ -18,4 +18,5 @@
* [System on Chip-specific documentation](soc/index.md)
* [Mainboard-specific documentation](mainboard/index.md)
* [SuperIO-specific documentation](superio/index.md)
+* [Vendorcode-specific documentation](vendorcode/index.md)
* [Release notes for past releases](releases/index.md)
diff --git a/Documentation/mainboard/cavium/cavium_cn81xx_sff_evb.jpg b/Documentation/mainboard/cavium/cavium_cn81xx_sff_evb.jpg
new file mode 100644
index 0000000..0afe778
--- /dev/null
+++ b/Documentation/mainboard/cavium/cavium_cn81xx_sff_evb.jpg
Binary files differ
diff --git a/Documentation/mainboard/cavium/cn8100_sff_evb.md b/Documentation/mainboard/cavium/cn8100_sff_evb.md
new file mode 100644
index 0000000..b16a8ae
--- /dev/null
+++ b/Documentation/mainboard/cavium/cn8100_sff_evb.md
@@ -0,0 +1,76 @@
+# CN81xx Evaluation-board SFF
+
+## Specs
+
+* 3 mini PCIe slots
+* 4 SATA ports
+* one USB3.0 A connector
+* 20Pin JTAG
+* 4 Gigabit Ethernet
+* 2 SFP+ connectors
+* PCIe x4 slot
+* UART over USB
+* eMMC Flash or MicroSD card slot for on-board storage
+* 1 Slot with DDR-4 memory with ECC support
+* SPI flash
+* MMC and uSD-card
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+----------------+
+| Type | Value |
++=====================+================+
+| Socketed flash | no |
++---------------------+----------------+
+| Model | Micron 25Q128A |
++---------------------+----------------+
+| Size | 8 MiB |
++---------------------+----------------+
+| In circuit flashing | no |
++---------------------+----------------+
+| Package | SOIC-8 |
++---------------------+----------------+
+| Write protection | No |
++---------------------+----------------+
+| Dual BIOS feature | No |
++---------------------+----------------+
+| Internal flashing | ? |
++---------------------+----------------+
+```
+
+## Notes about the hardware
+
+1. Cavium connected *GPIO10* to a global reset line.
+ It's unclear which chips are connected, but at least the PHY and SATA chips
+ are connected.
+
+2. The 4 QLMs can be configured using DIP switches (SW1). That means only a
+ subset of of the available connectors is working at time.
+
+3. The boot source can be configure using DIP switches (SW1).
+
+4. The core and system clock frequency can be configured using DIP switches
+ (SW3 / SW2).
+
+5. The JTAG follows Cavium's own protocol. Support for it is missing in
+ OpenOCD. You have to use ARMs official hardware and software.
+
+## Technology
+
+```eval_rst
++---------------+----------------------------------------+
+| SoC | :doc:`../../soc/cavium/cn81xx/index` |
++---------------+----------------------------------------+
+| CPU | Cavium ARMv8-Quadcore `CN81XX`_ |
++---------------+----------------------------------------+
+
+.. _CN81XX: https://www.cavium.com/product-octeon-tx-cn80xx-81xx.html
+
+```
+
+## Picture
+
+![][cn81xx_board]
+
+[cn81xx_board]: cavium_cn81xx_sff_evb.jpg
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index 23e1ed2..198211d 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -2,10 +2,14 @@
This section contains documentation about coreboot on specific mainboards.
-## SiFive
+## Cavium
-- [SiFive HiFive Unleashed](sifive/hifive-unleashed.md)
+- [CN81XX EVB SFF](cavium/cn8100_sff_evb.md)
## HP
- [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md)
+
+## SiFive
+
+- [SiFive HiFive Unleashed](sifive/hifive-unleashed.md)
diff --git a/Documentation/soc/cavium/bootflow.md b/Documentation/soc/cavium/bootflow.md
new file mode 100644
index 0000000..70bf865
--- /dev/null
+++ b/Documentation/soc/cavium/bootflow.md
@@ -0,0 +1,19 @@
+# Cavium bootflow
+
+The on-chip **BOOTROM** first sets up the L2 cache and the SPI controller.
+It then reads **CSIB_NBL1FW** and **CLIB_NBL1FW** configuration data to get
+the position of the bootstage in flash. It then loads 192KiB from flash into
+L2 cache to a fixed address. The boot mode is called "Non-Secure-Boot" as
+the signature of the bootstage isn't verified.
+The **BOOTROM** can do AES decryption for obfuscation or verify the signature
+of the bootstage. Both features aren't used and won't be described any further.
+
+* The typical position of bootstage in flash is at address **0x20000**.
+* The entry point in physical DRAM is at address **0x100000**.
+
+## Layout
+
+![Bootflow of Cavium CN8xxx SoCs][cavium_bootflow]
+
+[cavium_bootflow]: cavium_bootflow.png
+
diff --git a/Documentation/soc/cavium/cavium_bootflow.png b/Documentation/soc/cavium/cavium_bootflow.png
new file mode 100644
index 0000000..1e90173
--- /dev/null
+++ b/Documentation/soc/cavium/cavium_bootflow.png
Binary files differ
diff --git a/Documentation/soc/cavium/cn81xx/index.md b/Documentation/soc/cavium/cn81xx/index.md
new file mode 100644
index 0000000..69fe710
--- /dev/null
+++ b/Documentation/soc/cavium/cn81xx/index.md
@@ -0,0 +1,119 @@
+# Cavium CN81xx documentation
+
+## Reference code
+
+```eval_rst
+The Cavium reference code is called `BDK`_ (board development kit) and is part
+of the `Octeon-TX-SDK`_. Parts of the `BDK`_ have been integrated into coreoboot.
+```
+
+## SOC code
+
+The SOC folder contains functions for:
+* TWSI
+* UART
+* TIMER
+* SPI
+* MMU
+* DRAM
+* CLOCK
+* GPIO
+* Secondary CPUs
+* PCI
+
+All other hardware is initilized by the BDK code, which is invoked from
+ramstage.
+
+## Notes about the hardware
+
+Cavium SoC do **not** have embedded SRAM. The **BOOTROM** setups the
+L2 cache and loads 192KiB of firmware starting from 0x20000 to a fixed
+location. It then jumps to the firmware.
+
+```eval_rst
+For more details have a look at `Cavium CN8XXX Bootflow`_.
+```
+
+## CAR setup
+
+For Cache-as-RAM we only need to lock the cachelines which are used by bootblock
+or romstage until DRAM has been set up. At the end of romstage the cachelines
+are unlocked and the contents are flushed to DRAM.
+Locked cachelines are never evicted.
+
+The CAR setup is done in '''bootblock_custom.S''' and thus doesn't use the common
+aarch64 '''bootblock.S''' code.
+
+## DRAM setup
+
+```eval_rst
+The DRAM setup is done by the `BDK`_.
+```
+
+## PCI setup
+
+The PCI setup is done using the MMCONF mechanism.
+Besides configuring device visibility (secure/unsecure) the MSI-X interrupts
+needs to be configured.
+
+## Devicetree patching
+
+The Linux devicetree needs to be patched, depending on the available hardware
+and their configuration. Some values depends on fuses, some on user selectable
+configuration.
+
+The following SoC specific fixes are made:
+
+1. Fix SCLK
+2. Fix UUA refclock
+3. Remove unused PEM entries
+4. Remove unused QLM entries
+5. Set local MAC address
+
+## CN81xx quirks
+
+The CN81xx needs some quirks that are not documented or hidden in the code.
+
+### Violation of PCI spec
+
+**Problem:**
+
+* The PCI device 01:01.0 is disabled, but a multifunction device.
+* The PCI device 01:01.2 - 00:01.7 is enabled and can't be found by the coreboot
+ PCI allocator.
+
+**Solution:**
+
+The PCI Bus 0 and 1 are scanned manually in SOC's PCI code.
+
+
+### Crash accessing SLI memory
+
+**Problem:**
+
+The SLI memory region decodes to attached PCIe devices.
+Accessing the memory region results in 'Data Abort Exception' if the link of the
+PCIe device never had been enabled.
+
+**Solution:**
+
+Enable the PCIe link at least once. (You can disabling the link and the SLI
+memory reads as 0xffffffff.)
+
+
+### RNG Data Abort Exception
+
+**Problem:**
+
+'Data Abort Exception' on accessing the enabled RNG.
+
+**Solution**:
+
+Read the BDK_RNM_CTL_STATUS register at least once after writing it.
+
+
+```eval_rst
+.. _Octeon-TX-SDK: https://github.com/Cavium-Open-Source-Distributions/OCTEON-TX-SDK
+.. _Cavium CN8XXX Bootflow: ../bootflow.html
+.. _BDK: ../../../vendorcode/cavium/bdk.html
+```
diff --git a/Documentation/soc/cavium/index.md b/Documentation/soc/cavium/index.md
new file mode 100644
index 0000000..5ccb47f
--- /dev/null
+++ b/Documentation/soc/cavium/index.md
@@ -0,0 +1,8 @@
+# Cavium SOC-specific documentation
+
+This section contains documentation about coreboot on specific Cavium SOCs.
+
+## Platforms
+
+- [CN81xx series](cn81xx/index.md)
+- [CN8xxx bootflow](bootflow.md)
diff --git a/Documentation/soc/index.md b/Documentation/soc/index.md
index ca50dc8..04e2b2f 100644
--- a/Documentation/soc/index.md
+++ b/Documentation/soc/index.md
@@ -4,4 +4,5 @@
## Vendor
+- [Cavium](cavium/index.md)
- [Intel](intel/index.md)
diff --git a/Documentation/vendorcode/cavium/bdk.md b/Documentation/vendorcode/cavium/bdk.md
new file mode 100644
index 0000000..5763ece
--- /dev/null
+++ b/Documentation/vendorcode/cavium/bdk.md
@@ -0,0 +1,30 @@
+# Cavium's BDK
+
+## BDK
+A part of Cavium's BDK can be found in '''src/vendorcode/cavium/bdk'''.
+It does the **DRAM init** in romstage and the **PCIe**, **QLM**, **SLI**,
+**PHY**, **BGX**, **SATA** init in ramstage.
+
+## Devicetree
+The BDK does use it's own devicetree, as coreboot's devicetree isn't
+compatible. The devicetree stores key-value pairs (see **bdk-devicetree.h**
+for implementation details), where the key and the value are stored as strings.
+
+The key-value pairs must be advertised in romstage and ramstage using the
+'''bdk_config_set_fdt()''' method.
+
+The tool '''util/cavium/devicetree_convert.py''' can be used to convert a
+devicetree to a key-value array.
+
+## Modifications
+
+* The BDK has been modified to compile under coreboot's toolchain.
+* Removed FDT devicetree support.
+* Dropped files that aren't required for SoC bringup
+* Added Kconfig values for verbose console output
+
+## Debugging
+
+You can enable verbose console output in *menuconfig*:
+
+Go to **Chipset**, **BDK** and enable one or multiple stages.
diff --git a/Documentation/vendorcode/cavium/index.md b/Documentation/vendorcode/cavium/index.md
new file mode 100644
index 0000000..e06e2ba
--- /dev/null
+++ b/Documentation/vendorcode/cavium/index.md
@@ -0,0 +1,8 @@
+# Cavium vendorcode-specific documentation
+
+This section contains documentation about coreboot on Cavium specific
+vendorcode.
+
+## Sections
+
+- [BDK](bdk.md)
diff --git a/Documentation/vendorcode/index.md b/Documentation/vendorcode/index.md
new file mode 100644
index 0000000..3374eaf
--- /dev/null
+++ b/Documentation/vendorcode/index.md
@@ -0,0 +1,7 @@
+# Vendorcode-specific documentation
+
+This section contains documentation about coreboot on specific vendorcode.
+
+## Vendor
+
+- [Cavium](cavium/index.md)
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