coreboot-gerrit June 2018

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Change in coreboot[master]: drivers/fsp1_1: fix VBT Loading by using GMA common function
by Matt DeVillier (Code Review) 20 Jun '18

20 Jun '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27169 to look at the new patch set (#2). Change subject: drivers/fsp1_1: fix VBT Loading by using GMA common function ...................................................................... drivers/fsp1_1: fix VBT Loading by using GMA common function Commit 77034fa [intel/common: compress VBT] compressed vbt.bin in CBFS, but only changed the loader in soc/intel/common, forgetting the separate one used by FSP 1.0. As the soc/intel/common loader has now been rolled into the one in drivers/intel/gma, replace the VBT loader used by FSP 1.1 with the GMA one. Test: build/boot google/chell, observe display initialized prior to OS load, no FSP warning in cbmem console due to invalid VBT signature. Change-Id: Iba882ee4d9e83dcd88bdf7dd2f5591f66005a3fe Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- D src/drivers/intel/fsp1_1/include/fsp/gop.h M src/drivers/intel/fsp1_1/vbt.c 2 files changed, 12 insertions(+), 65 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/27169/2 -- To view, visit https://review.coreboot.org/27169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iba882ee4d9e83dcd88bdf7dd2f5591f66005a3fe Gerrit-Change-Number: 27169 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: drivers/fsp1_1: fix VBT Loading by using GMA common function
by build bot (Jenkins) (Code Review) 20 Jun '18

20 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27169 ) Change subject: drivers/fsp1_1: fix VBT Loading by using GMA common function ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29197/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75117/ : SUCCESS -- To view, visit https://review.coreboot.org/27169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iba882ee4d9e83dcd88bdf7dd2f5591f66005a3fe Gerrit-Change-Number: 27169 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 20 Jun 2018 05:51:14 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: drivers/fsp1_1: fix VBT Loading by using GMA common function
by Matt DeVillier (Code Review) 20 Jun '18

20 Jun '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/27169 Change subject: drivers/fsp1_1: fix VBT Loading by using GMA common function ...................................................................... drivers/fsp1_1: fix VBT Loading by using GMA common function Commit 77034fa [intel/common: compress VBT] compressed vbt.bin in CBFS, but only changed the loader in soc/intel/common, forgetting the separate one used by FSP 1.0. As the soc/intel/common loader has now been rolled into the one in drivers/intel/gma, replace the VBT loader used by FSP 1.1 with the GMA one. Test: build/boot google/chell, observe display initialized prior to OS load, no FSP warning in cbmem console due to invalid VBT signature. Change-Id: Iba882ee4d9e83dcd88bdf7dd2f5591f66005a3fe Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- D src/drivers/intel/fsp1_1/include/fsp/gop.h M src/drivers/intel/fsp1_1/vbt.c 2 files changed, 8 insertions(+), 63 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/27169/1 diff --git a/src/drivers/intel/fsp1_1/include/fsp/gop.h b/src/drivers/intel/fsp1_1/include/fsp/gop.h deleted file mode 100644 index 66c8a3c..0000000 --- a/src/drivers/intel/fsp1_1/include/fsp/gop.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _FSP1_1_GOP_H_ -#define _FSP1_1_GOP_H_ - -#include <fsp/gma.h> - -const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len); - -#endif /* _FSP1_1_GOP_H_ */ diff --git a/src/drivers/intel/fsp1_1/vbt.c b/src/drivers/intel/fsp1_1/vbt.c index 92a4c91..4091340 100644 --- a/src/drivers/intel/fsp1_1/vbt.c +++ b/src/drivers/intel/fsp1_1/vbt.c @@ -17,47 +17,9 @@ #include <bootmode.h> #include <cbfs.h> #include <console/console.h> -#include <fsp/gop.h> #include <fsp/ramstage.h> #include <fsp/util.h> - -/* Reading VBT table from flash */ -const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len) -{ - size_t vbt_size; - union { - const optionrom_vbt_t *data; - uint32_t *signature; - } vbt; - - /* Locate the vbt file in cbfs */ - vbt.data = cbfs_boot_map_with_leak("vbt.bin", CBFS_TYPE_RAW, &vbt_size); - if (!vbt.data) { - printk(BIOS_INFO, - "FSP_INFO: VBT data file (vbt.bin) not found in CBFS"); - return NULL; - } - - /* Validate the vbt file */ - if (*vbt.signature != VBT_SIGNATURE) { - printk(BIOS_WARNING, - "FSP_WARNING: Invalid signature in VBT data file (vbt.bin)!\n"); - return NULL; - } - *vbt_len = vbt_size; - printk(BIOS_DEBUG, "FSP_INFO: VBT found at %p, 0x%08x bytes\n", - vbt.data, *vbt_len); - -#if IS_ENABLED(CONFIG_DISPLAY_VBT) - /* Display the vbt file contents */ - printk(BIOS_DEBUG, "VBT Data:\n"); - hexdump(vbt.data, *vbt_len); - printk(BIOS_DEBUG, "\n"); -#endif - - /* Return the pointer to the vbt file data */ - return vbt.data; -} +#include <drivers/intel/gma/opregion.h> /* Locate VBT and pass it to FSP GOP */ void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params) @@ -70,9 +32,15 @@ printk(BIOS_DEBUG, "S3 resume do not pass VBT to GOP\n"); } else if (display_init_required()) { /* Get VBT data */ - vbt_data = fsp_get_vbt(&vbt_len); + vbt_data = locate_vbt(&vbt_len); if (vbt_data != NULL) printk(BIOS_DEBUG, "Passing VBT to GOP\n"); +#if IS_ENABLED(CONFIG_DISPLAY_VBT) + /* Display the vbt file contents */ + printk(BIOS_DEBUG, "VBT Data:\n"); + hexdump(vbt.data, *vbt_len); + printk(BIOS_DEBUG, "\n"); +#endif else printk(BIOS_DEBUG, "VBT not found!\n"); } else { -- To view, visit https://review.coreboot.org/27169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iba882ee4d9e83dcd88bdf7dd2f5591f66005a3fe Gerrit-Change-Number: 27169 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: mediatek/mt8183: Add watchdog timer support
by build bot (Jenkins) (Code Review) 19 Jun '18

19 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27026 ) Change subject: mediatek/mt8183: Add watchdog timer support ...................................................................... Patch Set 6: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/75116/ : SUCCESS -- To view, visit https://review.coreboot.org/27026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4be3a133dbb8a64604133cefb0c5f02d01afd0d4 Gerrit-Change-Number: 27026 Gerrit-PatchSet: 6 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 20 Jun 2018 01:19:07 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: inteltool: Add PCI IDs for the C220 PCH series
by build bot (Jenkins) (Code Review) 19 Jun '18

19 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27168 ) Change subject: inteltool: Add PCI IDs for the C220 PCH series ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29196/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75115/ : SUCCESS -- To view, visit https://review.coreboot.org/27168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I07a8f2e9cb0ee8677c8fe2c51881147ed81c1a35 Gerrit-Change-Number: 27168 Gerrit-PatchSet: 1 Gerrit-Owner: Quan Tran <qeed.quan(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 20 Jun 2018 00:07:52 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: inteltool: Add PCI IDs for the C220 PCH series
by Quan Tran (Code Review) 19 Jun '18

19 Jun '18

Quan Tran has uploaded this change for review. ( https://review.coreboot.org/27168 Change subject: inteltool: Add PCI IDs for the C220 PCH series ...................................................................... inteltool: Add PCI IDs for the C220 PCH series The C220 PCH series is a ICH8 generation southbridge. There is already existing code to dump this southbridge. This patch adds the missing PCI IDs to allow the tool to dump them. Documentation on the PCH can be found here: https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/8-s… Change-Id: I07a8f2e9cb0ee8677c8fe2c51881147ed81c1a35 Signed-off-by: Quan Tran <qeed.quan(a)gmail.com> --- M util/inteltool/gpio.c M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/powermgt.c M util/inteltool/rootcmplx.c M util/inteltool/spi.c 6 files changed, 121 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/27168/1 diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 5e31035..5ef96fd 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -849,6 +849,21 @@ case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE: case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM: case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP: + case PCI_DEVICE_ID_INTEL_C8_MOBILE: + case PCI_DEVICE_ID_INTEL_C8_DESKTOP: + case PCI_DEVICE_ID_INTEL_Z87: + case PCI_DEVICE_ID_INTEL_Z85: + case PCI_DEVICE_ID_INTEL_HM86: + case PCI_DEVICE_ID_INTEL_H87: + case PCI_DEVICE_ID_INTEL_HM87: + case PCI_DEVICE_ID_INTEL_Q85: + case PCI_DEVICE_ID_INTEL_Q87: + case PCI_DEVICE_ID_INTEL_QM87: + case PCI_DEVICE_ID_INTEL_B85: + case PCI_DEVICE_ID_INTEL_C222: + case PCI_DEVICE_ID_INTEL_C224: + case PCI_DEVICE_ID_INTEL_C226: + case PCI_DEVICE_ID_INTEL_H81: gpiobase = pci_read_word(sb, 0x48) & 0xfffc; gpio_registers = lynxpoint_lp_gpio_registers; size = ARRAY_SIZE(lynxpoint_lp_gpio_registers); diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 24d62e1..e475157 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -232,6 +232,36 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM175, "HM175" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM175, "QM175" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CM238, "CM238" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C8_MOBILE, + "Intel(R) C8 Mobile"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C8_DESKTOP, + "Intel(R) C8 Desktop"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z87, + "Intel(R) Z87"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z85, + "Intel(R) Z85"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM86, + "Intel(R) HM86"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H87, + "Intel(R) H87"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM87, + "Intel(R) HM87"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q85, + "Intel(R) Q85"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q87, + "Intel(R) Q87"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM87, + "Intel(R) QM87"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B85, + "Intel(R) B85"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C222, + "Intel(R) C222"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C224, + "Intel(R) C224"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C226, + "Intel(R) C226"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H81, + "Intel(R) H81"}, /* Intel GPUs */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_G35_EXPRESS, "Intel(R) G35 Express Chipset Family" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 3ca91cd..7f2372b 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -184,6 +184,22 @@ #define PCI_DEVICE_ID_INTEL_82B43 0x2e40 #define PCI_DEVICE_ID_INTEL_82B43_2 0x2e90 +#define PCI_DEVICE_ID_INTEL_C8_MOBILE 0x8c41 +#define PCI_DEVICE_ID_INTEL_C8_DESKTOP 0x8c42 +#define PCI_DEVICE_ID_INTEL_Z87 0x8c44 +#define PCI_DEVICE_ID_INTEL_Z85 0x8c46 +#define PCI_DEVICE_ID_INTEL_HM86 0x8c49 +#define PCI_DEVICE_ID_INTEL_H87 0x8c4a +#define PCI_DEVICE_ID_INTEL_HM87 0x8c4b +#define PCI_DEVICE_ID_INTEL_Q85 0x8c4c +#define PCI_DEVICE_ID_INTEL_Q87 0x8c4e +#define PCI_DEVICE_ID_INTEL_QM87 0x8c4f +#define PCI_DEVICE_ID_INTEL_B85 0x8c50 +#define PCI_DEVICE_ID_INTEL_C222 0x8c52 +#define PCI_DEVICE_ID_INTEL_C224 0x8c54 +#define PCI_DEVICE_ID_INTEL_C226 0x8c56 +#define PCI_DEVICE_ID_INTEL_H81 0x8c5c + #define PCI_DEVICE_ID_INTEL_82X58 0x3405 #define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100 #define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000 diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index f022904..45cbb33 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -730,6 +730,21 @@ case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM: case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP: case PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC: + case PCI_DEVICE_ID_INTEL_C8_MOBILE: + case PCI_DEVICE_ID_INTEL_C8_DESKTOP: + case PCI_DEVICE_ID_INTEL_Z87: + case PCI_DEVICE_ID_INTEL_Z85: + case PCI_DEVICE_ID_INTEL_HM86: + case PCI_DEVICE_ID_INTEL_H87: + case PCI_DEVICE_ID_INTEL_HM87: + case PCI_DEVICE_ID_INTEL_Q85: + case PCI_DEVICE_ID_INTEL_Q87: + case PCI_DEVICE_ID_INTEL_QM87: + case PCI_DEVICE_ID_INTEL_B85: + case PCI_DEVICE_ID_INTEL_C222: + case PCI_DEVICE_ID_INTEL_C224: + case PCI_DEVICE_ID_INTEL_C226: + case PCI_DEVICE_ID_INTEL_H81: pmbase = pci_read_word(sb, 0x40) & 0xff80; pm_registers = pch_pm_registers; size = ARRAY_SIZE(pch_pm_registers); diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c index 2ad3410..76cb287 100644 --- a/util/inteltool/rootcmplx.c +++ b/util/inteltool/rootcmplx.c @@ -97,6 +97,21 @@ case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE: case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM: case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP: + case PCI_DEVICE_ID_INTEL_C8_MOBILE: + case PCI_DEVICE_ID_INTEL_C8_DESKTOP: + case PCI_DEVICE_ID_INTEL_Z87: + case PCI_DEVICE_ID_INTEL_Z85: + case PCI_DEVICE_ID_INTEL_HM86: + case PCI_DEVICE_ID_INTEL_H87: + case PCI_DEVICE_ID_INTEL_HM87: + case PCI_DEVICE_ID_INTEL_Q85: + case PCI_DEVICE_ID_INTEL_Q87: + case PCI_DEVICE_ID_INTEL_QM87: + case PCI_DEVICE_ID_INTEL_B85: + case PCI_DEVICE_ID_INTEL_C222: + case PCI_DEVICE_ID_INTEL_C224: + case PCI_DEVICE_ID_INTEL_C226: + case PCI_DEVICE_ID_INTEL_H81: rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; break; case PCI_DEVICE_ID_INTEL_ICH: diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c index 6d11fa5..18600b6 100644 --- a/util/inteltool/spi.c +++ b/util/inteltool/spi.c @@ -160,6 +160,21 @@ case PCI_DEVICE_ID_INTEL_HM75: case PCI_DEVICE_ID_INTEL_HM70: case PCI_DEVICE_ID_INTEL_NM70: + case PCI_DEVICE_ID_INTEL_C8_MOBILE: + case PCI_DEVICE_ID_INTEL_C8_DESKTOP: + case PCI_DEVICE_ID_INTEL_Z87: + case PCI_DEVICE_ID_INTEL_Z85: + case PCI_DEVICE_ID_INTEL_HM86: + case PCI_DEVICE_ID_INTEL_H87: + case PCI_DEVICE_ID_INTEL_HM87: + case PCI_DEVICE_ID_INTEL_Q85: + case PCI_DEVICE_ID_INTEL_Q87: + case PCI_DEVICE_ID_INTEL_QM87: + case PCI_DEVICE_ID_INTEL_B85: + case PCI_DEVICE_ID_INTEL_C222: + case PCI_DEVICE_ID_INTEL_C224: + case PCI_DEVICE_ID_INTEL_C226: + case PCI_DEVICE_ID_INTEL_H81: bios_cntl = pci_read_byte(sb, 0xdc); bios_cntl_register = pch_bios_cntl_registers; size = ARRAY_SIZE(pch_bios_cntl_registers); @@ -273,6 +288,21 @@ case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE: case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM: case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP: + case PCI_DEVICE_ID_INTEL_C8_MOBILE: + case PCI_DEVICE_ID_INTEL_C8_DESKTOP: + case PCI_DEVICE_ID_INTEL_Z87: + case PCI_DEVICE_ID_INTEL_Z85: + case PCI_DEVICE_ID_INTEL_HM86: + case PCI_DEVICE_ID_INTEL_H87: + case PCI_DEVICE_ID_INTEL_HM87: + case PCI_DEVICE_ID_INTEL_Q85: + case PCI_DEVICE_ID_INTEL_Q87: + case PCI_DEVICE_ID_INTEL_QM87: + case PCI_DEVICE_ID_INTEL_B85: + case PCI_DEVICE_ID_INTEL_C222: + case PCI_DEVICE_ID_INTEL_C224: + case PCI_DEVICE_ID_INTEL_C226: + case PCI_DEVICE_ID_INTEL_H81: spibaroffset = ICH9_SPIBAR; rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; size = ARRAY_SIZE(spi_bar_registers); -- To view, visit https://review.coreboot.org/27168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I07a8f2e9cb0ee8677c8fe2c51881147ed81c1a35 Gerrit-Change-Number: 27168 Gerrit-PatchSet: 1 Gerrit-Owner: Quan Tran <qeed.quan(a)gmail.com>

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Change in coreboot[master]: mainboard/google/nocturne: Enable Image Unit
by build bot (Jenkins) (Code Review) 19 Jun '18

19 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27124 ) Change subject: mainboard/google/nocturne: Enable Image Unit ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29195/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75114/ : SUCCESS -- To view, visit https://review.coreboot.org/27124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic2edf5ec7bde5c55ce1b13cf7b680094a9fffc6a Gerrit-Change-Number: 27124 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Tue, 19 Jun 2018 22:50:20 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mainboard/google/nocturne: Set camera power sequence
by build bot (Jenkins) (Code Review) 19 Jun '18

19 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27094 ) Change subject: mainboard/google/nocturne: Set camera power sequence ...................................................................... Patch Set 5: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29194/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75113/ : SUCCESS -- To view, visit https://review.coreboot.org/27094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4833c0e303174b297c1d193495e08e55d294a717 Gerrit-Change-Number: 27094 Gerrit-PatchSet: 5 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Comment-Date: Tue, 19 Jun 2018 22:50:11 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mainboard/google/nocturne: Enable camera sensors
by build bot (Jenkins) (Code Review) 19 Jun '18

19 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26283 ) Change subject: mainboard/google/nocturne: Enable camera sensors ...................................................................... Patch Set 9: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29193/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75112/ : SUCCESS -- To view, visit https://review.coreboot.org/26283 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I37c877df8062d5c79e25ed27775ab58e977555db Gerrit-Change-Number: 26283 Gerrit-PatchSet: 9 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.corp-partner.google.com> Gerrit-Reviewer: Hyungwoo Yang <hyungwoo.yang(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Ricky Liang <jcliang(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anonymous Coward #1002003 Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Tomasz Figa <tfiga(a)google.com> Gerrit-Comment-Date: Tue, 19 Jun 2018 22:50:10 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variants/nocturne: disable p-states
by build bot (Jenkins) (Code Review) 19 Jun '18

19 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27156 ) Change subject: mb/google/poppy/variants/nocturne: disable p-states ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/75111/ : SUCCESS -- To view, visit https://review.coreboot.org/27156 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I71ed4c80c109b28ffa85d48338ce3a62396d272e Gerrit-Change-Number: 27156 Gerrit-PatchSet: 4 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 19 Jun 2018 22:23:40 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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