coreboot-gerrit June 2018

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Change in coreboot[master]: arch/arm/armv7: Fix coding style
by Elyes HAOUAS (Code Review) 04 Jun '18

04 Jun '18

Elyes HAOUAS has posted comments on this change. ( https://review.coreboot.org/26831 ) Change subject: arch/arm/armv7: Fix coding style ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/26831 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib5d574347373009c8021597f555e6e86c2c0c41f Gerrit-Change-Number: 26831 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 Jun 2018 13:07:33 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: arch/arm/armv7: Fix coding style
by build bot (Jenkins) (Code Review) 04 Jun '18

04 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26831 ) Change subject: arch/arm/armv7: Fix coding style ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/26831/1/src/arch/arm/armv7/mmu.c File src/arch/arm/armv7/mmu.c: https://review.coreboot.org/#/c/26831/1/src/arch/arm/armv7/mmu.c@49 PS1, Line 49: * fault when accessed for the first time */ \ Avoid unnecessary line continuations https://review.coreboot.org/#/c/26831/1/src/arch/arm/armv7/thread.c File src/arch/arm/armv7/thread.c: https://review.coreboot.org/#/c/26831/1/src/arch/arm/armv7/thread.c@42 PS1, Line 42: void asmlinkage(*thread_entry)(void *), void *arg) storage class 'asmlinkage' should be located before type 'void' -- To view, visit https://review.coreboot.org/26831 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib5d574347373009c8021597f555e6e86c2c0c41f Gerrit-Change-Number: 26831 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 Jun 2018 12:56:25 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: arch/arm/armv7: Fix coding style
by Elyes HAOUAS (Code Review) 04 Jun '18

04 Jun '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/26831 Change subject: arch/arm/armv7: Fix coding style ...................................................................... arch/arm/armv7: Fix coding style Change-Id: Ib5d574347373009c8021597f555e6e86c2c0c41f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm/armv7/bootblock.S M src/arch/arm/armv7/cpu.S M src/arch/arm/armv7/mmu.c M src/arch/arm/armv7/thread.c 4 files changed, 72 insertions(+), 72 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/26831/1 diff --git a/src/arch/arm/armv7/bootblock.S b/src/arch/arm/armv7/bootblock.S index da7509d..e2d76a1 100644 --- a/src/arch/arm/armv7/bootblock.S +++ b/src/arch/arm/armv7/bootblock.S @@ -89,11 +89,11 @@ /* Set stackpointer in internal RAM to call bootblock main() */ ldr sp, =_estack ldr r0,=0x00000000 - /* - * The current design of cpu_info places the struct at the top of the - * stack. Free enough space to accommodate for that, but make sure it's - * 8-byte aligned for ABI compliance. - */ + /* + * The current design of cpu_info places the struct at the top of the + * stack. Free enough space to accommodate for that, but make sure it's + * 8-byte aligned for ABI compliance. + */ sub sp, sp, #16 bl main diff --git a/src/arch/arm/armv7/cpu.S b/src/arch/arm/armv7/cpu.S index 21a16d2..1f6cd5b 100644 --- a/src/arch/arm/armv7/cpu.S +++ b/src/arch/arm/armv7/cpu.S @@ -84,7 +84,7 @@ lsl ip, ip, r2 @ shift by that into way position mov r0, #1 lsl r2, r0, r2 @ r2 now contains the way decr - mov r0, r3 @ get sets/level (no way yet) + mov r0, r3 @ get sets/level (no way yet) orr r3, r3, ip @ merge way into way/set/level bfc r0, #0, #4 @ clear low 4 bits (level) to get numset - 1 sub r2, r2, r0 @ subtract from way decr diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c index 957b4b6..4f1f08e 100644 --- a/src/arch/arm/armv7/mmu.c +++ b/src/arch/arm/armv7/mmu.c @@ -46,7 +46,7 @@ 0ULL << 54 | /* XN. 0:Not restricted */ \ 0ULL << 53 | /* PXN. 0:Not restricted */ \ 1 << 10 | /* AF. 1:Accessed. This is to prevent access \ - * fault when accessed for the first time */ \ + * fault when accessed for the first time */ \ 0 << 6 | /* AP[2:1]. 0b00:full access from PL1 */ \ 0 << 5 | /* NS. 0:Output address is in Secure space */ \ 0 << 1 | /* block/table. 0:block entry */ \ @@ -196,7 +196,7 @@ /* Make sure the range is contained within a single superpage. */ assert(((start_kb + size_kb - 1) & (BLOCK_MASK/KiB)) - == (start_kb & (BLOCK_MASK/KiB)) && start_kb < 4 * (GiB/KiB)); + == (start_kb & (BLOCK_MASK/KiB)) && start_kb < 4 * (GiB/KiB)); if ((*pgd_entry & ~NEXTLEVEL_MASK) != ATTR_NEXTLEVEL) table = mmu_create_subtable(pgd_entry); @@ -219,7 +219,7 @@ start_kb * KiB, (start_kb + size_kb) * KiB, attrs[policy].name); u32 end_kb = ALIGN_UP((start_kb + size_kb), PAGE_SIZE/KiB) - - (start_kb & ~mask); + (start_kb & ~mask); assert(end_kb <= BLOCK_SIZE/KiB); @@ -238,7 +238,7 @@ start_kb * KiB, (start_kb + size_kb) * KiB); mmu_fill_table(table, (start_kb & mask) / (PAGE_SIZE/KiB), div_round_up((start_kb + size_kb) & mask, PAGE_SIZE/KiB), - (start_kb & ~mask) * KiB, PAGE_SHIFT, 0); + start_kb & ~mask) * KiB, PAGE_SHIFT, 0); } void mmu_disable_range(u32 start_mb, u32 size_mb) @@ -285,53 +285,53 @@ int i; printk(BIOS_DEBUG, "LPAE Translation tables are @ %p\n", - ttb_buff); + ttb_buff); ASSERT((read_mmfr0() & 0xf) >= 5); /* - * Set MAIR - * See B4.1.104 of ARMv7 Architecture Reference Manual - */ + * Set MAIR + * See B4.1.104 of ARMv7 Architecture Reference Manual + */ write_mair0( 0x00 << (MAIR_INDX_NC*8) | /* Strongly-ordered, - * Non-Cacheable */ + * Non-Cacheable */ 0xaa << (MAIR_INDX_WT*8) | /* Write-Thru, - * Read-Allocate */ + * Read-Allocate */ 0xff << (MAIR_INDX_WB*8) /* Write-Back, - * Read/Write-Allocate */ + * Read/Write-Allocate */ ); /* - * Set up L1 table - * Once set here, L1 table won't be modified by coreboot. - * See B3.6.1 of ARMv7 Architecture Reference Manual - */ + * Set up L1 table + * Once set here, L1 table won't be modified by coreboot. + * See B3.6.1 of ARMv7 Architecture Reference Manual + */ for (i = 0; i < 4; i++) { pgd_buff[i] = ((uint32_t)pmd & NEXTLEVEL_MASK) | - ATTR_NEXTLEVEL; + ATTR_NEXTLEVEL; pmd += BLOCK_SIZE / PAGE_SIZE; } /* - * Set TTBR0 - */ + * Set TTBR0 + */ write_ttbr0((uintptr_t)pgd_buff); } else { printk(BIOS_DEBUG, "Translation table is @ %p\n", ttb_buff); /* - * Translation table base 0 address is in bits 31:14-N, where N - * is given by bits 2:0 in TTBCR (which we set to 0). All lower - * bits in this register should be zero for coreboot. - */ + * Translation table base 0 address is in bits 31:14-N, where N + * is given by bits 2:0 in TTBCR (which we set to 0). All lower + * bits in this register should be zero for coreboot. + */ write_ttbr0((uintptr_t)ttb_buff); } /* - * Set TTBCR - * See B4.1.153 of ARMv7 Architecture Reference Manual - * See B3.5.4 and B3.6.4 for how TTBR0 or TTBR1 is selected. - */ + * Set TTBCR + * See B4.1.153 of ARMv7 Architecture Reference Manual + * See B3.5.4 and B3.6.4 for how TTBR0 or TTBR1 is selected. + */ write_ttbcr( CONFIG_ARM_LPAE << 31 | /* EAE. 1:Enable LPAE */ 0 << 16 | 0 << 0 /* Use TTBR0 for all addresses */ diff --git a/src/arch/arm/armv7/thread.c b/src/arch/arm/armv7/thread.c index 3b8d1af..e27fc41 100644 --- a/src/arch/arm/armv7/thread.c +++ b/src/arch/arm/armv7/thread.c @@ -39,22 +39,22 @@ } void arch_prepare_thread(struct thread *t, - void asmlinkage(*thread_entry)(void *), void *arg) + void asmlinkage(*thread_entry)(void *), void *arg) { uintptr_t stack = t->stack_current; int i; uintptr_t poison = 0xdeadbeef; /* Push the LR. thread_entry() - * is assumed to never return. - */ + * is assumed to never return. + */ stack = push_stack(stack, (uintptr_t)thread_entry); /* Make room for the registers. - * Poison the initial stack. This is good hygiene and finds bugs. - * Poisoning the stack with different values helps when you're - * hunting for (e.g.) misaligned stacks or other such - * weirdness. The -1 is because we already pushed lr. - */ + * Poison the initial stack. This is good hygiene and finds bugs. + * Poisoning the stack with different values helps when you're + * hunting for (e.g.) misaligned stacks or other such + * weirdness. The -1 is because we already pushed lr. + */ for (i = 0; i < sizeof(struct pushed_regs) / sizeof(u32) - 1; i++) stack = push_stack(stack, poison++); @@ -71,38 +71,38 @@ switch_to_thread(uintptr_t new_stack, uintptr_t *saved_stack) { /* Defintions for those of us not totally familiar with ARM: - * R15 -- PC, R14 -- LR, R13 -- SP - * R0-R3 need not be saved, nor R12. - * on entry, the only saved state is in LR -- the old PC. - * The args are in R0,R1. - * R0 is the new stack - * R1 is a pointer to the old stack save location - * Push R4-R11 and LR - * then switch stacks - * then pop R0-R12 and LR - * then mov PC,LR - * - * stack layout - * +------------+ - * | LR | <-- sp + 0x20 - * +------------+ - * | R11 | <-- sp + 0x1c - * +------------+ - * | R10 | <-- sp + 0x18 - * +------------+ - * | R9 | <-- sp + 0x14 - * +------------+ - * | R8 | <-- sp + 0x10 - * +------------+ - * | R7 | <-- sp + 0x0c - * +------------+ - * | R6 | <-- sp + 0x08 - * +------------+ - * | R5 | <-- sp + 0x04 - * +------------+ - * | R4 | <-- sp + 0x00 - * +------------+ - */ + * R15 -- PC, R14 -- LR, R13 -- SP + * R0-R3 need not be saved, nor R12. + * on entry, the only saved state is in LR -- the old PC. + * The args are in R0,R1. + * R0 is the new stack + * R1 is a pointer to the old stack save location + * Push R4-R11 and LR + * then switch stacks + * then pop R0-R12 and LR + * then mov PC,LR + * + * stack layout + * +------------+ + * | LR | <-- sp + 0x20 + * +------------+ + * | R11 | <-- sp + 0x1c + * +------------+ + * | R10 | <-- sp + 0x18 + * +------------+ + * | R9 | <-- sp + 0x14 + * +------------+ + * | R8 | <-- sp + 0x10 + * +------------+ + * | R7 | <-- sp + 0x0c + * +------------+ + * | R6 | <-- sp + 0x08 + * +------------+ + * | R5 | <-- sp + 0x04 + * +------------+ + * | R4 | <-- sp + 0x00 + * +------------+ + */ asm volatile ( /* save context. */ "push {r4-r11,lr}\n\t" -- To view, visit https://review.coreboot.org/26831 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib5d574347373009c8021597f555e6e86c2c0c41f Gerrit-Change-Number: 26831 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: src/driver/i2c/{generic, hid, tpm, max}: Update device name based on dev...
by build bot (Jenkins) (Code Review) 04 Jun '18

04 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26830 ) Change subject: src/driver/i2c/{generic,hid,tpm,max}: Update device name based on devicetree.cb ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/74167/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/28275/ : SUCCESS -- To view, visit https://review.coreboot.org/26830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5dbb66ab705cd8601b8b1dc94bc6ee9f181b7be2 Gerrit-Change-Number: 26830 Gerrit-PatchSet: 2 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 Jun 2018 12:43:53 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: opencellular/supabrckv1: Add LPC TPM to devicetree
by build bot (Jenkins) (Code Review) 04 Jun '18

04 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25705 ) Change subject: opencellular/supabrckv1: Add LPC TPM to devicetree ...................................................................... Patch Set 3: Build Failed https://qa.coreboot.org/job/coreboot-gerrit/74166/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/28274/ : SUCCESS -- To view, visit https://review.coreboot.org/25705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2ec0fca97f4581a1da35d424ace0526017a8e651 Gerrit-Change-Number: 25705 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 Jun 2018 12:39:38 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/fsp_baytrail: Fix vboot and TPM support
by build bot (Jenkins) (Code Review) 04 Jun '18

04 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23798 ) Change subject: soc/fsp_baytrail: Fix vboot and TPM support ...................................................................... Patch Set 13: Build Failed https://qa.coreboot.org/job/coreboot-gerrit/74165/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/28273/ : SUCCESS -- To view, visit https://review.coreboot.org/23798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id33b7f2b9269593cd3e62f63752a660a144600da Gerrit-Change-Number: 23798 Gerrit-PatchSet: 13 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 Jun 2018 12:39:18 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: src/driver/i2c/{generic, hid, tpm, max}: Update device name based on dev...
by build bot (Jenkins) (Code Review) 04 Jun '18

04 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26830 ) Change subject: src/driver/i2c/{generic,hid,tpm,max}: Update device name based on devicetree.cb ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/74164/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/28272/ : SUCCESS -- To view, visit https://review.coreboot.org/26830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5dbb66ab705cd8601b8b1dc94bc6ee9f181b7be2 Gerrit-Change-Number: 26830 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 Jun 2018 12:38:58 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src/driver/i2c/{generic, hid, tpm, max}: Update device name based on dev...
by Naresh Solanki (Code Review) 04 Jun '18

04 Jun '18

Naresh Solanki has uploaded a new patch set (#2). ( https://review.coreboot.org/26830 ) Change subject: src/driver/i2c/{generic,hid,tpm,max}: Update device name based on devicetree.cb ...................................................................... src/driver/i2c/{generic,hid,tpm,max}: Update device name based on devicetree.cb Name i2c device structure based on that in devicetree.cb Now log looks like: I2C: 01:0a (WCOM Touchscreen) I2C: 03:13 (Realtek RT5663) I2C: 03:39 (SSM4567 Right Speaker Amp) I2C: 03:3a (SSM4567 Left Speaker Amp) BUG=None BRANCH=None TEST=Build & boot Soraka Change-Id: I5dbb66ab705cd8601b8b1dc94bc6ee9f181b7be2 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- M src/drivers/i2c/generic/generic.c M src/drivers/i2c/hid/hid.c M src/drivers/i2c/max98373/max98373.c M src/drivers/i2c/max98927/max98927.c M src/drivers/i2c/tpm/chip.c 5 files changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/26830/2 -- To view, visit https://review.coreboot.org/26830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I5dbb66ab705cd8601b8b1dc94bc6ee9f181b7be2 Gerrit-Change-Number: 26830 Gerrit-PatchSet: 2 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)intel.com>

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Change in coreboot[master]: opencellular/rotundu: Introduce variants for OC
by build bot (Jenkins) (Code Review) 04 Jun '18

04 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22924 ) Change subject: opencellular/rotundu: Introduce variants for OC ...................................................................... Patch Set 21: Build Failed https://qa.coreboot.org/job/coreboot-gerrit/74163/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/28271/ : SUCCESS -- To view, visit https://review.coreboot.org/22924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id20e9d4ed7ac071d25a69eee63c9ec544d2ad152 Gerrit-Change-Number: 22924 Gerrit-PatchSet: 21 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Reg Orton <reg(a)brck.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 Jun 2018 12:38:04 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: opencellular/rotundu: Add LPC TPM support
by build bot (Jenkins) (Code Review) 04 Jun '18

04 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22829 ) Change subject: opencellular/rotundu: Add LPC TPM support ...................................................................... Patch Set 18: Build Failed https://qa.coreboot.org/job/coreboot-gerrit/74162/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/28270/ : SUCCESS -- To view, visit https://review.coreboot.org/22829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4154841de553d198d5a5d113e31b7be14a12dcd0 Gerrit-Change-Number: 22829 Gerrit-PatchSet: 18 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Bernard Adongo <bernard(a)brck.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Reg Orton <reg(a)brck.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 Jun 2018 12:37:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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coreboot-gerrit June 2018