Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/25863
Change subject: soc/intel/cannonlake: Switch to common block for GSPI
......................................................................
soc/intel/cannonlake: Switch to common block for GSPI
>From cannonlake onwards we'll use GSPI functionality from common block
which was created in previous patch and remove gspi.c file from soc. We
need to implement/move one soc specific function which is moved to
chip_config.c which returns soc specific configuration for gspi.
This will reduce redundant copy of code which is common across multiple
soc.
BUG=none
BRANCH=none
TEST=Coreboot builds with different board configuration. Also coreboot
boots with these changes on cannonlake board.
Change-Id: Ia456f6d8e03fcca1a916dc86b3d8cc68fb45a155
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/Makefile.inc
M src/soc/intel/cannonlake/chip_config.c
D src/soc/intel/cannonlake/gspi.c
4 files changed, 25 insertions(+), 79 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/25863/1
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 55f2ea8..c9b3bd3 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -54,7 +54,7 @@
select SOC_INTEL_COMMON_BLOCK_FAST_SPI
select SOC_INTEL_COMMON_BLOCK_GPIO
select SOC_INTEL_COMMON_BLOCK_GRAPHICS
- select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
+ select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_3
select SOC_INTEL_COMMON_BLOCK_ITSS
select SOC_INTEL_COMMON_BLOCK_I2C_V2
select SOC_INTEL_COMMON_BLOCK_LPC
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index afebb24..1e463c2 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -13,16 +13,16 @@
bootblock-y += bootblock/pch.c
bootblock-y += pmutil.c
bootblock-y += bootblock/report_platform.c
+bootblock-y += chip_config.c
bootblock-y += gpio.c
-bootblock-y += gspi.c
bootblock-y += memmap.c
bootblock-y += spi.c
bootblock-y += lpc.c
bootblock-$(CONFIG_UART_DEBUG) += uart.c
romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_LPDDR4_INIT) += cnl_lpddr4_init.c
+romstage-y += chip_config.c
romstage-y += gpio.c
-romstage-y += gspi.c
romstage-y += lpc.c
romstage-y += memmap.c
romstage-y += pmutil.c
@@ -36,7 +36,6 @@
ramstage-y += finalize.c
ramstage-y += gpio.c
ramstage-y += graphics.c
-ramstage-y += gspi.c
ramstage-y += gpio.c
ramstage-y += lpc.c
ramstage-y += memmap.c
@@ -61,7 +60,7 @@
postcar-y += pmutil.c
postcar-$(CONFIG_UART_DEBUG) += uart.c
-verstage-y += gspi.c
+verstage-y += chip_config.c
verstage-y += pmutil.c
verstage-y += spi.c
verstage-$(CONFIG_UART_DEBUG) += uart.c
diff --git a/src/soc/intel/cannonlake/chip_config.c b/src/soc/intel/cannonlake/chip_config.c
index 191d0d8..230d205 100644
--- a/src/soc/intel/cannonlake/chip_config.c
+++ b/src/soc/intel/cannonlake/chip_config.c
@@ -17,7 +17,7 @@
#include <device/device.h>
#include <drivers/i2c/designware/dw_i2c.h>
#include <intelbasecode/lockdown.h>
-
+#include <intelblocks/gspi.h>
/*
* This function will return SOC specific lockdown configuration.
* Function can return 3 possible values:
@@ -28,7 +28,7 @@
int soc_get_lockdown_config(void)
{
const struct soc_intel_cannonlake_config *config;
- struct device *dev = dev_find_slot(0, PCH_DEVFN_SPI);
+ const struct device *dev = dev_find_slot(0, PCH_DEVFN_SPI);
if (dev == NULL || dev->chip_info == NULL)
return -1;
@@ -53,3 +53,22 @@
return &config->i2c[bus];
}
+
+const struct gspi_cfg *gspi_get_soc_cfg(void)
+{
+ DEVTREE_CONST struct soc_intel_cannonlake_config *config;
+ int devfn = SA_DEVFN_ROOT;
+ DEVTREE_CONST struct device *dev = dev_find_slot(0, devfn);
+
+ if (!dev || !dev->chip_info) {
+ printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
+ __func__);
+ return NULL;
+ }
+
+ config = dev->chip_info;
+
+ return &config->gspi[0];
+}
+
+
diff --git a/src/soc/intel/cannonlake/gspi.c b/src/soc/intel/cannonlake/gspi.c
deleted file mode 100644
index e4f682d..0000000
--- a/src/soc/intel/cannonlake/gspi.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2017 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <assert.h>
-#include <device/device.h>
-#include <intelblocks/gspi.h>
-#include <intelblocks/spi.h>
-#include <soc/iomap.h>
-#include <soc/pci_devs.h>
-#include "chip.h"
-
-const struct gspi_cfg *gspi_get_soc_cfg(void)
-{
- DEVTREE_CONST struct soc_intel_cannonlake_config *config;
- int devfn = SA_DEVFN_ROOT;
- DEVTREE_CONST struct device *dev = dev_find_slot(0, devfn);
-
- if (!dev || !dev->chip_info) {
- printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
- __func__);
- return NULL;
- }
-
- config = dev->chip_info;
-
- return &config->gspi[0];
-}
-
-uintptr_t gspi_get_soc_early_base(void)
-{
- return EARLY_GSPI_BASE_ADDRESS;
-}
-
-/*
- * SPI Bus 0 is Fast SPI and GSPI starts from SPI bus # 1 onwards. Thus, adjust
- * the bus # accordingly when referring to SPI / GSPI bus numbers.
- */
-#define GSPI_TO_SPI_BUS(x) ((x) + 1)
-#define SPI_TO_GSPI_BUS(x) ((x) - 1)
-
-int gspi_soc_spi_to_gspi_bus(unsigned int spi_bus, unsigned int *gspi_bus)
-{
- if (spi_bus == 0)
- return -1;
-
- *gspi_bus = SPI_TO_GSPI_BUS(spi_bus);
- if (*gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)
- return -1;
-
- return 0;
-}
-
-int gspi_soc_bus_to_devfn(unsigned int gspi_bus)
-{
- if (gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)
- return -1;
-
- return spi_soc_bus_to_devfn(GSPI_TO_SPI_BUS(gspi_bus));
-}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia456f6d8e03fcca1a916dc86b3d8cc68fb45a155
Gerrit-Change-Number: 25863
Gerrit-PatchSet: 1
Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/25862
Change subject: soc/intel/common/block: Create a common gspi V3 block
......................................................................
soc/intel/common/block: Create a common gspi V3 block
There is already GSPI block available in common and this patch tries to
take common functionality from existing soc and tries to push it into
new block named gspi_v3.
This will remove code which lies inside soc folder but still can be used
as common code across multiple soc. This is applicable from cannonlake
onwards only. To select GSPI from common block instead of using it from
SOC, select "SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_3" inside Kconfig.
BUG=none
BRANCH=none
TEST=code is compiling with different configurations.
Change-Id: Ie8573c4b487394893b467bddccb702d4942a4b87
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
---
A src/soc/intel/common/block/gspi_v3/Kconfig
A src/soc/intel/common/block/gspi_v3/Makefile.inc
A src/soc/intel/common/block/gspi_v3/gspi.c
3 files changed, 64 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/25862/1
diff --git a/src/soc/intel/common/block/gspi_v3/Kconfig b/src/soc/intel/common/block/gspi_v3/Kconfig
new file mode 100644
index 0000000..88ced7b
--- /dev/null
+++ b/src/soc/intel/common/block/gspi_v3/Kconfig
@@ -0,0 +1,8 @@
+config SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_3
+ bool
+ default n
+ select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
+ help
+ Intel Processor Common GSPI support for cannonlake onwards. Enabling
+ this feature requires soc to implement function which returns soc
+ based GSPI configuration.
diff --git a/src/soc/intel/common/block/gspi_v3/Makefile.inc b/src/soc/intel/common/block/gspi_v3/Makefile.inc
new file mode 100644
index 0000000..128e0ff
--- /dev/null
+++ b/src/soc/intel/common/block/gspi_v3/Makefile.inc
@@ -0,0 +1,4 @@
+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_3) += gspi.c
+romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_3) += gspi.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_3) += gspi.c
+verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_3) += gspi.c
diff --git a/src/soc/intel/common/block/gspi_v3/gspi.c b/src/soc/intel/common/block/gspi_v3/gspi.c
new file mode 100644
index 0000000..e9d1f78
--- /dev/null
+++ b/src/soc/intel/common/block/gspi_v3/gspi.c
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <assert.h>
+#include <intelblocks/gspi.h>
+#include <intelblocks/spi.h>
+#include <soc/iomap.h>
+
+uintptr_t gspi_get_soc_early_base(void)
+{
+ return EARLY_GSPI_BASE_ADDRESS;
+}
+
+/*
+ * SPI Bus 0 is Fast SPI and GSPI starts from SPI bus # 1 onwards. Thus, adjust
+ * the bus # accordingly when referring to SPI / GSPI bus numbers.
+ */
+#define GSPI_TO_SPI_BUS(x) ((x) + 1)
+#define SPI_TO_GSPI_BUS(x) ((x) - 1)
+
+int gspi_soc_spi_to_gspi_bus(unsigned int spi_bus, unsigned int *gspi_bus)
+{
+ if (spi_bus == 0)
+ return -1;
+
+ *gspi_bus = SPI_TO_GSPI_BUS(spi_bus);
+ if (*gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)
+ return -1;
+
+ return 0;
+}
+
+int gspi_soc_bus_to_devfn(unsigned int gspi_bus)
+{
+ if (gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)
+ return -1;
+
+ return spi_soc_bus_to_devfn(GSPI_TO_SPI_BUS(gspi_bus));
+}
--
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Gerrit-Change-Number: 25862
Gerrit-PatchSet: 1
Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25583 )
Change subject: lib/bootmem: Add method to walk memory tables
......................................................................
Patch Set 10:
Build Successful
https://qa.coreboot.org/job/coreboot-checkpatch/24957/ : SUCCESS
--
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Gerrit-Change-Id: I0004e5ad5fe2289827f370f0d0f9979d3cbd3926
Gerrit-Change-Number: 25583
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Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
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Gerrit-Comment-Date: Thu, 26 Apr 2018 08:38:01 +0000
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Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/25859
Change subject: commonlib/cbfs: Make cbfsf_file_type public
......................................................................
commonlib/cbfs: Make cbfsf_file_type public
Make cbfsf_file_type public to support multiple payload types in
prog_loaders.
Change-Id: I37e9fb06f926dc71b001722a6c3b6205a2f20462
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/commonlib/cbfs.c
M src/commonlib/include/commonlib/cbfs.h
2 files changed, 7 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/25859/1
diff --git a/src/commonlib/cbfs.c b/src/commonlib/cbfs.c
index 1db8d31..11e8a27 100644
--- a/src/commonlib/cbfs.c
+++ b/src/commonlib/cbfs.c
@@ -156,7 +156,7 @@
return 0;
}
-static int cbfsf_file_type(struct cbfsf *fh, uint32_t *ftype)
+int cbfsf_file_type(struct cbfsf *fh, uint32_t *ftype)
{
const size_t sz = sizeof(*ftype);
diff --git a/src/commonlib/include/commonlib/cbfs.h b/src/commonlib/include/commonlib/cbfs.h
index 163bef2..c31df51 100644
--- a/src/commonlib/include/commonlib/cbfs.h
+++ b/src/commonlib/include/commonlib/cbfs.h
@@ -71,6 +71,12 @@
int cbfsf_decompression_info(struct cbfsf *fh, uint32_t *algo, size_t *size);
/*
+ * Return the CBFS file type as out-parameter.
+ * Returns 0 on success and < 0 on error.
+ */
+int cbfsf_file_type(struct cbfsf *fh, uint32_t *ftype);
+
+/*
* Perform the vb2 hash over the CBFS region skipping empty file contents.
* Caller is responsible for providing the hash algorithm as well as storage
* for the final digest. Return 0 on success or non-zero on error.
--
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Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>