coreboot-gerrit April 2018

coreboot-gerrit@coreboot.org

1 participants
2168 discussions

Change in coreboot[master]: docker/coreboot-sdk: Add device-tree-compiler
by build bot (Jenkins) (Code Review) 06 Apr '18

06 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25525 ) Change subject: docker/coreboot-sdk: Add device-tree-compiler ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23919/ : SUCCESS -- To view, visit https://review.coreboot.org/25525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifa3608f0a83431e75fbd402385863cce06e249fb Gerrit-Change-Number: 25525 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Apr 2018 07:10:15 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: docker/coreboot-sdk: Add device-tree-compiler
by build bot (Jenkins) (Code Review) 06 Apr '18

06 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25525 ) Change subject: docker/coreboot-sdk: Add device-tree-compiler ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69608/ : SUCCESS -- To view, visit https://review.coreboot.org/25525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifa3608f0a83431e75fbd402385863cce06e249fb Gerrit-Change-Number: 25525 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Apr 2018 07:04:26 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: amd/common/block/pi: Make agesa_heap_base() static
by Patrick Georgi (Code Review) 06 Apr '18

06 Apr '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/25457 ) Change subject: amd/common/block/pi: Make agesa_heap_base() static ...................................................................... amd/common/block/pi: Make agesa_heap_base() static Convert agesa_heap_base() to static since it's unused outside of heapmanager.c. Change-Id: I3ee162985ca1ea36461ea413416d98451a700f8c Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-on: https://review.coreboot.org/25457 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/common/block/include/amdblocks/agesawrapper.h M src/soc/amd/common/block/pi/heapmanager.c 2 files changed, 1 insertion(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Richard Spiegel: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h index 44ddba2..986d6f8 100644 --- a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h +++ b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h @@ -63,6 +63,4 @@ void SetFchMidParams(FCH_INTERFACE *params); void SetNbMidParams(GNB_MID_CONFIGURATION *params); -void *agesa_heap_base(void); - #endif /* __AGESAWRAPPER_H__ */ diff --git a/src/soc/amd/common/block/pi/heapmanager.c b/src/soc/amd/common/block/pi/heapmanager.c index 79c8403..a469a45 100644 --- a/src/soc/amd/common/block/pi/heapmanager.c +++ b/src/soc/amd/common/block/pi/heapmanager.c @@ -19,7 +19,7 @@ #include <cbmem.h> #include <string.h> -void *agesa_heap_base(void) +static void *agesa_heap_base(void) { return cbmem_add(CBMEM_ID_RESUME_SCRATCH, BIOS_HEAP_SIZE); } -- To view, visit https://review.coreboot.org/25457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I3ee162985ca1ea36461ea413416d98451a700f8c Gerrit-Change-Number: 25457 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: vc/amd/stoneyridge: Add definition for AGESA heap rebase
by Patrick Georgi (Code Review) 06 Apr '18

06 Apr '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/25456 ) Change subject: vc/amd/stoneyridge: Add definition for AGESA heap rebase ...................................................................... vc/amd/stoneyridge: Add definition for AGESA heap rebase AgesaHeapRebase is an optional callout that allows AGESA to use a coreboot-managed heap base address. Its internal default location is determined by AMD_HEAP_START_ADDRESS which is defined as 4 MB. Add a #define that AGESA may use once the feature is available. BUG=b:74518368 Change-Id: Id23455779b1c8c4931ad1a3122587e09ad237ecc Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-on: https://review.coreboot.org/25456 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/vendorcode/amd/pi/00670F00/AGESA.h 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Richard Spiegel: Looks good to me, approved diff --git a/src/vendorcode/amd/pi/00670F00/AGESA.h b/src/vendorcode/amd/pi/00670F00/AGESA.h index 2b2a8b6..ba1e505 100644 --- a/src/vendorcode/amd/pi/00670F00/AGESA.h +++ b/src/vendorcode/amd/pi/00670F00/AGESA.h @@ -68,6 +68,7 @@ #define AGESA_IDLE_AN_AP 0x00028107ul #define AGESA_WAIT_FOR_ALL_APS 0x00028108ul #define AGESA_HALT_THIS_AP 0x00028109ul +#define AGESA_HEAP_REBASE 0x0002810aul // AGESA ADVANCED CALLOUTS, Memory #define AGESA_READ_SPD 0x00028140ul -- To view, visit https://review.coreboot.org/25456 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Id23455779b1c8c4931ad1a3122587e09ad237ecc Gerrit-Change-Number: 25456 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: amd/stoneyridge: Use defined value for SPI flash MTRR
by Patrick Georgi (Code Review) 06 Apr '18

06 Apr '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/25455 ) Change subject: amd/stoneyridge: Use defined value for SPI flash MTRR ...................................................................... amd/stoneyridge: Use defined value for SPI flash MTRR Replace an absolute value with a #define value in bootblock. This is in preparation for using an additional MTRR in a subsequent patch. Change-Id: I006c7cfa0057b3ed4a21359fc8367caf6ec5baf3 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-on: https://review.coreboot.org/25455 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/bootblock/bootblock.c M src/soc/amd/stoneyridge/include/soc/cpu.h 2 files changed, 13 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Richard Spiegel: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index fafaf07..db5c9b6 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -25,6 +25,7 @@ #include <amdblocks/agesawrapper.h> #include <amdblocks/agesawrapper_call.h> #include <soc/pci_devs.h> +#include <soc/cpu.h> #include <soc/northbridge.h> #include <soc/southbridge.h> #include <amdblocks/psp.h> @@ -61,7 +62,7 @@ * todo: AGESA currently writes variable MTRRs. Once that is * corrected, un-hardcode this MTRR. */ - mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - 2; + mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_FLASH; set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); } diff --git a/src/soc/amd/stoneyridge/include/soc/cpu.h b/src/soc/amd/stoneyridge/include/soc/cpu.h index d2c412f..bf8ed49 100644 --- a/src/soc/amd/stoneyridge/include/soc/cpu.h +++ b/src/soc/amd/stoneyridge/include/soc/cpu.h @@ -16,6 +16,17 @@ #ifndef __STONEYRIDGE_CPU_H__ #define __STONEYRIDGE_CPU_H__ +#include <device/device.h> + +/* + * Set a variable MTRR in bootblock and/or romstage. AGESA will use the lowest + * numbered registers. Any values defined below are subtracted from the + * highest numbered registers. + * + * todo: Revisit this once AGESA no longer programs MTRRs. + */ +#define SOC_EARLY_VMTRR_FLASH 2 + void stoney_init_cpus(struct device *dev); #endif /* __STONEYRIDGE_CPU_H__ */ -- To view, visit https://review.coreboot.org/25455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I006c7cfa0057b3ed4a21359fc8367caf6ec5baf3 Gerrit-Change-Number: 25455 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: mb/intel/dg41wv: Add mainboard
by build bot (Jenkins) (Code Review) 06 Apr '18

06 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20003 ) Change subject: mb/intel/dg41wv: Add mainboard ...................................................................... Patch Set 16: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69606/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23917/ : SUCCESS -- To view, visit https://review.coreboot.org/20003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If01bf658e52d273c3c203d362f21c3cb9c623f40 Gerrit-Change-Number: 20003 Gerrit-PatchSet: 16 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Apr 2018 01:37:24 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: nb/intel/x4x/raminit: Add DDR3 specific dra/drb settings
by build bot (Jenkins) (Code Review) 06 Apr '18

06 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22996 ) Change subject: nb/intel/x4x/raminit: Add DDR3 specific dra/drb settings ...................................................................... Patch Set 10: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69603/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23915/ : SUCCESS -- To view, visit https://review.coreboot.org/22996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I11a79f6800dbfe19c2bd33c0d6caca14b034e384 Gerrit-Change-Number: 22996 Gerrit-PatchSet: 10 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Apr 2018 01:33:57 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: nb/intel/x4x: Adapt post JEDEC for DDR3
by build bot (Jenkins) (Code Review) 06 Apr '18

06 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19918 ) Change subject: nb/intel/x4x: Adapt post JEDEC for DDR3 ...................................................................... Patch Set 15: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69605/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23918/ : SUCCESS -- To view, visit https://review.coreboot.org/19918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I708f98dc2f36af73bb5933d186b4984649e149a1 Gerrit-Change-Number: 19918 Gerrit-PatchSet: 15 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Apr 2018 01:33:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settings
by build bot (Jenkins) (Code Review) 06 Apr '18

06 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19917 ) Change subject: nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settings ...................................................................... Patch Set 15: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69604/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23916/ : SUCCESS -- To view, visit https://review.coreboot.org/19917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9d34154d3ac1dd1e5400d692d4dcce70d95662c8 Gerrit-Change-Number: 19917 Gerrit-PatchSet: 15 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Apr 2018 01:31:08 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: nb/intel/x4x: Add DDR3 JEDEC init
by build bot (Jenkins) (Code Review) 06 Apr '18

06 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22994 ) Change subject: nb/intel/x4x: Add DDR3 JEDEC init ...................................................................... Patch Set 10: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69601/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23912/ : SUCCESS -- To view, visit https://review.coreboot.org/22994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I510b8669aaa48ba99fb4dcf1ece716aef26741bb Gerrit-Change-Number: 22994 Gerrit-PatchSet: 10 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Apr 2018 01:27:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2018