coreboot-gerrit March 2018

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Change in coreboot[master]: mainboard/google/kahlee: Set GPIO 40 to input
by Martin Roth (Code Review) 06 Mar '18

06 Mar '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/25016 Change subject: mainboard/google/kahlee: Set GPIO 40 to input ...................................................................... mainboard/google/kahlee: Set GPIO 40 to input GPIO 40 isn't currently being used, so set it to be an input. BUG=b:73387647 TEST=Build & boot grunt Change-Id: I5a04cbab1276cd20e7f9c7576e8111089dd2b155 Signed-off-by: Martin Roth <martinroth(a)chromium.org> --- M src/mainboard/google/kahlee/variants/baseboard/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/25016/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index de70be4..9964e6f 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -83,8 +83,8 @@ /* GPIO_26 - APU_PCIE_RST_L */ PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), - /* GPIO_40 - EMMC_BRIDGE_RST_L */ - PAD_GPO(GPIO_40, HIGH), + /* GPIO_40 - EMMC_BRIDGE_RST_L - Currently unused */ + PAD_GPI(GPIO_40, PULL_NONE), /* GPIO_42 - S5_MUX_CTRL */ PAD_NF(GPIO_42, S5_MUX_CTRL, PULL_NONE), -- To view, visit https://review.coreboot.org/25016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5a04cbab1276cd20e7f9c7576e8111089dd2b155 Gerrit-Change-Number: 25016 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: mainboard/google/kahlee: Disable Bayhub part on board_id 0
by Martin Roth (Code Review) 06 Mar '18

06 Mar '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/25015 Change subject: mainboard/google/kahlee: Disable Bayhub part on board_id 0 ...................................................................... mainboard/google/kahlee: Disable Bayhub part on board_id 0 The Bayhub part is not used on proto with board_id 0, so disable it. BUG=b:74248569 TEST=Build & boot Grunt. Bayhub part is disabled. Change-Id: I635356d41bab637726594d403d66dde730f12256 Signed-off-by: Martin Roth <martinroth(a)chromium.org> --- M src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c 1 file changed, 99 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/25015/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c index aa0edf7..c9ce900 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c +++ b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c @@ -15,6 +15,7 @@ #include <amdblocks/agesawrapper.h> #include <variant/gpio.h> +#include <boardid.h> static const PCIe_PORT_DESCRIPTOR PortList[] = { /* Initialize Port descriptor (PCIe port, Lanes 7:4, D2F1) for NC*/ @@ -127,6 +128,98 @@ .DdiLinkList = (void *)DdiList }; +/* + * TODO: Remove after we're done with Grunt Proto + */ +static const PCIe_PORT_DESCRIPTOR PortListNoBayhub[] = { + /* Initialize Port descriptor (PCIe port, Lanes 7:4, D2F1) for NC*/ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 4, 7), + PCIE_PORT_DATA_INITIALIZER_V2( + PortDisabled, /* mPortPresent */ + ChannelTypeExt6db, /* mChannelType */ + 2, /* mDevAddress */ + 1, /* mDevFunction */ + HotplugDisabled, /* mHotplug */ + PcieGenMaxSupported, /* mMaxLinkSpeed */ + PcieGenMaxSupported, /* mMaxLinkCap */ + AspmL0sL1, /* mAspm */ + 0, /* mResetId */ + 0) /* mClkPmSupport */ + }, + /* Initialize Port descriptor (PCIe port, Lanes 0:0, D2F2) for WLAN */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0), + PCIE_PORT_DATA_INITIALIZER_V2( + PortEnabled, /* mPortPresent */ + ChannelTypeExt6db, /* mChannelType */ + 2, /* mDevAddress */ + 2, /* mDevFunction */ + HotplugDisabled, /* mHotplug */ + PcieGenMaxSupported, /* mMaxLinkSpeed */ + PcieGenMaxSupported, /* mMaxLinkCap */ + AspmL0sL1, /* mAspm */ + PCIE_0_RST, /* mResetId */ + 0) /* mClkPmSupport */ + }, + /* Init Port descriptor (PCIe port, Lanes 1:1, D2F3) NC */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 1, 1), + PCIE_PORT_DATA_INITIALIZER_V2( + PortDisabled, /* mPortPresent */ + ChannelTypeExt6db, /* mChannelType */ + 2, /* mDevAddress */ + 3, /* mDevFunction */ + HotplugDisabled, /* mHotplug */ + PcieGenMaxSupported, /* mMaxLinkSpeed */ + PcieGenMaxSupported, /* mMaxLinkCap */ + AspmL0sL1, /* mAspm */ + PCIE_1_RST, /* mResetId */ + 0) /* mClkPmSupport */ + }, + /* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for EMMC */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 2, 2), + PCIE_PORT_DATA_INITIALIZER_V2( + PortDisabled, /* mPortPresent */ + ChannelTypeExt6db, /* mChannelType */ + 2, /* mDevAddress */ + 4, /* mDevFunction */ + HotplugDisabled, /* mHotplug */ + PcieGenMaxSupported, /* mMaxLinkSpeed */ + PcieGenMaxSupported, /* mMaxLinkCap */ + AspmL0sL1, /* mAspm */ + PCIE_2_RST, /* mResetId */ + 0) /* mClkPmSupport */ + }, + /* Initialize Port descriptor (PCIe port, Lane3, D2F5) for NC */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 3, 3), + PCIE_PORT_DATA_INITIALIZER_V2( + PortDisabled, /* mPortPresent */ + ChannelTypeExt6db, /* mChannelType */ + 2, /* mDevAddress */ + 5, /* mDevFunction */ + HotplugDisabled, /* mHotplug */ + PcieGenMaxSupported, /* mMaxLinkSpeed */ + PcieGenMaxSupported, /* mMaxLinkCap */ + AspmL0sL1, /* mAspm */ + PCIE_3_RST, /* mResetId */ + 0) /* mClkPmSupport */ + }, +}; +static const PCIe_COMPLEX_DESCRIPTOR PcieNoBayhub = { + .Flags = DESCRIPTOR_TERMINATE_LIST, + .SocketId = 0, + .PciePortList = (void *)PortListNoBayhub, + .DdiLinkList = (void *)DdiList +}; + /*---------------------------------------------------------------------------*/ /** * OemCustomizeInitEarly @@ -148,4 +241,10 @@ InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex; InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus; InitEarly->PlatformConfig.GnbAzI2sBusPinConfig = GnbAcp2Tx4RxBluetooth; + + /* Completely disable Bayhub EMMC bridge on Proto with board_id 0 */ + /* Todo: Remove when we're done with Proto */ + if (board_id() == 0) + InitEarly->GnbConfig.PcieComplexList = (void *)&PcieNoBayhub; + } -- To view, visit https://review.coreboot.org/25015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I635356d41bab637726594d403d66dde730f12256 Gerrit-Change-Number: 25015 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: ec/google/chromeec: Add boardid.c to bootblock
by Martin Roth (Code Review) 06 Mar '18

06 Mar '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/25014 Change subject: ec/google/chromeec: Add boardid.c to bootblock ...................................................................... ec/google/chromeec: Add boardid.c to bootblock Update build so that we can get the board ID in bootblock. BUG=b:74248569 TEST=build and boot grunt with follow-on patch. Bayhub part is disabled. Change-Id: I6353bcb4abcef4e8dc2b625082e33b73525c8525 Signed-off-by: Martin Roth <martinroth(a)chromium.org> --- M src/ec/google/chromeec/Makefile.inc 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/25014/1 diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 7b43f63..240b16a 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_EC_GOOGLE_CHROMEEC),y) +bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDID) += ec_boardid.c romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDID) += ec_boardid.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDID) += ec_boardid.c -- To view, visit https://review.coreboot.org/25014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6353bcb4abcef4e8dc2b625082e33b73525c8525 Gerrit-Change-Number: 25014 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: soc/intel/common/block/gspi: set cs polarity before using
by build bot (Jenkins) (Code Review) 06 Mar '18

06 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25013 ) Change subject: soc/intel/common/block/gspi: set cs polarity before using ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22750/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68314/ : SUCCESS -- To view, visit https://review.coreboot.org/25013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I20b4f584663477d751a07889bccc865efbf9c469 Gerrit-Change-Number: 25013 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Mar 2018 21:28:17 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/common/block/gspi: set cs polarity before using
by Nick Vaccaro (Code Review) 06 Mar '18

06 Mar '18

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/25013 Change subject: soc/intel/common/block/gspi: set cs polarity before using ...................................................................... soc/intel/common/block/gspi: set cs polarity before using Move call to __gspi_cs_change() in gspi_ctrlr_setup() to after initialization of cs polarity since it requires polarity to be set to work properly. Failure to do so confuses cr50. BUG=b:70628116 BRANCH=chromeos-2016.05 TEST='emerge-meowth coreboot' and verify on scope that chip select polarity is correct for the first transaction. Change-Id: I20b4f584663477d751a07889bccc865efbf9c469 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/soc/intel/common/block/gspi/gspi.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/25013/1 diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 2f574a4..60c7391 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -414,9 +414,6 @@ /* Take controller out of reset, keeping DMA in reset. */ gspi_write_mmio_reg(p, RESETS, CTRLR_ACTIVE | DMA_RESET); - /* De-assert chip select. */ - __gspi_cs_change(p, CS_DEASSERT); - /* * CS control: * - Set SW mode. @@ -430,6 +427,9 @@ cs_ctrl |= gspi_csctrl_state(pol, CS_DEASSERT); gspi_write_mmio_reg(p, SPI_CS_CONTROL, cs_ctrl); + /* De-assert chip select. */ + __gspi_cs_change(p, CS_DEASSERT); + /* Disable SPI controller. */ gspi_write_mmio_reg(p, SSCR0, SSCR0_SSE_DISABLE); -- To view, visit https://review.coreboot.org/25013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I20b4f584663477d751a07889bccc865efbf9c469 Gerrit-Change-Number: 25013 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com>

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Change in coreboot[master]: util/gitconfig/test: Add shellcheck test
by build bot (Jenkins) (Code Review) 06 Mar '18

06 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23283 ) Change subject: util/gitconfig/test: Add shellcheck test ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22748/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68312/ : SUCCESS -- To view, visit https://review.coreboot.org/23283 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2792f28e1ce14bb0b3097924eedfe520780ddc49 Gerrit-Change-Number: 23283 Gerrit-PatchSet: 4 Gerrit-Owner: Alex Thiessen <alex.thiessen.de+coreboot(a)gmail.com> Gerrit-Reviewer: Alex Thiessen <alex.thiessen.de+coreboot(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Mar 2018 21:03:09 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: util/gitconfig: support pre-v2.5.0 git
by build bot (Jenkins) (Code Review) 06 Mar '18

06 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24981 ) Change subject: util/gitconfig: support pre-v2.5.0 git ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22749/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68313/ : SUCCESS -- To view, visit https://review.coreboot.org/24981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I232499c51e30bee546994eedcd2534642cd534e6 Gerrit-Change-Number: 24981 Gerrit-PatchSet: 2 Gerrit-Owner: Alex Thiessen <alex.thiessen.de+coreboot(a)gmail.com> Gerrit-Reviewer: Alex Thiessen <alex.thiessen.de+coreboot(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: T Michael Turney <mturney(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Mar 2018 21:01:55 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: util/gitconfig/test: Add commit-msg hook test
by build bot (Jenkins) (Code Review) 06 Mar '18

06 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23281 ) Change subject: util/gitconfig/test: Add commit-msg hook test ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22747/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68311/ : SUCCESS -- To view, visit https://review.coreboot.org/23281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icdaf0109c60cb5b6952b1a2468ab050a742e4201 Gerrit-Change-Number: 23281 Gerrit-PatchSet: 4 Gerrit-Owner: Alex Thiessen <alex.thiessen.de+coreboot(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Mar 2018 20:57:58 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: util/gitconfig: Add timeout test
by build bot (Jenkins) (Code Review) 06 Mar '18

06 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23280 ) Change subject: util/gitconfig: Add timeout test ...................................................................... Patch Set 5: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22745/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68309/ : SUCCESS -- To view, visit https://review.coreboot.org/23280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id46f905b9f782e67be97a65d10045c3345dc996b Gerrit-Change-Number: 23280 Gerrit-PatchSet: 5 Gerrit-Owner: Alex Thiessen <alex.thiessen.de+coreboot(a)gmail.com> Gerrit-Reviewer: Alex Thiessen <alex.thiessen.de+coreboot(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Mar 2018 20:57:11 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: util/gitconfig/test: Add shellcheck test
by build bot (Jenkins) (Code Review) 06 Mar '18

06 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23283 ) Change subject: util/gitconfig/test: Add shellcheck test ...................................................................... Patch Set 3: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/22746/ : ABORTED https://qa.coreboot.org/job/coreboot-gerrit/68310/ : ABORTED -- To view, visit https://review.coreboot.org/23283 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2792f28e1ce14bb0b3097924eedfe520780ddc49 Gerrit-Change-Number: 23283 Gerrit-PatchSet: 3 Gerrit-Owner: Alex Thiessen <alex.thiessen.de+coreboot(a)gmail.com> Gerrit-Reviewer: Alex Thiessen <alex.thiessen.de+coreboot(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Mar 2018 20:53:59 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit March 2018