coreboot-gerrit February 2018

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Change in coreboot[master]: purism/librem_skl: Enable TPM support
by Youness Alaoui (Code Review) 10 Feb '18

10 Feb '18

Youness Alaoui has uploaded this change for review. ( https://review.coreboot.org/23683 Change subject: purism/librem_skl: Enable TPM support ...................................................................... purism/librem_skl: Enable TPM support Change the GPIO to match the TPM-enabled motherboards, and add TPM support in devicetree and enable the config. After changing the GPIO table, the librem 13v2 and librem 15v3 now have the same GPIOs, so use a single gpio.h file instead of one file per variant. Change-Id: I425654c1c972118aa81c27961246238c2eef782d Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> --- M src/mainboard/purism/librem_skl/Kconfig M src/mainboard/purism/librem_skl/Makefile.inc R src/mainboard/purism/librem_skl/gpio.h M src/mainboard/purism/librem_skl/ramstage.c M src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb D src/mainboard/purism/librem_skl/variants/librem15v3/include/variant/gpio.h 7 files changed, 16 insertions(+), 211 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/23683/1 diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index f68fd23..be4b7a3 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -9,6 +9,7 @@ select SERIRQ_CONTINUOUS_MODE select MAINBOARD_USES_FSP2_0 select SPD_READ_BY_WORD + select MAINBOARD_HAS_LPC_TPM if BOARD_PURISM_BASEBOARD_LIBREM_SKL diff --git a/src/mainboard/purism/librem_skl/Makefile.inc b/src/mainboard/purism/librem_skl/Makefile.inc index 18c9ad6..eb01360 100644 --- a/src/mainboard/purism/librem_skl/Makefile.inc +++ b/src/mainboard/purism/librem_skl/Makefile.inc @@ -19,4 +19,3 @@ ramstage-y += ramstage.c ramstage-y += hda_verb.c -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/include/variant/gpio.h b/src/mainboard/purism/librem_skl/gpio.h similarity index 93% rename from src/mainboard/purism/librem_skl/variants/librem13v2/include/variant/gpio.h rename to src/mainboard/purism/librem_skl/gpio.h index 148e40b..e3328a3 100644 --- a/src/mainboard/purism/librem_skl/variants/librem13v2/include/variant/gpio.h +++ b/src/mainboard/purism/librem_skl/gpio.h @@ -41,9 +41,9 @@ /* SUSACK# */ PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1), /* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), /* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), -/* ISH_GP0 */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), +/* ISH_GP0 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A18, NONE, DEEP), +/* ISH_GP1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A19, NONE, DEEP), +/* ISH_GP2 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A20, NONE, DEEP), /* ISH_GP3 */ PAD_CFG_NC(GPP_A21), /* ISH_GP4 */ PAD_CFG_NC(GPP_A22), /* ISH_GP5 */ PAD_CFG_NC(GPP_A23), @@ -108,18 +108,18 @@ /* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6), /* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), /* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CS# */ PAD_CFG_NC(GPP_D9), -/* ISH_SPI_CLK */ PAD_CFG_NC(GPP_D10), -/* ISH_SPI_MISO */ PAD_CFG_NC(GPP_D11), +/* ISH_SPI_CS# */ PAD_CFG_TERM_GPO(GPP_D9, 0, NONE, DEEP), +/* ISH_SPI_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, DEEP), +/* ISH_SPI_MISO */ PAD_CFG_TERM_GPO(GPP_D11, 1, NONE, DEEP), /* ISH_SPI_MOSI */ PAD_CFG_NC(GPP_D12), /* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), /* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), /* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), /* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), /* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), -/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), +/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, DN_20K, DEEP, NF1), /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), -/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), +/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, DN_20K, DEEP, NF1), /* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), /* SPI1_IO3 */ PAD_CFG_NC(GPP_D22), /* I2S_MCLK */ PAD_CFG_NC(GPP_D23), diff --git a/src/mainboard/purism/librem_skl/ramstage.c b/src/mainboard/purism/librem_skl/ramstage.c index 15912cf..94f8071 100644 --- a/src/mainboard/purism/librem_skl/ramstage.c +++ b/src/mainboard/purism/librem_skl/ramstage.c @@ -15,7 +15,7 @@ */ #include <soc/ramstage.h> -#include <variant/gpio.h> +#include "gpio.h" void mainboard_silicon_init_params(FSP_SIL_UPD *params) { diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb index 1fc19a5..e2e2ac0 100644 --- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb @@ -195,6 +195,9 @@ chip ec/purism/librem device pnp 0c09.0 on end end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb index 647f054..6cf183a 100644 --- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb @@ -202,6 +202,9 @@ chip ec/purism/librem device pnp 0c09.0 on end end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/include/variant/gpio.h b/src/mainboard/purism/librem_skl/variants/librem15v3/include/variant/gpio.h deleted file mode 100644 index 9c22f00..0000000 --- a/src/mainboard/purism/librem_skl/variants/librem15v3/include/variant/gpio.h +++ /dev/null @@ -1,201 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_GPIO_H -#define MAINBOARD_GPIO_H - -#include <soc/gpe.h> -#include <soc/gpio.h> - -#ifndef __ACPI__ - -/* Pad configuration in ramstage. */ -static const struct pad_config gpio_table[] = { -/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LAD0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), -/* LAD1 */ PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), -/* LAD2 */ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), -/* LAD3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), -/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), -/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* PIRQA# */ PAD_CFG_NC(GPP_A7), -/* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), -/* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), -/* CLKOUT_LPC1 */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), -/* PME# */ PAD_CFG_NC(GPP_A11), -/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), -/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), -/* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), -/* SUSACK# */ PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1), -/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), -/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), -/* ISH_GP0 */ PAD_CFG_GPI(GPP_A18, NONE, DEEP), -/* ISH_GP1 */ PAD_CFG_GPI(GPP_A19, NONE, DEEP), -/* ISH_GP2 */ PAD_CFG_GPI(GPP_A20, NONE, DEEP), -/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), - -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), -/* VRALERT# */ PAD_CFG_NC(GPP_B2), -/* CPU_GP2 */ PAD_CFG_NC(GPP_B3), -/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), -/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), -/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), -/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), -/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), -/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), -/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), -/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11), -/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), -/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* SPKR */ PAD_CFG_TERM_GPO(GPP_B14, 1, DN_20K, DEEP), -/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), -/* GSPI0_CLK */ PAD_CFG_NC(GPP_B16), -/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17), -/* GSPI0_MOSI */ PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT), -/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), -/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20), -/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21), -/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1), -/* SM1ALERT# */ PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP), - -/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), -/* SMBDATA */ PAD_CFG_NF(GPP_C1, DN_20K, DEEP, NF1), -/* SMBALERT# */ PAD_CFG_TERM_GPO(GPP_C2, 1, DN_20K, DEEP), -/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), -/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), -/* SML0ALERT# */ PAD_CFG_GPI_APIC_INVERT(GPP_C5, DN_20K, DEEP), -/* SML1CLK */ PAD_CFG_NC(GPP_C6), /* RESERVED */ -/* SML1DATA */ PAD_CFG_NC(GPP_C7), /* RESERVED */ -/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), -/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), -/* UART0_RTS# */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), -/* UART0_CTS# */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), -/* UART1_RXD */ PAD_CFG_NC(GPP_C12), -/* UART1_TXD */ PAD_CFG_NC(GPP_C13), -/* UART1_RTS# */ PAD_CFG_NC(GPP_C14), -/* UART1_CTS# */ PAD_CFG_NC(GPP_C15), -/* I2C0_SDA */ PAD_CFG_GPI(GPP_C16, NONE, DEEP), -/* I2C0_SCL */ PAD_CFG_GPI(GPP_C17, NONE, DEEP), -/* I2C1_SDA */ PAD_CFG_GPI(GPP_C18, NONE, DEEP), -/* I2C1_SCL */ PAD_CFG_NC(GPP_C19), -/* UART2_RXD */ PAD_CFG_NC(GPP_C20), -/* UART2_TXD */ PAD_CFG_NC(GPP_C21), -/* UART2_RTS# */ PAD_CFG_NC(GPP_C22), -/* UART2_CTS# */ PAD_CFG_NC(GPP_C23), - -/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), -/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), -/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), -/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), -/* FASHTRIG */ PAD_CFG_NC(GPP_D4), -/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5), -/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6), -/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CS# */ PAD_CFG_TERM_GPO(GPP_D9, 0, NONE, DEEP), -/* ISH_SPI_CLK */ PAD_CFG_GPI(GPP_D10, NONE, DEEP), -/* ISH_SPI_MISO */ PAD_CFG_TERM_GPO(GPP_D11, 1, NONE, DEEP), -/* ISH_SPI_MOSI */ PAD_CFG_NC(GPP_D12), -/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), -/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), -/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), -/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), -/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), -/* SPI1_IO3 */ PAD_CFG_NC(GPP_D22), -/* I2S_MCLK */ PAD_CFG_NC(GPP_D23), - -/* SATAXPCI0 */ PAD_CFG_NC(GPP_E0), -/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), -/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1), -/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), -/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* CPU_GP1 */ PAD_CFG_NC(GPP_E7), -/* SATALED# */ PAD_CFG_NC(GPP_E8), -/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), -/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), -/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), -/* USB2_OC3# */ PAD_CFG_NC(GPP_E12), -/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), -/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), -/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, PLTRST, NONE), -/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), -/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), -/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1), -/* DDPD_CTRLCLK */ PAD_CFG_GPI_APIC(GPP_E22, NONE, DEEP), -/* DDPD_CTRLDATA */ PAD_CFG_TERM_GPO(GPP_E23, 1, DN_20K, DEEP), - -/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), -/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), -/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), -/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), -/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), -/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), -/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), -/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), -/* I2C5_SDA */ PAD_CFG_NC(GPP_F10), -/* I2C5_SCL */ PAD_CFG_NC(GPP_F11), -/* EMMC_CMD */ PAD_CFG_NC(GPP_F12), -/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13), -/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14), -/* EMMC_DATA2 */ PAD_CFG_NC(GPP_F15), -/* EMMC_DATA3 */ PAD_CFG_NC(GPP_F16), -/* EMMC_DATA4 */ PAD_CFG_NC(GPP_F17), -/* EMMC_DATA5 */ PAD_CFG_NC(GPP_F18), -/* EMMC_DATA6 */ PAD_CFG_NC(GPP_F19), -/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20), -/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21), -/* EMMC_CLK */ PAD_CFG_NC(GPP_F22), -/* RSVD */ PAD_CFG_NC(GPP_F23), - -/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), -/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), -/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), -/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), -/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), -/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), -/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), -/* SD_WP */ PAD_CFG_NF(GPP_G7, UP_20K, DEEP, NF1), - -/* BATLOW# */ PAD_CFG_NC(GPD0), -/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, PWROK, NF1), -/* LAN_WAKE# */ PAD_CFG_NC(GPD2), -/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), -/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), -/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), -/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), -/* RSVD */ PAD_CFG_NC(GPD7), -/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), -/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), -/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), -/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), -}; - -#endif - -#endif -- To view, visit https://review.coreboot.org/23683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I425654c1c972118aa81c27961246238c2eef782d Gerrit-Change-Number: 23683 Gerrit-PatchSet: 1 Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com>

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Change in coreboot[master]: soc/intel/skylake: Add IOMMU support
by Youness Alaoui (Code Review) 10 Feb '18

10 Feb '18

Youness Alaoui has uploaded this change for review. ( https://review.coreboot.org/23682 Change subject: soc/intel/skylake: Add IOMMU support ...................................................................... soc/intel/skylake: Add IOMMU support Sets up the IOMMU if VT-d is supported by the chipset. Once the MCHBAR and the IBDF/HBDF are set, the ACPI DMAR table should be properly filled with those values. This work is based on the IOMMU work on sandybridge [1] by Nico Huber. Tested on Purism Librem 13 v2 [1] Commits bb9469c4 and b2dae793 Change-Id: Ifadaa11340406d1da0f98813589d20118744cc6f Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> --- M src/soc/intel/skylake/Makefile.inc M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/skylake/include/soc/iomap.h A src/soc/intel/skylake/include/soc/iommu.h A src/soc/intel/skylake/iommu.c M src/soc/intel/skylake/romstage/systemagent.c M src/soc/intel/skylake/systemagent.c 7 files changed, 112 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/23682/1 diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index ef95cf7..a358f35 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -37,6 +37,7 @@ romstage-y += pmutil.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c romstage-y += spi.c +romstage-y += iommu.c romstage-$(CONFIG_UART_DEBUG) += uart.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 34cfaa3..0f97d1d 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -28,6 +28,7 @@ #include <intelblocks/smbus.h> #include <soc/bootblock.h> #include <soc/iomap.h> +#include <soc/iommu.h> #include <soc/p2sb.h> #include <soc/pch.h> #include <soc/pci_devs.h> @@ -59,6 +60,13 @@ * selected by bits 1:0 */ pci_write_config8(dev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT); + + /* Assign unique bus/dev/fn for I/O APIC and HPET */ + pci_write_config16(dev, PCH_P2SB_IBDF, + PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3); + + pci_write_config16(dev, PCH_P2SB_HBDF, + PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3); } void bootblock_pch_early_init(void) diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index 0a573ac..cc38e2e 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -54,6 +54,10 @@ #define HPET_BASE_ADDRESS 0xfed00000 +#define IOMMU_BASE_ADDRESS1 0xfed90000ULL +#define IOMMU_BASE_ADDRESS2 0xfed91000ULL +#define IOMMU_BASE_SIZE 0x1000 + #define PCH_PWRM_BASE_ADDRESS 0xfe000000 #define PCH_PWRM_BASE_SIZE 0x10000 diff --git a/src/soc/intel/skylake/include/soc/iommu.h b/src/soc/intel/skylake/include/soc/iommu.h new file mode 100644 index 0000000..56df714 --- /dev/null +++ b/src/soc/intel/skylake/include/soc/iommu.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Purism SPC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _SOC_IOMMU_H_ +#define _SOC_IOMMU_H_ + +#include <stdint.h> + +#define PCH_IOAPIC_PCI_BUS 0xF0 +#define PCH_IOAPIC_PCI_SLOT 0x1F + +#define PCH_HPET_PCI_BUS 0x00 +#define PCH_HPET_PCI_SLOT 0x1F + +void skylake_init_iommu(void); + +#endif diff --git a/src/soc/intel/skylake/iommu.c b/src/soc/intel/skylake/iommu.c new file mode 100644 index 0000000..81028de --- /dev/null +++ b/src/soc/intel/skylake/iommu.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> + +#include <device/device.h> +#include <intelblocks/systemagent.h> +#include <soc/iomap.h> +#include <soc/iommu.h> +#include <soc/pci_devs.h> +#include <soc/systemagent.h> + +void skylake_init_iommu(void) +{ + static const struct sa_mmio_descriptor iommu_fixed_mch_resources[] = { + {IOMMU1BAR, IOMMU_BASE_ADDRESS1, IOMMU_BASE_SIZE, "IOMMU1BAR"}, + {IOMMU2BAR, IOMMU_BASE_ADDRESS2, IOMMU_BASE_SIZE, "IOMMU2BAR"}, + }; + + if (pci_read_config32(SA_DEV_ROOT, CAPID0_A) & VTDD) + return; + + /* setup BARs */ + sa_set_mch_bar(iommu_fixed_mch_resources, + ARRAY_SIZE(iommu_fixed_mch_resources)); + + /* lock policies */ + write32((void *)(IOMMU_BASE_ADDRESS1 + 0xff0), 0x80000000); + + const struct device *const azalia = dev_find_slot(0, PCH_DEVFN_HDA); + if (azalia && azalia->enabled) { + write32((void *)(IOMMU_BASE_ADDRESS2 + 0xff0), 0x20000000); + write32((void *)(IOMMU_BASE_ADDRESS2 + 0xff0), 0xa0000000); + } else { + write32((void *)(IOMMU_BASE_ADDRESS2 + 0xff0), 0x80000000); + } +} diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c index 8f2fb33..e7a2f4a 100644 --- a/src/soc/intel/skylake/romstage/systemagent.c +++ b/src/soc/intel/skylake/romstage/systemagent.c @@ -18,6 +18,7 @@ #include <device/device.h> #include <intelblocks/systemagent.h> #include <soc/iomap.h> +#include <soc/iommu.h> #include <soc/romstage.h> #include <soc/systemagent.h> @@ -34,12 +35,15 @@ { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, }; - /* Set Fixed MMIO addresss into PCI configuration space */ + /* Set Fixed MMIO addresses into PCI configuration space */ sa_set_pci_bar(soc_fixed_pci_resources, ARRAY_SIZE(soc_fixed_pci_resources)); - /* Set Fixed MMIO addresss into MCH base address */ + /* Set Fixed MMIO addresses into MCH base address */ sa_set_mch_bar(soc_fixed_mch_resources, ARRAY_SIZE(soc_fixed_mch_resources)); - /* Enable PAM regisers */ + /* Enable PAM registers */ enable_pam_region(); + /* Enable IOMMU. This will set the IOMMU Fixed MMIO addresses into + * MCH base address if device has IOMMU capabilities */ + skylake_init_iommu(); } diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index 8af995d..880593d 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <cpu/x86/msr.h> #include <console/console.h> #include <delay.h> @@ -23,6 +24,7 @@ #include <soc/cpu.h> #include <soc/iomap.h> #include <soc/msr.h> +#include <soc/pci_devs.h> #include <soc/systemagent.h> /* @@ -42,9 +44,19 @@ { GDXCBAR, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE, "GDXCBAR" }, { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, }; + static const struct sa_mmio_descriptor iommu_fixed_resources[] = { + { IOMMU1BAR, IOMMU_BASE_ADDRESS1, IOMMU_BASE_SIZE, "IOMMU1" }, + { IOMMU2BAR, IOMMU_BASE_ADDRESS2, IOMMU_BASE_SIZE, "IOMMU2" }, + }; + struct device *const root_dev = dev_find_slot(0, SA_DEVFN_ROOT); sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, ARRAY_SIZE(soc_fixed_resources)); + + /* Add IOMMU Fixed resources only if we have VT-d capability. */ + if (root_dev && !(pci_read_config32(root_dev, CAPID0_A) & VTDD)) + sa_add_fixed_mmio_resources(dev, index, iommu_fixed_resources, + ARRAY_SIZE(iommu_fixed_resources)); } /* -- To view, visit https://review.coreboot.org/23682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifadaa11340406d1da0f98813589d20118744cc6f Gerrit-Change-Number: 23682 Gerrit-PatchSet: 1 Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com>

1 0

Change in coreboot[master]: soc/intel/skylake: Generate ACPI DMAR table
by Youness Alaoui (Code Review) 10 Feb '18

10 Feb '18

Youness Alaoui has uploaded this change for review. ( https://review.coreboot.org/23681 Change subject: soc/intel/skylake: Generate ACPI DMAR table ...................................................................... soc/intel/skylake: Generate ACPI DMAR table The DMAR ACPI table gets added if VT-d is supported and if IOMMU is enabled and properly configured. This code was influenced by Nico Huber's implementation [1]. [1] https://review.coreboot.org/#/c/coreboot/+/21588/ Change-Id: Iea48a349d60bdd2e7d3bc74b4e1036b050d2ae71 Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> --- M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/include/soc/acpi.h M src/soc/intel/skylake/include/soc/p2sb.h M src/soc/intel/skylake/include/soc/systemagent.h 6 files changed, 79 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/23681/1 diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index a0be5f5..42c7350 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -39,9 +39,11 @@ #include <soc/cpu.h> #include <soc/iomap.h> #include <soc/msr.h> +#include <soc/p2sb.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/ramstage.h> +#include <soc/systemagent.h> #include <string.h> #include <types.h> #include <vendorcode/google/chromeos/gnvs.h> @@ -341,6 +343,51 @@ fadt->x_gpe1_blk.addrh = 0x0; } +static unsigned long acpi_fill_dmar(unsigned long current) +{ + struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD); + struct device *const p2sb_dev = dev_find_slot(0, PCH_DEVFN_P2SB); + const u32 gfx_vtbar = MCHBAR32(IOMMU1BAR) & ~0xfff; + const u32 vtdpvc0_bar = MCHBAR32(IOMMU2BAR) & ~0xfff; + + /* iGFX has to be enabled, GFXVTBAR set and in 32-bit space. */ + if (igfx_dev && igfx_dev->enabled && + gfx_vtbar && !MCHBAR32(IOMMU1BAR + 4)) { + const unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, gfx_vtbar); + current += acpi_create_dmar_drhd_ds_pci(current, 0, 2, 0); + acpi_dmar_drhd_fixup(tmp, current); + } + + + /* General VTBAR has to be set and in 32-bit space. */ + if (p2sb_dev && vtdpvc0_bar && !MCHBAR32(IOMMU2BAR + 4)) { + const unsigned long tmp = current; + + /* P2SB may already be hidden. There's no clear rule, when. */ + const u8 p2sb_hidden = + pci_read_config8(p2sb_dev, PCH_P2SB_E0 + 1); + pci_write_config8(p2sb_dev, PCH_P2SB_E0 + 1, 0); + + const u16 ibdf = pci_read_config16(p2sb_dev, PCH_P2SB_IBDF); + const u16 hbdf = pci_read_config16(p2sb_dev, PCH_P2SB_HBDF); + + pci_write_config8(p2sb_dev, PCH_P2SB_E0 + 1, p2sb_hidden); + + current += acpi_create_dmar_drhd(current, + DRHD_INCLUDE_PCI_ALL, 0, vtdpvc0_bar); + current += acpi_create_dmar_drhd_ds_ioapic(current, + 2, ibdf >> 8, PCI_SLOT(ibdf), PCI_FUNC(ibdf)); + current += acpi_create_dmar_drhd_ds_msi_hpet(current, + 0, hbdf >> 8, PCI_SLOT(hbdf), PCI_FUNC(hbdf)); + + acpi_dmar_drhd_fixup(tmp, current); + } + + return current; +} + static void generate_c_state_entries(int s0ix_enable, int max_cstate) { @@ -566,6 +613,27 @@ return acpi_align_current(current); } +unsigned long northbridge_write_acpi_tables(device_t device, + unsigned long current, + struct acpi_rsdp *rsdp) +{ + acpi_dmar_t *const dmar = (acpi_dmar_t *) current; + struct device *const root_dev = dev_find_slot(0, SA_DEVFN_ROOT); + + /* Create DMAR table only if we have VT-d capability. */ + if (!root_dev || pci_read_config32(root_dev, CAPID0_A) & VTDD) + return current; + + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + + acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar); + if (dmar->header.length > sizeof(acpi_dmar_t)) { + current += dmar->header.length; + acpi_add_table(rsdp, dmar); + } + return acpi_align_current(current); +} + void southbridge_inject_dsdt(device_t device) { global_nvs_t *gnvs; diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index f60c08d..f2fd9fe 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -49,6 +49,7 @@ .scan_bus = &pci_domain_scan_bus, .ops_pci_bus = &pci_bus_default_ops, #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .write_acpi_tables = &northbridge_write_acpi_tables, .acpi_name = &soc_acpi_name, #endif }; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 3bc66b2..abfb049 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -57,6 +57,7 @@ .scan_bus = &pci_domain_scan_bus, .ops_pci_bus = &pci_bus_default_ops, #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .write_acpi_tables = &northbridge_write_acpi_tables, .acpi_name = &soc_acpi_name, #endif }; diff --git a/src/soc/intel/skylake/include/soc/acpi.h b/src/soc/intel/skylake/include/soc/acpi.h index b0d2194..d9524e6 100644 --- a/src/soc/intel/skylake/include/soc/acpi.h +++ b/src/soc/intel/skylake/include/soc/acpi.h @@ -32,5 +32,7 @@ void southbridge_inject_dsdt(device_t device); unsigned long southbridge_write_acpi_tables(device_t device, unsigned long current, struct acpi_rsdp *rsdp); +unsigned long northbridge_write_acpi_tables(device_t device, + unsigned long current, struct acpi_rsdp *rsdp); #endif /* _SOC_ACPI_H_ */ diff --git a/src/soc/intel/skylake/include/soc/p2sb.h b/src/soc/intel/skylake/include/soc/p2sb.h index d846dfc..9fb2653 100644 --- a/src/soc/intel/skylake/include/soc/p2sb.h +++ b/src/soc/intel/skylake/include/soc/p2sb.h @@ -19,6 +19,9 @@ #define HPTC_OFFSET 0x60 #define HPTC_ADDR_ENABLE_BIT (1 << 7) +#define PCH_P2SB_IBDF 0x6C +#define PCH_P2SB_HBDF 0x70 + #define PCH_P2SB_EPMASK0 0xB0 #define PCH_P2SB_EPMASK(mask_number) (PCH_P2SB_EPMASK0 + ((mask_number) * 4)) diff --git a/src/soc/intel/skylake/include/soc/systemagent.h b/src/soc/intel/skylake/include/soc/systemagent.h index d8192a3..54ff121 100644 --- a/src/soc/intel/skylake/include/soc/systemagent.h +++ b/src/soc/intel/skylake/include/soc/systemagent.h @@ -32,9 +32,13 @@ #define D_LCK (1 << 4) #define G_SMRAME (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define CAPID0_A 0x94 +#define VTDD (1 << 23) #define BIOS_RESET_CPL 0x5da8 #define EDRAMBAR 0x5408 +#define IOMMU1BAR 0x5400 +#define IOMMU2BAR 0x5410 #define GDXCBAR 0x5420 #define MCH_PKG_POWER_LIMIT_LO 0x59a0 -- To view, visit https://review.coreboot.org/23681 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iea48a349d60bdd2e7d3bc74b4e1036b050d2ae71 Gerrit-Change-Number: 23681 Gerrit-PatchSet: 1 Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com>

1 0

Change in coreboot[master]: intel/fsp: Fix TPM initialization when vboot is disabled
by Youness Alaoui (Code Review) 10 Feb '18

10 Feb '18

Youness Alaoui has uploaded this change for review. ( https://review.coreboot.org/23680 Change subject: intel/fsp: Fix TPM initialization when vboot is disabled ...................................................................... intel/fsp: Fix TPM initialization when vboot is disabled A change introduced by commit fe4983e5 [1] in order to prevent re-initialization of the TPM if already setup in verstage had the wrong logic in the if statement, causing the TPM to never be initialized if vboot is disabled. The RESUME_PATH_SAME_AS_BOOT config is enabled by default for ARCH_X86 and therefore the if statement would be false. The behavior that was intended was probably meant to use an OR instead of an AND. [1] https://review.coreboot.org/#/c/coreboot/+/14106/ Change-Id: Ic43d1aa31a296386c7eab6d997f9b701e9ea0fe5 Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> --- M src/drivers/intel/fsp1_1/romstage.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/23680/1 diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 69ea786..6c80ce7 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -172,8 +172,8 @@ * in verstage and used to verify romstage. */ if (IS_ENABLED(CONFIG_LPC_TPM) && - !IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && - !IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK)) + (!IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) || + !IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK))) init_tpm(params->power_state->prev_sleep_state == ACPI_S3); } -- To view, visit https://review.coreboot.org/23680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic43d1aa31a296386c7eab6d997f9b701e9ea0fe5 Gerrit-Change-Number: 23680 Gerrit-PatchSet: 1 Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com>

1 0

Change in coreboot[master]: DRAFT: Normalize GPIO initialization on kahlee.
by Justin TerAvest (Code Review) 09 Feb '18

09 Feb '18

Justin TerAvest has uploaded this change for review. ( https://review.coreboot.org/23679 Change subject: DRAFT: Normalize GPIO initialization on kahlee. ...................................................................... DRAFT: Normalize GPIO initialization on kahlee. This makes the flow for GPIO initialization more closely folllow that for other boards. Note: This will probably break gardenia so this can't go in as is, but I'm curious about comments on the strategy here. Change-Id: Ic97db96581a69798b193a6bdeb93644f6a74fc9d Signed-off-by: Justin TerAvest <teravest(a)chromium.org> --- M src/mainboard/google/kahlee/Makefile.inc M src/mainboard/google/kahlee/bootblock/bootblock.c A src/mainboard/google/kahlee/ramstage.c M src/mainboard/google/kahlee/variants/baseboard/gpio.c M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/kahlee/variants/kahlee/gpio.c M src/soc/amd/stoneyridge/bootblock/bootblock.c M src/soc/amd/stoneyridge/chip.c A src/soc/amd/stoneyridge/include/soc/ramstage.h M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 11 files changed, 86 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/23679/1 diff --git a/src/mainboard/google/kahlee/Makefile.inc b/src/mainboard/google/kahlee/Makefile.inc index 770a999..514373e 100644 --- a/src/mainboard/google/kahlee/Makefile.inc +++ b/src/mainboard/google/kahlee/Makefile.inc @@ -25,6 +25,7 @@ ramstage-y += chromeos.c ramstage-y += ec.c ramstage-y += OemCustomize.c +ramstage-y += ramstage.c verstage-y += chromeos.c verstage-y += ec.c diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c index 90c8acb..244abe0 100644 --- a/src/mainboard/google/kahlee/bootblock/bootblock.c +++ b/src/mainboard/google/kahlee/bootblock/bootblock.c @@ -13,12 +13,18 @@ * GNU General Public License for more details. */ +#include <baseboard/variants.h> #include <bootblock_common.h> #include <soc/southbridge.h> #include <variant/ec.h> void bootblock_mainboard_init(void) { + size_t num_gpios; + const struct soc_amd_stoneyridge_gpio *gpios; + gpios = variant_early_gpio_table(&num_gpios); + sb_program_gpios(gpios, num_gpios); + /* Enable the EC as soon as we have visibility */ mainboard_ec_init(); diff --git a/src/mainboard/google/kahlee/ramstage.c b/src/mainboard/google/kahlee/ramstage.c new file mode 100644 index 0000000..7fdf495 --- /dev/null +++ b/src/mainboard/google/kahlee/ramstage.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <soc/ramstage.h> +#include <soc/southbridge.h> + +void ramstage_mainboard_init(void) +{ + size_t num_gpios; + const struct soc_amd_stoneyridge_gpio *gpios; + gpios = variant_gpio_table(&num_gpios); + sb_program_gpios(gpios, num_gpios); +} + diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index a6bcea5..8d90174 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -258,13 +258,14 @@ { GPIO_135, Function1, FCH_GPIO_PULL_UP_ENABLE | INPUT }, }; -const __attribute__((weak)) const struct soc_amd_stoneyridge_gpio - *board_get_gpio(size_t *size) +const struct soc_amd_stoneyridge_gpio *variant_early_gpio_table(size_t *size) { - if (GPIO_TABLE_BOOTBLOCK) { - *size = ARRAY_SIZE(gpio_set_stage_reset); - return gpio_set_stage_reset; - } + *size = ARRAY_SIZE(gpio_set_stage_reset); + return gpio_set_stage_reset; +} + +const struct soc_amd_stoneyridge_gpio *variant_gpio_table(size_t *size) +{ *size = ARRAY_SIZE(gpio_set_stage_ram); return gpio_set_stage_ram; } diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h index bf14ef4..5bbc11d 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h @@ -26,5 +26,7 @@ int variant_mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len); int variant_get_xhci_oc_map(uint16_t *usb_oc_map); int variant_get_ehci_oc_map(uint16_t *usb_oc_map); +const struct soc_amd_stoneyridge_gpio *variant_early_gpio_table(size_t *size); +const struct soc_amd_stoneyridge_gpio *variant_gpio_table(size_t *size); #endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/kahlee/variants/kahlee/gpio.c b/src/mainboard/google/kahlee/variants/kahlee/gpio.c index e357c7e..d1cc017 100644 --- a/src/mainboard/google/kahlee/variants/kahlee/gpio.c +++ b/src/mainboard/google/kahlee/variants/kahlee/gpio.c @@ -96,12 +96,14 @@ {GPIO_119, Function2, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H }, }; -const struct soc_amd_stoneyridge_gpio *board_get_gpio(size_t *size) +const struct soc_amd_stoneyridge_gpio *variant_early_gpio_table(size_t *size) { - if (GPIO_TABLE_BOOTBLOCK) { - *size = ARRAY_SIZE(gpio_set_stage_reset); - return gpio_set_stage_reset; - } + *size = ARRAY_SIZE(gpio_set_stage_reset); + return gpio_set_stage_reset; +} + +const struct soc_amd_stoneyridge_gpio *variant_gpio_table(size_t *size) +{ *size = ARRAY_SIZE(gpio_set_stage_ram); return gpio_set_stage_ram; } diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index 709b413..3eff5eb 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -125,8 +125,6 @@ post_code(0x37); do_agesawrapper(agesawrapper_amdinitreset, "amdinitreset"); - sb_program_gpio(); - post_code(0x38); /* APs will not exit amdinitearly */ do_agesawrapper(agesawrapper_amdinitearly, "amdinitearly"); diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index d3a8bc4..bd48c74 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -24,6 +24,7 @@ #include <soc/cpu.h> #include <soc/northbridge.h> #include <soc/pci_devs.h> +#include <soc/ramstage.h> #include <soc/southbridge.h> #include <amdblocks/psp.h> #include <amdblocks/agesawrapper.h> @@ -89,9 +90,16 @@ dev->ops = &stoneyridge_i2c_mmio_ops; } +/* Mainboard GPIO configuration */ +__attribute__((weak)) void ramstage_mainboard_init(void) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + static void soc_init(void *chip_info) { southbridge_init(chip_info); + ramstage_mainboard_init(); setup_bsp_ramtop(); } diff --git a/src/soc/amd/stoneyridge/include/soc/ramstage.h b/src/soc/amd/stoneyridge/include/soc/ramstage.h new file mode 100644 index 0000000..014c48b --- /dev/null +++ b/src/soc/amd/stoneyridge/include/soc/ramstage.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_RAMSTAGE_H_ +#define _SOC_RAMSTAGE_H_ + +void ramstage_mainboard_init(void); + +#endif diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index f4d6b17..259e8b5 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -350,9 +350,13 @@ /** * @brief program a particular set of GPIO * + * @param gpio_ptr = pointer to array of gpio configurations + * @param size = number of entries in array + * * @return none */ -void sb_program_gpio(void); +void sb_program_gpios(const struct soc_amd_stoneyridge_gpio *gpio_ptr, + size_t size); /** * @brief Find the size of a particular wide IO * diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 735642f..a14213f 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -155,15 +155,13 @@ return irq_association; } -void sb_program_gpio(void) +void sb_program_gpios(const struct soc_amd_stoneyridge_gpio *gpio_ptr, + size_t size) { void *tmp_ptr; - const struct soc_amd_stoneyridge_gpio *gpio_ptr; - size_t size; uint8_t control, mux, index; printk(BIOS_SPEW, "GPIO programming stage %s\n", STR_GPIO_STAGE); - gpio_ptr = board_get_gpio(&size); for (index = 0; index < size; index++) { mux = gpio_ptr[index].function; control = gpio_ptr[index].control; @@ -181,14 +179,6 @@ printk(BIOS_SPEW, "End GPIO programming\n"); } -static void sb_program_gpio_ram(void *unused) -{ - sb_program_gpio(); -} - -BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, - sb_program_gpio_ram, NULL); - /** * @brief Find the size of a particular wide IO * -- To view, visit https://review.coreboot.org/23679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic97db96581a69798b193a6bdeb93644f6a74fc9d Gerrit-Change-Number: 23679 Gerrit-PatchSet: 1 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org>

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Change in coreboot[master]: intel/fsp: Update cannonlake fsp header
by build bot (Jenkins) (Code Review) 09 Feb '18

09 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23677 ) Change subject: intel/fsp: Update cannonlake fsp header ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67302/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21848/ : SUCCESS -- To view, visit https://review.coreboot.org/23677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I32e976eacf39d2cd75f8288c86d1de1a54c194c6 Gerrit-Change-Number: 23677 Gerrit-PatchSet: 3 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Feb 2018 21:44:52 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: intel/fsp: Update cannonlake fsp header
by build bot (Jenkins) (Code Review) 09 Feb '18

09 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23677 ) Change subject: intel/fsp: Update cannonlake fsp header ...................................................................... Patch Set 2: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/67301/ : UNSTABLE -- To view, visit https://review.coreboot.org/23677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I32e976eacf39d2cd75f8288c86d1de1a54c194c6 Gerrit-Change-Number: 23677 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Feb 2018 21:16:29 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: intel/fsp: Update cannonlake fsp header
by build bot (Jenkins) (Code Review) 09 Feb '18

09 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23677 ) Change subject: intel/fsp: Update cannonlake fsp header ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/67300/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/21847/ : ABORTED -- To view, visit https://review.coreboot.org/23677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I32e976eacf39d2cd75f8288c86d1de1a54c194c6 Gerrit-Change-Number: 23677 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Feb 2018 21:11:22 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: intel/fsp: Update cannonlake fsp header
by Lijian Zhao (Code Review) 09 Feb '18

09 Feb '18

Lijian Zhao has uploaded a new patch set (#2). ( https://review.coreboot.org/23677 ) Change subject: intel/fsp: Update cannonlake fsp header ...................................................................... intel/fsp: Update cannonlake fsp header Update Cannonlake FSP header to revision 7.x.25.31. Following changes had been made: 1. Add PeciSxRest option. 2. Add Thermal Velocity Boost option. 3. Add VR power deliver design option. 4. Match MrcChannelSts. TEST=NONE Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I32e976eacf39d2cd75f8288c86d1de1a54c194c6 --- M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h A src/vendorcode/intel/fsp/fsp2_0/cannonlake/FsptUpd.h M src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h 4 files changed, 207 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/23677/2 -- To view, visit https://review.coreboot.org/23677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I32e976eacf39d2cd75f8288c86d1de1a54c194c6 Gerrit-Change-Number: 23677 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

1 0

Change in coreboot[master]: intel/fsp: Update cannonlake fsp header
by Lijian Zhao (Code Review) 09 Feb '18

09 Feb '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/23677 Change subject: intel/fsp: Update cannonlake fsp header ...................................................................... intel/fsp: Update cannonlake fsp header Update Cannonlake FSP header to revision 7.x.25.31. Following changes had been made: TBD TEST=NONE Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I32e976eacf39d2cd75f8288c86d1de1a54c194c6 --- M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h A src/vendorcode/intel/fsp/fsp2_0/cannonlake/FsptUpd.h M src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h 4 files changed, 207 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/23677/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h index d504f96..d014f81 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h @@ -474,9 +474,21 @@ **/ UINT8 CpuTraceHubMemReg1Size; -/** Offset 0x00F6 +/** Offset 0x00F6 - Enable or Disable Peci C10 Reset command + Enable or Disable Peci C10 Reset command; 0: Disable; 1: Enable. + $EN_DIS **/ - UINT8 UnusedUpdSpace3[6]; + UINT8 PeciC10Reset; + +/** Offset 0x00F7 - Enable or Disable Peci Sx Reset command + Enable or Disable Peci Sx Reset command; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PeciSxReset; + +/** Offset 0x00F8 +**/ + UINT8 UnusedUpdSpace3[4]; /** Offset 0x00FC - Enable Intel HD Audio (Azalia) 0: Disable, 1: Enable (Default) Azalia controller @@ -691,9 +703,24 @@ **/ UINT8 DmiGen3RxCtlePeaking[4]; -/** Offset 0x0144 +/** Offset 0x0144 - Thermal Velocity Boost Ratio clipping + 0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction + caused by high package temperatures for processors that implement the Intel Thermal + Velocity Boost (TVB) feature + 0: Disabled, 1: Enabled **/ - UINT8 UnusedUpdSpace6[4]; + UINT8 TvbRatioClipping; + +/** Offset 0x0145 - Thermal Velocity Boost voltage optimization + 0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations + for processors that implement the Intel Thermal Velocity Boost (TVB) feature. + 0: Disabled, 1: Enabled +**/ + UINT8 TvbVoltageOptimization; + +/** Offset 0x0146 +**/ + UINT8 UnusedUpdSpace6[2]; /** Offset 0x0148 - PEG Gen3 RxCTLEp per-Bundle control Range: 0-15, 12 is default for each bundle, must be specified based upon platform design @@ -1374,8 +1401,8 @@ **/ UINT8 PchSmbAlertEnable; -/** Offset 0x0463 - ReservedSecurityPreMem - Reserved for Security Pre-Mem +/** Offset 0x0463 - ReservedPchPreMem + Reserved for Pch Pre-Mem $EN_DIS **/ UINT8 ReservedPchPreMem[13]; @@ -2428,7 +2455,7 @@ **/ UINT8 Gen3SwEqEnableVocTest; -/** Offset 0x0537 - PPCIe Rx Compliance Testing Mode +/** Offset 0x0537 - PCIe Rx Compliance Testing Mode Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1): PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode; it should only be set when doing PCIe compliance testing @@ -2522,7 +2549,7 @@ /** Offset 0x0583 - BdatTestType Indicates the type of Memory Training data to populate into the BDAT ACPI table. - 0:Rank Marign Tool, 1:Margin2D + 0:Rank Margin Tool, 1:Margin2D **/ UINT8 BdatTestType; @@ -2542,11 +2569,17 @@ **/ UINT16 BiosSize; -/** Offset 0x0594 - SecurityTestRsvd +/** Offset 0x0594 - TxtAcheckRequest + Enable/Disable. When Enabled, it will forcing calling TXT Acheck once. + $EN_DIS +**/ + UINT8 TxtAcheckRequest; + +/** Offset 0x0595 - SecurityTestRsvd Reserved for SA Pre-Mem Test $EN_DIS **/ - UINT8 SecurityTestRsvd[4]; + UINT8 SecurityTestRsvd[3]; /** Offset 0x0598 - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating. diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h index 0285dd1..0f3577a 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h @@ -1093,15 +1093,22 @@ **/ UINT16 ImonSlope1[5]; -/** Offset 0x0324 - ReservedCpuPostMemProduction +/** Offset 0x0324 - CPU VR Power Delivery Design + Used to communicate the power delivery design capability of the board. This value + is an enum of the available power delivery segments that are defined in the Platform + Design Guide. +**/ + UINT32 VrPowerDeliveryDesign; + +/** Offset 0x0328 - ReservedCpuPostMemProduction Reserved for CPU Post-Mem Production $EN_DIS **/ UINT8 ReservedCpuPostMemProduction[1]; -/** Offset 0x0325 +/** Offset 0x0329 **/ - UINT8 UnusedUpdSpace10[33]; + UINT8 UnusedUpdSpace10[29]; /** Offset 0x0346 - Enable DMI ASPM Deprecated. @@ -1869,7 +1876,6 @@ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5 pads termination respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on. - 0x1:None, 0x13:1kOhm WPU, 0x15:5kOhm WPU, 0x19:20kOhm WPU **/ UINT8 PchSerialIoI2cPadsTermination[6]; @@ -2283,7 +2289,7 @@ **/ UINT8 ChapDeviceEnable; -/** Offset 0x07B2 - Skip PAM regsiter lock +/** Offset 0x07B2 - Skip PAM register lock Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC $EN_DIS @@ -2830,9 +2836,10 @@ **/ UINT16 PsysPmax; -/** Offset 0x0858 +/** Offset 0x0858 - Interrupt Response Time Limit of C-State LatencyContol0 + Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF **/ - UINT8 Reserved0[2]; + UINT16 CstateLatencyControl0Irtl; /** Offset 0x085A - Interrupt Response Time Limit of C-State LatencyContol1 Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF @@ -3074,8 +3081,7 @@ UINT8 PchUnlockGpioPads; /** Offset 0x08C2 - PCH Unlock SBI access - This unlock the SBI lock bit to allow SBI after post time. 0: Lock SBI access; 1: - Unlock SBI access. + Deprecated $EN_DIS **/ UINT8 PchSbiUnlock; diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FsptUpd.h new file mode 100644 index 0000000..eeba7ae --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FsptUpd.h @@ -0,0 +1,136 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPTUPD_H__ +#define __FSPTUPD_H__ + +#include <FspUpd.h> + +#pragma pack(1) + + +/** Fsp T Core UPD +**/ +typedef struct { + +/** Offset 0x0020 +**/ + UINT32 MicrocodeRegionBase; + +/** Offset 0x0024 +**/ + UINT32 MicrocodeRegionSize; + +/** Offset 0x0028 +**/ + UINT32 CodeRegionBase; + +/** Offset 0x002C +**/ + UINT32 CodeRegionSize; + +/** Offset 0x0030 +**/ + UINT8 Reserved[16]; +} FSPT_CORE_UPD; + +/** Fsp T Configuration +**/ +typedef struct { + +/** Offset 0x0040 - PcdSerialIoUartDebugEnable + Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP. + 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing +**/ + UINT8 PcdSerialIoUartDebugEnable; + +/** Offset 0x0041 - PcdSerialIoUartNumber - FSPT + Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT + Core interface, it cannot be used for debug purpose. + 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 +**/ + UINT8 PcdSerialIoUartNumber; + +/** Offset 0x0042 - PcdSerialIoUart0PinMuxing - FSPT + Select SerialIo Uart0 pin muxing. Setting valid only if PcdSerialIoUartNumber is + set to UART0. + 0:default pins, 1:pins muxed with CNV_BRI/RGI +**/ + UINT8 PcdSerialIoUart0PinMuxing; + +/** Offset 0x0043 +**/ + UINT8 UnusedUpdSpace0; + +/** Offset 0x0044 +**/ + UINT32 PcdSerialIoUartInputClock; + +/** Offset 0x0048 - Pci Express Base Address + Base address to be programmed for Pci Express +**/ + UINT64 PcdPciExpressBaseAddress; + +/** Offset 0x0050 - Pci Express Region Length + Region Length to be programmed for Pci Express +**/ + UINT32 PcdPciExpressRegionLength; + +/** Offset 0x0054 +**/ + UINT8 ReservedFsptUpd1[44]; +} FSP_T_CONFIG; + +/** Fsp T UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPT_CORE_UPD FsptCoreUpd; + +/** Offset 0x0040 +**/ + FSP_T_CONFIG FsptConfig; + +/** Offset 0x0080 +**/ + UINT16 UpdTerminator; +} FSPT_UPD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h index 435eccb..941a891 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h @@ -84,6 +84,19 @@ } SiMrcVersion; // +// Matches MrcChannelSts enum in MRC +// +#ifndef CHANNEL_NOT_PRESENT +#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller. +#endif +#ifndef CHANNEL_DISABLED +#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled. +#endif +#ifndef CHANNEL_PRESENT +#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled. +#endif + +// // Matches MrcDimmSts enum in MRC // #ifndef DIMM_ENABLED -- To view, visit https://review.coreboot.org/23677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I32e976eacf39d2cd75f8288c86d1de1a54c194c6 Gerrit-Change-Number: 23677 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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coreboot-gerrit February 2018