coreboot-gerrit February 2018

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Change in coreboot[master]: soc/intel/common: Add generic PCR asl
by Lijian Zhao (Code Review) 12 Feb '18

12 Feb '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/23698 Change subject: soc/intel/common: Add generic PCR asl ...................................................................... soc/intel/common: Add generic PCR asl Access to PCH Private Configuration Space Register can be addressed via SBERG_BAR, the method is generic across several generations of Intel SOC. BUG=None TEST=None Change-Id: Iaf8c386824ee08cb93cb419ce3cdb2d3fe22a026 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- A src/soc/intel/common/acpi/pcr.asl 1 file changed, 90 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/23698/1 diff --git a/src/soc/intel/common/acpi/pcr.asl b/src/soc/intel/common/acpi/pcr.asl new file mode 100644 index 0000000..9dc77e2 --- /dev/null +++ b/src/soc/intel/common/acpi/pcr.asl @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/pcr.h> + +/* + * Calculate PCR register base at specified PID + * Arg0 - PCR Port ID + */ +Method (PCRB, 1, NotSerialized) +{ + Return (Add (CONFIG_PCR_BASE_ADDRESS, + ShiftLeft (Arg0, PCR_PORTID_SHIFT))) +} + +/* + * Read a PCR register at specified PID and offset + * Arg0 - PCR Port ID + * Arg1 - Register Offset + */ +Method (PCRR, 2, Serialized) +{ + OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4) + Field (PCRD, DWordAcc, NoLock, Preserve) + { + DATA, 32 + } + Return (DATA) +} + +/* + * AND a value with PCR register at specified PID and offset + * Arg0 - PCR Port ID + * Arg1 - Register Offset + * Arg2 - Value to AND + */ +Method (PCRA, 3, Serialized) +{ + OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4) + Field (PCRD, DWordAcc, NoLock, Preserve) + { + DATA, 32 + } + And (DATA, Arg2, DATA) + + /* + * After every write one needs to read an innocuous register + * to ensure the writes are completed for certain ports. This is done + * for all ports so that the callers don't need the per-port knowledge + * for each transaction. + */ + PCRR (Arg0, Arg1) +} + +/* + * OR a value with PCR register at specified PID and offset + * Arg0 - PCR Port ID + * Arg1 - Register Offset + * Arg2 - Value to OR + */ +Method (PCRO, 3, Serialized) +{ + OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4) + Field (PCRD, DWordAcc, NoLock, Preserve) + { + DATA, 32 + } + Or (DATA, Arg2, DATA) + + /* + * After every write one needs to read an innocuous register + * to ensure the writes are completed for certain ports. This is done + * for all ports so that the callers don't need the per-port knowledge + * for each transaction. + */ + PCRR (Arg0, Arg1) +} -- To view, visit https://review.coreboot.org/23698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iaf8c386824ee08cb93cb419ce3cdb2d3fe22a026 Gerrit-Change-Number: 23698 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: ec/chromeec: Fix battery ACPI mutex level
by build bot (Jenkins) (Code Review) 11 Feb '18

11 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23697 ) Change subject: ec/chromeec: Fix battery ACPI mutex level ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67332/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21877/ : SUCCESS -- To view, visit https://review.coreboot.org/23697 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icfb0817cfe0c49eb4527a12b507362939a6d32c6 Gerrit-Change-Number: 23697 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nicolas Boichat <drinkcat(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 11 Feb 2018 22:22:38 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: drivers/intel/gma: fix opregion SCI register for Atom platforms
by build bot (Jenkins) (Code Review) 11 Feb '18

11 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23696 ) Change subject: drivers/intel/gma: fix opregion SCI register for Atom platforms ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67331/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21876/ : SUCCESS -- To view, visit https://review.coreboot.org/23696 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I636986226ff951dae637dca5bc3ad0e023d94243 Gerrit-Change-Number: 23696 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 11 Feb 2018 22:15:14 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: ec/chromeec: Fix battery ACPI mutex level
by Matt DeVillier (Code Review) 11 Feb '18

11 Feb '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/23697 Change subject: ec/chromeec: Fix battery ACPI mutex level ...................................................................... ec/chromeec: Fix battery ACPI mutex level Commit 07fe618 [chromeec: Add support for reading second battery info] added a Mutex as part of the ACPI code to determine battery statuses. Windows is extremely picky about ACPI code, and attempting to acquire a level 1 mutex without first having acquired a level 0 mutex causes Windows to hang on boot. Since there's no reason to use a level 1 mutex here, change it to level 0. Test: Boot Windows on device with ChromeEC without hanging Change-Id: Icfb0817cfe0c49eb4527a12b507362939a6d32c6 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/ec/google/chromeec/acpi/battery.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/23697/1 diff --git a/src/ec/google/chromeec/acpi/battery.asl b/src/ec/google/chromeec/acpi/battery.asl index d8056b0..0a0caec 100644 --- a/src/ec/google/chromeec/acpi/battery.asl +++ b/src/ec/google/chromeec/acpi/battery.asl @@ -17,7 +17,7 @@ // Scope (EC0) /* Mutex for EC battery index interface */ -Mutex (BATM, 1) +Mutex (BATM, 0) // Wait for desired battery index to be presented in shared memory // Arg0 = battery index -- To view, visit https://review.coreboot.org/23697 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icfb0817cfe0c49eb4527a12b507362939a6d32c6 Gerrit-Change-Number: 23697 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: drivers/intel/gma: fix opregion SCI register for Atom platforms
by Matt DeVillier (Code Review) 11 Feb '18

11 Feb '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/23696 Change subject: drivers/intel/gma: fix opregion SCI register for Atom platforms ...................................................................... drivers/intel/gma: fix opregion SCI register for Atom platforms Most Intel platforms use separate registers for software-based SMI (0xe0) and SCI (0xe8), but Atom-based platforms use a single combined register (0xe0) for both. Adjust opregion implementation to use the correct register for Atom-based platforms. Test: Boot Windows on Atom-based ChromeOS device with Tianocore payload and non-VBIOS graphics init; observe Intel display driver loaded correctly and internal display not blank. Change-Id: I636986226ff951dae637dca5bc3ad0e023d94243 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/drivers/intel/gma/opregion.c M src/drivers/intel/gma/opregion.h 2 files changed, 15 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/23696/1 diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c index 74c629c..4565173 100644 --- a/src/drivers/intel/gma/opregion.c +++ b/src/drivers/intel/gma/opregion.c @@ -32,6 +32,7 @@ { device_t igd; u16 reg16; + u16 sci; igd = dev_find_slot(0, PCI_DEVFN(0x2, 0)); if (!igd || !igd->enabled) @@ -44,14 +45,25 @@ pci_write_config32(igd, ASLS, opregion); /* + * Atom-based platforms use a combined SMI/SCI register, + * whereas non-Atom platforms use a separate SCI register + */ + if (IS_ENABLED(CONFIG_SOC_INTEL_BAYTRAIL) || + IS_ENABLED(CONFIG_SOC_INTEL_BRASWELL) || + IS_ENABLED(CONFIG_SOC_INTEL_APOLLOLAKE)) + sci = SWSMISCI; + else + sci = SWSCI; + + /* * Intel's Windows driver relies on this: * Intel BIOS Specification * Chapter 5.4 "ASL Software SCI Handler" */ - reg16 = pci_read_config16(igd, SWSCI); + reg16 = pci_read_config16(igd, sci); reg16 &= ~GSSCIE; reg16 |= SMISCISEL; - pci_write_config16(igd, SWSCI, reg16); + pci_write_config16(igd, sci, reg16); } /* Restore ASLS register on S3 resume and prepare SWSCI. */ diff --git a/src/drivers/intel/gma/opregion.h b/src/drivers/intel/gma/opregion.h index 3ae68e5..8ef3dcf 100644 --- a/src/drivers/intel/gma/opregion.h +++ b/src/drivers/intel/gma/opregion.h @@ -25,6 +25,7 @@ /* IGD PCI Configuration register */ #define ASLS 0xfc /* OpRegion Base */ #define SWSCI 0xe8 /* SWSCI Register */ +#define SWSMISCI 0xe0 /* SWSMISCI Register */ #define GSSCIE (1 << 0) /* SCI Event trigger */ #define SMISCISEL (1 << 15) /* Select SMI or SCI event source */ -- To view, visit https://review.coreboot.org/23696 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I636986226ff951dae637dca5bc3ad0e023d94243 Gerrit-Change-Number: 23696 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: driver/spi: Warn when probed SF size differs from CONFIG_ROM_SIZE
by build bot (Jenkins) (Code Review) 11 Feb '18

11 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23695 ) Change subject: driver/spi: Warn when probed SF size differs from CONFIG_ROM_SIZE ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67330/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21875/ : SUCCESS -- To view, visit https://review.coreboot.org/23695 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib5d6cc61ea29214d338d4c52ff799d6620a9cac7 Gerrit-Change-Number: 23695 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 11 Feb 2018 20:01:57 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: driver/spi: Warn when probed SF size differs from CONFIG_ROM_SIZE
by build bot (Jenkins) (Code Review) 11 Feb '18

11 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23695 ) Change subject: driver/spi: Warn when probed SF size differs from CONFIG_ROM_SIZE ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67329/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21874/ : SUCCESS -- To view, visit https://review.coreboot.org/23695 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib5d6cc61ea29214d338d4c52ff799d6620a9cac7 Gerrit-Change-Number: 23695 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 11 Feb 2018 19:05:31 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: driver/spi: Warn when probed SF size differs from CONFIG_ROM_SIZE
by Arthur Heymans (Code Review) 11 Feb '18

11 Feb '18

Hello build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/23695 to look at the new patch set (#3). Change subject: driver/spi: Warn when probed SF size differs from CONFIG_ROM_SIZE ...................................................................... driver/spi: Warn when probed SF size differs from CONFIG_ROM_SIZE Some assumptions are made with respect to CONFIG_ROM_SIZE being the actual size of the boot medium, e.g. when automatically creating an fmap with and RW_MRC_CACHE region. With this patch the user is warned when this is detected. Change-Id: Ib5d6cc61ea29214d338d4c52ff799d6620a9cac7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/spi/spi_flash.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/23695/3 -- To view, visit https://review.coreboot.org/23695 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ib5d6cc61ea29214d338d4c52ff799d6620a9cac7 Gerrit-Change-Number: 23695 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: driver/spi: Warn when probed SF size differs from CONFIG_ROM_SIZE
by build bot (Jenkins) (Code Review) 11 Feb '18

11 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23695 ) Change subject: driver/spi: Warn when probed SF size differs from CONFIG_ROM_SIZE ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67328/ : SUCCESS -- To view, visit https://review.coreboot.org/23695 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib5d6cc61ea29214d338d4c52ff799d6620a9cac7 Gerrit-Change-Number: 23695 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 11 Feb 2018 18:51:20 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: driver/spi: Warn when probed SF size differs from CONFIG_ROM_SIZE
by Arthur Heymans (Code Review) 11 Feb '18

11 Feb '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/23695 ) Change subject: driver/spi: Warn when probed SF size differs from CONFIG_ROM_SIZE ...................................................................... Patch Set 2: not sure if you'd want to change the return type here... -- To view, visit https://review.coreboot.org/23695 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib5d6cc61ea29214d338d4c52ff799d6620a9cac7 Gerrit-Change-Number: 23695 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 11 Feb 2018 18:46:41 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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coreboot-gerrit February 2018