coreboot-gerrit February 2018

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Change in coreboot[master]: driver/uart: Reintroduce default_baudrate as weak function.
by Julien Viard de Galbert (Code Review) 12 Feb '18

12 Feb '18

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/23713 Change subject: driver/uart: Reintroduce default_baudrate as weak function. ...................................................................... driver/uart: Reintroduce default_baudrate as weak function. The rationale is to allow the mainboard to override the default baudrate for instance by sampling GPIOs at boot. This partially reverts the commit named "mb/*/*: Remove rtc nvram configurable baud rate" commit b29078e4015bbc3e8cf00ba64f0799c087546563. Change-Id: I970ee788bf90b9e1a8c6ccdc5eee8029d9af0ecc Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/cpu/allwinner/a10/uart.c M src/cpu/allwinner/a10/uart_console.c M src/cpu/ti/am335x/uart.c M src/drivers/uart/pl011.c M src/drivers/uart/uart8250io.c M src/drivers/uart/uart8250mem.c M src/drivers/uart/util.c M src/include/console/uart.h M src/soc/broadcom/cygnus/ns16550.c M src/soc/imgtec/pistachio/uart.c M src/soc/mediatek/mt8173/uart.c M src/soc/nvidia/tegra124/uart.c M src/soc/nvidia/tegra210/uart.c M src/soc/qualcomm/ipq40xx/uart.c M src/soc/samsung/exynos5250/uart.c M src/soc/samsung/exynos5420/uart.c 16 files changed, 35 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/23713/1 diff --git a/src/cpu/allwinner/a10/uart.c b/src/cpu/allwinner/a10/uart.c index f7c2db9..45dcaed 100644 --- a/src/cpu/allwinner/a10/uart.c +++ b/src/cpu/allwinner/a10/uart.c @@ -105,7 +105,7 @@ struct a10_uart *uart_base = uart_platform_baseptr(idx); /* Use default 8N1 encoding */ - a10_uart_configure(uart_base, CONFIG_TTYS0_BAUD, + a10_uart_configure(uart_base, default_baudrate(), 8, UART_PARITY_NONE, 1); a10_uart_enable_fifos(uart_base); } diff --git a/src/cpu/allwinner/a10/uart_console.c b/src/cpu/allwinner/a10/uart_console.c index 03d4122..e7774c9 100644 --- a/src/cpu/allwinner/a10/uart_console.c +++ b/src/cpu/allwinner/a10/uart_console.c @@ -44,7 +44,7 @@ struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); - serial.baud = CONFIG_TTYS0_BAUD; + serial.baud = default_baudrate(); serial.regwidth = 1; serial.input_hertz = uart_platform_refclk(); serial.uart_pci_addr = 0; diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index 47b9a3d..45a693a 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -163,7 +163,7 @@ { struct am335x_uart *uart = uart_platform_baseptr(idx); uint16_t div = (uint16_t) uart_baudrate_divisor( - CONFIG_TTYS0_BAUD, uart_platform_refclk(), 16); + default_baudrate(), uart_platform_refclk(), 16); am335x_uart_init(uart, div); } @@ -189,7 +189,7 @@ struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); - serial.baud = CONFIG_TTYS0_BAUD; + serial.baud = default_baudrate(); serial.regwidth = 2; lb_add_serial(&serial, data); diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c index 709320b..0c7ac08 100644 --- a/src/drivers/uart/pl011.c +++ b/src/drivers/uart/pl011.c @@ -46,7 +46,7 @@ struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); - serial.baud = CONFIG_TTYS0_BAUD; + serial.baud = default_baudrate(); serial.regwidth = 1; serial.input_hertz = uart_platform_refclk(); serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index ace2c59..4cc7fe3 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -107,7 +107,7 @@ { if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250IO_SKIP_INIT)) { unsigned int div; - div = uart_baudrate_divisor(CONFIG_TTYS0_BAUD, + div = uart_baudrate_divisor(default_baudrate(), uart_platform_refclk(), uart_input_clock_divider()); uart8250_init(uart_platform_base(idx), div); } @@ -134,7 +134,7 @@ struct lb_serial serial; serial.type = LB_SERIAL_TYPE_IO_MAPPED; serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); - serial.baud = CONFIG_TTYS0_BAUD; + serial.baud = default_baudrate(); serial.regwidth = 1; serial.input_hertz = uart_platform_refclk(); serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 9eb50cb..5a1e366 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -119,7 +119,7 @@ return; unsigned int div; - div = uart_baudrate_divisor(CONFIG_TTYS0_BAUD, + div = uart_baudrate_divisor(default_baudrate(), uart_platform_refclk(), uart_input_clock_divider()); uart8250_mem_init(base, div); } @@ -156,7 +156,7 @@ serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); if (!serial.baseaddr) return; - serial.baud = CONFIG_TTYS0_BAUD; + serial.baud = default_baudrate(); if (IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) serial.regwidth = sizeof(uint32_t); else diff --git a/src/drivers/uart/util.c b/src/drivers/uart/util.c index c7b9ab2..9f9b01b 100644 --- a/src/drivers/uart/util.c +++ b/src/drivers/uart/util.c @@ -14,6 +14,17 @@ #include <console/console.h> #include <console/uart.h> +#define DEFAULT_BAUDRATE 115200 + +__attribute__((weak)) unsigned int default_baudrate(void) +{ + /* + * If TTYS0_BAUD is not configured, then by default use 115200 as the + * baud rate. + */ + return CONFIG_TTYS0_BAUD ? CONFIG_TTYS0_BAUD : DEFAULT_BAUDRATE; +} + /* Calculate divisor. Do not floor but round to nearest integer. */ unsigned int uart_baudrate_divisor(unsigned int baudrate, unsigned int refclk, unsigned int oversample) diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 0dccd00..e2df893 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -23,6 +23,11 @@ * baudrate generator. */ unsigned int uart_platform_refclk(void); +/* Return the baudrate, defaults to CONFIG_TTYS0_BAUD. + * This function is weak and can be overridden by mainboard if needed. + */ +unsigned int default_baudrate(void); + /* Returns the divisor value for a given baudrate. * The formula to satisfy is: * refclk / divisor = baudrate * oversample diff --git a/src/soc/broadcom/cygnus/ns16550.c b/src/soc/broadcom/cygnus/ns16550.c index e700827..aa9dd2d 100644 --- a/src/soc/broadcom/cygnus/ns16550.c +++ b/src/soc/broadcom/cygnus/ns16550.c @@ -120,7 +120,7 @@ struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; serial.baseaddr = (uintptr_t)regs; - serial.baud = CONFIG_TTYS0_BAUD; + serial.baud = default_baudrate(); serial.regwidth = 4; lb_add_serial(&serial, data); diff --git a/src/soc/imgtec/pistachio/uart.c b/src/soc/imgtec/pistachio/uart.c index df1a5ac..1f39e8b 100644 --- a/src/soc/imgtec/pistachio/uart.c +++ b/src/soc/imgtec/pistachio/uart.c @@ -150,7 +150,7 @@ struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; serial.baseaddr = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; - serial.baud = CONFIG_TTYS0_BAUD; + serial.baud = default_baudrate(); serial.regwidth = 1 << UART_SHIFT; lb_add_serial(&serial, data); diff --git a/src/soc/mediatek/mt8173/uart.c b/src/soc/mediatek/mt8173/uart.c index 36a279f..d0b140d 100644 --- a/src/soc/mediatek/mt8173/uart.c +++ b/src/soc/mediatek/mt8173/uart.c @@ -177,7 +177,7 @@ struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; serial.baseaddr = UART0_BASE; - serial.baud = CONFIG_TTYS0_BAUD; + serial.baud = default_baudrate(); serial.regwidth = 4; lb_add_serial(&serial, data); diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c index 0d52337..76ea426 100644 --- a/src/soc/nvidia/tegra124/uart.c +++ b/src/soc/nvidia/tegra124/uart.c @@ -136,7 +136,7 @@ struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); - serial.baud = CONFIG_TTYS0_BAUD; + serial.baud = default_baudrate(); serial.regwidth = 4; lb_add_serial(&serial, data); diff --git a/src/soc/nvidia/tegra210/uart.c b/src/soc/nvidia/tegra210/uart.c index 1c52687..608b443 100644 --- a/src/soc/nvidia/tegra210/uart.c +++ b/src/soc/nvidia/tegra210/uart.c @@ -123,7 +123,7 @@ struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; serial.baseaddr = CONFIG_CONSOLE_SERIAL_TEGRA210_UART_ADDRESS; - serial.baud = CONFIG_TTYS0_BAUD; + serial.baud = default_baudrate(); serial.regwidth = 4; lb_add_serial(&serial, data); diff --git a/src/soc/qualcomm/ipq40xx/uart.c b/src/soc/qualcomm/ipq40xx/uart.c index 671a6d1..2ea390b 100644 --- a/src/soc/qualcomm/ipq40xx/uart.c +++ b/src/soc/qualcomm/ipq40xx/uart.c @@ -297,7 +297,7 @@ serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; serial.baseaddr = (uint32_t)UART1_DM_BASE; - serial.baud = CONFIG_TTYS0_BAUD; + serial.baud = default_baudrate(); serial.regwidth = 1; lb_add_serial(&serial, data); diff --git a/src/soc/samsung/exynos5250/uart.c b/src/soc/samsung/exynos5250/uart.c index 7ad6cbe..07f1e34 100644 --- a/src/soc/samsung/exynos5250/uart.c +++ b/src/soc/samsung/exynos5250/uart.c @@ -61,7 +61,7 @@ // All UARTs share the same clock. uclk = clock_get_periph_rate(PERIPH_ID_UART3); - val = uclk / CONFIG_TTYS0_BAUD; + val = uclk / default_baudrate(); write32(&uart->ubrdiv, val / 16 - 1); @@ -191,7 +191,7 @@ struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); - serial.baud = CONFIG_TTYS0_BAUD; + serial.baud = default_baudrate(); serial.regwidth = 4; lb_add_serial(&serial, data); diff --git a/src/soc/samsung/exynos5420/uart.c b/src/soc/samsung/exynos5420/uart.c index a38be07..6f54c00 100644 --- a/src/soc/samsung/exynos5420/uart.c +++ b/src/soc/samsung/exynos5420/uart.c @@ -61,7 +61,7 @@ // All UARTs share the same clock. uclk = clock_get_periph_rate(PERIPH_ID_UART3); - val = uclk / CONFIG_TTYS0_BAUD; + val = uclk / default_baudrate(); write32(&uart->ubrdiv, val / 16 - 1); @@ -182,7 +182,7 @@ struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); - serial.baud = CONFIG_TTYS0_BAUD; + serial.baud = default_baudrate(); serial.regwidth = 4; serial.input_hertz = uart_platform_refclk(); serial.uart_pci_addr = 0; -- To view, visit https://review.coreboot.org/23713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I970ee788bf90b9e1a8c6ccdc5eee8029d9af0ecc Gerrit-Change-Number: 23713 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net>

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Change in coreboot[master]: console: Introduce a way for mainboard to override the loglevel
by Julien Viard de Galbert (Code Review) 12 Feb '18

12 Feb '18

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/23712 Change subject: console: Introduce a way for mainboard to override the loglevel ...................................................................... console: Introduce a way for mainboard to override the loglevel This change add a weak function to allow mainboard to override the default console loglevel. This allows a mainboard to sample a GPIO to switch the loglevel value between different environments (qualification vs production) without re-flashing. Change-Id: Id6cc72b8fe5c4c50a6f83ce80e6440b078eec6e2 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/console/init.c M src/include/console/console.h 2 files changed, 17 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/23712/1 diff --git a/src/console/init.c b/src/console/init.c index 422315a..b14dc3d 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -29,12 +29,20 @@ #define CONSOLE_LEVEL_CONST 0 #endif +__attribute__((weak)) const int mainboard_get_default_console_loglevel(void) +{ + return -1; +} + static int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; static inline int get_log_level(void) { - if (CONSOLE_LEVEL_CONST) + if (CONSOLE_LEVEL_CONST) { + int lvl = mainboard_get_default_console_loglevel(); + if (lvl >= 0) return lvl; return CONFIG_DEFAULT_CONSOLE_LOGLEVEL; + } return console_loglevel; } @@ -54,6 +62,9 @@ if (CONSOLE_LEVEL_CONST) return; + int lvl = mainboard_get_default_console_loglevel(); + if (lvl >= 0) debug_level = lvl; + get_option(&debug_level, "debug_level"); set_log_level(debug_level); diff --git a/src/include/console/console.h b/src/include/console/console.h index aa935e4..d21b3c4 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -64,6 +64,11 @@ #define printk(LEVEL, fmt, args...) \ do { do_printk(LEVEL, fmt, ##args); } while (0) +/* + * this function is weak and can be overridden by a mainboard function. + * return -1 to not override the configuration default. + */ +const int mainboard_get_default_console_loglevel(void); #else static inline void console_init(void) {} static inline int console_log_level(int msg_level) { return 0; } -- To view, visit https://review.coreboot.org/23712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id6cc72b8fe5c4c50a6f83ce80e6440b078eec6e2 Gerrit-Change-Number: 23712 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net>

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Change in coreboot[master]: security/tpm: Add SW hash functions for measurements
by build bot (Jenkins) (Code Review) 12 Feb '18

12 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23711 ) Change subject: security/tpm: Add SW hash functions for measurements ...................................................................... Patch Set 2: Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/67351/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/21896/ : SUCCESS -- To view, visit https://review.coreboot.org/23711 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ice8a0de0294fe619ff725dc5126319fc2bc657ad Gerrit-Change-Number: 23711 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 12 Feb 2018 13:57:01 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: security/crypto: Add crypto primitives for hashing data
by build bot (Jenkins) (Code Review) 12 Feb '18

12 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22872 ) Change subject: security/crypto: Add crypto primitives for hashing data ...................................................................... Patch Set 17: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67350/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21895/ : SUCCESS -- To view, visit https://review.coreboot.org/22872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I807084ebfffdc159fe95c45b4e5f0820bbfee5e1 Gerrit-Change-Number: 22872 Gerrit-PatchSet: 17 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Anonymous Coward #1001824 Gerrit-Reviewer: Anonymous Coward #1001845 Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 12 Feb 2018 13:52:06 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: security/tpm: Add TPM measurement code
by build bot (Jenkins) (Code Review) 12 Feb '18

12 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22867 ) Change subject: security/tpm: Add TPM measurement code ...................................................................... Patch Set 19: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67349/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21894/ : SUCCESS -- To view, visit https://review.coreboot.org/22867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0a52494f647d21e2587231af26ed13d62b3a72f5 Gerrit-Change-Number: 22867 Gerrit-PatchSet: 19 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 12 Feb 2018 13:44:58 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: security/tpm: Add SW hash functions for measurements
by build bot (Jenkins) (Code Review) 12 Feb '18

12 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23711 ) Change subject: security/tpm: Add SW hash functions for measurements ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/67348/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/21893/ : SUCCESS -- To view, visit https://review.coreboot.org/23711 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ice8a0de0294fe619ff725dc5126319fc2bc657ad Gerrit-Change-Number: 23711 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 12 Feb 2018 13:33:57 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: security/tpm: Add SW hash functions for measurements
by Philipp Deppenwiese (Code Review) 12 Feb '18

12 Feb '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/23711 Change subject: security/tpm: Add SW hash functions for measurements ...................................................................... security/tpm: Add SW hash functions for measurements * Make SW measurements first class citizen. * Add kconfig option TPM hardware accerlated hashes. Change-Id: Ice8a0de0294fe619ff725dc5126319fc2bc657ad Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/security/crypto/Makefile.inc M src/security/tpm/Kconfig M src/security/tpm/tspi/tspi.c 3 files changed, 72 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/23711/1 diff --git a/src/security/crypto/Makefile.inc b/src/security/crypto/Makefile.inc index b1c5cfc..97040f9 100644 --- a/src/security/crypto/Makefile.inc +++ b/src/security/crypto/Makefile.inc @@ -3,19 +3,19 @@ verstage-$(CONFIG_CRYPTO_HASH_SHA1) += hash/sha1.c romstage-$(CONFIG_CRYPTO_HASH_SHA1) += hash/sha1.c ramstage-$(CONFIG_CRYPTO_HASH_SHA1) += hash/sha1.c -smm-$(CONFIG_CRYPTO_HASH_SHA1) += hash/sha1.c +postcar-$(CONFIG_CRYPTO_HASH_SHA1) += hash/sha1.c verstage-$(CONFIG_CRYPTO_HASH_SHA256) += hash/sha256.c romstage-$(CONFIG_CRYPTO_HASH_SHA256) += hash/sha256.c ramstage-$(CONFIG_CRYPTO_HASH_SHA256) += hash/sha256.c -smm-$(CONFIG_CRYPTO_HASH_SHA256) += hash/sha256.c +postcar-$(CONFIG_CRYPTO_HASH_SHA256) += hash/sha256.c verstage-$(CONFIG_CRYPTO_HASH_SHA512) += hash/sha512.c romstage-$(CONFIG_CRYPTO_HASH_SHA512) += hash/sha512.c ramstage-$(CONFIG_CRYPTO_HASH_SHA512) += hash/sha512.c -smm-$(CONFIG_CRYPTO_HASH_SHA512) += hash/sha512.c +postcar-$(CONFIG_CRYPTO_HASH_SHA512) += hash/sha512.c verstage-$(CONFIG_CRYPTO_HASH) += hash/hash.c romstage-$(CONFIG_CRYPTO_HASH) += hash/hash.c ramstage-$(CONFIG_CRYPTO_HASH) += hash/hash.c -smm-$(CONFIG_CRYPTO_HASH) += hash/hash.c +postcar-$(CONFIG_CRYPTO_HASH) += hash/hash.c diff --git a/src/security/tpm/Kconfig b/src/security/tpm/Kconfig index 47c37ce..7f8a2e9 100644 --- a/src/security/tpm/Kconfig +++ b/src/security/tpm/Kconfig @@ -81,4 +81,11 @@ help Deactivate TPM by issuing deactivate command. +config TPM_HW_HASHES + bool "Enable TPM HW hashes" + default n + depends on (TPM1 || TPM2) + help + Enables hardware accerlated hashes. A TPM HW feature. + endmenu # Trusted Platform Module (tpm) diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index 8d11148..f4c3520 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -17,6 +17,7 @@ #include <console/cbmem_console.h> #include <console/console.h> #include <reset.h> +#include <security/crypto/hash.h> #include <security/tpm/tspi.h> #include <security/tpm/tss.h> #include <stdlib.h> @@ -176,7 +177,7 @@ } uint32_t tpm_measure_region(int pcr, const struct region_device *rd, - const char *name) + const char *name) { uint8_t block[TPM_HASH_MAX_COUNT]; uint8_t digest[TPM_PCR_MAX_LENGTH]; @@ -192,6 +193,7 @@ return result; } +#if IS_ENABLED(CONFIG_TPM_HW_HASHES) result = tlcl_hash_start(&data_max_length); if (result != TPM_SUCCESS) { printk(BIOS_ERR, "TPM: TPM_Hash_Start returned error: %u.\n", @@ -240,6 +242,64 @@ result); return result; } +#else + struct digest_context dc; + data_max_length = 1024; + + if (IS_ENABLED(CONFIG_TPM1)) { + digest_init(&dc, HASH_SHA1); + digest_length = SHA1_DIGEST_SIZE; + } else if (IS_ENABLED(CONFIG_TPM2)) { + digest_init(&dc, HASH_SHA256); + digest_length = SHA256_DIGEST_SIZE; + } + + hash_rounds = (region_device_sz(rd) / data_max_length); + for (i = 0; i < hash_rounds; i++) { + if (rdev_readat(rd, block, (i * data_max_length), + data_max_length) < 0) + return TPM_E_IOERROR; + result = digest_extend(&dc, block, data_max_length); + if (result != SUCCESS) { + printk(BIOS_ERR, + "CRYPTO: digest_extend returned error: %u.\n", + result); + return result; + } + } + + hash_rest = (region_device_sz(rd) % data_max_length); + if (hash_rest > 0) { + size_t hash_complete = + ((hash_rest / TPM_HASH_MIN_COUNT) * TPM_HASH_MIN_COUNT); + + if (rdev_readat(rd, block, (hash_rounds * data_max_length), + hash_complete) < 0) + return TPM_E_IOERROR; + result = digest_extend(&dc, block, hash_complete); + if (result != SUCCESS) { + printk(BIOS_ERR, + "CRYPTO: digest_extend returned error: %u.\n", + result); + return result; + } + + result = digest_extend(&dc, block, TPM_HASH_MIN_COUNT); + if (result != SUCCESS) { + printk(BIOS_ERR, + "CRYPTO: digest_extend returned error: %u.\n", + result); + return result; + } + } + + result = digest_finalize(&dc, digest, digest_length); + if (result != SUCCESS) { + printk(BIOS_ERR, + "CRYPTO: digest_finalize returned error: %u.\n", result); + return result; + } +#endif result = tlcl_extend(pcr, digest, NULL); if (result != TPM_SUCCESS) { -- To view, visit https://review.coreboot.org/23711 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ice8a0de0294fe619ff725dc5126319fc2bc657ad Gerrit-Change-Number: 23711 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

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Change in coreboot[master]: nb/x4x/raminit_ddr2: Refactor clock configuration slightly
by build bot (Jenkins) (Code Review) 12 Feb '18

12 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23710 ) Change subject: nb/x4x/raminit_ddr2: Refactor clock configuration slightly ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67347/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21892/ : SUCCESS -- To view, visit https://review.coreboot.org/23710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic51c05d7aa791250d775bd7a640213065d4caba0 Gerrit-Change-Number: 23710 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 12 Feb 2018 13:12:18 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/x4x/raminit_ddr2: Refactor clock configuration slightly
by build bot (Jenkins) (Code Review) 12 Feb '18

12 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23710 ) Change subject: nb/x4x/raminit_ddr2: Refactor clock configuration slightly ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/67346/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/21891/ : SUCCESS -- To view, visit https://review.coreboot.org/23710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic51c05d7aa791250d775bd7a640213065d4caba0 Gerrit-Change-Number: 23710 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 12 Feb 2018 12:42:30 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/x4x/raminit_ddr2: Refactor clock configuration slightly
by Jonathan Neuschäfer (Code Review) 12 Feb '18

12 Feb '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/23710 Change subject: nb/x4x/raminit_ddr2: Refactor clock configuration slightly ...................................................................... nb/x4x/raminit_ddr2: Refactor clock configuration slightly The result is shorter and (IMHO) more readable code. Change-Id: Ic51c05d7aa791250d775bd7a640213065d4caba0 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/northbridge/intel/x4x/raminit_ddr2.c 1 file changed, 14 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/23710/1 diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index e6ba2dc..e28a613 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -722,23 +722,20 @@ } FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { - if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) { - clkset0(i, &dll_setting_667[CLKSET0]); - clkset1(i, &dll_setting_667[CLKSET1]); - ctrlset0(i, &dll_setting_667[CTRL0]); - ctrlset1(i, &dll_setting_667[CTRL1]); - ctrlset2(i, &dll_setting_667[CTRL2]); - ctrlset3(i, &dll_setting_667[CTRL3]); - cmdset(i, &dll_setting_667[CMD]); - } else { - clkset0(i, &dll_setting_800[CLKSET0]); - clkset1(i, &dll_setting_800[CLKSET1]); - ctrlset0(i, &dll_setting_800[CTRL0]); - ctrlset1(i, &dll_setting_800[CTRL1]); - ctrlset2(i, &dll_setting_800[CTRL2]); - ctrlset3(i, &dll_setting_800[CTRL3]); - cmdset(i, &dll_setting_800[CMD]); - } + struct dll_setting *setting; + + if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) + setting = dll_setting_667; + else + setting = dll_setting_800; + + clkset0(i, &setting[CLKSET0]); + clkset1(i, &setting[CLKSET1]); + ctrlset0(i, &setting[CTRL0]); + ctrlset1(i, &setting[CTRL1]); + ctrlset2(i, &setting[CTRL2]); + ctrlset3(i, &setting[CTRL3]); + cmdset(i, &setting[CMD]); } // XXX if not async mode -- To view, visit https://review.coreboot.org/23710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic51c05d7aa791250d775bd7a640213065d4caba0 Gerrit-Change-Number: 23710 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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coreboot-gerrit February 2018