coreboot-gerrit February 2018

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Change in coreboot[master]: mb/google/kahlee/mainboard.c: Fix mainboard_picr_data
by build bot (Jenkins) (Code Review) 12 Feb '18

12 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23716 ) Change subject: mb/google/kahlee/mainboard.c: Fix mainboard_picr_data ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/67358/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/21902/ : SUCCESS -- To view, visit https://review.coreboot.org/23716 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic285036290519ed3ee617dffa616bd26c61575c5 Gerrit-Change-Number: 23716 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 12 Feb 2018 15:50:47 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: drivers/i2c/designware: Remove spurious word ("familuar")
by build bot (Jenkins) (Code Review) 12 Feb '18

12 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23714 ) Change subject: drivers/i2c/designware: Remove spurious word ("familuar") ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67355/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21899/ : SUCCESS -- To view, visit https://review.coreboot.org/23714 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic521a2d60b403b322ae583bb2c26da6019bf0ab0 Gerrit-Change-Number: 23714 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 12 Feb 2018 15:50:25 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: device/ddr2, ddr3: Rename and move a few things
by Arthur Heymans (Code Review) 12 Feb '18

12 Feb '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/23717 Change subject: device/ddr2,ddr3: Rename and move a few things ...................................................................... device/ddr2,ddr3: Rename and move a few things In order for ddr2.h and ddr3.h to be included in the same file it cannot have conflicting definitions, therefore rename a few things and move some things to a common header. Change-Id: I6056148872076048e055f1d20a60ac31afd7cde6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/device/dram/ddr2.c A src/include/device/dram/common.h M src/include/device/dram/ddr2.h M src/include/device/dram/ddr3.h M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/x4x/raminit.c 6 files changed, 100 insertions(+), 101 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/23717/1 diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index 0117b93..eefb569 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -38,11 +38,11 @@ * * @param type DIMM type. This is byte[20] of the SPD. */ -int spd_dimm_is_registered_ddr2(enum spd_dimm_type type) +int spd_dimm_is_registered_ddr2(enum spd_dimm_type_ddr2 type) { - if ((type == SPD_DIMM_TYPE_RDIMM) - || (type == SPD_DIMM_TYPE_72B_SO_RDIMM) - || (type == SPD_DIMM_TYPE_MINI_RDIMM)) + if ((type == SPD_DDR2_DIMM_TYPE_RDIMM) + || (type == SPD_DDR2_DIMM_TYPE_72B_SO_RDIMM) + || (type == SPD_DDR2_DIMM_TYPE_MINI_RDIMM)) return 1; return 0; @@ -297,7 +297,7 @@ * SPD_STATUS_INVALID_FIELD -- A field with an invalid value was * detected. */ -int spd_decode_ddr2(struct dimm_attr_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2]) +int spd_decode_ddr2(struct dimm_attr_ddr2_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2]) { u8 spd_size, cl, reg8; u16 eeprom_size; @@ -582,7 +582,7 @@ } printram("\n"); - dimm->dimm_type = spd[20] & SPD_DIMM_TYPE_MASK; + dimm->dimm_type = spd[20] & SPD_DDR2_DIMM_TYPE_MASK; printram(" Dimm type : %x\n", dimm->dimm_type); dimm->flags.is_ecc = !!(spd[11] & 0x3); @@ -648,7 +648,7 @@ * * @param dimm pointer to already decoded @ref dimm_attr structure */ -void dram_print_spd_ddr2(const struct dimm_attr_st *dimm) +void dram_print_spd_ddr2(const struct dimm_attr_ddr2_st *dimm) { char buf[32]; int i; diff --git a/src/include/device/dram/common.h b/src/include/device/dram/common.h new file mode 100644 index 0000000..4702370 --- /dev/null +++ b/src/include/device/dram/common.h @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef DEVICE_DRAM_COMMON_H +#define DEVICE_DRAM_COMMON_H + +/** + * \brief Convenience definitions for TCK values + * + * Different values for tCK, representing standard DDR3 frequencies. + * These values are in 1/256 ns units. + * @{ + */ +#define NS2MHZ_DIV256 (1000 << 8) + +#define TCK_1333MHZ 192 +#define TCK_1200MHZ 212 +#define TCK_1100MHZ 232 +#define TCK_1066MHZ 240 +#define TCK_1000MHZ 256 +#define TCK_933MHZ 274 +#define TCK_900MHZ 284 +#define TCK_800MHZ 320 +#define TCK_700MHZ 365 +#define TCK_666MHZ 384 +#define TCK_533MHZ 480 +#define TCK_400MHZ 640 +#define TCK_333MHZ 768 +#define TCK_266MHZ 960 +#define TCK_200MHZ 1280 +/** @} */ + +/** + * \brief Convenience macro for enabling printk with CONFIG_DEBUG_RAM_SETUP + * + * Use this macro instead of printk(); for verbose RAM initialization messages. + * When CONFIG_DEBUG_RAM_SETUP is not selected, these messages are automatically + * disabled. + * @{ + */ +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#define printram(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__) +#else +#define printram(x, ...) +#endif +/** @} */ + +/** Result of the SPD decoding process */ +enum spd_status { + SPD_STATUS_OK = 0, + SPD_STATUS_INVALID, + SPD_STATUS_CRC_ERROR, + SPD_STATUS_INVALID_FIELD, +}; + +#endif /* DEVICE_DRAM_COMMON_H */ diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h index 7322b12..4aad1bc 100644 --- a/src/include/device/dram/ddr2.h +++ b/src/include/device/dram/ddr2.h @@ -30,55 +30,24 @@ #include <stdint.h> #include <spd.h> - -/** - * \brief Convenience definitions for TCK values - * - * Different values for tCK, representing standard DDR2 frequencies. - * These values are in 1/256 ns units. - * @{ - */ -#define TCK_800MHZ 320 -#define TCK_700MHZ 365 -#define TCK_666MHZ 384 -#define TCK_533MHZ 480 -#define TCK_400MHZ 640 -#define TCK_333MHZ 768 -#define TCK_266MHZ 960 -#define TCK_200MHZ 1280 -/** @} */ - -/** - * \brief Convenience macro for enabling printk with CONFIG_DEBUG_RAM_SETUP - * - * Use this macro instead of printk(); for verbose RAM initialization messages. - * When CONFIG_DEBUG_RAM_SETUP is not selected, these messages are automatically - * disabled. - * @{ - */ -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) -#define printram(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__) -#else -#define printram(x, ...) -#endif -/** @} */ +#include <device/dram/common.h> /* * Module type (byte 20, bits 5:0) of SPD * This definition is specific to DDR2. DDR3 SPDs have a different structure. */ -enum spd_dimm_type { - SPD_DIMM_TYPE_UNDEFINED = 0x00, - SPD_DIMM_TYPE_RDIMM = 0x01, - SPD_DIMM_TYPE_UDIMM = 0x02, - SPD_DIMM_TYPE_SO_DIMM = 0x04, - SPD_DIMM_TYPE_72B_SO_CDIMM = 0x06, - SPD_DIMM_TYPE_72B_SO_RDIMM = 0x07, - SPD_DIMM_TYPE_MICRO_DIMM = 0x08, - SPD_DIMM_TYPE_MINI_RDIMM = 0x10, - SPD_DIMM_TYPE_MINI_UDIMM = 0x20, +enum spd_dimm_type_ddr2 { + SPD_DDR2_DIMM_TYPE_UNDEFINED = 0x00, + SPD_DDR2_DIMM_TYPE_RDIMM = 0x01, + SPD_DDR2_DIMM_TYPE_UDIMM = 0x02, + SPD_DDR2_DIMM_TYPE_SO_DIMM = 0x04, + SPD_DDR2_DIMM_TYPE_72B_SO_CDIMM = 0x06, + SPD_DDR2_DIMM_TYPE_72B_SO_RDIMM = 0x07, + SPD_DDR2_DIMM_TYPE_MICRO_DIMM = 0x08, + SPD_DDR2_DIMM_TYPE_MINI_RDIMM = 0x10, + SPD_DDR2_DIMM_TYPE_MINI_UDIMM = 0x20, /* Masks to bits 5:0 to give the dimm type */ - SPD_DIMM_TYPE_MASK = 0x3f, + SPD_DDR2_DIMM_TYPE_MASK = 0x3f, }; /** @@ -86,7 +55,7 @@ * * Characteristic flags for the DIMM, as presented by the SPD */ -union dimm_flags_st { +union dimm_flags_ddr2_st { /* The whole point of the union/struct construct is to allow us to clear * all the bits with one line: flags.raw = 0. * We do not care how these bits are ordered */ @@ -130,9 +99,9 @@ * * The characteristics of each DIMM, as presented by the SPD */ -struct dimm_attr_st { +struct dimm_attr_ddr2_st { enum spd_memory_type dram_type; - enum spd_dimm_type dimm_type; + enum spd_dimm_type_ddr2 dimm_type; /* BCD SPD revision */ u8 rev; /* Supported CAS mask, bit 0 == CL0 .. bit7 == CL7 */ @@ -144,7 +113,7 @@ * Fields 0 and 1 are unused. */ u32 access_time[8]; /* Flags extracted from SPD */ - union dimm_flags_st flags; + union dimm_flags_ddr2_st flags; /* Number of banks */ u8 banks; /* SDRAM width */ @@ -199,23 +168,15 @@ u32 serial; }; -/** Result of the SPD decoding process */ -enum spd_status { - SPD_STATUS_OK = 0, - SPD_STATUS_INVALID, - SPD_STATUS_CRC_ERROR, - SPD_STATUS_INVALID_FIELD, -}; - /** Maximum SPD size supported */ #define SPD_SIZE_MAX_DDR2 128 -int spd_dimm_is_registered_ddr2(enum spd_dimm_type type); +int spd_dimm_is_registered_ddr2(enum spd_dimm_type_ddr2 type); u8 spd_ddr2_calc_checksum(u8 *spd, int len); u32 spd_decode_spd_size_ddr2(u8 byte0); u32 spd_decode_eeprom_size_ddr2(u8 byte1); -int spd_decode_ddr2(struct dimm_attr_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2]); -void dram_print_spd_ddr2(const struct dimm_attr_st *dimm); +int spd_decode_ddr2(struct dimm_attr_ddr2_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2]); +void dram_print_spd_ddr2(const struct dimm_attr_ddr2_st *dimm); void normalize_tck(u32 *tclk); u8 spd_get_msbs(u8 c); diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 2cfd6ac..0756095 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -31,6 +31,8 @@ #include <stdint.h> #include <spd.h> +#include <device/dram/common.h> + /** * Convenience definitions for SPD offsets @@ -46,32 +48,6 @@ /** @} */ /** - * \brief Convenience definitions for TCK values - * - * Different values for tCK, representing standard DDR3 frequencies. - * These values are in 1/256 ns units. - * @{ - */ -#define NS2MHZ_DIV256 (1000 << 8) - -#define TCK_1333MHZ 192 -#define TCK_1200MHZ 212 -#define TCK_1100MHZ 232 -#define TCK_1066MHZ 240 -#define TCK_1000MHZ 256 -#define TCK_933MHZ 274 -#define TCK_900MHZ 284 -#define TCK_800MHZ 320 -#define TCK_700MHZ 365 -#define TCK_666MHZ 384 -#define TCK_533MHZ 480 -#define TCK_400MHZ 640 -#define TCK_333MHZ 768 -#define TCK_266MHZ 960 -#define TCK_200MHZ 1280 -/** @} */ - -/** * \brief Convenience macro for enabling printk with CONFIG_DEBUG_RAM_SETUP * * Use this macro instead of printk(); for verbose RAM initialization messages. @@ -198,14 +174,6 @@ u8 part_number[17]; } dimm_attr; -/** Result of the SPD decoding process */ -enum spd_status { - SPD_STATUS_OK = 0, - SPD_STATUS_INVALID, - SPD_STATUS_CRC_ERROR, - SPD_STATUS_INVALID_FIELD, -}; - enum ddr3_xmp_profile { DDR3_XMP_PROFILE_1 = 0, DDR3_XMP_PROFILE_2 = 1, diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index b350b67..b2348f5 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -362,7 +362,7 @@ for (i = 0; i < (2 * DIMM_SOCKETS); i++) { int device = get_dimm_spd_address(sysinfo, i), bytes_read; - struct dimm_attr_st dimm_info; + struct dimm_attr_ddr2_st dimm_info; /* Initialize the socket information with a sane value */ sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED; diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index cd786bb..7bb5f2b 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -119,7 +119,7 @@ static int ddr2_save_dimminfo(u8 dimm_idx, u8 *raw_spd, struct abs_timings *saved_timings, struct sysinfo *s) { - struct dimm_attr_st decoded_dimm; + struct dimm_attr_ddr2_st decoded_dimm; int i; if (spd_decode_ddr2(&decoded_dimm, raw_spd) != SPD_STATUS_OK) { -- To view, visit https://review.coreboot.org/23717 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6056148872076048e055f1d20a60ac31afd7cde6 Gerrit-Change-Number: 23717 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: driver/uart: Reintroduce default_baudrate as weak function.
by Arthur Heymans (Code Review) 12 Feb '18

12 Feb '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/23713 ) Change subject: driver/uart: Reintroduce default_baudrate as weak function. ...................................................................... Patch Set 1: > Hello, you were involved in the commit I partially revert, so I'm > adding you. > > Also I could do it by adding an config option to not reintroduce > the function by default. > > Best Regards The rationale behind removing this was that nobody seems to use it, that it is confusing to have both a cmos setting and a Kconfig to do the same thing and that when fetching the baud rate from cmos it actually tried to print stuff before baud rate was set which could result in very long delays in the boot time. To avoid having a something override the value defined in Kconfig (to avoid confusion) I think it would be better to not have it show this option in Kconfig at all. something like MAINBOARD_SET_KCONFIG which is mutually exlusive with TTYS0_BAUD... -- To view, visit https://review.coreboot.org/23713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I970ee788bf90b9e1a8c6ccdc5eee8029d9af0ecc Gerrit-Change-Number: 23713 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 12 Feb 2018 15:45:04 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/kahlee/mainboard.c: Fix mainboard_picr_data
by Richard Spiegel (Code Review) 12 Feb '18

12 Feb '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/23716 Change subject: mb/google/kahlee/mainboard.c: Fix mainboard_picr_data ...................................................................... mb/google/kahlee/mainboard.c: Fix mainboard_picr_data While programming interrupts, a message "perhaps this device was defined wrong?" shows up twice. This is caused because some devices have interrupt programmed for APIC mode, but not for non-APIC mode. Fix mainboard_picr_data table by identifying devices programmed with value 0x1F while programmed differently on mainboard_intr_data table. Do so only for devices that are used by kahlee or interrupt required by old OS. BUG=b:70788755 TEST=Build and run kahlee, Verify that message disappears from serial output. Change-Id: Ic285036290519ed3ee617dffa616bd26c61575c5 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/mainboard/google/kahlee/mainboard.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/23716/1 diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index b7adfc0..dd435fd 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -46,13 +46,13 @@ const u8 mainboard_picr_data[] = { [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, - [0x10] = 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, + [0x10] = 0x09, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x03, [0x18] = 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, [0x30] = 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x40] = 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x40] = 0x04, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, [0x50] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, [0x58] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, @@ -84,13 +84,13 @@ const u8 mainboard_picr_data[] = { [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x1F, 0x1F, 0x1F, [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, - [0x10] = 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, + [0x10] = 0x09, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x03, [0x18] = 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, [0x30] = 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x40] = 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x40] = 0x04, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, [0x50] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, [0x58] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, -- To view, visit https://review.coreboot.org/23716 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic285036290519ed3ee617dffa616bd26c61575c5 Gerrit-Change-Number: 23716 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: security/tpm: Add SW hash functions for measurements
by Philipp Deppenwiese (Code Review) 12 Feb '18

12 Feb '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/23711 to look at the new patch set (#3). Change subject: security/tpm: Add SW hash functions for measurements ...................................................................... security/tpm: Add SW hash functions for measurements * Make SW measurements first class citizen. * Add kconfig option TPM hardware accerlated hashes. Change-Id: Ice8a0de0294fe619ff725dc5126319fc2bc657ad Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/security/crypto/Makefile.inc M src/security/tpm/Kconfig M src/security/tpm/tspi/tspi.c 3 files changed, 72 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/23711/3 -- To view, visit https://review.coreboot.org/23711 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ice8a0de0294fe619ff725dc5126319fc2bc657ad Gerrit-Change-Number: 23711 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/intel/gm45/raminit: Use CxDRT*_MCHBAR instead of magic numbers
by build bot (Jenkins) (Code Review) 12 Feb '18

12 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23709 ) Change subject: nb/intel/gm45/raminit: Use CxDRT*_MCHBAR instead of magic numbers ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67354/ : SUCCESS -- To view, visit https://review.coreboot.org/23709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I079d5353633a3d58ce0e5e616f3fad687a064d65 Gerrit-Change-Number: 23709 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 12 Feb 2018 14:15:03 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: driver/uart: Reintroduce default_baudrate as weak function.
by Julien Viard de Galbert (Code Review) 12 Feb '18

12 Feb '18

Julien Viard de Galbert has posted comments on this change. ( https://review.coreboot.org/23713 ) Change subject: driver/uart: Reintroduce default_baudrate as weak function. ...................................................................... Patch Set 1: Hello, you were involved in the commit I partially revert, so I'm adding you. Also I could do it by adding an config option to not reintroduce the function by default. Best Regards -- To view, visit https://review.coreboot.org/23713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I970ee788bf90b9e1a8c6ccdc5eee8029d9af0ecc Gerrit-Change-Number: 23713 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 12 Feb 2018 14:13:40 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: driver/uart: Reintroduce default_baudrate as weak function.
by Julien Viard de Galbert (Code Review) 12 Feb '18

12 Feb '18

Julien Viard de Galbert has posted comments on this change. ( https://review.coreboot.org/23713 ) Change subject: driver/uart: Reintroduce default_baudrate as weak function. ...................................................................... Patch Set 1: Hello all, I'm doing this change using weak function. This could also be done with config options and would probably reduce the final binary as I'm not sure the weak function can be optimized out. Best Regards -- To view, visit https://review.coreboot.org/23713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I970ee788bf90b9e1a8c6ccdc5eee8029d9af0ecc Gerrit-Change-Number: 23713 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Comment-Date: Mon, 12 Feb 2018 14:08:14 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: console: Introduce a way for mainboard to override the loglevel
by Julien Viard de Galbert (Code Review) 12 Feb '18

12 Feb '18

Julien Viard de Galbert has posted comments on this change. ( https://review.coreboot.org/23712 ) Change subject: console: Introduce a way for mainboard to override the loglevel ...................................................................... Patch Set 1: Hello all, I'm doing this change using weak function. This could also be done with config options and would probably reduce the final binary as I'm not sure the weak function can be optimized out. Best Regards -- To view, visit https://review.coreboot.org/23712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id6cc72b8fe5c4c50a6f83ce80e6440b078eec6e2 Gerrit-Change-Number: 23712 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Comment-Date: Mon, 12 Feb 2018 14:07:46 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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coreboot-gerrit February 2018