Change in coreboot[master]: mb/scaleway/tagada: Update GPIO configuration
by Julien Viard de Galbert (Code Review) 13 Feb '18
by Julien Viard de Galbert (Code Review) 13 Feb '18
13 Feb '18
Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/23740
Change subject: mb/scaleway/tagada: Update GPIO configuration
......................................................................
mb/scaleway/tagada: Update GPIO configuration
Change-Id: Ia0293a0ec85c752686750dadb9730a159fd0c073
Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net>
---
M src/mainboard/scaleway/tagada/gpio.h
M src/mainboard/scaleway/tagada/romstage.c
2 files changed, 613 insertions(+), 621 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/23740/1
diff --git a/src/mainboard/scaleway/tagada/gpio.h b/src/mainboard/scaleway/tagada/gpio.h
index a96b435..d8468f6 100644
--- a/src/mainboard/scaleway/tagada/gpio.h
+++ b/src/mainboard/scaleway/tagada/gpio.h
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2014 - 2017 Intel Corporation.
+ * Copyright (C) 2017 - 2018 Online SAS.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -20,615 +21,615 @@
#include <soc/gpio.h>
#ifndef __ACPI__
-const struct pad_config harcuvar_gpio_table[] = {
- // GBE0_SDP0 (GPIO_14)
- {NORTH_ALL_GBE0_SDP0,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // GBE1_SDP0 (GPIO_15)
- {NORTH_ALL_GBE1_SDP0,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // GBE2_I2C_CLK (GPIO_16)
- {NORTH_ALL_GBE0_SDP1,
- {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // GBE2_I2C_DATA (GPIO_17)
- {NORTH_ALL_GBE1_SDP1,
- {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // GBE2_SDP0 (GPIO_18)
- {NORTH_ALL_GBE0_SDP2,
- {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // GBE3_SDP0 (GPIO_19)
- {NORTH_ALL_GBE1_SDP2,
- {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // GBE3_I2C_CLK (GPIO_20)
- {NORTH_ALL_GBE0_SDP3,
- {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // GBE3_I2C_DATA (GPIO_21)
- {NORTH_ALL_GBE1_SDP3,
- {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // GBE2_LED0 (GPIO_22)
- {NORTH_ALL_GBE2_LED0,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // GBE2_LED1 (GPIO_23)
- {NORTH_ALL_GBE2_LED1,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // GBE0_I2C_CLK (GPIO_24)
- {NORTH_ALL_GBE0_I2C_CLK,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // GBE0_I2C_DATA (GPIO_25)
- {NORTH_ALL_GBE0_I2C_DATA,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // GBE1_I2C_CLK (GPIO_26)
- {NORTH_ALL_GBE1_I2C_CLK,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // GBE1_I2C_DATA (GPIO_27)
- {NORTH_ALL_GBE1_I2C_DATA,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // NCSI_RXD0 (GPIO_28)
- {NORTH_ALL_NCSI_RXD0,
- {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
- // NCSI_CLK_IN (GPIO_29)
- {NORTH_ALL_NCSI_CLK_IN,
- {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
- // NCSI_RXD1 (GPIO_30)
- {NORTH_ALL_NCSI_RXD1,
- {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
- // NCSI_CRS_DV (GPIO_31)
- {NORTH_ALL_NCSI_CRS_DV,
- {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
- // NCSI_ARB_IN (GPIO_32)
- {NORTH_ALL_NCSI_ARB_IN,
- {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
- // NCSI_TX_EN (GPIO_33)
- {NORTH_ALL_NCSI_TX_EN,
- {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
- // NCSI_TXD0 (GPIO_34)
- {NORTH_ALL_NCSI_TXD0,
- {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
- // NCSI_TXD1 (GPIO_35)
- {NORTH_ALL_NCSI_TXD1,
- {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
- // NCSI_ARB_OUT (GPIO_36)
- {NORTH_ALL_NCSI_ARB_OUT,
- {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
- // GBE0_LED0 (GPIO_37)
- {NORTH_ALL_GBE0_LED0,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
- // GBE0_LED1 (GPIO_38)
- {NORTH_ALL_GBE0_LED1,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
- // GBE1_LED0 (GPIO_39)
- {NORTH_ALL_GBE1_LED0,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
- // GBE1_LED1 (GPIO_40)
- {NORTH_ALL_GBE1_LED1,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
- // ADR-COMPLETE (GPIO_0)
- {NORTH_ALL_GPIO_0,
- {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // PCIE_CLKREQ0_N (GPIO_41)
- {NORTH_ALL_PCIE_CLKREQ0_N,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // PCIE_CLKREQ1_N (GPIO_42)
- {NORTH_ALL_PCIE_CLKREQ1_N,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // PCIE_CLKREQ2_N (GPIO_43)
- {NORTH_ALL_PCIE_CLKREQ2_N,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // PCIE_CLKREQ3_N (GPIO_44)
- {NORTH_ALL_PCIE_CLKREQ3_N,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // FORCE_POWER (GPIO_45)
- {NORTH_ALL_PCIE_CLKREQ4_N,
- {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // GBE_MDC (GPIO_1)
- {NORTH_ALL_GPIO_1,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // GBE_MDIO (GPIO_2)
- {NORTH_ALL_GPIO_2,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SVID_ALERT_N (GPIO_47)
- {NORTH_ALL_SVID_ALERT_N,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SVID_DATA (GPIO_48)
- {NORTH_ALL_SVID_DATA,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SVID_CLK (GPIO_49)
- {NORTH_ALL_SVID_CLK,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // THERMTRIP_N (GPIO_50)
- {NORTH_ALL_THERMTRIP_N,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // PROCHOT_N (GPIO_51)
- {NORTH_ALL_PROCHOT_N,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // MEMHOT_N (GPIO_52)
- {NORTH_ALL_MEMHOT_N,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // DFX_PORT_CLK0 (GPIO_53)
- {SOUTH_DFX_DFX_PORT_CLK0,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // DFX_PORT_CLK1 (GPIO_54)
- {SOUTH_DFX_DFX_PORT_CLK1,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // DFX_PORT0 (GPIO_55)
- {SOUTH_DFX_DFX_PORT0,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // DFX_PORT1 (GPIO_56)
- {SOUTH_DFX_DFX_PORT1,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // DFX_PORT2 (GPIO_57)
- {SOUTH_DFX_DFX_PORT2,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // DFX_PORT3 (GPIO_58)
- {SOUTH_DFX_DFX_PORT3,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // DFX_PORT4 (GPIO_59)
- {SOUTH_DFX_DFX_PORT4,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // DFX_PORT5 (GPIO_60)
- {SOUTH_DFX_DFX_PORT5,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // DFX_PORT6 (GPIO_61)
- {SOUTH_DFX_DFX_PORT6,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // DFX_PORT7 (GPIO_62)
- {SOUTH_DFX_DFX_PORT7,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // DFX_PORT8 (GPIO_63)
- {SOUTH_DFX_DFX_PORT8,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // DFX_PORT9 (GPIO_134)
- {SOUTH_DFX_DFX_PORT9,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // DFX_PORT10 (GPIO_135)
- {SOUTH_DFX_DFX_PORT10,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // DFX_PORT11 (GPIO_136)
- {SOUTH_DFX_DFX_PORT11,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // DFX_PORT12 (GPIO_137)
- {SOUTH_DFX_DFX_PORT12,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // DFX_PORT13 (GPIO_138)
- {SOUTH_DFX_DFX_PORT13,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // DFX_PORT14 (GPIO_139)
- {SOUTH_DFX_DFX_PORT14,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // DFX_PORT15 (GPIO_140)
- {SOUTH_DFX_DFX_PORT15,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SPI_TPM_CS_N (GPIO_12)
- {SOUTH_GROUP0_GPIO_12,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SMB5_GBE_ALRT_N (GPIO_13)
- {SOUTH_GROUP0_SMB5_GBE_ALRT_N,
- {GpioPadModeNative3, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
- // SMI (GPIO_98)
- {SOUTH_GROUP0_PCIE_CLKREQ5_N,
- {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntSmi, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // NMI (GPIO_99)
- {SOUTH_GROUP0_PCIE_CLKREQ6_N,
- {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntNmi, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // GBE3_LED0 (GPIO_100)
- {SOUTH_GROUP0_PCIE_CLKREQ7_N,
- {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // UART0_RXD (GPIO_101)
- {SOUTH_GROUP0_UART0_RXD,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // UART0_TXD (GPIO_102)
- {SOUTH_GROUP0_UART0_TXD,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SMB5_GBE_CLK (GPIO_103)
- {SOUTH_GROUP0_SMB5_GBE_CLK,
- {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
- // SMB_GBE_DATA (GPIO_104)
- {SOUTH_GROUP0_SMB5_GBE_DATA,
- {GpioPadModeNative3, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
- // ERROR2_N (GPIO_105)
- {SOUTH_GROUP0_ERROR2_N,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // ERROR1_N (GPIO_106)
- {SOUTH_GROUP0_ERROR1_N,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // ERROR0_N (GPIO_107)
- {SOUTH_GROUP0_ERROR0_N,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // IERR_N (CATERR_N) (GPIO_108)
- {SOUTH_GROUP0_IERR_N,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // MCERR_N (GPIO_109)
- {SOUTH_GROUP0_MCERR_N,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SMB0_LEG_CLK (GPIO_110)
- {SOUTH_GROUP0_SMB0_LEG_CLK,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SMB0_LEG_DATA (GPIO_111)
- {SOUTH_GROUP0_SMB0_LEG_DATA,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SMB0_LEG_ALRT_N (GPIO_112)
- {SOUTH_GROUP0_SMB0_LEG_ALRT_N,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SMB1_HOST_DATA (GPIO_113)
- {SOUTH_GROUP0_SMB1_HOST_DATA,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SMB1_HOST_CLK (GPIO_114)
- {SOUTH_GROUP0_SMB1_HOST_CLK,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SMB2_PECI_DATA (GPIO_115)
- {SOUTH_GROUP0_SMB2_PECI_DATA,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SMB2_PECI_CLK (GPIO_116)
- {SOUTH_GROUP0_SMB2_PECI_CLK,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SMB4_CSME0_DATA (GPIO_117)
- {SOUTH_GROUP0_SMB4_CSME0_DATA,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SMB4_CSME0_CLK (GPIO_118)
- {SOUTH_GROUP0_SMB4_CSME0_CLK,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SMB4_CSME0_ALRT_N (GPIO_119)
- {SOUTH_GROUP0_SMB4_CSME0_ALRT_N,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // USB_OC0_N (GPIO_120)
- {SOUTH_GROUP0_USB_OC0_N,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // FLEX_CLK_SE0 (GPIO_121)
- {SOUTH_GROUP0_FLEX_CLK_SE0,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // FLEX_CLK_SE1 (GPIO_122)
- {SOUTH_GROUP0_FLEX_CLK_SE1,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // GBE3_LED1 (GPIO_4)
- {SOUTH_GROUP0_GPIO_4,
- {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SMB3_IE0_CLK (GPIO_5)
- {SOUTH_GROUP0_GPIO_5,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SMB3_IE0_DATA (GPIO_6)
- {SOUTH_GROUP0_GPIO_6,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SMB3_IE0_ALERT_N (GPIO_7)
- {SOUTH_GROUP0_GPIO_7,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SATA0_LED (GPIO_90)
- {SOUTH_GROUP0_SATA0_LED_N,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SATA1_LED (GPIO_91)
- {SOUTH_GROUP0_SATA1_LED_N,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SATA_PDETECT0 (GPIO_92)
- {SOUTH_GROUP0_SATA_PDETECT0,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SATA_PDETECT1 (GPIO_93)
- {SOUTH_GROUP0_SATA_PDETECT1,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // UART1_RTS (GPIO_94)
- {SOUTH_GROUP0_SATA0_SDOUT,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // UART1_CTS (GPIO_95)
- {SOUTH_GROUP0_SATA1_SDOUT,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // UART1_RXD (GPIO_96)
- {SOUTH_GROUP0_UART1_RXD,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // UART1_TXD (GPIO_97)
- {SOUTH_GROUP0_UART1_TXD,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SMB6_CSME1_DATA (GPIO_8)
- {SOUTH_GROUP0_GPIO_8,
- {GpioPadModeNative3, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SMB6_CSME1_CLK (GPIO_9)
- {SOUTH_GROUP0_GPIO_9,
- {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // TCK (GPIO_141)
- {SOUTH_GROUP0_TCK,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // TRST_N (GPIO_142)
- {SOUTH_GROUP0_TRST_N,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // TMS (GPIO_143)
- {SOUTH_GROUP0_TMS,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // TDI (GPIO_144)
- {SOUTH_GROUP0_TDI,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // TDO (GPIO_145)
- {SOUTH_GROUP0_TDO,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // CX_PRDY_N (GPIO_146)
- {SOUTH_GROUP0_CX_PRDY_N,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // CX-PREQ_N (GPIO_147)
- {SOUTH_GROUP0_CX_PREQ_N,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // ME_RECVR_HDR (GPIO_148)
- {SOUTH_GROUP0_CTBTRIGINOUT,
- {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // ADV_DBG_DFX_HDR (GPIO_149)
- {SOUTH_GROUP0_CTBTRIGOUT,
- {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // LAD2_SPI_IRQ_N (GPIO_150)
- {SOUTH_GROUP0_DFX_SPARE2,
- {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SMB_PECI_ALRT_N (GPIO_151)
- {SOUTH_GROUP0_DFX_SPARE3,
- {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SMB_CSME1_ALRT_N (GPIO_152)
- {SOUTH_GROUP0_DFX_SPARE4,
- {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SUSPWRDNACK (GPIO_79)
- {SOUTH_GROUP1_SUSPWRDNACK,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // PMU_SUSCLK (GPIO_80)
- {SOUTH_GROUP1_PMU_SUSCLK,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // ADR_TRIGGER_N (GPIO_81)
- {SOUTH_GROUP1_ADR_TRIGGER,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // PMU_SLP_S45_N (GPIO_82)
- {SOUTH_GROUP1_PMU_SLP_S45_N,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // PMU_SLP_S3_N (GPIO_83)
- {SOUTH_GROUP1_PMU_SLP_S3_N,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // PMU_WAKE_N (GPIO_84)
- {SOUTH_GROUP1_PMU_WAKE_N,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // PMU_PWRBTN_N (GPIO_85)
- {SOUTH_GROUP1_PMU_PWRBTN_N,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // PMU_RESETBUTTON_N (GPIO_86)
- {SOUTH_GROUP1_PMU_RESETBUTTON_N,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // PMU_PLTRST_N (GPIO_87)
- {SOUTH_GROUP1_PMU_PLTRST_N,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // PMU_SUS_STAT_N (GPIO_88)
- {SOUTH_GROUP1_SUS_STAT_N,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // TDB_CIO_PLUG_EVENT (GPIO_89)
- {SOUTH_GROUP1_SLP_S0IX_N,
- {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SPI_CS0_N (GPIO_72)
- {SOUTH_GROUP1_SPI_CS0_N,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SPI_CS1_N (GPIO_73)
- {SOUTH_GROUP1_SPI_CS1_N,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SPI_MOSI_IO0 (GPIO_74)
- {SOUTH_GROUP1_SPI_MOSI_IO0,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SPI_MISO_IO1 (GPIO_75)
- {SOUTH_GROUP1_SPI_MISO_IO1,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SPI_IO2 (GPIO_76)
- {SOUTH_GROUP1_SPI_IO2,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SPI_IO3 (GPIO_77)
- {SOUTH_GROUP1_SPI_IO3,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // SPI_CLK (GPIO_78)
- {SOUTH_GROUP1_SPI_CLK,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // LPC_AD0 (GPIO_64)
- {SOUTH_GROUP1_ESPI_IO0,
- {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // LPC_AD1 (GPIO_65)
- {SOUTH_GROUP1_ESPI_IO1,
- {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // LPC_AD2 (GPIO_66)
- {SOUTH_GROUP1_ESPI_IO2,
- {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // LPC_AD3 (GPIO_67)
- {SOUTH_GROUP1_ESPI_IO3,
- {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // LPC_FRAME_N (GPIO_68)
- {SOUTH_GROUP1_ESPI_CS0_N,
- {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // LPC_CLKOUT0 (GPIO_69)
- {SOUTH_GROUP1_ESPI_CLK,
- {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // LPC_CLKOUT1 (GPIO_70)
- {SOUTH_GROUP1_ESPI_RST_N,
- {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // LPC_CLKRUN_N (GPIO_71)
- {SOUTH_GROUP1_ESPI_ALRT0_N,
- {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // MFG_MODE_HDR (GPIO_10)
- {SOUTH_GROUP1_GPIO_10,
- {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // LPC_SERIRQ (GPIO_11)
- {SOUTH_GROUP1_GPIO_11,
- {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // EMMC-CMD (GPIO_123)
- {SOUTH_GROUP1_EMMC_CMD,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
- // EMMC-CSTROBE (GPIO_124)
- {SOUTH_GROUP1_EMMC_STROBE,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
- // EMMC-CLK (GPIO_125)
- {SOUTH_GROUP1_EMMC_CLK,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermWpd20K, GpioLockDefault} },
- // EMMC-D0 (GPIO_126)
- {SOUTH_GROUP1_EMMC_D0,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
- // EMMC-D1 (GPIO_127)
- {SOUTH_GROUP1_EMMC_D1,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
- // EMMC-D2 (GPIO_128)
- {SOUTH_GROUP1_EMMC_D2,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
- // EMMC-D3 (GPIO_129)
- {SOUTH_GROUP1_EMMC_D3,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
- // EMMC-D4 (GPIO_130)
- {SOUTH_GROUP1_EMMC_D4,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
- // EMMC-D5 (GPIO_131)
- {SOUTH_GROUP1_EMMC_D5,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
- // EMMC-D6 (GPIO_132)
- {SOUTH_GROUP1_EMMC_D6,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
- // EMMC-D7 (GPIO_133)
- {SOUTH_GROUP1_EMMC_D7,
- {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
- // IE_ROM GPIO (GPIO_3)
- {SOUTH_GROUP1_GPIO_3,
- {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
- GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+const struct pad_config tagada_gpio_config[] = {
+ // GBE0_SDP0 (GPIO_14) NC
+/*ME { NORTH_ALL_GBE0_SDP0, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } }, */
+ // GBE1_SDP0 (GPIO_15) NC
+ { NORTH_ALL_GBE1_SDP0, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE2_I2C_CLK (GPIO_16) NC
+ { NORTH_ALL_GBE0_SDP1, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE2_I2C_DATA (GPIO_17) NC
+ { NORTH_ALL_GBE1_SDP1, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE2_SDP0 (GPIO_18) NC
+ { NORTH_ALL_GBE0_SDP2, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE3_SDP0 (GPIO_19) NC
+ { NORTH_ALL_GBE1_SDP2, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE3_I2C_CLK (GPIO_20) NC
+ { NORTH_ALL_GBE0_SDP3, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE3_I2C_DATA (GPIO_21) NC
+ { NORTH_ALL_GBE1_SDP3, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE2_LED0 (GPIO_22) Z1:NC / A0:ETH0_LED0
+ { NORTH_ALL_GBE2_LED0, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE2_LED1 (GPIO_23) Z1:NC / A0:ETH0_LED1
+ { NORTH_ALL_GBE2_LED1, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE0_I2C_CLK (GPIO_24) NC
+ { NORTH_ALL_GBE0_I2C_CLK, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE0_I2C_DATA (GPIO_25) NC
+ { NORTH_ALL_GBE0_I2C_DATA, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE1_I2C_CLK (GPIO_26) NC
+ { NORTH_ALL_GBE1_I2C_CLK, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE1_I2C_DATA (GPIO_27) NC
+ { NORTH_ALL_GBE1_I2C_DATA, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // NCSI_RXD0 (GPIO_28) NC
+ { NORTH_ALL_NCSI_RXD0, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // NCSI_CLK_IN (GPIO_29) Pull Down
+ { NORTH_ALL_NCSI_CLK_IN, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // NCSI_RXD1 (GPIO_30) NC
+ { NORTH_ALL_NCSI_RXD1, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // NCSI_CRS_DV (GPIO_31) NC
+ { NORTH_ALL_NCSI_CRS_DV, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // NCSI_ARB_IN (GPIO_32) NC
+ { NORTH_ALL_NCSI_ARB_IN, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // NCSI_TX_EN (GPIO_33) Pull Down
+ { NORTH_ALL_NCSI_TX_EN, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // NCSI_TXD0 (GPIO_34) Pull Down
+ { NORTH_ALL_NCSI_TXD0, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // NCSI_TXD1 (GPIO_35) Pull Down
+ { NORTH_ALL_NCSI_TXD1, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // NCSI_ARB_OUT (GPIO_36) NC
+ { NORTH_ALL_NCSI_ARB_OUT, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE0_LED0 (GPIO_37) Z1:ETH0_LED0 / A1:ETH1_LED0
+ { NORTH_ALL_GBE0_LED0, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE0_LED1 (GPIO_38) Z1:ETH0_LED1 / A1:ETH1_LED1
+ { NORTH_ALL_GBE0_LED1, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE1_LED0 (GPIO_39) Z1:ETH1_LED0 / A1:NC
+ { NORTH_ALL_GBE1_LED0, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE1_LED1 (GPIO_40) Z1:ETH1_LED1 / A1:NC
+ { NORTH_ALL_GBE1_LED1, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // ADR-COMPLETE (GPIO_0) LFFF: DVT_GPIO<0> : BOOTED, output
+ { NORTH_ALL_GPIO_0, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock } },
+ // PCIE_CLKREQ0_N (GPIO_41) Pull Up
+ { NORTH_ALL_PCIE_CLKREQ0_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // PCIE_CLKREQ1_N (GPIO_42) Pull Up
+ { NORTH_ALL_PCIE_CLKREQ1_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // PCIE_CLKREQ2_N (GPIO_43) Pull Up
+ { NORTH_ALL_PCIE_CLKREQ2_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // PCIE_CLKREQ3_N (GPIO_44) Pull Up
+ { NORTH_ALL_PCIE_CLKREQ3_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // PCIE_CLKREQ4_N (GPIO_45) Pull Up
+ { NORTH_ALL_PCIE_CLKREQ4_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE_MDC (GPIO_1) NC
+ { NORTH_ALL_GPIO_1, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE_MDIO (GPIO_2) NC
+ { NORTH_ALL_GPIO_2, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SVID_ALERT_N (GPIO_47) SVID_ALERTn
+ { NORTH_ALL_SVID_ALERT_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SVID_DATA (GPIO_48) SVID_DATA
+ { NORTH_ALL_SVID_DATA, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SVID_CLK (GPIO_49) SVID_CLK
+ { NORTH_ALL_SVID_CLK, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // THERMTRIP_N (GPIO_50) SOC_THERMTRIPn Pull Up
+ { NORTH_ALL_THERMTRIP_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // PROCHOT_N (GPIO_51) PROCHOTn Pull Up
+ { NORTH_ALL_PROCHOT_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // MEMHOT_N (GPIO_52) SOC_MEMHOTn
+ { NORTH_ALL_MEMHOT_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT_CLK0 (GPIO_53) NC
+ { SOUTH_DFX_DFX_PORT_CLK0, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT_CLK1 (GPIO_54) NC
+ { SOUTH_DFX_DFX_PORT_CLK1, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT0 (GPIO_55) NC
+ { SOUTH_DFX_DFX_PORT0, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT1 (GPIO_56) NC
+ { SOUTH_DFX_DFX_PORT1, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT2 (GPIO_57) NC
+ { SOUTH_DFX_DFX_PORT2, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT3 (GPIO_58) NC
+ { SOUTH_DFX_DFX_PORT3, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT4 (GPIO_59) NC
+ { SOUTH_DFX_DFX_PORT4, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT5 (GPIO_60) NC
+ { SOUTH_DFX_DFX_PORT5, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT6 (GPIO_61) NC
+ { SOUTH_DFX_DFX_PORT6, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT7 (GPIO_62) NC
+ { SOUTH_DFX_DFX_PORT7, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT8 (GPIO_63) NC
+ { SOUTH_DFX_DFX_PORT8, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT9 (GPIO_134) NC
+ { SOUTH_DFX_DFX_PORT9, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT10 (GPIO_135) NC
+ { SOUTH_DFX_DFX_PORT10, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT11 (GPIO_136) NC
+ { SOUTH_DFX_DFX_PORT11, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT12 (GPIO_137) NC
+ { SOUTH_DFX_DFX_PORT12, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT13 (GPIO_138) NC
+ { SOUTH_DFX_DFX_PORT13, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT14 (GPIO_139) NC
+ { SOUTH_DFX_DFX_PORT14, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT15 (GPIO_140) NC
+ { SOUTH_DFX_DFX_PORT15, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SPI_TPM_CS_N (GPIO_12) HS_TCO_WDT NC (Possible Pull Up)
+ { SOUTH_GROUP0_GPIO_12, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SMB5_GBE_ALRT_N (GPIO_13) LAN_ALRTn Pull Up
+ { SOUTH_GROUP0_SMB5_GBE_ALRT_N, { GpioPadModeNative3, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // PCIE_CLKREQ5_N (GPIO_98) Pull Up
+ { SOUTH_GROUP0_PCIE_CLKREQ5_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // PCIE_CLKREQ6_N (GPIO_99) Pull Up
+ { SOUTH_GROUP0_PCIE_CLKREQ6_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // PCIE_CLKREQ7_N (GPIO_100) Pull Up
+ { SOUTH_GROUP0_PCIE_CLKREQ7_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // UART0_RXD (GPIO_101) CONSOLE_RX
+ { SOUTH_GROUP0_UART0_RXD, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // UART0_TXD (GPIO_102) CONSOLE_TX
+ { SOUTH_GROUP0_UART0_TXD, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SMB5_GBE_CLK (GPIO_103) LAN_SLC Pull Up
+ { SOUTH_GROUP0_SMB5_GBE_CLK, { GpioPadModeNative3, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SMB_GBE_DATA (GPIO_104) LAN_SDA Pull UP
+ { SOUTH_GROUP0_SMB5_GBE_DATA, { GpioPadModeNative3, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // ERROR2_N (GPIO_105) ERRORn2
+ { SOUTH_GROUP0_ERROR2_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // ERROR1_N (GPIO_106) ERRORn1
+ { SOUTH_GROUP0_ERROR1_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // ERROR0_N (GPIO_107) ERRORn0 Pull Up
+ { SOUTH_GROUP0_ERROR0_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // IERR_N (CATERR_N) (GPIO_108) IERRn (HardStrap Pull Up)
+ { SOUTH_GROUP0_IERR_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // MCERR_N (GPIO_109) MCERR
+ { SOUTH_GROUP0_MCERR_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SMB0_LEG_CLK (GPIO_110) LEG_SCL Pull Up
+ { SOUTH_GROUP0_SMB0_LEG_CLK, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SMB0_LEG_DATA (GPIO_111) LEG_SDA Pull Up
+ { SOUTH_GROUP0_SMB0_LEG_DATA, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SMB0_LEG_ALRT_N (GPIO_112) Pull Up
+ { SOUTH_GROUP0_SMB0_LEG_ALRT_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SMB1_HOST_DATA (GPIO_113) HOST_SDA Pull Up
+/*ME { SOUTH_GROUP0_SMB1_HOST_DATA, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },*/
+ // SMB1_HOST_CLK (GPIO_114) HOST_SCL Pull Up
+/*ME { SOUTH_GROUP0_SMB1_HOST_CLK, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },*/
+ // SMB2_PECI_DATA (GPIO_115) Pull Up
+ { SOUTH_GROUP0_SMB2_PECI_DATA, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SMB2_PECI_CLK (GPIO_116) Pull Up
+ { SOUTH_GROUP0_SMB2_PECI_CLK, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SMB4_CSME0_DATA (GPIO_117) ME_SDA Pull Up
+/*ME { SOUTH_GROUP0_SMB4_CSME0_DATA, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },*/
+ // SMB4_CSME0_CLK (GPIO_118) ME_SCL Pull Up
+/*ME { SOUTH_GROUP0_SMB4_CSME0_CLK, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },*/
+ // SMB4_CSME0_ALRT_N (GPIO_119) ME_ALRTn Pull Up
+ { SOUTH_GROUP0_SMB4_CSME0_ALRT_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // USB_OC0_N (GPIO_120) Pull Up
+ { SOUTH_GROUP0_USB_OC0_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // FLEX_CLK_SE0 (GPIO_121) NC
+ { SOUTH_GROUP0_FLEX_CLK_SE0, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // FLEX_CLK_SE1 (GPIO_122) NC
+ { SOUTH_GROUP0_FLEX_CLK_SE1, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE3_LED1 (GPIO_4) LFFF: M2A_CFGn : M2A_SATAn, input
+ { SOUTH_GROUP0_GPIO_4, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SMB3_IE0_CLK (GPIO_5) LFFF: M2B_CFGn : M2B_SATAn, input
+ { SOUTH_GROUP0_GPIO_5, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SMB3_IE0_DATA (GPIO_6) NC
+ { SOUTH_GROUP0_GPIO_6, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SMB3_IE0_ALERT_N (GPIO_7) NC
+ { SOUTH_GROUP0_GPIO_7, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SATA0_LED (GPIO_90) SATA_LED0 Pull Up
+ { SOUTH_GROUP0_SATA0_LED_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SATA1_LED (GPIO_91) SATA_LED1 Pull Up
+ { SOUTH_GROUP0_SATA1_LED_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SATA_PDETECT0 (GPIO_92) Pull Up
+ { SOUTH_GROUP0_SATA_PDETECT0, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SATA_PDETECT1 (GPIO_93) Pull Up
+ { SOUTH_GROUP0_SATA_PDETECT1, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // UART1_RTS (GPIO_94) NC (Possible Pull Up)
+ { SOUTH_GROUP0_SATA0_SDOUT, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // UART1_CTS (GPIO_95) NC (Possible Pull Up)
+ { SOUTH_GROUP0_SATA1_SDOUT, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // UART1_RXD (GPIO_96) NC
+ { SOUTH_GROUP0_UART1_RXD, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // UART1_TXD (GPIO_97) NC
+ { SOUTH_GROUP0_UART1_TXD, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SMB6_CSME1_DATA (GPIO_8) LFFF: DVT_GPIO<1> : Baud select, input
+ { SOUTH_GROUP0_GPIO_8, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SMB6_CSME1_CLK (GPIO_9) LFFF: DVT_GPIO<2> : Verbose Traces, input
+ { SOUTH_GROUP0_GPIO_9, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // TCK (GPIO_141) n/a NC
+ { SOUTH_GROUP0_TCK, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // TRST_N (GPIO_142) n/a NC
+ { SOUTH_GROUP0_TRST_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // TMS (GPIO_143) n/a NC
+ { SOUTH_GROUP0_TMS, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // TDI (GPIO_144) n/a NC
+ { SOUTH_GROUP0_TDI, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // TDO (GPIO_145) n/a NC
+ { SOUTH_GROUP0_TDO, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // CX_PRDY_N (GPIO_146) NC
+ { SOUTH_GROUP0_CX_PRDY_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // CX-PREQ_N (GPIO_147) Pull Up
+ { SOUTH_GROUP0_CX_PREQ_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // ME_RECVR_HDR (GPIO_148) ME_RECVR Pull Up
+/*ME { SOUTH_GROUP0_CTBTRIGINOUT, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },*/
+ // ADV_DBG_DFX_HDR (GPIO_149) NC
+ { SOUTH_GROUP0_CTBTRIGOUT, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // LAD2_SPI_IRQ_N (GPIO_150) NC
+ { SOUTH_GROUP0_DFX_SPARE2, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SMB_PECI_ALRT_N (GPIO_151) Pull Up
+ { SOUTH_GROUP0_DFX_SPARE3, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SMB_CSME1_ALRT_N (GPIO_152) NC
+ { SOUTH_GROUP0_DFX_SPARE4, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SUSPWRDNACK (GPIO_79) SUSPWRDNACK Pull Up
+ { SOUTH_GROUP1_SUSPWRDNACK, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // PMU_SUSCLK (GPIO_80) PMU_SUSCLK
+ { SOUTH_GROUP1_PMU_SUSCLK, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // ADR_TRIGGER_N (GPIO_81) Pull Down
+ { SOUTH_GROUP1_ADR_TRIGGER, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // PMU_SLP_S45_N (GPIO_82) SLP_S45n
+ { SOUTH_GROUP1_PMU_SLP_S45_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // PMU_SLP_S3_N (GPIO_83) SLP_S3n
+ { SOUTH_GROUP1_PMU_SLP_S3_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // PMU_WAKE_N (GPIO_84) PMU_WAKEn Pull Up
+ { SOUTH_GROUP1_PMU_WAKE_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // PMU_PWRBTN_N (GPIO_85) PWNBTNn
+ { SOUTH_GROUP1_PMU_PWRBTN_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // PMU_RESETBUTTON_N (GPIO_86) RSTBTNn
+ { SOUTH_GROUP1_PMU_RESETBUTTON_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // PMU_PLTRST_N (GPIO_87) PLTRSTn
+ { SOUTH_GROUP1_PMU_PLTRST_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // PMU_SUS_STAT_N (GPIO_88) SUS_STATn
+ { SOUTH_GROUP1_SUS_STAT_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // TDB_CIO_PLUG_EVENT (GPIO_89) NC
+ { SOUTH_GROUP1_SLP_S0IX_N, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SPI_CS0_N (GPIO_72) SPI_CS0
+ { SOUTH_GROUP1_SPI_CS0_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SPI_CS1_N (GPIO_73) NC
+ { SOUTH_GROUP1_SPI_CS1_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SPI_MOSI_IO0 (GPIO_74) SPI_MOSI
+ { SOUTH_GROUP1_SPI_MOSI_IO0, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SPI_MISO_IO1 (GPIO_75) SPI_MISO
+ { SOUTH_GROUP1_SPI_MISO_IO1, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SPI_IO2 (GPIO_76) NC
+ { SOUTH_GROUP1_SPI_IO2, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SPI_IO3 (GPIO_77) NC
+ { SOUTH_GROUP1_SPI_IO3, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SPI_CLK (GPIO_78) SPI_CLK
+ { SOUTH_GROUP1_SPI_CLK, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // LPC_AD0 (GPIO_64) NC
+ { SOUTH_GROUP1_ESPI_IO0, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // LPC_AD1 (GPIO_65) NC
+ { SOUTH_GROUP1_ESPI_IO1, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // LPC_AD2 (GPIO_66) NC
+ { SOUTH_GROUP1_ESPI_IO2, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // LPC_AD3 (GPIO_67) NC
+ { SOUTH_GROUP1_ESPI_IO3, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // LPC_FRAME_N (GPIO_68) NC
+ { SOUTH_GROUP1_ESPI_CS0_N, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // LPC_CLKOUT0 (GPIO_69) NC
+ { SOUTH_GROUP1_ESPI_CLK, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // LPC_CLKOUT1 (GPIO_70) NC
+ { SOUTH_GROUP1_ESPI_RST_N, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // LPC_CLKRUN_N (GPIO_71) Pull Up
+ { SOUTH_GROUP1_ESPI_ALRT0_N, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // MFG_MODE_HDR (GPIO_10) MFG_MODE Pull Up
+ { SOUTH_GROUP1_GPIO_10, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // LPC_SERIRQ (GPIO_11) NC
+ { SOUTH_GROUP1_GPIO_11, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // EMMC-CMD (GPIO_123) NC
+ { SOUTH_GROUP1_EMMC_CMD, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // EMMC-CSTROBE (GPIO_124) NC
+ { SOUTH_GROUP1_EMMC_STROBE, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // EMMC-CLK (GPIO_125) NC
+ { SOUTH_GROUP1_EMMC_CLK, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // EMMC-D0 (GPIO_126) NC
+ { SOUTH_GROUP1_EMMC_D0, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermWpu20K, GpioPadConfigLock | GpioOutputStateLock } },
+ // EMMC-D1 (GPIO_127) NC
+ { SOUTH_GROUP1_EMMC_D1, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermWpu20K, GpioPadConfigLock | GpioOutputStateLock } },
+ // EMMC-D2 (GPIO_128) NC
+ { SOUTH_GROUP1_EMMC_D2, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermWpu20K, GpioPadConfigLock | GpioOutputStateLock } },
+ // EMMC-D3 (GPIO_129) NC
+ { SOUTH_GROUP1_EMMC_D3, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermWpu20K, GpioPadConfigLock | GpioOutputStateLock } },
+ // EMMC-D4 (GPIO_130) NC
+ { SOUTH_GROUP1_EMMC_D4, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermWpu20K, GpioPadConfigLock | GpioOutputStateLock } },
+ // EMMC-D5 (GPIO_131) NC
+ { SOUTH_GROUP1_EMMC_D5, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermWpu20K, GpioPadConfigLock | GpioOutputStateLock } },
+ // EMMC-D6 (GPIO_132) NC
+ { SOUTH_GROUP1_EMMC_D6, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermWpu20K, GpioPadConfigLock | GpioOutputStateLock } },
+ // EMMC-D7 (GPIO_133) NC
+ { SOUTH_GROUP1_EMMC_D7, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermWpu20K, GpioPadConfigLock | GpioOutputStateLock } },
+ // IE_ROM GPIO (GPIO_3) HS_TSO NC (Possible Pull Up)
+ { SOUTH_GROUP1_GPIO_3, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
};
#endif
diff --git a/src/mainboard/scaleway/tagada/romstage.c b/src/mainboard/scaleway/tagada/romstage.c
index 144d1e8..d6a1282 100644
--- a/src/mainboard/scaleway/tagada/romstage.c
+++ b/src/mainboard/scaleway/tagada/romstage.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Intel Corp.
+ * Copyright (C) 2017 - 2018 Online SAS.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -14,7 +15,6 @@
* GNU General Public License for more details.
*/
-#include "harcuvar_boardid.h"
#include "gpio.h"
#include <console/console.h>
#include <fsp/api.h>
@@ -31,21 +31,12 @@
{
size_t num;
const struct pad_config *table;
- uint8_t boardid = board_id();
/* Configure pads prior to SiliconInit() in case there's any
* dependencies during hardware initialization.
*/
- switch (boardid) {
- case BoardIdHarcuvar:
- table = harcuvar_gpio_table;
- num = ARRAY_SIZE(harcuvar_gpio_table);
- break;
- default:
- table = NULL;
- num = 0;
- break;
- }
+ table = tagada_gpio_config;
+ num = ARRAY_SIZE(tagada_gpio_config);
if ((!table) || (!num)) {
printk(BIOS_ERR, "ERROR: No valid GPIO table found!\n");
--
To view, visit https://review.coreboot.org/23740
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia0293a0ec85c752686750dadb9730a159fd0c073
Gerrit-Change-Number: 23740
Gerrit-PatchSet: 1
Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net>
1
0
Change in coreboot[master]: mb/scaleway/tagada: Remove eMMC configuration
by Julien Viard de Galbert (Code Review) 13 Feb '18
by Julien Viard de Galbert (Code Review) 13 Feb '18
13 Feb '18
Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/23739
Change subject: mb/scaleway/tagada: Remove eMMC configuration
......................................................................
mb/scaleway/tagada: Remove eMMC configuration
The board does no support eMMC so no need to configure it.
Change-Id: If29009a09f39484b1da16fb650b4f9cbee2a6d19
Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net>
---
D src/mainboard/scaleway/tagada/emmc.h
M src/mainboard/scaleway/tagada/ramstage.c
2 files changed, 3 insertions(+), 67 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/23739/1
diff --git a/src/mainboard/scaleway/tagada/emmc.h b/src/mainboard/scaleway/tagada/emmc.h
deleted file mode 100644
index 9832191..0000000
--- a/src/mainboard/scaleway/tagada/emmc.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 - 2017 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _MAINBOARD_EMMC_H
-#define _MAINBOARD_EMMC_H
-
-#include <fsp/util.h>
-
-#define DEFAULT_EMMC_DLL_SIGN 0x55aa
-
-#ifndef __ACPI__
-BL_EMMC_INFORMATION harcuvar_emmc_config[] = {
- /*
- * Default eMMC DLL configuration.
- */
- {DEFAULT_EMMC_DLL_SIGN,
- {0x00000508, 0x00000c11, 0x1c2a2a2a, 0x00191e27, 0x00000a0a,
- 0x00010013, 0x00000001} } };
-#endif
-
-#endif /* _MAINBOARD_EMMC_H */
diff --git a/src/mainboard/scaleway/tagada/ramstage.c b/src/mainboard/scaleway/tagada/ramstage.c
index 4d90858..0aa6f13 100644
--- a/src/mainboard/scaleway/tagada/ramstage.c
+++ b/src/mainboard/scaleway/tagada/ramstage.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2014 - 2017 Intel Corporation
+ * Copyright (C) 2017 - 2018 Online SAS.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,40 +18,9 @@
#include <console/console.h>
#include <fsp/api.h>
#include <soc/ramstage.h>
-#include "emmc.h"
-
-static int get_emmc_dll_info(uint16_t signature, size_t num_of_entry,
- BL_EMMC_INFORMATION **config)
-{
- uint8_t entry;
-
- if ((signature == 0) || (num_of_entry == 0) || (*config == NULL))
- return 1;
-
- for (entry = 0; entry < num_of_entry; entry++) {
- if ((*config)[entry].Signature == signature) {
- *config = &(*config)[entry];
- return 0;
- }
- }
-
- return 1;
-}
void mainboard_silicon_init_params(FSPS_UPD *params)
{
- size_t num;
- uint16_t emmc_dll_sign;
- BL_EMMC_INFORMATION *emmc_config;
-
- /* Configure eMMC DLL PCD */
- emmc_dll_sign = DEFAULT_EMMC_DLL_SIGN;
- num = ARRAY_SIZE(harcuvar_emmc_config);
- emmc_config = harcuvar_emmc_config;
-
- if (get_emmc_dll_info(emmc_dll_sign, num, &emmc_config))
- die("eMMC DLL Configuration is invalid, please correct it!");
-
- params->FspsConfig.PcdEMMCDLLConfigPtr =
- (uint32_t)&emmc_config->eMMCDLLConfig;
+ /* Disable eMMC */
+ params->FspsConfig.PcdEnableEmmc = 0;
}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: If29009a09f39484b1da16fb650b4f9cbee2a6d19
Gerrit-Change-Number: 23739
Gerrit-PatchSet: 1
Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net>
1
0
Change in coreboot[master]: mb/scaleway/tagada: Remove memory down option
by Julien Viard de Galbert (Code Review) 13 Feb '18
by Julien Viard de Galbert (Code Review) 13 Feb '18
13 Feb '18
Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/23738
Change subject: mb/scaleway/tagada: Remove memory down option
......................................................................
mb/scaleway/tagada: Remove memory down option
The board does not have memory down, only 2 DDR4 Slots.
Change-Id: I70eda83fbce7a707da170c7e555ed1a6dc6b1f4a
Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net>
---
M src/mainboard/scaleway/tagada/Kconfig
M src/mainboard/scaleway/tagada/Makefile.inc
M src/mainboard/scaleway/tagada/romstage.c
D src/mainboard/scaleway/tagada/spd/Makefile.inc
D src/mainboard/scaleway/tagada/spd/micron_4GiB_dimm_MTA9ASF51272PZ-2G1A2.spd.hex
D src/mainboard/scaleway/tagada/spd/spd.c
D src/mainboard/scaleway/tagada/spd/spd.h
7 files changed, 5 insertions(+), 740 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/23738/1
diff --git a/src/mainboard/scaleway/tagada/Kconfig b/src/mainboard/scaleway/tagada/Kconfig
index 4c9aafd..53c1f6d 100644
--- a/src/mainboard/scaleway/tagada/Kconfig
+++ b/src/mainboard/scaleway/tagada/Kconfig
@@ -33,17 +33,4 @@
string
default "Scaleway"
-config ENABLE_FSP_MEMORY_DOWN
- bool "Enable Memory Down"
- default n
- help
- Select this option to enable Memory Down function.
-
-config SPD_LOC
- depends on ENABLE_FSP_MEMORY_DOWN
- hex "SPD binary location in cbfs"
- default 0xfffdf000
- help
- Location of SPD binary for memory down function.
-
endif # BOARD_SCALEWAY_TAGADA
diff --git a/src/mainboard/scaleway/tagada/Makefile.inc b/src/mainboard/scaleway/tagada/Makefile.inc
index d100688..7421f38 100644
--- a/src/mainboard/scaleway/tagada/Makefile.inc
+++ b/src/mainboard/scaleway/tagada/Makefile.inc
@@ -14,8 +14,6 @@
## GNU General Public License for more details.
##
-subdirs-$(CONFIG_ENABLE_FSP_MEMORY_DOWN) += spd
-
romstage-y += boardid.c
romstage-y += hsio.c
diff --git a/src/mainboard/scaleway/tagada/romstage.c b/src/mainboard/scaleway/tagada/romstage.c
index f0c7cb9..144d1e8 100644
--- a/src/mainboard/scaleway/tagada/romstage.c
+++ b/src/mainboard/scaleway/tagada/romstage.c
@@ -16,70 +16,11 @@
#include "harcuvar_boardid.h"
#include "gpio.h"
-#include "spd/spd.h"
#include <console/console.h>
#include <fsp/api.h>
#include <fsp/soc_binding.h>
#include <string.h>
-#if IS_ENABLED(CONFIG_ENABLE_FSP_MEMORY_DOWN)
-
-/*
- * Define platform specific Memory Down Configure structure.
- *
- * If CONFIG_ENABLE_FSP_MEMORY_DOWN is enabled, the MEMORY_DOWN_CONFIG
- * structure should be customized to match the design.
- *
- * .SlotState indicates the memory down state of the specific channel/DIMM.
- *
- * SlotState options:
- *
- * STATE_MEMORY_DOWN: Memory down.
- * STATE_MEMORY_SLOT: Physical memory slot.
- *
- * .SpdDataLen should always be MAX_SPD_BYTES/512.
- *
- * .SpdDataPtr is pointing to the SPD data structure when memory modules
- * are memory down.
- *
- * SpdDataPtr options:
- *
- * Non-NULL: Pointing to SPD data structure.
- * NULL: Physical memory slot, no SPD data used.
- *
- * DIMM Mapping of SlotState & SpdDataPtr:
- *
- * {{CH0DIMM0, CH0DIMM1}, {CH1DIMM0, CH1DIMM1}}
- *
- * Sample: Channel 0 is memory down and channel 1 is physical slot.
- *
- * const MEMORY_DOWN_CONFIG mMemoryDownConfig = {
- * .SlotState = {
- * {STATE_MEMORY_DOWN, STATE_MEMORY_DOWN},
- * {STATE_MEMORY_SLOT, STATE_MEMORY_SLOT}
- * },
- * .SpdDataLen = MAX_SPD_BYTES,
- * .SpdDataPtr = {
- * {(void *)CONFIG_SPD_LOC, (void *)CONFIG_SPD_LOC},
- * {(void *)NULL, (void *)NULL}
- * }
- * }
- */
-
-const MEMORY_DOWN_CONFIG mMemoryDownConfig = {
- .SlotState = {
- {STATE_MEMORY_SLOT, STATE_MEMORY_SLOT},
- {STATE_MEMORY_SLOT, STATE_MEMORY_SLOT}
- },
- .SpdDataLen = MAX_SPD_BYTES,
- .SpdDataPtr = {
- {(void *)NULL, (void *)NULL},
- {(void *)NULL, (void *)NULL}
- }
-};
-
-#endif /* CONFIG_ENABLE_FSP_MEMORY_DOWN */
-
void mainboard_config_gpios(void);
void mainboard_memory_init_params(FSPM_UPD *mupd);
@@ -118,27 +59,10 @@
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
-#if IS_ENABLED(CONFIG_ENABLE_FSP_MEMORY_DOWN)
- uint8_t *spd_data_ptr = NULL;
+ mupd->FspmConfig.PcdFspDebugPrintErrorLevel = 3; // Verbose
- /* Get SPD data pointer */
- spd_data_ptr = mainboard_find_spd_data();
-
- if (spd_data_ptr != NULL) {
- printk(BIOS_DEBUG, "Memory Down function is enabled!\n");
-
- /* Enable Memory Down function, set Memory
- * Down Configure structure pointer.
- */
- mupd->FspmConfig.PcdMemoryDown = 1;
- mupd->FspmConfig.PcdMemoryDownConfigPtr =
- (uint32_t)&mMemoryDownConfig;
- } else {
- printk(BIOS_DEBUG, "Memory Down function is disabled!\n");
-
- /* Disable Memory Down function */
- mupd->FspmConfig.PcdMemoryDown = 0;
- mupd->FspmConfig.PcdMemoryDownConfigPtr = 0;
- }
-#endif /* CONFIG_ENABLE_FSP_MEMORY_DOWN */
+ // Enable Rmt and Fast Boot by default, RMT will be run only on first
+ // boot or when dimms change
+ mupd->FspmConfig.PcdMrcRmtSupport = 1;
+ mupd->FspmConfig.PcdFastBoot = 1;
}
diff --git a/src/mainboard/scaleway/tagada/spd/Makefile.inc b/src/mainboard/scaleway/tagada/spd/Makefile.inc
deleted file mode 100644
index 38d5046..0000000
--- a/src/mainboard/scaleway/tagada/spd/Makefile.inc
+++ /dev/null
@@ -1,38 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013 Google Inc.
-## Copyright (C) 2015 - 2017 Intel Corporation.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-romstage-y += spd.c
-
-SPD_BIN = $(obj)/spd.bin
-
-# Order matters for SPD sources. The following indices
-# define the SPD data to use.
-SPD_SOURCES = micron_4GiB_dimm_MTA9ASF51272PZ-2G1A2
-
-SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
-
-# Include spd rom data
-$(SPD_BIN): $(SPD_DEPS)
- for f in $+; \
- do for c in $$(cat $$f | grep -v ^#); \
- do echo -e -n "\\x$$c"; \
- done; \
- done > $@
-
-cbfs-files-y += spd.bin
-spd.bin-file := $(SPD_BIN)
-spd.bin-position := $(CONFIG_SPD_LOC)
-spd.bin-type := spd
diff --git a/src/mainboard/scaleway/tagada/spd/micron_4GiB_dimm_MTA9ASF51272PZ-2G1A2.spd.hex b/src/mainboard/scaleway/tagada/spd/micron_4GiB_dimm_MTA9ASF51272PZ-2G1A2.spd.hex
deleted file mode 100644
index 4abad8d..0000000
--- a/src/mainboard/scaleway/tagada/spd/micron_4GiB_dimm_MTA9ASF51272PZ-2G1A2.spd.hex
+++ /dev/null
@@ -1,513 +0,0 @@
-#DDR4_4GB_RDIMM_Micron_MTA9ASF51272PZ-2G1A2.txt
-23
-10
-0C
-01
-84
-19
-00
-05
-00
-00
-00
-03
-01
-0B
-80
-00
-00
-00
-08
-0C
-F4
-1B
-00
-00
-6C
-6C
-6C
-11
-08
-74
-20
-08
-00
-05
-70
-03
-00
-A8
-1E
-2B
-2B
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-0E
-2E
-16
-36
-16
-36
-16
-36
-0E
-2E
-23
-04
-2B
-0C
-2B
-0C
-23
-04
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
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-00
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-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-EC
-B5
-CE
-00
-00
-00
-00
-00
-C2
-64
-2B
-11
-11
-03
-05
-00
-86
-32
-B1
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
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-00
-00
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-00
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-00
-00
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-00
-00
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-00
-EF
-9E
-00
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-00
-00
-00
-00
-00
-00
-80
-2C
-00
-00
-00
-00
-00
-00
-00
-39
-41
-53
-46
-35
-31
-32
-37
-32
-50
-5a
-2d
-32
-47
-31
-41
-32
-00
-00
-00
-32
-80
-2C
-41
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
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-00
-00
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-00
-00
-00
-00
-00
-00
-00
-00
-00
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-00
-00
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-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
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-00
-00
-00
-00
-00
-00
-00
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-00
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-00
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-00
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-00
-00
-00
-00
-00
-00
-00
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-00
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-00
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-00
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-00
-00
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-00
diff --git a/src/mainboard/scaleway/tagada/spd/spd.c b/src/mainboard/scaleway/tagada/spd/spd.c
deleted file mode 100644
index 37f4424..0000000
--- a/src/mainboard/scaleway/tagada/spd/spd.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 - 2017 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <arch/byteorder.h>
-#include <cbfs.h>
-#include <console/console.h>
-#include <string.h>
-
-#include "spd.h"
-
-/* Get SPD data for on-board memory */
-uint8_t *mainboard_find_spd_data()
-{
- uint8_t *spd_data;
- int spd_index;
- size_t spd_file_len;
- char *spd_file;
-
- spd_index = 0;
-
- spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
- &spd_file_len);
- if (!spd_file)
- die("SPD data not found.");
-
- if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
- printk(BIOS_ERR,
- "SPD index override to 0 due to incorrect SPD index.\n");
- spd_index = 0;
- }
-
- if (spd_file_len < SPD_LEN)
- die("Missing SPD data.");
-
- /* Assume same memory in both channels */
- spd_index *= SPD_LEN;
- spd_data = (uint8_t *)(spd_file + spd_index);
-
- /* Make sure a valid SPD was found */
- if (spd_data[0] == 0)
- die("Invalid SPD data.");
-
- return spd_data;
-}
diff --git a/src/mainboard/scaleway/tagada/spd/spd.h b/src/mainboard/scaleway/tagada/spd/spd.h
deleted file mode 100644
index 13692d7..0000000
--- a/src/mainboard/scaleway/tagada/spd/spd.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 - 2017 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef MAINBOARD_SPD_H
-#define MAINBOARD_SPD_H
-
-#define SPD_LEN 512
-
-#define SPD_DRAM_TYPE 2
-#define SPD_DRAM_DDR3 0x0b
-#define SPD_DRAM_LPDDR3 0xf1
-#define SPD_DENSITY_BANKS 4
-#define SPD_ADDRESSING 5
-#define SPD_ORGANIZATION 7
-#define SPD_BUS_DEV_WIDTH 8
-#define SPD_PART_OFF 128
-#define SPD_PART_LEN 18
-
-uint8_t *mainboard_find_spd_data(void);
-
-#endif
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I70eda83fbce7a707da170c7e555ed1a6dc6b1f4a
Gerrit-Change-Number: 23738
Gerrit-PatchSet: 1
Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net>
1
0
Change in coreboot[master]: mb/scaleway/tagada: Update HSIO configuration
by Julien Viard de Galbert (Code Review) 13 Feb '18
by Julien Viard de Galbert (Code Review) 13 Feb '18
13 Feb '18
Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/23737
Change subject: mb/scaleway/tagada: Update HSIO configuration
......................................................................
mb/scaleway/tagada: Update HSIO configuration
Change-Id: I213ea13078fdc28489eb4572a084146df333a31d
Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net>
---
M src/mainboard/scaleway/tagada/hsio.c
M src/mainboard/scaleway/tagada/hsio.h
2 files changed, 528 insertions(+), 531 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/23737/1
diff --git a/src/mainboard/scaleway/tagada/hsio.c b/src/mainboard/scaleway/tagada/hsio.c
index fa17130..a8a2035 100644
--- a/src/mainboard/scaleway/tagada/hsio.c
+++ b/src/mainboard/scaleway/tagada/hsio.c
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Intel Corporation.
- * Copyright (C) 2017 Online SAS.
+ * Copyright (C) 2017 - 2018 Online SAS.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -14,23 +14,13 @@
* GNU General Public License for more details.
*/
-#include <harcuvar_boardid.h>
#include <hsio.h>
#include <soc/fiamux.h>
size_t mainboard_get_hsio_config(BL_HSIO_INFORMATION **p_hsio_config)
{
- uint8_t boardid = board_id();
size_t num;
- switch (boardid) {
- case BoardIdHarcuvar:
- num = ARRAY_SIZE(harcuvar_hsio_config);
- (*p_hsio_config) = (BL_HSIO_INFORMATION *)harcuvar_hsio_config;
- break;
- default:
- num = 0;
- (*p_hsio_config) = NULL;
- break;
- }
+ num = ARRAY_SIZE(tagada_hsio_config);
+ (*p_hsio_config) = (BL_HSIO_INFORMATION *)tagada_hsio_config;
return num;
}
diff --git a/src/mainboard/scaleway/tagada/hsio.h b/src/mainboard/scaleway/tagada/hsio.h
index ce059fd..e49fefd 100644
--- a/src/mainboard/scaleway/tagada/hsio.h
+++ b/src/mainboard/scaleway/tagada/hsio.h
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2016-2017 Intel Corporation.
+ * Copyright (C) 2017 - 2018 Online SAS.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -20,605 +21,611 @@
#include <fsp/util.h>
#ifndef __ACPI__
-const BL_HSIO_INFORMATION harcuvar_hsio_config[] = {
+const BL_HSIO_INFORMATION tagada_hsio_config[] = {
/*
* Supported Lanes:
* 20
*
* Bifurcation:
- * PCIE cluster #0: x8
- * PCIE cluster #1: x4x4
+ * PCIE cluster #0: x4x4
+ * PCIE cluster #1: x2x2x2x2 (used for M2)
*
* FIA MUX config:
- * Lane[00:07]->x8 PCIE slot
- * Lane[08:11]->a x4 PCIe slot
- * Lane[12:15]->a 2nd x4 PCIe slot
- * Lane[16]->a SATA connector with pin7 to 5V adapter capable
- * Lane[17:18] -> 2 SATA connectors
+ * Lane[00:03]-> disconnected
+ * Lane[08:11]-> 4 SATA side connectors
+ * Lane[12:15]-> 4 PCIe or 2 SATA (12,14) on M2 Connectors.
+ * M2 modules are detected; configuration updated by coreboot
* Lane[19]->USB3 rear I/O panel connector
*/
- /* SKU HSIO 20 (pcie [0-15] sata [16-18] usb [19]) */
+ /* SKU HSIO 20 (pcie [12-15] sata [8-11,12,14] usb [19]) */
{BL_SKU_HSIO_20,
- {PCIE_BIF_CTRL_x8, PCIE_BIF_CTRL_x4x4},
- {/* ME_FIA_MUX_CONFIG */
- {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE00) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE01) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE02) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE03) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE04) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE05) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE06) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE07) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE08) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE09) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE10) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE11) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE13) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE14) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE15) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE16) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE17) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE18) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},
-
- /* ME_FIA_SATA_CONFIG */
- {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE04) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE05) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE06) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE07) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE08) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE09) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE10) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE11) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE12) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE13) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE14) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE15) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
- BL_FIA_SATA_LANE16) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
- BL_FIA_SATA_LANE17) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
- BL_FIA_SATA_LANE18) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE19)},
-
- /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */
- {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
- BL_FIA_PCIE_ROOT_PORT_0) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
- BL_FIA_PCIE_ROOT_PORT_1) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
- BL_FIA_PCIE_ROOT_PORT_2) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
- BL_FIA_PCIE_ROOT_PORT_3) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
- BL_FIA_PCIE_ROOT_PORT_4) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
- BL_FIA_PCIE_ROOT_PORT_5) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
- BL_FIA_PCIE_ROOT_PORT_6) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
- BL_FIA_PCIE_ROOT_PORT_7) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_0) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_1) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_2) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_3) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_4) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_5) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_6) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_7)} } },
-
- /* SKU HSIO 12 (pcie [0-3, 8-9, 12-13] sata [16-18] usb [19]) */
- {BL_SKU_HSIO_12,
{PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},
- {/*ME_FIA_MUX_CONFIG */
- {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE00) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE01) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE02) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE03) |
+ {/* ME_FIA_MUX_CONFIG */
+ {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE00) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE01) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE02) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE03) |
BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) |
BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) |
BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) |
BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE08) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE09) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE10) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE11) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE13) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE14) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE15) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE16) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE17) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE18) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE08) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE09) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE10) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE11) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE13) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE14) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE15) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE16) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE17) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},
/* ME_FIA_SATA_CONFIG */
{BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE04) |
+ BL_FIA_SATA_LANE04) |
BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE05) |
+ BL_FIA_SATA_LANE05) |
BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE06) |
+ BL_FIA_SATA_LANE06) |
BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE07) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE08) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE09) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE10) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE11) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE12) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE13) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE14) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE15) |
+ BL_FIA_SATA_LANE07) |
BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
- BL_FIA_SATA_LANE16) |
+ BL_FIA_SATA_LANE08) |
BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
- BL_FIA_SATA_LANE17) |
+ BL_FIA_SATA_LANE09) |
BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
- BL_FIA_SATA_LANE18) |
+ BL_FIA_SATA_LANE10) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE11) |
BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE19)},
+ BL_FIA_SATA_LANE12) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE13) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE14) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE15) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE16) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE17) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE18) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE19)},
/* ME_FIA_PCIE_ROOT_PORTS_CONFIG */
{BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
- BL_FIA_PCIE_ROOT_PORT_0) |
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_0) |
BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
- BL_FIA_PCIE_ROOT_PORT_1) |
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_1) |
BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
- BL_FIA_PCIE_ROOT_PORT_2) |
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_2) |
BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
- BL_FIA_PCIE_ROOT_PORT_3) |
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_3) |
BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
- BL_FIA_PCIE_ROOT_PORT_4) |
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_4) |
BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
- BL_FIA_PCIE_ROOT_PORT_5) |
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_5) |
BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
- BL_FIA_PCIE_ROOT_PORT_6) |
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_6) |
BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
- BL_FIA_PCIE_ROOT_PORT_7) |
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_7) |
BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_0) |
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_0) |
BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_1) |
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_1) |
BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_2) |
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_2) |
BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_3) |
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_3) |
BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_4) |
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_4) |
BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_5) |
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_5) |
BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_6) |
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_6) |
BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_7)} } },
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_7)} } },
- /* SKU HSIO 10 (pcie [0-3, 8-9, 12] sata [16-17] usb [19]) */
+ /* SKU HSIO 12 (pcie [12-15] sata [8-11,12,14] usb [19]) */
+ {BL_SKU_HSIO_12,
+ {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},
+ {/* ME_FIA_MUX_CONFIG */
+ {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE00) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE01) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE02) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE03) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE08) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE09) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE10) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE11) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE13) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE14) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE15) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE16) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE17) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},
+
+ /* ME_FIA_SATA_CONFIG */
+ {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE04) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE05) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE06) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE07) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE08) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE09) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE10) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE11) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE12) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE13) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE14) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE15) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE16) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE17) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE18) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE19)},
+
+ /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */
+ {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_0) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_1) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_2) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_3) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_4) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG( BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_5) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_6) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_7) |
+
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_0) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_1) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_2) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_3) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_4) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_5) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_6) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_7)} } },
+
+ /* SKU HSIO 10 (pcie [12-15] sata [8-11,12,14] usb [19]) */
{BL_SKU_HSIO_10,
{PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},
{/* ME_FIA_MUX_CONFIG */
- {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE00) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE01) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE02) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE03) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE08) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE09) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE10) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE11) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE13) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE14) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE15) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE16) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE17) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},
-
- /* ME_FIA_SATA_CONFIG */
- {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE04) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE05) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE06) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE07) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE08) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE09) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE10) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE11) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE12) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE13) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE14) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE15) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
- BL_FIA_SATA_LANE16) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
- BL_FIA_SATA_LANE17) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE18) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE19)},
-
- /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */
- {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
- BL_FIA_PCIE_ROOT_PORT_0) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
- BL_FIA_PCIE_ROOT_PORT_1) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
- BL_FIA_PCIE_ROOT_PORT_2) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
- BL_FIA_PCIE_ROOT_PORT_3) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
- BL_FIA_PCIE_ROOT_PORT_4) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
- BL_FIA_PCIE_ROOT_PORT_5) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
- BL_FIA_PCIE_ROOT_PORT_6) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
- BL_FIA_PCIE_ROOT_PORT_7) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_0) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_1) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_2) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_3) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_4) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_5) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1,
- BL_FIA_PCIE_ROOT_PORT_6) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_7)} } },
-
- /* SKU HSIO 8 (pcie [0-1, 8-9, 12] sata [16-17] usb [19]) */
- {BL_SKU_HSIO_08,
- {PCIE_BIF_CTRL_x2x2x2x2, PCIE_BIF_CTRL_x2x2x2x2},
- {/* ME_FIA_MUX_CONFIG */
- {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE00) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE01) |
+ {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE00) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE01) |
BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE02) |
BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE03) |
BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) |
BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) |
BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) |
BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE08) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE09) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE10) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE11) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE13) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE14) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE15) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE16) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE17) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},
-
- /* ME_FIA_SATA_CONFIG */
- {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE04) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE05) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE06) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE07) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE08) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE09) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE10) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE11) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE12) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE13) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE14) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE15) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
- BL_FIA_SATA_LANE16) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
- BL_FIA_SATA_LANE17) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE18) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE19)},
-
- /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */
- {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
- BL_FIA_PCIE_ROOT_PORT_0) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
- BL_FIA_PCIE_ROOT_PORT_1) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
- BL_FIA_PCIE_ROOT_PORT_2) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
- BL_FIA_PCIE_ROOT_PORT_3) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
- BL_FIA_PCIE_ROOT_PORT_4) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
- BL_FIA_PCIE_ROOT_PORT_5) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
- BL_FIA_PCIE_ROOT_PORT_6) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
- BL_FIA_PCIE_ROOT_PORT_7) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_0) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_1) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_2) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_3) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_4) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_5) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1,
- BL_FIA_PCIE_ROOT_PORT_6) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_7)} } },
-
- /* SKU HSIO 6 (pcie [0-1, 8, 12] sata [16] usb [19]) */
- {BL_SKU_HSIO_06,
- {PCIE_BIF_CTRL_x2x2x2x2, PCIE_BIF_CTRL_x2x2x2x2},
- {/* ME_FIA_MUX_CONFIG */
- {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE00) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE01) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE02) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE03) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE08) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE09) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE10) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE11) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE13) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE14) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE15) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE16) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE08) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE09) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE10) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE11) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE13) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE14) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE15) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE16) |
BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE17) |
BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) |
- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},
/* ME_FIA_SATA_CONFIG */
{BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE04) |
+ BL_FIA_SATA_LANE04) |
BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE05) |
+ BL_FIA_SATA_LANE05) |
BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE06) |
+ BL_FIA_SATA_LANE06) |
BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE07) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE08) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE09) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE10) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE11) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE12) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE13) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE14) |
- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE15) |
+ BL_FIA_SATA_LANE07) |
BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
- BL_FIA_SATA_LANE16) |
+ BL_FIA_SATA_LANE08) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE09) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE10) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE11) |
BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE17) |
+ BL_FIA_SATA_LANE12) |
BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE18) |
+ BL_FIA_SATA_LANE13) |
BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
- BL_FIA_SATA_LANE19)},
+ BL_FIA_SATA_LANE14) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE15) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE16) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE17) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE18) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE19)},
/* ME_FIA_PCIE_ROOT_PORTS_CONFIG */
{BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
- BL_FIA_PCIE_ROOT_PORT_0) |
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_0) |
BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
- BL_FIA_PCIE_ROOT_PORT_1) |
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_1) |
BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
- BL_FIA_PCIE_ROOT_PORT_2) |
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_2) |
BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
- BL_FIA_PCIE_ROOT_PORT_3) |
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_3) |
BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
- BL_FIA_PCIE_ROOT_PORT_4) |
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_4) |
BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
- BL_FIA_PCIE_ROOT_PORT_5) |
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_5) |
BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
- BL_FIA_PCIE_ROOT_PORT_6) |
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_6) |
BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
- BL_FIA_PCIE_ROOT_PORT_7) |
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_7) |
+
BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_0) |
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_0) |
BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_1) |
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_1) |
BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_2) |
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_2) |
BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_3) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1,
- BL_FIA_PCIE_ROOT_PORT_4) |
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_3) |
BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_5) |
- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1,
- BL_FIA_PCIE_ROOT_PORT_6) |
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_4) |
BL_FIA_PCIE_ROOT_PORT_CONFIG(
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
- BL_FIA_PCIE_ROOT_PORT_7)} } }
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_5) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_6) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_7)} } },
+
+ /* SKU HSIO 8 (pcie [12-14] sata [8-11,12,14] usb [19]) */
+ {BL_SKU_HSIO_08,
+ {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},
+ {/* ME_FIA_MUX_CONFIG */
+ {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE00) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE01) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE02) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE03) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE08) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE09) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE10) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE11) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE13) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE14) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE15) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE16) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE17) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},
+
+ /* ME_FIA_SATA_CONFIG */
+ {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE04) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE05) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE06) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE07) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE08) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE09) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE10) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE11) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE12) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE13) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE14) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE15) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE16) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE17) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE18) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE19)},
+
+ /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */
+ {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_0) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_1) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_2) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_3) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_4) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_5) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_6) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_7) |
+
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_0) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_1) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_2) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_3) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_4) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_5) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_6) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_7)} } },
+
+ /* SKU HSIO 6 (pcie [12,14] sata [8-11,12,14] usb []) */
+ {BL_SKU_HSIO_06,
+ {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},
+ {/* ME_FIA_MUX_CONFIG */
+ {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE00) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE01) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE02) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE03) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE08) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE09) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE10) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE11) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE13) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE14) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE15) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE16) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE17) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE19)},
+
+ /* ME_FIA_SATA_CONFIG */
+ {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE04) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE05) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE06) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE07) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE08) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE09) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE10) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE11) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE12) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE13) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE14) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE15) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE16) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE17) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE18) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE19)},
+
+ /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */
+ {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_0) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_1) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_2) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_3) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_4) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_5) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_6) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_7) |
+
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_0) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_1) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_2) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_3) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_4) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_5) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_6) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_7)} } }
};
#endif
-#endif
-/* _MAINBOARD_HSIO_H */
+#endif /* _MAINBOARD_HSIO_H */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I213ea13078fdc28489eb4572a084146df333a31d
Gerrit-Change-Number: 23737
Gerrit-PatchSet: 1
Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net>
1
0
Change in coreboot[master]: mb/scaleway/tagada: Update device tree
by Julien Viard de Galbert (Code Review) 13 Feb '18
by Julien Viard de Galbert (Code Review) 13 Feb '18
13 Feb '18
Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/23736
Change subject: mb/scaleway/tagada: Update device tree
......................................................................
mb/scaleway/tagada: Update device tree
Change-Id: I1c42519dbe848b0bbcafa7f923d862ba7c9d8ed5
Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net>
---
M src/mainboard/scaleway/tagada/devicetree.cb
1 file changed, 6 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/23736/1
diff --git a/src/mainboard/scaleway/tagada/devicetree.cb b/src/mainboard/scaleway/tagada/devicetree.cb
index 7fce211..acf56a0 100644
--- a/src/mainboard/scaleway/tagada/devicetree.cb
+++ b/src/mainboard/scaleway/tagada/devicetree.cb
@@ -53,18 +53,19 @@
device pci 04.0 on end # RAS
device pci 05.0 on end # RCEC(Root Complex Event Collector)
device pci 06.0 on end # Virtual root port 2 (QAT)
- device pci 09.0 on end # PCI Express Port 0, cluster #0, x8
- device pci 0e.0 on end # PCI Express Port 4, cluster #1, x4
- device pci 10.0 on end # PCI Express Port 6, cluster #1, x4
+ device pci 09.0 on end # PCI Express Port 0, cluster #0, x4
+ device pci 10.0 on end # PCI Express Port 6, cluster #1, x2
+ device pci 11.0 on end # PCI Express Port 7, cluster #1, x2
device pci 12.0 on end # SMBus Controller 1
+ device pci 13.0 on end # SATA Controller 0
device pci 14.0 on end # SATA Controller 1
device pci 15.0 on end # XHCI USB Controller
device pci 16.0 on end # Virtual root port 0 (10GBE0)
device pci 17.0 on end # Virtual root port 1 (10GBE1)
device pci 18.0 on end # CSME HECI 1
device pci 1a.0 on end # UART 0
- device pci 1a.1 on end # UART 1
- device pci 1a.2 on end # UART 2
+ device pci 1a.1 off end # UART 1
+ device pci 1a.2 off end # UART 2
device pci 1c.0 on end # eMMC
device pci 1f.0 on end # LPC bridge
device pci 1f.2 on end # PMC/ACPI
--
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Gerrit-Project: coreboot
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Gerrit-Change-Number: 23736
Gerrit-PatchSet: 1
Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net>
1
0
Change in coreboot[master]: mb/scaleway/tagada: Copy intel/harcuvar and rename
by Julien Viard de Galbert (Code Review) 13 Feb '18
by Julien Viard de Galbert (Code Review) 13 Feb '18
13 Feb '18
Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/23735
Change subject: mb/scaleway/tagada: Copy intel/harcuvar and rename
......................................................................
mb/scaleway/tagada: Copy intel/harcuvar and rename
Change-Id: I6fc1f8393ce3f5ba6f52edad7cf8efa5524d2704
Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net>
---
A src/mainboard/scaleway/Kconfig
A src/mainboard/scaleway/Kconfig.name
A src/mainboard/scaleway/tagada/Kconfig
A src/mainboard/scaleway/tagada/Kconfig.name
A src/mainboard/scaleway/tagada/Makefile.inc
A src/mainboard/scaleway/tagada/acpi/mainboard.asl
A src/mainboard/scaleway/tagada/acpi/mainboard_pci_irqs.asl
A src/mainboard/scaleway/tagada/acpi/platform.asl
A src/mainboard/scaleway/tagada/acpi/thermal.asl
A src/mainboard/scaleway/tagada/acpi_tables.c
A src/mainboard/scaleway/tagada/board_info.txt
A src/mainboard/scaleway/tagada/boardid.c
A src/mainboard/scaleway/tagada/devicetree.cb
A src/mainboard/scaleway/tagada/dsdt.asl
A src/mainboard/scaleway/tagada/emmc.h
A src/mainboard/scaleway/tagada/fadt.c
A src/mainboard/scaleway/tagada/gpio.h
A src/mainboard/scaleway/tagada/harcuvar_boardid.h
A src/mainboard/scaleway/tagada/hsio.c
A src/mainboard/scaleway/tagada/hsio.h
A src/mainboard/scaleway/tagada/ramstage.c
A src/mainboard/scaleway/tagada/romstage.c
A src/mainboard/scaleway/tagada/spd/Makefile.inc
A src/mainboard/scaleway/tagada/spd/micron_4GiB_dimm_MTA9ASF51272PZ-2G1A2.spd.hex
A src/mainboard/scaleway/tagada/spd/spd.c
A src/mainboard/scaleway/tagada/spd/spd.h
26 files changed, 2,874 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/23735/1
diff --git a/src/mainboard/scaleway/Kconfig b/src/mainboard/scaleway/Kconfig
new file mode 100644
index 0000000..2af3e29
--- /dev/null
+++ b/src/mainboard/scaleway/Kconfig
@@ -0,0 +1,16 @@
+if VENDOR_SCALEWAY
+
+choice
+ prompt "Mainboard model"
+
+source "src/mainboard/scaleway/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/scaleway/*/Kconfig"
+
+config MAINBOARD_VENDOR
+ string
+ default "Scaleway"
+
+endif # VENDOR_SCALEWAY
diff --git a/src/mainboard/scaleway/Kconfig.name b/src/mainboard/scaleway/Kconfig.name
new file mode 100644
index 0000000..abbc9e7
--- /dev/null
+++ b/src/mainboard/scaleway/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_SCALEWAY
+ bool "Scaleway"
diff --git a/src/mainboard/scaleway/tagada/Kconfig b/src/mainboard/scaleway/tagada/Kconfig
new file mode 100644
index 0000000..4c9aafd
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/Kconfig
@@ -0,0 +1,49 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 - 2017 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+if BOARD_SCALEWAY_TAGADA
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select SOC_INTEL_DENVERTON_NS
+ select BOARD_ROMSIZE_KB_16384
+ select HAVE_ACPI_TABLES
+
+config MAINBOARD_DIR
+ string
+ default scaleway/tagada
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "TAGADA"
+
+config MAINBOARD_VENDOR
+ string
+ default "Scaleway"
+
+config ENABLE_FSP_MEMORY_DOWN
+ bool "Enable Memory Down"
+ default n
+ help
+ Select this option to enable Memory Down function.
+
+config SPD_LOC
+ depends on ENABLE_FSP_MEMORY_DOWN
+ hex "SPD binary location in cbfs"
+ default 0xfffdf000
+ help
+ Location of SPD binary for memory down function.
+
+endif # BOARD_SCALEWAY_TAGADA
diff --git a/src/mainboard/scaleway/tagada/Kconfig.name b/src/mainboard/scaleway/tagada/Kconfig.name
new file mode 100644
index 0000000..67e5e0a
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_SCALEWAY_TAGADA
+ bool "TAGADA"
diff --git a/src/mainboard/scaleway/tagada/Makefile.inc b/src/mainboard/scaleway/tagada/Makefile.inc
new file mode 100644
index 0000000..d100688
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/Makefile.inc
@@ -0,0 +1,28 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 - 2017 Intel Corporation.
+## Copyright (C) 2017 Online SAS.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+subdirs-$(CONFIG_ENABLE_FSP_MEMORY_DOWN) += spd
+
+romstage-y += boardid.c
+romstage-y += hsio.c
+
+ramstage-y += ramstage.c
+ramstage-y += boardid.c
+ramstage-y += hsio.c
+ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.c
+ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
+
+CPPFLAGS_common += -Isrc/mainboard/$(MAINBOARDDIR)/
diff --git a/src/mainboard/scaleway/tagada/acpi/mainboard.asl b/src/mainboard/scaleway/tagada/acpi/mainboard.asl
new file mode 100644
index 0000000..41da382
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/acpi/mainboard.asl
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ * Copyright (C) 2014 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+Scope (\_SB)
+{
+ Device (PWRB)
+ {
+ Name(_HID, EisaId("PNP0C0C"))
+
+ // Wake
+ Name(_PRW, Package(){0x1d, 0x05})
+ }
+}
diff --git a/src/mainboard/scaleway/tagada/acpi/mainboard_pci_irqs.asl b/src/mainboard/scaleway/tagada/acpi/mainboard_pci_irqs.asl
new file mode 100644
index 0000000..e253cea
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/acpi/mainboard_pci_irqs.asl
@@ -0,0 +1,187 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+/* This is board specific information: IRQ routing */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+ If (PICM) {
+ Return (Package() {
+ // [GREG]: Global Registers
+ Package() { 0x0004ffff, 0, 0, 16 },
+
+ // [RCEC]: Root Complex Event Collector
+ Package() { 0x0005ffff, 0, 0, 23 },
+
+ // [VRP2]: Virtual root port 2
+ Package() { 0x0006ffff, 2, 0, 18 },
+
+ // [PEX0]: PCI Express Port 0
+ Package() { 0x0009ffff, 0, 0, 16 },
+
+ // [PEX1]: PCI Express Port 1
+ Package() { 0x000affff, 1, 0, 17 },
+
+ // [PEX2]: PCI Express Port 2
+ Package() { 0x000bffff, 2, 0, 18 },
+
+ // [PEX3]: PCI Express Port 3
+ Package() { 0x000cffff, 3, 0, 19 },
+
+ // [PEX4]: PCI Express Port 4
+ Package() { 0x000effff, 0, 0, 20 },
+
+ // [PEX5]: PCI Express Port 5
+ Package() { 0x000fffff, 1, 0, 21 },
+
+ // [PEX6]: PCI Express Port 6
+ Package() { 0x0010ffff, 2, 0, 22 },
+
+ // [PEX7]: PCI Express Port 7
+ Package() { 0x0011ffff, 3, 0, 23 },
+
+ // [SMB1]: SMBus controller
+ Package() { 0x0012ffff, 0, 0, 16 },
+
+ // [SAT0]: SATA controller 0
+ Package() { 0x0013ffff, 0, 0, 20 },
+
+ // [SAT1]: SATA controller 1
+ Package() { 0x0014ffff, 0, 0, 21 },
+
+ // [XHC0]: XHCI USB controller
+ Package() { 0x0015ffff, 0, 0, 19 },
+
+ // [VRP0]: Virtual root port 0
+ Package() { 0x0016ffff, 0, 0, 16 },
+
+ // [VRP1]: Virtual root port 1
+ Package() { 0x0017ffff, 1, 0, 17 },
+
+ // [HECI]: ME HECI
+ Package() { 0x0018ffff, 0, 0, 16 },
+
+ // [HEC2]: ME HECI2
+ Package() { 0x0018ffff, 1, 0, 17 },
+
+ // [MEKT]: MEKT on PCH
+ Package() { 0x0018ffff, 2, 0, 18 },
+
+ // [HEC3]: ME HECI3
+ Package() { 0x0018ffff, 3, 0, 19 },
+
+ // [UAR0]: UART 0
+ Package() { 0x001affff, 0, 0, 16 },
+
+ // [UAR1]: UART 1
+ Package() { 0x001affff, 1, 0, 17 },
+
+ // [UAR2]: UART 2
+ Package() { 0x001affff, 2, 0, 18 },
+
+ // [EMMC]: eMMC
+ Package() { 0x001cffff, 0, 0, 16 },
+
+ // [P2SB]: Primary to sideband bridge
+ // [SMB0]: SMBus controller
+ // [NPK0]: Northpeak DFX
+ Package() { 0x001fffff, 0, 0, 23 },
+ })
+ } Else {
+ Return (Package() {
+ // [GREG]: Global Registers 0:4.0
+ Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+
+ // [RCEC]: Root Complex Event Collector 0:5.0
+ Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
+
+ // [VRP2]: Virtual root port 2 0:6.0
+ Package() { 0x0006ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+
+ // [PEX0]: PCI Express Port 0 0:9.0
+ Package() { 0x0009ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+
+ // [PEX1]: PCI Express Port 1 0:a.0
+ Package() { 0x000affff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+
+ // [PEX2]: PCI Express Port 2 0:b.0
+ Package() { 0x000bffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+
+ // [PEX3]: PCI Express Port 3 0:c.0
+ Package() { 0x000cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+
+ // [PEX4]: PCI Express Port 4 0:e.0
+ Package() { 0x000effff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
+
+ // [PEX5]: PCI Express Port 5 0:f.0
+ Package() { 0x000fffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
+
+ // [PEX6]: PCI Express Port 6 0:10.0
+ Package() { 0x0010ffff, 2, \_SB.PCI0.LPCB.LNKG, 0 },
+
+ // [PEX7]: PCI Express Port 7 0:11.0
+ Package() { 0x0011ffff, 3, \_SB.PCI0.LPCB.LNKH, 0 },
+
+ // [SMB1]: SMBus controller 0:12.0
+ Package() { 0x0012ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+
+ // [SAT0]: SATA controller 0 0:13.0
+ Package() { 0x0013ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
+
+ // [SAT1]: SATA controller 1 0:14.0
+ Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+
+ // [XHC0]: XHCI USB controller 0:15.0
+ Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+
+ // [VRP0]: Virtual root port 0 0:16.0
+ Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+
+ // [VRP1]: Virtual root port 1 0:17.0
+ Package() { 0x0017ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+
+ // [HECI]: ME HECI 0:18.0
+ Package() { 0x0018ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+
+ // [HEC2]: ME HECI2 0:18.1
+ Package() { 0x0018ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+
+ // [MEKT]: MEKT on PCH 0:18.2
+ Package() { 0x0018ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+
+ // [HEC3]: ME HECI3 0:18.3
+ Package() { 0x0018ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+
+ // [UAR0]: UART 0 0:1a.0
+ Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+
+ // [UAR1]: UART 1 0:1a.1
+ Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+
+ // [UAR2]: UART 2 0:1a.2
+ Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+
+ // [EMMC]: eMMC 0:1c.0
+ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+
+ // [P2SB]: Primary to sideband bridge
+ // [SMB0]: SMBus controller
+ // [NPK0]: Northpeak DFX
+ Package() { 0x001ffffF, 0, \_SB.PCI0.LPCB.LNKH, 0 },
+ })
+ }
+}
diff --git a/src/mainboard/scaleway/tagada/acpi/platform.asl b/src/mainboard/scaleway/tagada/acpi/platform.asl
new file mode 100644
index 0000000..ea66a9f
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/acpi/platform.asl
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 - 2009 coresystems GmbH
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+ APMC, 8, // APM command
+ APMS, 8 // APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+ DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+ Store (Arg0, SMIF) // SMI Function
+ Store (0, TRP0) // Generate trap
+ Return (SMIF) // Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+ // Remember the OS' IRQ routing choice.
+ Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ Return(Package(){0,0})
+}
diff --git a/src/mainboard/scaleway/tagada/acpi/thermal.asl b/src/mainboard/scaleway/tagada/acpi/thermal.asl
new file mode 100644
index 0000000..5f9164d
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/acpi/thermal.asl
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+ // Thermal Zone
+
+Scope (\_TZ)
+{
+}
diff --git a/src/mainboard/scaleway/tagada/acpi_tables.c b/src/mainboard/scaleway/tagada/acpi_tables.c
new file mode 100644
index 0000000..acbdb30
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/acpi_tables.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ * Copyright (C) 2014 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/msr.h>
+
+#include <soc/acpi.h>
+#include <soc/nvs.h>
+
+extern const unsigned char AmlCode[];
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ acpi_init_gnvs(gnvs);
+
+ /* Disable USB ports in S5 */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ /* TPM Present */
+ gnvs->tpmp = 0;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Local APICs */
+ current = acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, 2,
+ IO_APIC_ADDR, 0);
+
+ current = acpi_madt_irq_overrides(current);
+
+ return current;
+}
diff --git a/src/mainboard/scaleway/tagada/board_info.txt b/src/mainboard/scaleway/tagada/board_info.txt
new file mode 100644
index 0000000..2b94d46
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Scaleway
+Board name: Tagada
+Category: server
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/scaleway/tagada/boardid.c b/src/mainboard/scaleway/tagada/boardid.c
new file mode 100644
index 0000000..c9df766
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/boardid.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 - 2017 Intel Corporation.
+ * Copyright (C) 2017 - 2018 Online SAS.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <console/console.h>
+
+#include "harcuvar_boardid.h"
+
+uint8_t board_id(void)
+{
+ int id = BoardIdHarcuvar;
+
+ printk(BIOS_SPEW, "Board ID: %#x.\n", id);
+
+ return id;
+}
diff --git a/src/mainboard/scaleway/tagada/devicetree.cb b/src/mainboard/scaleway/tagada/devicetree.cb
new file mode 100644
index 0000000..7fce211
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/devicetree.cb
@@ -0,0 +1,74 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 - 2017 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+chip soc/intel/denverton_ns
+
+ # configure pirq routing
+ register "pirqa_routing" = "11"
+ register "pirqb_routing" = "10"
+ register "pirqc_routing" = "06"
+ register "pirqd_routing" = "07"
+ register "pirqe_routing" = "12"
+ register "pirqf_routing" = "14"
+ register "pirqg_routing" = "15"
+ register "pirqh_routing" = "15"
+ # configure device interrupt routing
+ register "ir00_routing" = "0x3217" # IR00, Dev31
+ register "ir01_routing" = "0x3210" # IR01, Dev22
+ register "ir02_routing" = "0x3211" # IR02, Dev23
+ register "ir03_routing" = "0x3217" # IR03, Dev5
+ register "ir04_routing" = "0x3212" # IR04, Dev6
+ register "ir05_routing" = "0x3210" # IR05, Dev24
+ register "ir06_routing" = "0x3214" # IR06, Dev19
+ register "ir07_routing" = "0x3210" # IR07, Dev9/10/11/12
+ register "ir08_routing" = "0x7654" # IR08, Dev14/15/16/17
+ register "ir09_routing" = "0x3213" # IR09, Dev21
+ register "ir10_routing" = "0x3210" # IR10, Dev26/18
+ register "ir11_routing" = "0x3215" # IR11, Dev20
+ register "ir12_routing" = "0x3210" # IR12, Dev27
+ # configure interrupt polarity control
+ register "ipc0" = "0x00ff4000" # IPC0, PIRQA-H (IRQ16-23) should always be ActiveLow
+ register "ipc1" = "0x00000000" # IPC1
+ register "ipc2" = "0x00000000" # IPC2
+ register "ipc3" = "0x00000000" # IPC3
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 04.0 on end # RAS
+ device pci 05.0 on end # RCEC(Root Complex Event Collector)
+ device pci 06.0 on end # Virtual root port 2 (QAT)
+ device pci 09.0 on end # PCI Express Port 0, cluster #0, x8
+ device pci 0e.0 on end # PCI Express Port 4, cluster #1, x4
+ device pci 10.0 on end # PCI Express Port 6, cluster #1, x4
+ device pci 12.0 on end # SMBus Controller 1
+ device pci 14.0 on end # SATA Controller 1
+ device pci 15.0 on end # XHCI USB Controller
+ device pci 16.0 on end # Virtual root port 0 (10GBE0)
+ device pci 17.0 on end # Virtual root port 1 (10GBE1)
+ device pci 18.0 on end # CSME HECI 1
+ device pci 1a.0 on end # UART 0
+ device pci 1a.1 on end # UART 1
+ device pci 1a.2 on end # UART 2
+ device pci 1c.0 on end # eMMC
+ device pci 1f.0 on end # LPC bridge
+ device pci 1f.2 on end # PMC/ACPI
+ device pci 1f.4 on end # SMBus Controller 0
+ device pci 1f.5 on end # SPI Controller
+ end
+end
diff --git a/src/mainboard/scaleway/tagada/dsdt.asl b/src/mainboard/scaleway/tagada/dsdt.asl
new file mode 100644
index 0000000..4e66d17
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/dsdt.asl
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 - 2009 coresystems GmbH
+ * Copyright 2011 Google Inc.
+ * Copyright (C) 2014 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20110725 // OEM revision
+)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+ #include "acpi/mainboard.asl"
+
+ // General Purpose Events
+ //#include "acpi/gpe.asl"
+
+ // Thermal Handler
+ #include "acpi/thermal.asl"
+
+ // global NVS and variables
+ #include <soc/intel/denverton_ns/acpi/globalnvs.asl>
+
+ #include <soc/intel/denverton_ns/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <soc/intel/denverton_ns/acpi/northcluster.asl>
+ #include <soc/intel/denverton_ns/acpi/southcluster.asl>
+ }
+ }
+
+ /* Chipset specific sleep states */
+ #include <soc/intel/denverton_ns/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/scaleway/tagada/emmc.h b/src/mainboard/scaleway/tagada/emmc.h
new file mode 100644
index 0000000..9832191
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/emmc.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _MAINBOARD_EMMC_H
+#define _MAINBOARD_EMMC_H
+
+#include <fsp/util.h>
+
+#define DEFAULT_EMMC_DLL_SIGN 0x55aa
+
+#ifndef __ACPI__
+BL_EMMC_INFORMATION harcuvar_emmc_config[] = {
+ /*
+ * Default eMMC DLL configuration.
+ */
+ {DEFAULT_EMMC_DLL_SIGN,
+ {0x00000508, 0x00000c11, 0x1c2a2a2a, 0x00191e27, 0x00000a0a,
+ 0x00010013, 0x00000001} } };
+#endif
+
+#endif /* _MAINBOARD_EMMC_H */
diff --git a/src/mainboard/scaleway/tagada/fadt.c b/src/mainboard/scaleway/tagada/fadt.c
new file mode 100644
index 0000000..9f41f64
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/fadt.c
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 - 2009 coresystems GmbH
+ * Copyright (C) 2014 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <string.h>
+#include <arch/acpi.h>
+
+#include <soc/acpi.h>
+#include <soc/soc_util.h>
+
+void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+
+ memset((void *)fadt, 0, sizeof(acpi_fadt_t));
+ memcpy_s(header->signature, "FACP", 4);
+ header->length = sizeof(acpi_fadt_t);
+ header->revision = 3;
+ memcpy_s(header->oem_id, OEM_ID, 6);
+ memcpy_s(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+ memcpy_s(header->asl_compiler_id, ASLC, 4);
+ header->asl_compiler_revision = 1;
+
+ fadt->firmware_ctrl = (unsigned long)facs;
+ fadt->dsdt = (unsigned long)dsdt;
+ fadt->model = 1;
+ fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER;
+
+ fadt->x_firmware_ctl_l = (unsigned long)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (unsigned long)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ acpi_fill_in_fadt(fadt);
+
+ header->checksum = acpi_checksum((void *)fadt, header->length);
+}
diff --git a/src/mainboard/scaleway/tagada/gpio.h b/src/mainboard/scaleway/tagada/gpio.h
new file mode 100644
index 0000000..a96b435
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/gpio.h
@@ -0,0 +1,635 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _MAINBOARD_GPIO_H
+#define _MAINBOARD_GPIO_H
+
+#include <soc/gpio.h>
+
+#ifndef __ACPI__
+const struct pad_config harcuvar_gpio_table[] = {
+ // GBE0_SDP0 (GPIO_14)
+ {NORTH_ALL_GBE0_SDP0,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // GBE1_SDP0 (GPIO_15)
+ {NORTH_ALL_GBE1_SDP0,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // GBE2_I2C_CLK (GPIO_16)
+ {NORTH_ALL_GBE0_SDP1,
+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // GBE2_I2C_DATA (GPIO_17)
+ {NORTH_ALL_GBE1_SDP1,
+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // GBE2_SDP0 (GPIO_18)
+ {NORTH_ALL_GBE0_SDP2,
+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // GBE3_SDP0 (GPIO_19)
+ {NORTH_ALL_GBE1_SDP2,
+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // GBE3_I2C_CLK (GPIO_20)
+ {NORTH_ALL_GBE0_SDP3,
+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // GBE3_I2C_DATA (GPIO_21)
+ {NORTH_ALL_GBE1_SDP3,
+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // GBE2_LED0 (GPIO_22)
+ {NORTH_ALL_GBE2_LED0,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // GBE2_LED1 (GPIO_23)
+ {NORTH_ALL_GBE2_LED1,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // GBE0_I2C_CLK (GPIO_24)
+ {NORTH_ALL_GBE0_I2C_CLK,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // GBE0_I2C_DATA (GPIO_25)
+ {NORTH_ALL_GBE0_I2C_DATA,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // GBE1_I2C_CLK (GPIO_26)
+ {NORTH_ALL_GBE1_I2C_CLK,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // GBE1_I2C_DATA (GPIO_27)
+ {NORTH_ALL_GBE1_I2C_DATA,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // NCSI_RXD0 (GPIO_28)
+ {NORTH_ALL_NCSI_RXD0,
+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
+ // NCSI_CLK_IN (GPIO_29)
+ {NORTH_ALL_NCSI_CLK_IN,
+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
+ // NCSI_RXD1 (GPIO_30)
+ {NORTH_ALL_NCSI_RXD1,
+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
+ // NCSI_CRS_DV (GPIO_31)
+ {NORTH_ALL_NCSI_CRS_DV,
+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
+ // NCSI_ARB_IN (GPIO_32)
+ {NORTH_ALL_NCSI_ARB_IN,
+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
+ // NCSI_TX_EN (GPIO_33)
+ {NORTH_ALL_NCSI_TX_EN,
+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
+ // NCSI_TXD0 (GPIO_34)
+ {NORTH_ALL_NCSI_TXD0,
+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
+ // NCSI_TXD1 (GPIO_35)
+ {NORTH_ALL_NCSI_TXD1,
+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
+ // NCSI_ARB_OUT (GPIO_36)
+ {NORTH_ALL_NCSI_ARB_OUT,
+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
+ // GBE0_LED0 (GPIO_37)
+ {NORTH_ALL_GBE0_LED0,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
+ // GBE0_LED1 (GPIO_38)
+ {NORTH_ALL_GBE0_LED1,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
+ // GBE1_LED0 (GPIO_39)
+ {NORTH_ALL_GBE1_LED0,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
+ // GBE1_LED1 (GPIO_40)
+ {NORTH_ALL_GBE1_LED1,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
+ // ADR-COMPLETE (GPIO_0)
+ {NORTH_ALL_GPIO_0,
+ {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // PCIE_CLKREQ0_N (GPIO_41)
+ {NORTH_ALL_PCIE_CLKREQ0_N,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // PCIE_CLKREQ1_N (GPIO_42)
+ {NORTH_ALL_PCIE_CLKREQ1_N,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // PCIE_CLKREQ2_N (GPIO_43)
+ {NORTH_ALL_PCIE_CLKREQ2_N,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // PCIE_CLKREQ3_N (GPIO_44)
+ {NORTH_ALL_PCIE_CLKREQ3_N,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // FORCE_POWER (GPIO_45)
+ {NORTH_ALL_PCIE_CLKREQ4_N,
+ {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // GBE_MDC (GPIO_1)
+ {NORTH_ALL_GPIO_1,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // GBE_MDIO (GPIO_2)
+ {NORTH_ALL_GPIO_2,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SVID_ALERT_N (GPIO_47)
+ {NORTH_ALL_SVID_ALERT_N,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SVID_DATA (GPIO_48)
+ {NORTH_ALL_SVID_DATA,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SVID_CLK (GPIO_49)
+ {NORTH_ALL_SVID_CLK,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // THERMTRIP_N (GPIO_50)
+ {NORTH_ALL_THERMTRIP_N,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // PROCHOT_N (GPIO_51)
+ {NORTH_ALL_PROCHOT_N,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // MEMHOT_N (GPIO_52)
+ {NORTH_ALL_MEMHOT_N,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // DFX_PORT_CLK0 (GPIO_53)
+ {SOUTH_DFX_DFX_PORT_CLK0,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // DFX_PORT_CLK1 (GPIO_54)
+ {SOUTH_DFX_DFX_PORT_CLK1,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // DFX_PORT0 (GPIO_55)
+ {SOUTH_DFX_DFX_PORT0,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // DFX_PORT1 (GPIO_56)
+ {SOUTH_DFX_DFX_PORT1,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // DFX_PORT2 (GPIO_57)
+ {SOUTH_DFX_DFX_PORT2,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // DFX_PORT3 (GPIO_58)
+ {SOUTH_DFX_DFX_PORT3,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // DFX_PORT4 (GPIO_59)
+ {SOUTH_DFX_DFX_PORT4,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // DFX_PORT5 (GPIO_60)
+ {SOUTH_DFX_DFX_PORT5,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // DFX_PORT6 (GPIO_61)
+ {SOUTH_DFX_DFX_PORT6,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // DFX_PORT7 (GPIO_62)
+ {SOUTH_DFX_DFX_PORT7,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // DFX_PORT8 (GPIO_63)
+ {SOUTH_DFX_DFX_PORT8,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // DFX_PORT9 (GPIO_134)
+ {SOUTH_DFX_DFX_PORT9,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // DFX_PORT10 (GPIO_135)
+ {SOUTH_DFX_DFX_PORT10,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // DFX_PORT11 (GPIO_136)
+ {SOUTH_DFX_DFX_PORT11,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // DFX_PORT12 (GPIO_137)
+ {SOUTH_DFX_DFX_PORT12,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // DFX_PORT13 (GPIO_138)
+ {SOUTH_DFX_DFX_PORT13,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // DFX_PORT14 (GPIO_139)
+ {SOUTH_DFX_DFX_PORT14,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // DFX_PORT15 (GPIO_140)
+ {SOUTH_DFX_DFX_PORT15,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SPI_TPM_CS_N (GPIO_12)
+ {SOUTH_GROUP0_GPIO_12,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SMB5_GBE_ALRT_N (GPIO_13)
+ {SOUTH_GROUP0_SMB5_GBE_ALRT_N,
+ {GpioPadModeNative3, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
+ // SMI (GPIO_98)
+ {SOUTH_GROUP0_PCIE_CLKREQ5_N,
+ {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntSmi, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // NMI (GPIO_99)
+ {SOUTH_GROUP0_PCIE_CLKREQ6_N,
+ {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntNmi, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // GBE3_LED0 (GPIO_100)
+ {SOUTH_GROUP0_PCIE_CLKREQ7_N,
+ {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // UART0_RXD (GPIO_101)
+ {SOUTH_GROUP0_UART0_RXD,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // UART0_TXD (GPIO_102)
+ {SOUTH_GROUP0_UART0_TXD,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SMB5_GBE_CLK (GPIO_103)
+ {SOUTH_GROUP0_SMB5_GBE_CLK,
+ {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
+ // SMB_GBE_DATA (GPIO_104)
+ {SOUTH_GROUP0_SMB5_GBE_DATA,
+ {GpioPadModeNative3, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
+ // ERROR2_N (GPIO_105)
+ {SOUTH_GROUP0_ERROR2_N,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // ERROR1_N (GPIO_106)
+ {SOUTH_GROUP0_ERROR1_N,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // ERROR0_N (GPIO_107)
+ {SOUTH_GROUP0_ERROR0_N,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // IERR_N (CATERR_N) (GPIO_108)
+ {SOUTH_GROUP0_IERR_N,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // MCERR_N (GPIO_109)
+ {SOUTH_GROUP0_MCERR_N,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SMB0_LEG_CLK (GPIO_110)
+ {SOUTH_GROUP0_SMB0_LEG_CLK,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SMB0_LEG_DATA (GPIO_111)
+ {SOUTH_GROUP0_SMB0_LEG_DATA,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SMB0_LEG_ALRT_N (GPIO_112)
+ {SOUTH_GROUP0_SMB0_LEG_ALRT_N,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SMB1_HOST_DATA (GPIO_113)
+ {SOUTH_GROUP0_SMB1_HOST_DATA,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SMB1_HOST_CLK (GPIO_114)
+ {SOUTH_GROUP0_SMB1_HOST_CLK,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SMB2_PECI_DATA (GPIO_115)
+ {SOUTH_GROUP0_SMB2_PECI_DATA,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SMB2_PECI_CLK (GPIO_116)
+ {SOUTH_GROUP0_SMB2_PECI_CLK,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SMB4_CSME0_DATA (GPIO_117)
+ {SOUTH_GROUP0_SMB4_CSME0_DATA,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SMB4_CSME0_CLK (GPIO_118)
+ {SOUTH_GROUP0_SMB4_CSME0_CLK,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SMB4_CSME0_ALRT_N (GPIO_119)
+ {SOUTH_GROUP0_SMB4_CSME0_ALRT_N,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // USB_OC0_N (GPIO_120)
+ {SOUTH_GROUP0_USB_OC0_N,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // FLEX_CLK_SE0 (GPIO_121)
+ {SOUTH_GROUP0_FLEX_CLK_SE0,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // FLEX_CLK_SE1 (GPIO_122)
+ {SOUTH_GROUP0_FLEX_CLK_SE1,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // GBE3_LED1 (GPIO_4)
+ {SOUTH_GROUP0_GPIO_4,
+ {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SMB3_IE0_CLK (GPIO_5)
+ {SOUTH_GROUP0_GPIO_5,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SMB3_IE0_DATA (GPIO_6)
+ {SOUTH_GROUP0_GPIO_6,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SMB3_IE0_ALERT_N (GPIO_7)
+ {SOUTH_GROUP0_GPIO_7,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SATA0_LED (GPIO_90)
+ {SOUTH_GROUP0_SATA0_LED_N,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SATA1_LED (GPIO_91)
+ {SOUTH_GROUP0_SATA1_LED_N,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SATA_PDETECT0 (GPIO_92)
+ {SOUTH_GROUP0_SATA_PDETECT0,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SATA_PDETECT1 (GPIO_93)
+ {SOUTH_GROUP0_SATA_PDETECT1,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // UART1_RTS (GPIO_94)
+ {SOUTH_GROUP0_SATA0_SDOUT,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // UART1_CTS (GPIO_95)
+ {SOUTH_GROUP0_SATA1_SDOUT,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // UART1_RXD (GPIO_96)
+ {SOUTH_GROUP0_UART1_RXD,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // UART1_TXD (GPIO_97)
+ {SOUTH_GROUP0_UART1_TXD,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SMB6_CSME1_DATA (GPIO_8)
+ {SOUTH_GROUP0_GPIO_8,
+ {GpioPadModeNative3, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SMB6_CSME1_CLK (GPIO_9)
+ {SOUTH_GROUP0_GPIO_9,
+ {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // TCK (GPIO_141)
+ {SOUTH_GROUP0_TCK,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // TRST_N (GPIO_142)
+ {SOUTH_GROUP0_TRST_N,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // TMS (GPIO_143)
+ {SOUTH_GROUP0_TMS,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // TDI (GPIO_144)
+ {SOUTH_GROUP0_TDI,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // TDO (GPIO_145)
+ {SOUTH_GROUP0_TDO,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // CX_PRDY_N (GPIO_146)
+ {SOUTH_GROUP0_CX_PRDY_N,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // CX-PREQ_N (GPIO_147)
+ {SOUTH_GROUP0_CX_PREQ_N,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // ME_RECVR_HDR (GPIO_148)
+ {SOUTH_GROUP0_CTBTRIGINOUT,
+ {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // ADV_DBG_DFX_HDR (GPIO_149)
+ {SOUTH_GROUP0_CTBTRIGOUT,
+ {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // LAD2_SPI_IRQ_N (GPIO_150)
+ {SOUTH_GROUP0_DFX_SPARE2,
+ {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SMB_PECI_ALRT_N (GPIO_151)
+ {SOUTH_GROUP0_DFX_SPARE3,
+ {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SMB_CSME1_ALRT_N (GPIO_152)
+ {SOUTH_GROUP0_DFX_SPARE4,
+ {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SUSPWRDNACK (GPIO_79)
+ {SOUTH_GROUP1_SUSPWRDNACK,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // PMU_SUSCLK (GPIO_80)
+ {SOUTH_GROUP1_PMU_SUSCLK,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // ADR_TRIGGER_N (GPIO_81)
+ {SOUTH_GROUP1_ADR_TRIGGER,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // PMU_SLP_S45_N (GPIO_82)
+ {SOUTH_GROUP1_PMU_SLP_S45_N,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // PMU_SLP_S3_N (GPIO_83)
+ {SOUTH_GROUP1_PMU_SLP_S3_N,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // PMU_WAKE_N (GPIO_84)
+ {SOUTH_GROUP1_PMU_WAKE_N,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // PMU_PWRBTN_N (GPIO_85)
+ {SOUTH_GROUP1_PMU_PWRBTN_N,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // PMU_RESETBUTTON_N (GPIO_86)
+ {SOUTH_GROUP1_PMU_RESETBUTTON_N,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // PMU_PLTRST_N (GPIO_87)
+ {SOUTH_GROUP1_PMU_PLTRST_N,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // PMU_SUS_STAT_N (GPIO_88)
+ {SOUTH_GROUP1_SUS_STAT_N,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // TDB_CIO_PLUG_EVENT (GPIO_89)
+ {SOUTH_GROUP1_SLP_S0IX_N,
+ {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SPI_CS0_N (GPIO_72)
+ {SOUTH_GROUP1_SPI_CS0_N,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SPI_CS1_N (GPIO_73)
+ {SOUTH_GROUP1_SPI_CS1_N,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SPI_MOSI_IO0 (GPIO_74)
+ {SOUTH_GROUP1_SPI_MOSI_IO0,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SPI_MISO_IO1 (GPIO_75)
+ {SOUTH_GROUP1_SPI_MISO_IO1,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SPI_IO2 (GPIO_76)
+ {SOUTH_GROUP1_SPI_IO2,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SPI_IO3 (GPIO_77)
+ {SOUTH_GROUP1_SPI_IO3,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // SPI_CLK (GPIO_78)
+ {SOUTH_GROUP1_SPI_CLK,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // LPC_AD0 (GPIO_64)
+ {SOUTH_GROUP1_ESPI_IO0,
+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // LPC_AD1 (GPIO_65)
+ {SOUTH_GROUP1_ESPI_IO1,
+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // LPC_AD2 (GPIO_66)
+ {SOUTH_GROUP1_ESPI_IO2,
+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // LPC_AD3 (GPIO_67)
+ {SOUTH_GROUP1_ESPI_IO3,
+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // LPC_FRAME_N (GPIO_68)
+ {SOUTH_GROUP1_ESPI_CS0_N,
+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // LPC_CLKOUT0 (GPIO_69)
+ {SOUTH_GROUP1_ESPI_CLK,
+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // LPC_CLKOUT1 (GPIO_70)
+ {SOUTH_GROUP1_ESPI_RST_N,
+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // LPC_CLKRUN_N (GPIO_71)
+ {SOUTH_GROUP1_ESPI_ALRT0_N,
+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // MFG_MODE_HDR (GPIO_10)
+ {SOUTH_GROUP1_GPIO_10,
+ {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // LPC_SERIRQ (GPIO_11)
+ {SOUTH_GROUP1_GPIO_11,
+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // EMMC-CMD (GPIO_123)
+ {SOUTH_GROUP1_EMMC_CMD,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
+ // EMMC-CSTROBE (GPIO_124)
+ {SOUTH_GROUP1_EMMC_STROBE,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+ // EMMC-CLK (GPIO_125)
+ {SOUTH_GROUP1_EMMC_CLK,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermWpd20K, GpioLockDefault} },
+ // EMMC-D0 (GPIO_126)
+ {SOUTH_GROUP1_EMMC_D0,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
+ // EMMC-D1 (GPIO_127)
+ {SOUTH_GROUP1_EMMC_D1,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
+ // EMMC-D2 (GPIO_128)
+ {SOUTH_GROUP1_EMMC_D2,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
+ // EMMC-D3 (GPIO_129)
+ {SOUTH_GROUP1_EMMC_D3,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
+ // EMMC-D4 (GPIO_130)
+ {SOUTH_GROUP1_EMMC_D4,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
+ // EMMC-D5 (GPIO_131)
+ {SOUTH_GROUP1_EMMC_D5,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
+ // EMMC-D6 (GPIO_132)
+ {SOUTH_GROUP1_EMMC_D6,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
+ // EMMC-D7 (GPIO_133)
+ {SOUTH_GROUP1_EMMC_D7,
+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
+ // IE_ROM GPIO (GPIO_3)
+ {SOUTH_GROUP1_GPIO_3,
+ {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+};
+#endif
+
+#endif /* _MAINBOARD_GPIO_H */
diff --git a/src/mainboard/scaleway/tagada/harcuvar_boardid.h b/src/mainboard/scaleway/tagada/harcuvar_boardid.h
new file mode 100644
index 0000000..3bcd60c
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/harcuvar_boardid.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef HARCUVAR_MAINBOARD_BOARD_H
+#define HARCUVAR_MAINBOARD_BOARD_H
+
+#include <stdint.h>
+
+#define BoardIdHarcuvar 0x52
+
+uint8_t board_id(void);
+
+#endif /* MAINBOARD_BOARD_H */
diff --git a/src/mainboard/scaleway/tagada/hsio.c b/src/mainboard/scaleway/tagada/hsio.c
new file mode 100644
index 0000000..fa17130
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/hsio.c
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ * Copyright (C) 2017 Online SAS.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <harcuvar_boardid.h>
+#include <hsio.h>
+#include <soc/fiamux.h>
+
+size_t mainboard_get_hsio_config(BL_HSIO_INFORMATION **p_hsio_config)
+{
+ uint8_t boardid = board_id();
+ size_t num;
+ switch (boardid) {
+ case BoardIdHarcuvar:
+ num = ARRAY_SIZE(harcuvar_hsio_config);
+ (*p_hsio_config) = (BL_HSIO_INFORMATION *)harcuvar_hsio_config;
+ break;
+ default:
+ num = 0;
+ (*p_hsio_config) = NULL;
+ break;
+ }
+ return num;
+}
diff --git a/src/mainboard/scaleway/tagada/hsio.h b/src/mainboard/scaleway/tagada/hsio.h
new file mode 100644
index 0000000..ce059fd
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/hsio.h
@@ -0,0 +1,624 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016-2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _MAINBOARD_HSIO_H
+#define _MAINBOARD_HSIO_H
+
+#include <fsp/util.h>
+
+#ifndef __ACPI__
+const BL_HSIO_INFORMATION harcuvar_hsio_config[] = {
+ /*
+ * Supported Lanes:
+ * 20
+ *
+ * Bifurcation:
+ * PCIE cluster #0: x8
+ * PCIE cluster #1: x4x4
+ *
+ * FIA MUX config:
+ * Lane[00:07]->x8 PCIE slot
+ * Lane[08:11]->a x4 PCIe slot
+ * Lane[12:15]->a 2nd x4 PCIe slot
+ * Lane[16]->a SATA connector with pin7 to 5V adapter capable
+ * Lane[17:18] -> 2 SATA connectors
+ * Lane[19]->USB3 rear I/O panel connector
+ */
+
+ /* SKU HSIO 20 (pcie [0-15] sata [16-18] usb [19]) */
+ {BL_SKU_HSIO_20,
+ {PCIE_BIF_CTRL_x8, PCIE_BIF_CTRL_x4x4},
+ {/* ME_FIA_MUX_CONFIG */
+ {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE00) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE01) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE02) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE03) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE04) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE05) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE06) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE07) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE08) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE09) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE10) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE11) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE13) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE14) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE15) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE16) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE17) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE18) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},
+
+ /* ME_FIA_SATA_CONFIG */
+ {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE04) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE05) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE06) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE07) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE08) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE09) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE10) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE11) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE12) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE13) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE14) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE15) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE16) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE17) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE18) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE19)},
+
+ /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */
+ {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_0) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_1) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_2) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_3) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_4) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_5) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_6) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_7) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_0) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_1) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_2) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_3) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_4) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_5) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_6) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_7)} } },
+
+ /* SKU HSIO 12 (pcie [0-3, 8-9, 12-13] sata [16-18] usb [19]) */
+ {BL_SKU_HSIO_12,
+ {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},
+ {/*ME_FIA_MUX_CONFIG */
+ {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE00) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE01) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE02) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE03) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE08) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE09) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE10) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE11) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE13) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE14) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE15) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE16) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE17) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE18) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},
+
+ /* ME_FIA_SATA_CONFIG */
+ {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE04) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE05) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE06) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE07) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE08) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE09) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE10) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE11) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE12) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE13) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE14) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE15) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE16) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE17) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE18) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE19)},
+
+ /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */
+ {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_0) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_1) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_2) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_3) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_4) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_5) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_6) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_7) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_0) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_1) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_2) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_3) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_4) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_5) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_6) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_7)} } },
+
+ /* SKU HSIO 10 (pcie [0-3, 8-9, 12] sata [16-17] usb [19]) */
+ {BL_SKU_HSIO_10,
+ {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},
+ {/* ME_FIA_MUX_CONFIG */
+ {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE00) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE01) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE02) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE03) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE08) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE09) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE10) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE11) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE13) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE14) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE15) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE16) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE17) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},
+
+ /* ME_FIA_SATA_CONFIG */
+ {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE04) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE05) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE06) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE07) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE08) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE09) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE10) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE11) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE12) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE13) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE14) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE15) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE16) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE17) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE18) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE19)},
+
+ /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */
+ {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_0) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_1) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_2) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_3) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_4) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_5) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_6) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_7) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_0) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_1) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_2) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_3) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_4) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_5) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1,
+ BL_FIA_PCIE_ROOT_PORT_6) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_7)} } },
+
+ /* SKU HSIO 8 (pcie [0-1, 8-9, 12] sata [16-17] usb [19]) */
+ {BL_SKU_HSIO_08,
+ {PCIE_BIF_CTRL_x2x2x2x2, PCIE_BIF_CTRL_x2x2x2x2},
+ {/* ME_FIA_MUX_CONFIG */
+ {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE00) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE01) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE02) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE03) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE08) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE09) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE10) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE11) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE13) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE14) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE15) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE16) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE17) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},
+
+ /* ME_FIA_SATA_CONFIG */
+ {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE04) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE05) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE06) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE07) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE08) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE09) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE10) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE11) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE12) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE13) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE14) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE15) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE16) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE17) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE18) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE19)},
+
+ /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */
+ {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_0) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_1) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_2) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_3) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_4) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_5) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_6) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_7) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_0) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_1) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_2) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_3) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_4) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_5) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1,
+ BL_FIA_PCIE_ROOT_PORT_6) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_7)} } },
+
+ /* SKU HSIO 6 (pcie [0-1, 8, 12] sata [16] usb [19]) */
+ {BL_SKU_HSIO_06,
+ {PCIE_BIF_CTRL_x2x2x2x2, PCIE_BIF_CTRL_x2x2x2x2},
+ {/* ME_FIA_MUX_CONFIG */
+ {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE00) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE01) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE02) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE03) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE08) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE09) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE10) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE11) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE13) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE14) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE15) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE16) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE17) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},
+
+ /* ME_FIA_SATA_CONFIG */
+ {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE04) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE05) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE06) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE07) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE08) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE09) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE10) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE11) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE12) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE13) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE14) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE15) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE16) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE17) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE18) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE19)},
+
+ /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */
+ {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_0) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_1) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_2) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_3) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_4) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_5) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_6) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_7) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_0) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_1) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_2) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_3) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1,
+ BL_FIA_PCIE_ROOT_PORT_4) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_5) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1,
+ BL_FIA_PCIE_ROOT_PORT_6) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_7)} } }
+};
+#endif
+#endif
+/* _MAINBOARD_HSIO_H */
diff --git a/src/mainboard/scaleway/tagada/ramstage.c b/src/mainboard/scaleway/tagada/ramstage.c
new file mode 100644
index 0000000..4d90858
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/ramstage.c
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 - 2017 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <console/console.h>
+#include <fsp/api.h>
+#include <soc/ramstage.h>
+#include "emmc.h"
+
+static int get_emmc_dll_info(uint16_t signature, size_t num_of_entry,
+ BL_EMMC_INFORMATION **config)
+{
+ uint8_t entry;
+
+ if ((signature == 0) || (num_of_entry == 0) || (*config == NULL))
+ return 1;
+
+ for (entry = 0; entry < num_of_entry; entry++) {
+ if ((*config)[entry].Signature == signature) {
+ *config = &(*config)[entry];
+ return 0;
+ }
+ }
+
+ return 1;
+}
+
+void mainboard_silicon_init_params(FSPS_UPD *params)
+{
+ size_t num;
+ uint16_t emmc_dll_sign;
+ BL_EMMC_INFORMATION *emmc_config;
+
+ /* Configure eMMC DLL PCD */
+ emmc_dll_sign = DEFAULT_EMMC_DLL_SIGN;
+ num = ARRAY_SIZE(harcuvar_emmc_config);
+ emmc_config = harcuvar_emmc_config;
+
+ if (get_emmc_dll_info(emmc_dll_sign, num, &emmc_config))
+ die("eMMC DLL Configuration is invalid, please correct it!");
+
+ params->FspsConfig.PcdEMMCDLLConfigPtr =
+ (uint32_t)&emmc_config->eMMCDLLConfig;
+}
diff --git a/src/mainboard/scaleway/tagada/romstage.c b/src/mainboard/scaleway/tagada/romstage.c
new file mode 100644
index 0000000..f0c7cb9
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/romstage.c
@@ -0,0 +1,144 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "harcuvar_boardid.h"
+#include "gpio.h"
+#include "spd/spd.h"
+#include <console/console.h>
+#include <fsp/api.h>
+#include <fsp/soc_binding.h>
+#include <string.h>
+
+#if IS_ENABLED(CONFIG_ENABLE_FSP_MEMORY_DOWN)
+
+/*
+ * Define platform specific Memory Down Configure structure.
+ *
+ * If CONFIG_ENABLE_FSP_MEMORY_DOWN is enabled, the MEMORY_DOWN_CONFIG
+ * structure should be customized to match the design.
+ *
+ * .SlotState indicates the memory down state of the specific channel/DIMM.
+ *
+ * SlotState options:
+ *
+ * STATE_MEMORY_DOWN: Memory down.
+ * STATE_MEMORY_SLOT: Physical memory slot.
+ *
+ * .SpdDataLen should always be MAX_SPD_BYTES/512.
+ *
+ * .SpdDataPtr is pointing to the SPD data structure when memory modules
+ * are memory down.
+ *
+ * SpdDataPtr options:
+ *
+ * Non-NULL: Pointing to SPD data structure.
+ * NULL: Physical memory slot, no SPD data used.
+ *
+ * DIMM Mapping of SlotState & SpdDataPtr:
+ *
+ * {{CH0DIMM0, CH0DIMM1}, {CH1DIMM0, CH1DIMM1}}
+ *
+ * Sample: Channel 0 is memory down and channel 1 is physical slot.
+ *
+ * const MEMORY_DOWN_CONFIG mMemoryDownConfig = {
+ * .SlotState = {
+ * {STATE_MEMORY_DOWN, STATE_MEMORY_DOWN},
+ * {STATE_MEMORY_SLOT, STATE_MEMORY_SLOT}
+ * },
+ * .SpdDataLen = MAX_SPD_BYTES,
+ * .SpdDataPtr = {
+ * {(void *)CONFIG_SPD_LOC, (void *)CONFIG_SPD_LOC},
+ * {(void *)NULL, (void *)NULL}
+ * }
+ * }
+ */
+
+const MEMORY_DOWN_CONFIG mMemoryDownConfig = {
+ .SlotState = {
+ {STATE_MEMORY_SLOT, STATE_MEMORY_SLOT},
+ {STATE_MEMORY_SLOT, STATE_MEMORY_SLOT}
+ },
+ .SpdDataLen = MAX_SPD_BYTES,
+ .SpdDataPtr = {
+ {(void *)NULL, (void *)NULL},
+ {(void *)NULL, (void *)NULL}
+ }
+};
+
+#endif /* CONFIG_ENABLE_FSP_MEMORY_DOWN */
+
+void mainboard_config_gpios(void);
+void mainboard_memory_init_params(FSPM_UPD *mupd);
+
+/*
+* Configure GPIO depend on platform
+*/
+void mainboard_config_gpios(void)
+{
+ size_t num;
+ const struct pad_config *table;
+ uint8_t boardid = board_id();
+
+ /* Configure pads prior to SiliconInit() in case there's any
+ * dependencies during hardware initialization.
+ */
+ switch (boardid) {
+ case BoardIdHarcuvar:
+ table = harcuvar_gpio_table;
+ num = ARRAY_SIZE(harcuvar_gpio_table);
+ break;
+ default:
+ table = NULL;
+ num = 0;
+ break;
+ }
+
+ if ((!table) || (!num)) {
+ printk(BIOS_ERR, "ERROR: No valid GPIO table found!\n");
+ return;
+ }
+
+ printk(BIOS_INFO, "GPIO table: 0x%x, entry num: 0x%x!\n",
+ (uint32_t)table, (uint32_t)num);
+ gpio_configure_pads(table, num);
+}
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+#if IS_ENABLED(CONFIG_ENABLE_FSP_MEMORY_DOWN)
+ uint8_t *spd_data_ptr = NULL;
+
+ /* Get SPD data pointer */
+ spd_data_ptr = mainboard_find_spd_data();
+
+ if (spd_data_ptr != NULL) {
+ printk(BIOS_DEBUG, "Memory Down function is enabled!\n");
+
+ /* Enable Memory Down function, set Memory
+ * Down Configure structure pointer.
+ */
+ mupd->FspmConfig.PcdMemoryDown = 1;
+ mupd->FspmConfig.PcdMemoryDownConfigPtr =
+ (uint32_t)&mMemoryDownConfig;
+ } else {
+ printk(BIOS_DEBUG, "Memory Down function is disabled!\n");
+
+ /* Disable Memory Down function */
+ mupd->FspmConfig.PcdMemoryDown = 0;
+ mupd->FspmConfig.PcdMemoryDownConfigPtr = 0;
+ }
+#endif /* CONFIG_ENABLE_FSP_MEMORY_DOWN */
+}
diff --git a/src/mainboard/scaleway/tagada/spd/Makefile.inc b/src/mainboard/scaleway/tagada/spd/Makefile.inc
new file mode 100644
index 0000000..38d5046
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/spd/Makefile.inc
@@ -0,0 +1,38 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+## Copyright (C) 2015 - 2017 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+romstage-y += spd.c
+
+SPD_BIN = $(obj)/spd.bin
+
+# Order matters for SPD sources. The following indices
+# define the SPD data to use.
+SPD_SOURCES = micron_4GiB_dimm_MTA9ASF51272PZ-2G1A2
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd rom data
+$(SPD_BIN): $(SPD_DEPS)
+ for f in $+; \
+ do for c in $$(cat $$f | grep -v ^#); \
+ do echo -e -n "\\x$$c"; \
+ done; \
+ done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-position := $(CONFIG_SPD_LOC)
+spd.bin-type := spd
diff --git a/src/mainboard/scaleway/tagada/spd/micron_4GiB_dimm_MTA9ASF51272PZ-2G1A2.spd.hex b/src/mainboard/scaleway/tagada/spd/micron_4GiB_dimm_MTA9ASF51272PZ-2G1A2.spd.hex
new file mode 100644
index 0000000..4abad8d
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/spd/micron_4GiB_dimm_MTA9ASF51272PZ-2G1A2.spd.hex
@@ -0,0 +1,513 @@
+#DDR4_4GB_RDIMM_Micron_MTA9ASF51272PZ-2G1A2.txt
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diff --git a/src/mainboard/scaleway/tagada/spd/spd.c b/src/mainboard/scaleway/tagada/spd/spd.c
new file mode 100644
index 0000000..37f4424
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/spd/spd.c
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <arch/byteorder.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <string.h>
+
+#include "spd.h"
+
+/* Get SPD data for on-board memory */
+uint8_t *mainboard_find_spd_data()
+{
+ uint8_t *spd_data;
+ int spd_index;
+ size_t spd_file_len;
+ char *spd_file;
+
+ spd_index = 0;
+
+ spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
+ &spd_file_len);
+ if (!spd_file)
+ die("SPD data not found.");
+
+ if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
+ printk(BIOS_ERR,
+ "SPD index override to 0 due to incorrect SPD index.\n");
+ spd_index = 0;
+ }
+
+ if (spd_file_len < SPD_LEN)
+ die("Missing SPD data.");
+
+ /* Assume same memory in both channels */
+ spd_index *= SPD_LEN;
+ spd_data = (uint8_t *)(spd_file + spd_index);
+
+ /* Make sure a valid SPD was found */
+ if (spd_data[0] == 0)
+ die("Invalid SPD data.");
+
+ return spd_data;
+}
diff --git a/src/mainboard/scaleway/tagada/spd/spd.h b/src/mainboard/scaleway/tagada/spd/spd.h
new file mode 100644
index 0000000..13692d7
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/spd/spd.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef MAINBOARD_SPD_H
+#define MAINBOARD_SPD_H
+
+#define SPD_LEN 512
+
+#define SPD_DRAM_TYPE 2
+#define SPD_DRAM_DDR3 0x0b
+#define SPD_DRAM_LPDDR3 0xf1
+#define SPD_DENSITY_BANKS 4
+#define SPD_ADDRESSING 5
+#define SPD_ORGANIZATION 7
+#define SPD_BUS_DEV_WIDTH 8
+#define SPD_PART_OFF 128
+#define SPD_PART_LEN 18
+
+uint8_t *mainboard_find_spd_data(void);
+
+#endif
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Change in coreboot[master]: soc/intel/cannonlake: Add more HDA Audio Link settings
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Change subject: soc/intel/cannonlake: Add more HDA Audio Link settings
......................................................................
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Change in coreboot[master]: mainboard/google/zoombini: Add config for meowth audio
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Change subject: mainboard/google/zoombini: Add config for meowth audio
......................................................................
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