coreboot-gerrit February 2018

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Change in coreboot[master]: amd/stoneyridge: Move model_15_init.c to cpu.c
by Marshall Dawson (Code Review) 13 Feb '18

13 Feb '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/23724 Change subject: amd/stoneyridge: Move model_15_init.c to cpu.c ...................................................................... amd/stoneyridge: Move model_15_init.c to cpu.c Move the remaining model_15_init.c functionality to cpu.c, making it similar to other soc implementations. Change-Id: Ic8c62b09209fcdaa50ff8ffc7773ef155f979a1b Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/Makefile.inc M src/soc/amd/stoneyridge/cpu.c D src/soc/amd/stoneyridge/model_15_init.c 3 files changed, 31 insertions(+), 60 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/23724/1 diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 59405de..aae30ea 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -92,7 +92,6 @@ ramstage-y += sb_util.c ramstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c ramstage-y += lpc.c -ramstage-y += model_15_init.c ramstage-y += northbridge.c ramstage-y += pmutil.c ramstage-y += reset.c diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 5042cbc..14b6881 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -18,6 +18,7 @@ #include <cpu/x86/mp.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> +#include <cpu/x86/lapic.h> #include <cpu/amd/amdfam15.h> #include <device/device.h> #include <soc/pci_devs.h> @@ -113,3 +114,33 @@ if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) printk(BIOS_ERR, "MP initialization failure.\n"); } + +static void model_15_init(device_t dev) +{ + printk(BIOS_DEBUG, "Model 15 Init.\n"); + + int i; + msr_t msr; + + /* zero the machine check error status registers */ + msr.lo = 0; + msr.hi = 0; + for (i = 0 ; i < 6 ; i++) + wrmsr(MCI_STATUS + (i * 4), msr); + + setup_lapic(); +} + +static struct device_operations cpu_dev_ops = { + .init = model_15_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_AMD, 0x670f00 }, + { 0, 0 }, +}; + +static const struct cpu_driver model_15 __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/soc/amd/stoneyridge/model_15_init.c b/src/soc/amd/stoneyridge/model_15_init.c deleted file mode 100644 index 83fadd0..0000000 --- a/src/soc/amd/stoneyridge/model_15_init.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/msr.h> -#include <device/device.h> -#include <device/pci.h> -#include <string.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/pae.h> -#include <pc80/mc146818rtc.h> - -#include <cpu/cpu.h> -#include <cpu/x86/cache.h> -#include <cpu/amd/amdfam15.h> -#include <arch/acpi.h> - -static void model_15_init(device_t dev) -{ - printk(BIOS_DEBUG, "Model 15 Init.\n"); - - int i; - msr_t msr; - - /* zero the machine check error status registers */ - msr.lo = 0; - msr.hi = 0; - for (i = 0 ; i < 6 ; i++) - wrmsr(MCI_STATUS + (i * 4), msr); - - setup_lapic(); -} - -static struct device_operations cpu_dev_ops = { - .init = model_15_init, -}; - -static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_AMD, 0x670f00 }, - { 0, 0 }, -}; - -static const struct cpu_driver model_15 __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; -- To view, visit https://review.coreboot.org/23724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic8c62b09209fcdaa50ff8ffc7773ef155f979a1b Gerrit-Change-Number: 23724 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Use generic fixed MTRR setup
by Marshall Dawson (Code Review) 13 Feb '18

13 Feb '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/23723 Change subject: amd/stoneyridge: Use generic fixed MTRR setup ...................................................................... amd/stoneyridge: Use generic fixed MTRR setup Add the X86_AMD_FIXED_MTRRS select back to Kconfig. This got lost when stoneyridge was converted from a cpu/northbridge/southbridge implementation to soc/. Remove the setup from model_15_init.c because this is duplicated functionality. BUG=b:68019051 TEST=Boot Kahlee, check steps with HDT Change-Id: Id5526dcff12555efccab811fa3442ba1bff051bb Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/model_15_init.c 2 files changed, 1 insertion(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/23723/1 diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 8bf577c..de1cb92 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -31,6 +31,7 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select X86_AMD_FIXED_MTRRS select ACPI_AMD_HARDWARE_SLEEP_VALUES select COLLECT_TIMESTAMPS_NO_TSC select DRIVERS_I2C_DESIGNWARE diff --git a/src/soc/amd/stoneyridge/model_15_init.c b/src/soc/amd/stoneyridge/model_15_init.c index 4bde81e..83fadd0 100644 --- a/src/soc/amd/stoneyridge/model_15_init.c +++ b/src/soc/amd/stoneyridge/model_15_init.c @@ -16,7 +16,6 @@ #include <console/console.h> #include <cpu/x86/lapic.h> #include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> #include <device/device.h> #include <device/pci.h> #include <string.h> @@ -26,22 +25,9 @@ #include <cpu/cpu.h> #include <cpu/x86/cache.h> -#include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam15.h> #include <arch/acpi.h> -static void msr_rw_dram(unsigned int reg) -{ -#define RW_DRAM (MTRR_READ_MEM | MTRR_WRITE_MEM) -#define ALL_RW_DRAM ((RW_DRAM << 24) | (RW_DRAM << 16) | \ - (RW_DRAM << 8) | (RW_DRAM)) - - msr_t mtrr = rdmsr(reg); - mtrr.hi |= ALL_RW_DRAM; - mtrr.lo |= ALL_RW_DRAM; - wrmsr(reg, mtrr); -} - static void model_15_init(device_t dev) { printk(BIOS_DEBUG, "Model 15 Init.\n"); @@ -49,29 +35,6 @@ int i; msr_t msr; - disable_cache(); - - /* Enable access to AMD RdDram and WrDram extension bits */ - msr = rdmsr(SYSCFG_MSR); - msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; - msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; - wrmsr(SYSCFG_MSR, msr); - - /* Send all but A0000-BFFFF to DRAM */ - msr_rw_dram(MTRR_FIX_64K_00000); - msr_rw_dram(MTRR_FIX_16K_80000); - for (i = MTRR_FIX_4K_C0000 ; i <= MTRR_FIX_4K_F8000 ; i++) - msr_rw_dram(i); - - /* Hide RdDram and WrDram bits, and clear Tom2ForceMemTypeWB */ - msr = rdmsr(SYSCFG_MSR); - msr.lo &= ~SYSCFG_MSR_TOM2WB; - msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; - msr.lo |= SYSCFG_MSR_MtrrFixDramEn; - wrmsr(SYSCFG_MSR, msr); - - x86_enable_cache(); - /* zero the machine check error status registers */ msr.lo = 0; msr.hi = 0; -- To view, visit https://review.coreboot.org/23723 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id5526dcff12555efccab811fa3442ba1bff051bb Gerrit-Change-Number: 23723 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: x86/mtrr: Enable Rd/WrDram mod in AMD fixed MTRRs
by Marshall Dawson (Code Review) 13 Feb '18

13 Feb '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/23722 Change subject: x86/mtrr: Enable Rd/WrDram mod in AMD fixed MTRRs ...................................................................... x86/mtrr: Enable Rd/WrDram mod in AMD fixed MTRRs AMD fixed MTRRs have RdDram and WrDram bits that help route memory accesses to DRAM or MMIO. These are typically hidden for normal operation by clearing SYS_CFG[19] (MtrrFixDramModEn). According to BKDGs and AMD64 Programmer's Manual vol 2, this bit is clear at reset, should be set for configuration during POST, then cleared for normal operation. Attempting to modify the RdDram and WrDram settings without unhiding them causes a General Protection Fault. Add a function to enable or disable MtrrFixDramModEn. During commit_fixed_mtrrs() ensure the setting is enabled then disabled after writing the registers. In mp_init.c save_bsp_msrs() copies the fixed MTRR settings. Enable the bits so the complete MTRR contents may be read. Restore the setting when complete. Finally, modify sipi_vector.S to enable the bits prior to writing the fixed MTRRs and disable when complete. BUG=b:68019051 TEST=Boot Kahlee, check steps with HDT Change-Id: Ie195131ff752400eb886dfccc39b314b4fa6b3f3 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/cpu/x86/mp_init.c M src/cpu/x86/mtrr/mtrr.c M src/cpu/x86/sipi_vector.S M src/include/cpu/x86/mtrr.h 4 files changed, 50 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/23722/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index baa6aec..40349aa 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -310,6 +310,8 @@ msr_entry = save_msr(MTRR_DEF_TYPE_MSR, msr_entry); + fixed_mtrrs_hide_rwdram(); /* hide Rd/WrDram bits if supported */ + return msr_count; } diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index c2c629c..a2a04fb 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -36,8 +36,8 @@ #include <arch/cpu.h> #include <arch/acpi.h> #include <memrange.h> -#if IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS) #include <cpu/amd/mtrr.h> +#if IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS) #define MTRR_FIXED_WRBACK_BITS (MTRR_READ_MEM | MTRR_WRITE_MEM) #else #define MTRR_FIXED_WRBACK_BITS 0 @@ -83,6 +83,30 @@ wrmsr(MTRR_DEF_TYPE_MSR, msr); } +void fixed_mtrrs_expose_rwdram(void) +{ + msr_t syscfg; + + if (!IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS)) + return; + + syscfg = rdmsr(SYSCFG_MSR); + syscfg.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, syscfg); +} + +void fixed_mtrrs_hide_rwdram(void) +{ + msr_t syscfg; + + if (!IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS)) + return; + + syscfg = rdmsr(SYSCFG_MSR); + syscfg.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, syscfg); +} + static void enable_var_mtrr(unsigned char deftype) { msr_t msr; @@ -310,6 +334,8 @@ msr_t fixed_msrs[NUM_FIXED_MTRRS]; unsigned long msr_index[NUM_FIXED_MTRRS]; + fixed_mtrrs_expose_rwdram(); /* unhide Rd/WrDram bits if supported */ + memset(&fixed_msrs, 0, sizeof(fixed_msrs)); msr_num = 0; diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index bd60c65..83606bd 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -15,6 +15,7 @@ */ #include <cpu/x86/cr.h> +#include <cpu/amd/mtrr.h> /* The SIPI vector is responsible for initializing the APs in the sytem. It * loads microcode, sets up MSRs, and enables caching before calling into @@ -172,6 +173,15 @@ mov msr_count, %ebx test %ebx, %ebx jz 1f + +#if IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS) + /* Allow modification of RdDram and WrDram bits */ + mov $SYSCFG_MSR, %ecx + rdmsr + or $SYSCFG_MSR_MtrrFixDramModEn, %eax + wrmsr +#endif + load_msr: mov (%edi), %ecx mov 4(%edi), %eax @@ -181,6 +191,13 @@ dec %ebx jnz load_msr +#if IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS) + mov $SYSCFG_MSR, %ecx + rdmsr + and $~SYSCFG_MSR_MtrrFixDramModEn, %eax + wrmsr +#endif + 1: /* Enable caching. */ mov %cr0, %eax diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index a72d602..bc0f1fe 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -76,6 +76,10 @@ */ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb); void enable_fixed_mtrr(void); +/* Unhide Rd/WrDram bits in AMD fixed MTRRs and allow modification. */ +void fixed_mtrrs_expose_rwdram(void); +/* Hide Rd/WrDram bits in AMD fixed MTRRs and prevent modification */ +void fixed_mtrrs_hide_rwdram(void); void x86_setup_fixed_mtrrs(void); /* Set up fixed MTRRs but do not enable them. */ void x86_setup_fixed_mtrrs_no_enable(void); -- To view, visit https://review.coreboot.org/23722 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie195131ff752400eb886dfccc39b314b4fa6b3f3 Gerrit-Change-Number: 23722 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: driver/uart: Introduce a way for mainboard to override the baudrate
by build bot (Jenkins) (Code Review) 12 Feb '18

12 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23713 ) Change subject: driver/uart: Introduce a way for mainboard to override the baudrate ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67402/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21943/ : SUCCESS -- To view, visit https://review.coreboot.org/23713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I970ee788bf90b9e1a8c6ccdc5eee8029d9af0ecc Gerrit-Change-Number: 23713 Gerrit-PatchSet: 2 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 12 Feb 2018 20:55:03 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: drivers/adau7002: Fix include file
by build bot (Jenkins) (Code Review) 12 Feb '18

12 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23721 ) Change subject: drivers/adau7002: Fix include file ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67401/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21942/ : SUCCESS -- To view, visit https://review.coreboot.org/23721 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic359ed262086596a98131669f8eecd531857187a Gerrit-Change-Number: 23721 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 12 Feb 2018 20:41:05 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: drivers/adau7002: Fix include file
by Daniel Kurtz (Code Review) 12 Feb '18

12 Feb '18

Hello Daniel Kurtz, I'd like you to do a code review. Please visit https://review.coreboot.org/23721 to review the following change. Change subject: drivers/adau7002: Fix include file ...................................................................... drivers/adau7002: Fix include file Add missing license and include guard and remove unneeded include. BUG=b:72121803 TEST=compiles Change-Id: Ic359ed262086596a98131669f8eecd531857187a Signed-off-by: Daniel Kurtz <djkurtz(a)chromium.org> --- M src/drivers/generic/adau7002/chip.h 1 file changed, 19 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/23721/1 diff --git a/src/drivers/generic/adau7002/chip.h b/src/drivers/generic/adau7002/chip.h index 809a680..95b4d1e 100644 --- a/src/drivers/generic/adau7002/chip.h +++ b/src/drivers/generic/adau7002/chip.h @@ -1,4 +1,22 @@ -#include <arch/acpi_device.h> +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __I2C_GENERIC_ADAU7002_CHIP_H__ +#define __I2C_GENERIC_ADAU7002_CHIP_H__ struct drivers_generic_adau7002_config { }; + +#endif /* __I2C_GENERIC_ADAU7002_CHIP_H__ */ -- To view, visit https://review.coreboot.org/23721 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic359ed262086596a98131669f8eecd531857187a Gerrit-Change-Number: 23721 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)chromium.org>

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Change in coreboot[master]: soc/amd/stoneyridge: Add gpio_interrupt_status
by build bot (Jenkins) (Code Review) 12 Feb '18

12 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23625 ) Change subject: soc/amd/stoneyridge: Add gpio_interrupt_status ...................................................................... Patch Set 6: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67395/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21935/ : SUCCESS -- To view, visit https://review.coreboot.org/23625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7ed76eaf56338a314a8d0ee6faad1ab8dbf8dfb0 Gerrit-Change-Number: 23625 Gerrit-PatchSet: 6 Gerrit-Owner: Chris Ching <chingcodes(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Chris Ching <chingcodes(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 12 Feb 2018 19:54:54 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mainboard/google/meowth: Turn on SAR features
by Lijian Zhao (Code Review) 12 Feb '18

12 Feb '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/23720 Change subject: mainboard/google/meowth: Turn on SAR features ...................................................................... mainboard/google/meowth: Turn on SAR features TEST=None Change-Id: I8dafa19da05102258e853512b2f4cf85f0876d21 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/google/zoombini/Kconfig M src/mainboard/google/zoombini/variants/meowth/devicetree.cb 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/23720/1 diff --git a/src/mainboard/google/zoombini/Kconfig b/src/mainboard/google/zoombini/Kconfig index 64180f3..1d3fe35 100644 --- a/src/mainboard/google/zoombini/Kconfig +++ b/src/mainboard/google/zoombini/Kconfig @@ -44,6 +44,11 @@ default "MEOWTH TEST 5868" if BOARD_GOOGLE_MEOWTH default "ZOOMBINI TEST 5722" if BOARD_GOOGLE_ZOOMBINI +config CHROMEOS + select DSAR_ENABLE + select SAR_ENABLE + select USE_SAR + config MAINBOARD_DIR string default "google/zoombini" diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb index 88de878..bb6f785 100644 --- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb @@ -62,6 +62,12 @@ device pci 12.6 off end # GSPI #2 device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) + device pci 14.3 on + chip drivers/intel/wifi + register "wake" = "GPE0_PME_B0" + device pci 00.0 on end + end + end # CNVi wifi device pci 14.5 off end # SDCard device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 -- To view, visit https://review.coreboot.org/23720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8dafa19da05102258e853512b2f4cf85f0876d21 Gerrit-Change-Number: 23720 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: mainboard/google/kahlee: Add tis_plat_irq_status
by build bot (Jenkins) (Code Review) 12 Feb '18

12 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23626 ) Change subject: mainboard/google/kahlee: Add tis_plat_irq_status ...................................................................... Patch Set 6: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67394/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21936/ : SUCCESS -- To view, visit https://review.coreboot.org/23626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5786d334b6c1cc70f4c7107c75b07a7e27ac4428 Gerrit-Change-Number: 23626 Gerrit-PatchSet: 6 Gerrit-Owner: Chris Ching <chingcodes(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Chris Ching (using chromium account) <chingcodes+old(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 12 Feb 2018 19:43:53 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mainboard/intel/cannonlake_rvp: Enable SAR function
by Lijian Zhao (Code Review) 12 Feb '18

12 Feb '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/23719 Change subject: mainboard/intel/cannonlake_rvp: Enable SAR function ...................................................................... mainboard/intel/cannonlake_rvp: Enable SAR function Change-Id: I23fc4d519376b2079bf95ae496903728adfdca96 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/intel/cannonlake_rvp/Kconfig M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb 2 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/23719/1 diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig b/src/mainboard/intel/cannonlake_rvp/Kconfig index fb6f9b1..622a2eb 100644 --- a/src/mainboard/intel/cannonlake_rvp/Kconfig +++ b/src/mainboard/intel/cannonlake_rvp/Kconfig @@ -79,4 +79,10 @@ config VBOOT select VBOOT_LID_SWITCH select VBOOT_MOCK_SECDATA + +config CHROMEOS + select DSAR_ENABLE + select SAR_ENABLE + select USE_SAR + endif diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index 8502048..1e39253 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -77,7 +77,12 @@ device pci 12.6 off end # GSPI #2 device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - device pci 14.3 on end # CNVi wifi + device pci 14.3 on + chip drivers/intel/wifi + register "wake" = "GPE0_PME_B0" + device pci 00.0 on end + end + end # CNVi wifi device pci 14.5 on end # SDCard device pci 15.0 on chip drivers/i2c/hid -- To view, visit https://review.coreboot.org/23719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I23fc4d519376b2079bf95ae496903728adfdca96 Gerrit-Change-Number: 23719 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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coreboot-gerrit February 2018