coreboot-gerrit February 2018

coreboot-gerrit@coreboot.org

1 participants
1573 discussions

Change in coreboot[master]: payloads: Add LinuxBoot payload in u-root mode
by build bot (Jenkins) (Code Review) 15 Feb '18

15 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23071 ) Change subject: payloads: Add LinuxBoot payload in u-root mode ...................................................................... Patch Set 12: Build Failed https://qa.coreboot.org/job/coreboot-gerrit/67531/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/22058/ : SUCCESS -- To view, visit https://review.coreboot.org/23071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3a25ff6812e046acc688cbbb203cf262ad751659 Gerrit-Change-Number: 23071 Gerrit-PatchSet: 12 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Alex Thiessen <alex.thiessen.de+coreboot(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chris K <c(a)chrisko.ch> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich Gerrit-Comment-Date: Thu, 15 Feb 2018 14:43:39 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: payloads: Add LinuxBoot payload in u-root mode
by build bot (Jenkins) (Code Review) 15 Feb '18

15 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23071 ) Change subject: payloads: Add LinuxBoot payload in u-root mode ...................................................................... Patch Set 12: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/67530/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/22058/ : SUCCESS -- To view, visit https://review.coreboot.org/23071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3a25ff6812e046acc688cbbb203cf262ad751659 Gerrit-Change-Number: 23071 Gerrit-PatchSet: 12 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Alex Thiessen <alex.thiessen.de+coreboot(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chris K <c(a)chrisko.ch> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich Gerrit-Comment-Date: Thu, 15 Feb 2018 14:43:12 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: security/vboot: Add boot mode selection
by build bot (Jenkins) (Code Review) 15 Feb '18

15 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23756 ) Change subject: security/vboot: Add boot mode selection ...................................................................... Patch Set 17: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22057/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/67529/ : SUCCESS -- To view, visit https://review.coreboot.org/23756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I43d233d5a8766af2dd7f07cc0b64293a80d5d7d2 Gerrit-Change-Number: 23756 Gerrit-PatchSet: 17 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Feb 2018 14:25:49 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: security/vboot: Add boot mode selection
by build bot (Jenkins) (Code Review) 15 Feb '18

15 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23756 ) Change subject: security/vboot: Add boot mode selection ...................................................................... Patch Set 17: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/67528/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/22057/ : SUCCESS -- To view, visit https://review.coreboot.org/23756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I43d233d5a8766af2dd7f07cc0b64293a80d5d7d2 Gerrit-Change-Number: 23756 Gerrit-PatchSet: 17 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Feb 2018 13:45:38 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: arch/riscv: Delegate the page fault exceptions
by build bot (Jenkins) (Code Review) 15 Feb '18

15 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23774 ) Change subject: arch/riscv: Delegate the page fault exceptions ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22056/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/67527/ : SUCCESS -- To view, visit https://review.coreboot.org/23774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iec15afe9656107b9aeea1677c5b8dc7d654fa746 Gerrit-Change-Number: 23774 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Feb 2018 13:43:13 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: arch/riscv: Don't set up virtual memory
by build bot (Jenkins) (Code Review) 15 Feb '18

15 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23772 ) Change subject: arch/riscv: Don't set up virtual memory ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22054/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/67525/ : SUCCESS -- To view, visit https://review.coreboot.org/23772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4e69d15f8ee540d2f98c342bc4ec0c00fb48def0 Gerrit-Change-Number: 23772 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Feb 2018 13:42:50 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: arch/riscv: Update encoding.h and adjust related code
by build bot (Jenkins) (Code Review) 15 Feb '18

15 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23773 ) Change subject: arch/riscv: Update encoding.h and adjust related code ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/67526/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/22055/ : SUCCESS -- To view, visit https://review.coreboot.org/23773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I517042e5865986e88a589dc8623745f8d584d6b8 Gerrit-Change-Number: 23773 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Feb 2018 13:30:48 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: arch/riscv: Delegate the page fault exceptions
by Jonathan Neuschäfer (Code Review) 15 Feb '18

15 Feb '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/23774 Change subject: arch/riscv: Delegate the page fault exceptions ...................................................................... arch/riscv: Delegate the page fault exceptions These exceptions were new in the Privileged Architecture spec 1.10. We need to delegate them to S-mode. Change-Id: Iec15afe9656107b9aeea1677c5b8dc7d654fa746 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/arch/riscv/virtual_memory.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/23774/1 diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index 3cc2cc9..3bee868 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -32,6 +32,9 @@ | (1 << CAUSE_LOAD_ACCESS) | (1 << CAUSE_STORE_ACCESS) | (1 << CAUSE_USER_ECALL) + | (1 << CAUSE_FETCH_PAGE_FAULT) + | (1 << CAUSE_LOAD_PAGE_FAULT) + | (1 << CAUSE_STORE_PAGE_FAULT) ; void mstatus_init(void) -- To view, visit https://review.coreboot.org/23774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iec15afe9656107b9aeea1677c5b8dc7d654fa746 Gerrit-Change-Number: 23774 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

1 0

Change in coreboot[master]: arch/riscv: Update encoding.h and adjust related code
by Jonathan Neuschäfer (Code Review) 15 Feb '18

15 Feb '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/23773 Change subject: arch/riscv: Update encoding.h and adjust related code ...................................................................... arch/riscv: Update encoding.h and adjust related code Update encoding.h to the version shipped with spike commit 0185d36 ("Merge pull request #165 from riscv/small_progbuf"), and copy the license header from the LICENSE file. Change-Id: I517042e5865986e88a589dc8623745f8d584d6b8 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/arch/riscv/include/arch/encoding.h M src/arch/riscv/trap_handler.c M src/arch/riscv/virtual_memory.c 3 files changed, 238 insertions(+), 83 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/23773/1 diff --git a/src/arch/riscv/include/arch/encoding.h b/src/arch/riscv/include/arch/encoding.h index 5142a78..f84c9d4 100644 --- a/src/arch/riscv/include/arch/encoding.h +++ b/src/arch/riscv/include/arch/encoding.h @@ -1,6 +1,6 @@ /* - * Copyright (c) 2016, The Regents of the University of California (Regents). - * All Rights Reserved. + * Copyright (c) 2010-2017, The Regents of the University of California + * (Regents). All Rights Reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -42,17 +42,16 @@ #define MSTATUS_FS 0x00006000 #define MSTATUS_XS 0x00018000 #define MSTATUS_MPRV 0x00020000 -#define MSTATUS_PUM 0x00040000 +#define MSTATUS_SUM 0x00040000 #define MSTATUS_MXR 0x00080000 -#define MSTATUS_VM 0x1F000000 +#define MSTATUS_TVM 0x00100000 +#define MSTATUS_TW 0x00200000 +#define MSTATUS_TSR 0x00400000 #define MSTATUS32_SD 0x80000000 +#define MSTATUS_UXL 0x0000000300000000 +#define MSTATUS_SXL 0x0000000C00000000 #define MSTATUS64_SD 0x8000000000000000 -#define MIE_UTIE 0x00000010 -#define MIE_STIE 0x00000020 -#define MIE_HTIE 0x00000040 -#define MIE_MTIE 0x00000080 - #define SSTATUS_UIE 0x00000001 #define SSTATUS_SIE 0x00000002 #define SSTATUS_UPIE 0x00000010 @@ -60,8 +59,10 @@ #define SSTATUS_SPP 0x00000100 #define SSTATUS_FS 0x00006000 #define SSTATUS_XS 0x00018000 -#define SSTATUS_PUM 0x00040000 +#define SSTATUS_SUM 0x00040000 +#define SSTATUS_MXR 0x00080000 #define SSTATUS32_SD 0x80000000 +#define SSTATUS_UXL 0x0000000300000000 #define SSTATUS64_SD 0x8000000000000000 #define DCSR_XDEBUGVER (3U<<30) @@ -131,19 +132,36 @@ #define SIP_SSIP MIP_SSIP #define SIP_STIP MIP_STIP -#define SIE_STIE MIE_STIE #define PRV_U 0 #define PRV_S 1 #define PRV_H 2 #define PRV_M 3 -#define VM_MBARE 0 -#define VM_MBB 1 -#define VM_MBBID 2 -#define VM_SV32 8 -#define VM_SV39 9 -#define VM_SV48 10 +#define SATP32_MODE 0x80000000 +#define SATP32_ASID 0x7FC00000 +#define SATP32_PPN 0x003FFFFF +#define SATP64_MODE 0xF000000000000000 +#define SATP64_ASID 0x0FFFF00000000000 +#define SATP64_PPN 0x00000FFFFFFFFFFF + +#define SATP_MODE_OFF 0 +#define SATP_MODE_SV32 1 +#define SATP_MODE_SV39 8 +#define SATP_MODE_SV48 9 +#define SATP_MODE_SV57 10 +#define SATP_MODE_SV64 11 + +#define PMP_R 0x01 +#define PMP_W 0x02 +#define PMP_X 0x04 +#define PMP_A 0x18 +#define PMP_L 0x80 +#define PMP_SHIFT 2 + +#define PMP_TOR 0x08 +#define PMP_NA4 0x10 +#define PMP_NAPOT 0x18 #define IRQ_S_SOFT 1 #define IRQ_H_SOFT 2 @@ -158,9 +176,8 @@ #define IRQ_HOST 13 #define DEFAULT_RSTVEC 0x00001000 -#define DEFAULT_NMIVEC 0x00001004 -#define DEFAULT_MTVEC 0x00001010 -#define CONFIG_STRING_ADDR 0x0000100C +#define CLINT_BASE 0x02000000 +#define CLINT_SIZE 0x000c0000 #define EXT_IO_BASE 0x40000000 #define DRAM_BASE 0x80000000 @@ -181,14 +198,16 @@ #ifdef __riscv -#ifdef __riscv64 +#if __riscv_xlen == 64 # define MSTATUS_SD MSTATUS64_SD # define SSTATUS_SD SSTATUS64_SD # define RISCV_PGLEVEL_BITS 9 +# define SATP_MODE SATP64_MODE #else # define MSTATUS_SD MSTATUS32_SD # define SSTATUS_SD SSTATUS32_SD # define RISCV_PGLEVEL_BITS 10 +# define SATP_MODE SATP32_MODE #endif #define RISCV_PGSHIFT 12 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT) @@ -198,35 +217,23 @@ #ifdef __GNUC__ #define read_csr(reg) ({ unsigned long __tmp; \ - asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ - __tmp; }) + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) #define write_csr(reg, val) ({ \ - if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ - asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ - else \ - asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) + asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) #define swap_csr(reg, val) ({ unsigned long __tmp; \ - if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ - else \ - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ - __tmp; }) + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ + __tmp; }) #define set_csr(reg, bit) ({ unsigned long __tmp; \ - if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ - else \ - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ - __tmp; }) + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; }) #define clear_csr(reg, bit) ({ unsigned long __tmp; \ - if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ - else \ - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ - __tmp; }) + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; }) #define rdtime() read_csr(time) #define rdcycle() read_csr(cycle) @@ -239,7 +246,7 @@ #endif #endif -/* Automatically generated by parse-opcodes */ +/* Automatically generated by parse-opcodes. */ #ifndef RISCV_ENCODING_H #define RISCV_ENCODING_H #define MATCH_BEQ 0x63 @@ -422,14 +429,12 @@ #define MASK_URET 0xffffffff #define MATCH_SRET 0x10200073 #define MASK_SRET 0xffffffff -#define MATCH_HRET 0x20200073 -#define MASK_HRET 0xffffffff #define MATCH_MRET 0x30200073 #define MASK_MRET 0xffffffff #define MATCH_DRET 0x7b200073 #define MASK_DRET 0xffffffff -#define MATCH_SFENCE_VM 0x10400073 -#define MASK_SFENCE_VM 0xfff07fff +#define MATCH_SFENCE_VMA 0x12000073 +#define MASK_SFENCE_VMA 0xfe007fff #define MATCH_WFI 0x10500073 #define MASK_WFI 0xffffffff #define MATCH_CSRRW 0x1073 @@ -488,6 +493,34 @@ #define MASK_FCVT_D_S 0xfff0007f #define MATCH_FSQRT_D 0x5a000053 #define MASK_FSQRT_D 0xfff0007f +#define MATCH_FADD_Q 0x6000053 +#define MASK_FADD_Q 0xfe00007f +#define MATCH_FSUB_Q 0xe000053 +#define MASK_FSUB_Q 0xfe00007f +#define MATCH_FMUL_Q 0x16000053 +#define MASK_FMUL_Q 0xfe00007f +#define MATCH_FDIV_Q 0x1e000053 +#define MASK_FDIV_Q 0xfe00007f +#define MATCH_FSGNJ_Q 0x26000053 +#define MASK_FSGNJ_Q 0xfe00707f +#define MATCH_FSGNJN_Q 0x26001053 +#define MASK_FSGNJN_Q 0xfe00707f +#define MATCH_FSGNJX_Q 0x26002053 +#define MASK_FSGNJX_Q 0xfe00707f +#define MATCH_FMIN_Q 0x2e000053 +#define MASK_FMIN_Q 0xfe00707f +#define MATCH_FMAX_Q 0x2e001053 +#define MASK_FMAX_Q 0xfe00707f +#define MATCH_FCVT_S_Q 0x40300053 +#define MASK_FCVT_S_Q 0xfff0007f +#define MATCH_FCVT_Q_S 0x46000053 +#define MASK_FCVT_Q_S 0xfff0007f +#define MATCH_FCVT_D_Q 0x42300053 +#define MASK_FCVT_D_Q 0xfff0007f +#define MATCH_FCVT_Q_D 0x46100053 +#define MASK_FCVT_Q_D 0xfff0007f +#define MATCH_FSQRT_Q 0x5e000053 +#define MASK_FSQRT_Q 0xfff0007f #define MATCH_FLE_S 0xa0000053 #define MASK_FLE_S 0xfe00707f #define MATCH_FLT_S 0xa0001053 @@ -500,6 +533,12 @@ #define MASK_FLT_D 0xfe00707f #define MATCH_FEQ_D 0xa2002053 #define MASK_FEQ_D 0xfe00707f +#define MATCH_FLE_Q 0xa6000053 +#define MASK_FLE_Q 0xfe00707f +#define MATCH_FLT_Q 0xa6001053 +#define MASK_FLT_Q 0xfe00707f +#define MATCH_FEQ_Q 0xa6002053 +#define MASK_FEQ_Q 0xfe00707f #define MATCH_FCVT_W_S 0xc0000053 #define MASK_FCVT_W_S 0xfff0007f #define MATCH_FCVT_WU_S 0xc0100053 @@ -508,8 +547,8 @@ #define MASK_FCVT_L_S 0xfff0007f #define MATCH_FCVT_LU_S 0xc0300053 #define MASK_FCVT_LU_S 0xfff0007f -#define MATCH_FMV_X_S 0xe0000053 -#define MASK_FMV_X_S 0xfff0707f +#define MATCH_FMV_X_W 0xe0000053 +#define MASK_FMV_X_W 0xfff0707f #define MATCH_FCLASS_S 0xe0001053 #define MASK_FCLASS_S 0xfff0707f #define MATCH_FCVT_W_D 0xc2000053 @@ -524,6 +563,18 @@ #define MASK_FMV_X_D 0xfff0707f #define MATCH_FCLASS_D 0xe2001053 #define MASK_FCLASS_D 0xfff0707f +#define MATCH_FCVT_W_Q 0xc6000053 +#define MASK_FCVT_W_Q 0xfff0007f +#define MATCH_FCVT_WU_Q 0xc6100053 +#define MASK_FCVT_WU_Q 0xfff0007f +#define MATCH_FCVT_L_Q 0xc6200053 +#define MASK_FCVT_L_Q 0xfff0007f +#define MATCH_FCVT_LU_Q 0xc6300053 +#define MASK_FCVT_LU_Q 0xfff0007f +#define MATCH_FMV_X_Q 0xe6000053 +#define MASK_FMV_X_Q 0xfff0707f +#define MATCH_FCLASS_Q 0xe6001053 +#define MASK_FCLASS_Q 0xfff0707f #define MATCH_FCVT_S_W 0xd0000053 #define MASK_FCVT_S_W 0xfff0007f #define MATCH_FCVT_S_WU 0xd0100053 @@ -532,8 +583,8 @@ #define MASK_FCVT_S_L 0xfff0007f #define MATCH_FCVT_S_LU 0xd0300053 #define MASK_FCVT_S_LU 0xfff0007f -#define MATCH_FMV_S_X 0xf0000053 -#define MASK_FMV_S_X 0xfff0707f +#define MATCH_FMV_W_X 0xf0000053 +#define MASK_FMV_W_X 0xfff0707f #define MATCH_FCVT_D_W 0xd2000053 #define MASK_FCVT_D_W 0xfff0007f #define MATCH_FCVT_D_WU 0xd2100053 @@ -544,14 +595,28 @@ #define MASK_FCVT_D_LU 0xfff0007f #define MATCH_FMV_D_X 0xf2000053 #define MASK_FMV_D_X 0xfff0707f +#define MATCH_FCVT_Q_W 0xd6000053 +#define MASK_FCVT_Q_W 0xfff0007f +#define MATCH_FCVT_Q_WU 0xd6100053 +#define MASK_FCVT_Q_WU 0xfff0007f +#define MATCH_FCVT_Q_L 0xd6200053 +#define MASK_FCVT_Q_L 0xfff0007f +#define MATCH_FCVT_Q_LU 0xd6300053 +#define MASK_FCVT_Q_LU 0xfff0007f +#define MATCH_FMV_Q_X 0xf6000053 +#define MASK_FMV_Q_X 0xfff0707f #define MATCH_FLW 0x2007 #define MASK_FLW 0x707f #define MATCH_FLD 0x3007 #define MASK_FLD 0x707f +#define MATCH_FLQ 0x4007 +#define MASK_FLQ 0x707f #define MATCH_FSW 0x2027 #define MASK_FSW 0x707f #define MATCH_FSD 0x3027 #define MASK_FSD 0x707f +#define MATCH_FSQ 0x4027 +#define MASK_FSQ 0x707f #define MATCH_FMADD_S 0x43 #define MASK_FMADD_S 0x600007f #define MATCH_FMSUB_S 0x47 @@ -568,6 +633,14 @@ #define MASK_FNMSUB_D 0x600007f #define MATCH_FNMADD_D 0x200004f #define MASK_FNMADD_D 0x600007f +#define MATCH_FMADD_Q 0x6000043 +#define MASK_FMADD_Q 0x600007f +#define MATCH_FMSUB_Q 0x6000047 +#define MASK_FMSUB_Q 0x600007f +#define MATCH_FNMSUB_Q 0x600004b +#define MASK_FNMSUB_Q 0x600007f +#define MATCH_FNMADD_Q 0x600004f +#define MASK_FNMADD_Q 0x600007f #define MATCH_C_NOP 0x1 #define MASK_C_NOP 0xffff #define MATCH_C_ADDI16SP 0x6101 @@ -738,23 +811,45 @@ #define CSR_SSTATUS 0x100 #define CSR_SIE 0x104 #define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 #define CSR_SCAUSE 0x142 -#define CSR_SBADADDR 0x143 +#define CSR_STVAL 0x143 #define CSR_SIP 0x144 -#define CSR_SPTBR 0x180 +#define CSR_SATP 0x180 #define CSR_MSTATUS 0x300 #define CSR_MISA 0x301 #define CSR_MEDELEG 0x302 #define CSR_MIDELEG 0x303 #define CSR_MIE 0x304 #define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 #define CSR_MSCRATCH 0x340 #define CSR_MEPC 0x341 #define CSR_MCAUSE 0x342 -#define CSR_MBADADDR 0x343 +#define CSR_MTVAL 0x343 #define CSR_MIP 0x344 +#define CSR_PMPCFG0 0x3a0 +#define CSR_PMPCFG1 0x3a1 +#define CSR_PMPCFG2 0x3a2 +#define CSR_PMPCFG3 0x3a3 +#define CSR_PMPADDR0 0x3b0 +#define CSR_PMPADDR1 0x3b1 +#define CSR_PMPADDR2 0x3b2 +#define CSR_PMPADDR3 0x3b3 +#define CSR_PMPADDR4 0x3b4 +#define CSR_PMPADDR5 0x3b5 +#define CSR_PMPADDR6 0x3b6 +#define CSR_PMPADDR7 0x3b7 +#define CSR_PMPADDR8 0x3b8 +#define CSR_PMPADDR9 0x3b9 +#define CSR_PMPADDR10 0x3ba +#define CSR_PMPADDR11 0x3bb +#define CSR_PMPADDR12 0x3bc +#define CSR_PMPADDR13 0x3bd +#define CSR_PMPADDR14 0x3be +#define CSR_PMPADDR15 0x3bf #define CSR_TSELECT 0x7a0 #define CSR_TDATA1 0x7a1 #define CSR_TDATA2 0x7a2 @@ -793,8 +888,6 @@ #define CSR_MHPMCOUNTER29 0xb1d #define CSR_MHPMCOUNTER30 0xb1e #define CSR_MHPMCOUNTER31 0xb1f -#define CSR_MUCOUNTEREN 0x320 -#define CSR_MSCOUNTEREN 0x321 #define CSR_MHPMEVENT3 0x323 #define CSR_MHPMEVENT4 0x324 #define CSR_MHPMEVENT5 0x325 @@ -892,17 +985,20 @@ #define CSR_MHPMCOUNTER30H 0xb9e #define CSR_MHPMCOUNTER31H 0xb9f #define CAUSE_MISALIGNED_FETCH 0x0 -#define CAUSE_FAULT_FETCH 0x1 +#define CAUSE_FETCH_ACCESS 0x1 #define CAUSE_ILLEGAL_INSTRUCTION 0x2 #define CAUSE_BREAKPOINT 0x3 #define CAUSE_MISALIGNED_LOAD 0x4 -#define CAUSE_FAULT_LOAD 0x5 +#define CAUSE_LOAD_ACCESS 0x5 #define CAUSE_MISALIGNED_STORE 0x6 -#define CAUSE_FAULT_STORE 0x7 +#define CAUSE_STORE_ACCESS 0x7 #define CAUSE_USER_ECALL 0x8 #define CAUSE_SUPERVISOR_ECALL 0x9 #define CAUSE_HYPERVISOR_ECALL 0xa #define CAUSE_MACHINE_ECALL 0xb +#define CAUSE_FETCH_PAGE_FAULT 0xc +#define CAUSE_LOAD_PAGE_FAULT 0xd +#define CAUSE_STORE_PAGE_FAULT 0xf #endif #ifdef DECLARE_INSN DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) @@ -995,10 +1091,9 @@ DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) DECLARE_INSN(uret, MATCH_URET, MASK_URET) DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) -DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) -DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) +DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) @@ -1028,17 +1123,34 @@ DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) +DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) +DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) +DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) +DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) +DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) +DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) +DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) +DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) +DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) +DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) +DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) +DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) +DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) +DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) +DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) -DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) +DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W) DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) @@ -1046,20 +1158,33 @@ DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) +DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) +DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) +DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) +DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) +DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q) +DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) -DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) +DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X) DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) +DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) +DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) +DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) +DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X) DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) @@ -1068,6 +1193,10 @@ DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) +DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) +DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) +DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) @@ -1174,23 +1303,45 @@ DECLARE_CSR(sstatus, CSR_SSTATUS) DECLARE_CSR(sie, CSR_SIE) DECLARE_CSR(stvec, CSR_STVEC) +DECLARE_CSR(scounteren, CSR_SCOUNTEREN) DECLARE_CSR(sscratch, CSR_SSCRATCH) DECLARE_CSR(sepc, CSR_SEPC) DECLARE_CSR(scause, CSR_SCAUSE) -DECLARE_CSR(sbadaddr, CSR_SBADADDR) +DECLARE_CSR(stval, CSR_STVAL) DECLARE_CSR(sip, CSR_SIP) -DECLARE_CSR(sptbr, CSR_SPTBR) +DECLARE_CSR(satp, CSR_SATP) DECLARE_CSR(mstatus, CSR_MSTATUS) DECLARE_CSR(misa, CSR_MISA) DECLARE_CSR(medeleg, CSR_MEDELEG) DECLARE_CSR(mideleg, CSR_MIDELEG) DECLARE_CSR(mie, CSR_MIE) DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) DECLARE_CSR(mscratch, CSR_MSCRATCH) DECLARE_CSR(mepc, CSR_MEPC) DECLARE_CSR(mcause, CSR_MCAUSE) -DECLARE_CSR(mbadaddr, CSR_MBADADDR) +DECLARE_CSR(mtval, CSR_MTVAL) DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) +DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) +DECLARE_CSR(pmpcfg2, CSR_PMPCFG2) +DECLARE_CSR(pmpcfg3, CSR_PMPCFG3) +DECLARE_CSR(pmpaddr0, CSR_PMPADDR0) +DECLARE_CSR(pmpaddr1, CSR_PMPADDR1) +DECLARE_CSR(pmpaddr2, CSR_PMPADDR2) +DECLARE_CSR(pmpaddr3, CSR_PMPADDR3) +DECLARE_CSR(pmpaddr4, CSR_PMPADDR4) +DECLARE_CSR(pmpaddr5, CSR_PMPADDR5) +DECLARE_CSR(pmpaddr6, CSR_PMPADDR6) +DECLARE_CSR(pmpaddr7, CSR_PMPADDR7) +DECLARE_CSR(pmpaddr8, CSR_PMPADDR8) +DECLARE_CSR(pmpaddr9, CSR_PMPADDR9) +DECLARE_CSR(pmpaddr10, CSR_PMPADDR10) +DECLARE_CSR(pmpaddr11, CSR_PMPADDR11) +DECLARE_CSR(pmpaddr12, CSR_PMPADDR12) +DECLARE_CSR(pmpaddr13, CSR_PMPADDR13) +DECLARE_CSR(pmpaddr14, CSR_PMPADDR14) +DECLARE_CSR(pmpaddr15, CSR_PMPADDR15) DECLARE_CSR(tselect, CSR_TSELECT) DECLARE_CSR(tdata1, CSR_TDATA1) DECLARE_CSR(tdata2, CSR_TDATA2) @@ -1229,8 +1380,6 @@ DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) -DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN) -DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN) DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) @@ -1327,20 +1476,21 @@ DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) - +#endif #ifdef DECLARE_CAUSE DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) -DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH) +DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS) DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) -DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD) +DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS) DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) -DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE) +DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS) DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) +DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT) +DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT) +DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT) #endif - -#endif /* RISCV_CSR_ENCODING_H */ diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index 8fd0375..7b35c2e 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <arch/encoding.h> #include <arch/exception.h> #include <console/console.h> #include <string.h> @@ -33,8 +34,12 @@ "Store access fault", "Environment call from U-mode", "Environment call from S-mode", - "Environment call from H-mode", - "Environment call from M-mode" + "Reserved (10)", + "Environment call from M-mode", + "Instruction page fault", + "Load page fault", + "Reserved (14)", + "Store page fault", }; static const char *mstatus_to_previous_mode(uintptr_t ms) @@ -119,7 +124,7 @@ // at present, as we only search for // "core{0{0{timecmp" above. ssie = read_csr(sie); - if (!(ssie & SIE_STIE)) + if (!(ssie & SIP_STIP)) break; if (!timecmp) @@ -149,11 +154,11 @@ switch(tf->cause) { case CAUSE_MISALIGNED_FETCH: - case CAUSE_FAULT_FETCH: + case CAUSE_FETCH_ACCESS: case CAUSE_ILLEGAL_INSTRUCTION: case CAUSE_BREAKPOINT: - case CAUSE_FAULT_LOAD: - case CAUSE_FAULT_STORE: + case CAUSE_LOAD_ACCESS: + case CAUSE_STORE_ACCESS: case CAUSE_USER_ECALL: case CAUSE_SUPERVISOR_ECALL: case CAUSE_HYPERVISOR_ECALL: diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index 702d6b7..3cc2cc9 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -26,11 +26,11 @@ * the spec so for now we enumerate and set them all. */ static int delegate = 0 | (1 << CAUSE_MISALIGNED_FETCH) - | (1 << CAUSE_FAULT_FETCH) + | (1 << CAUSE_FETCH_ACCESS) | (1 << CAUSE_ILLEGAL_INSTRUCTION) | (1 << CAUSE_BREAKPOINT) - | (1 << CAUSE_FAULT_LOAD) - | (1 << CAUSE_FAULT_STORE) + | (1 << CAUSE_LOAD_ACCESS) + | (1 << CAUSE_STORE_ACCESS) | (1 << CAUSE_USER_ECALL) ; -- To view, visit https://review.coreboot.org/23773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I517042e5865986e88a589dc8623745f8d584d6b8 Gerrit-Change-Number: 23773 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

1 0

Change in coreboot[master]: arch/riscv: Don't set up virtual memory
by Jonathan Neuschäfer (Code Review) 15 Feb '18

15 Feb '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/23772 Change subject: arch/riscv: Don't set up virtual memory ...................................................................... arch/riscv: Don't set up virtual memory Due to changes in the RISC-V Privileged Architecture specification, Linux can now be started in physical memory and it will setup its own page tables. Thus we can delete most of virtual_memory.c. Change-Id: I4e69d15f8ee540d2f98c342bc4ec0c00fb48def0 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/Kconfig M src/arch/riscv/boot.c M src/arch/riscv/include/vm.h M src/arch/riscv/virtual_memory.c 4 files changed, 0 insertions(+), 266 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/23772/1 diff --git a/src/Kconfig b/src/Kconfig index 459280d..02abed2 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -975,14 +975,6 @@ Control debugging of the boot state machine. When selected displays the state boundaries in ramstage. -config DEBUG_PRINT_PAGE_TABLES - bool "Print the page tables after construction" - default n - depends on ARCH_RISCV - help - After the page tables have been built, print them on the debug - console. - config DEBUG_ADA_CODE bool "Compile debug code in Ada sources" default n diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index ac095bb..b73f3ca 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -27,7 +27,6 @@ if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { printk(BIOS_SPEW, "Config string: '%s'\n", config); - initVirtualMemory(); printk(BIOS_SPEW, "OK, let's go\n"); riscvpayload(config, doit); } diff --git a/src/arch/riscv/include/vm.h b/src/arch/riscv/include/vm.h index 1a8f7ad..fd0a2c9 100644 --- a/src/arch/riscv/include/vm.h +++ b/src/arch/riscv/include/vm.h @@ -32,36 +32,11 @@ #include <stdint.h> #include <arch/encoding.h> -#define SUPERPAGE_SIZE ((uintptr_t)(RISCV_PGSIZE << RISCV_PGLEVEL_BITS)) -#define VM_CHOICE VM_SV39 -#define VA_BITS 39 -#define MEGAPAGE_SIZE (SUPERPAGE_SIZE << RISCV_PGLEVEL_BITS) - #define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) #define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) -#define supervisor_paddr_valid(start, length) \ - ((uintptr_t)(start) >= current.first_user_vaddr + current.bias \ - && (uintptr_t)(start) + (length) < mem_size \ - && (uintptr_t)(start) + (length) >= (uintptr_t)(start)) - -typedef uintptr_t pte_t; -extern pte_t* root_page_table; - -void initVirtualMemory(void); - -size_t pte_ppn(pte_t pte); -pte_t ptd_create(uintptr_t ppn); -pte_t pte_create(uintptr_t ppn, int prot, int user); - -void print_page_table(void); - -void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, - pte_t *pageTableStart); void mstatus_init(void); // need to setup mstatus so we know we have virtual memory -void flush_tlb(void); - #define DEFINE_MPRV_READ(name, type, insn) \ static inline type name(type *p); \ diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index 27b4b82..702d6b7 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -14,13 +14,9 @@ * GNU General Public License for more details. */ -#include <arch/barrier.h> #include <arch/encoding.h> -#include <atomic.h> -#include <console/console.h> #include <stdint.h> #include <vm.h> -#include <symbols.h> /* Delegate controls which traps are delegated to the payload. If you * wish to temporarily disable some or all delegation you can, in a @@ -38,234 +34,6 @@ | (1 << CAUSE_USER_ECALL) ; -pte_t* root_page_table; - -/* Indent the following text by 2*level spaces */ -static void indent(int level) -{ - int i; - for (i = 0; i < level; i++) - printk(BIOS_DEBUG, " "); -} - -/* - * Convert a page table index at a given page table level to a virtual address - * offset - */ -static uintptr_t index_to_virt_addr(int index, int level) -{ - /* - * Index is at most RISCV_PGLEVEL_BITS bits wide (not considering the - * leading zeroes. If level==0, the below expression thus shifts index - * into the highest bits of a 64-bit number, and then shifts it down - * with sign extension. - * - * If level>0, then the expression should work as expected, without any - * magic. - */ - return ((intptr_t)index) - << (64 - RISCV_PGLEVEL_BITS - level * RISCV_PGLEVEL_BITS) - >> (64 - VA_BITS); -} - -/* Dump the page table structures to the console -- helper function */ -static void print_page_table_at(pte_t *pt, intptr_t virt_addr, int level) -{ - int i; - - indent(level); - printk(BIOS_DEBUG, "Level %d page table at 0x%p\n", level, pt); - - for (i = 0; i < RISCV_PGSIZE / sizeof(pte_t); i++) { - char urwx[8]; - uintptr_t pointer; - intptr_t next_virt_addr; - - if (!(pt[i] & PTE_V)) - continue; - - urwx[0] = (pt[i] & PTE_U)? 'u' : '-'; - urwx[1] = (pt[i] & PTE_R)? 'r' : '-'; - urwx[2] = (pt[i] & PTE_W)? 'w' : '-'; - urwx[3] = (pt[i] & PTE_X)? 'x' : '-'; - urwx[4] = '\0'; - - next_virt_addr = virt_addr + index_to_virt_addr(i, level); - - pointer = ((uintptr_t)pt[i] >> 10) << RISCV_PGSHIFT; - - indent(level + 1); - printk(BIOS_DEBUG, "Valid PTE at index %d (0x%016zx -> 0x%zx), ", - i, (size_t) next_virt_addr, (size_t) pointer); - if (PTE_TABLE(pt[i])) - printk(BIOS_DEBUG, "page table\n"); - else - printk(BIOS_DEBUG, "protections %s\n", urwx); - - if (PTE_TABLE(pt[i])) { - print_page_table_at((pte_t *)pointer, next_virt_addr, level + 1); - } - } -} - -/* Print the page table structures to the console */ -void print_page_table(void) { - print_page_table_at((void *)(read_csr(sptbr) << RISCV_PGSHIFT), 0, 0); -} - -void flush_tlb(void) -{ - asm volatile("sfence.vm"); -} - -size_t pte_ppn(pte_t pte) -{ - return pte >> PTE_PPN_SHIFT; -} - -pte_t ptd_create(uintptr_t ppn) -{ - return (ppn << PTE_PPN_SHIFT) | PTE_V; -} - -pte_t pte_create(uintptr_t ppn, int prot, int user) -{ - pte_t pte = (ppn << PTE_PPN_SHIFT) | PTE_R | PTE_V; - if (prot & PTE_W) - pte |= PTE_W; - if (prot & PTE_X) - pte |= PTE_X; - if (user) - pte |= PTE_U; - return pte; -} - -// The current RISCV *physical* address space is this: -// * 0 - 2 GiB: miscellaneous IO devices -// * 2 GiB - 4 GiB DRAM -// We have determined, also, that if code references a physical address -// not backed by a device, we'll take a fault. In other words, we don't -// need to finely map the memory-mapped devices as we would on an x86. -// We can use GiB mappings for the IO space and we will take a trap -// if we reference hardware that does not exist. -// -// The intent of the RISCV designers is that pages be set up in M mode -// for lower privilege software. They have also told me that they -// expect, unlike other platforms, that next level software use these -// page tables. Some kernels (Linux) prefer the old fashioned model, -// where kernel starts with an identity (ID) map and sets up page tables as -// it sees fit. Other kernels (harvey) are fine with using whatever -// firmware sets up. We need to accommodate both. So, we set up the -// identity map for Linux, but also set up the map for kernels that -// are more willing to conform to the RISCV model. The map is as -// follows: -// -// ID map: map IO space and all of DRAM 1:1 using 1 GiB PTEs -// I.e. we use 1 GiB PTEs for 4 GiB. -// Linux/BSD uses this mapping just enough to replace it. -// -// Top 2G map: map the 2 Gib - 4 GiB of physical address space to -// 0xffffffff_80000000. This will be needed until the GNU toolchain can compile -// code to run at 0xffffffc000000000, i.e. the start of Sv39. -// -// Only Harvey/Plan 9 uses this Mapping, and temporarily. -// -// standard RISCV map long term: Map IO space, and all of DRAM, to the *lowest* -// possible negative address for this implementation, -// e.g. 0xffffffc000000000 for Sv39 CPUs. For now we can use GiB PTEs. -// -// RISCV map for now: map IO space, and all of DRAM, starting at -// 0xffff_ffc0_0000_0000, i.e. just as for Sv39. -// -// It is our intent on Harvey (and eventually Akaros) that we use -// this map, once the toolchain can correctly support it. -// We have tested this arrangement and it lets us boot harvey to user mode. -void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, pte_t *pt) -{ - // 0xFFF... - 0xFFFFFFFF81000000 - RISCV_PGSIZE - intptr_t memorySize = 0x7F000000; - - // middle page table - pte_t* middle_pt = (void*)pt; - size_t num_middle_pts = 2; // 3 level page table, 39 bit virtual address space for now - - // root page table - pte_t* root_pt = (void*)middle_pt + num_middle_pts * RISCV_PGSIZE; - memset(middle_pt, 0, (num_middle_pts + 1) * RISCV_PGSIZE); // 0's out middle_pt and root_pt - for (size_t i = 0; i < num_middle_pts; i++) - root_pt[(1<<RISCV_PGLEVEL_BITS)-num_middle_pts+i] = ptd_create(((uintptr_t)middle_pt >> RISCV_PGSHIFT) + i); - - // fill the middle page table - for (uintptr_t vaddr = virtMemStart, paddr = physMemStart; - paddr < physMemStart + memorySize; - vaddr += SUPERPAGE_SIZE, paddr += SUPERPAGE_SIZE) { - int l2_shift = RISCV_PGLEVEL_BITS + RISCV_PGSHIFT; - size_t l2_idx = (virtMemStart >> l2_shift) & ((1 << RISCV_PGLEVEL_BITS)-1); - l2_idx += ((vaddr - virtMemStart) >> l2_shift); - middle_pt[l2_idx] = pte_create(paddr >> RISCV_PGSHIFT, - PTE_U|PTE_R|PTE_W|PTE_X, 0); - } - - // IO space. Identity mapped. - root_pt[0x000] = pte_create(0x00000000 >> RISCV_PGSHIFT, - PTE_R | PTE_W, 0); - root_pt[0x001] = pte_create(0x40000000 >> RISCV_PGSHIFT, - PTE_R | PTE_W, 0); - root_pt[0x002] = pte_create(0x80000000 >> RISCV_PGSHIFT, - PTE_R | PTE_W | PTE_X, 0); - root_pt[0x003] = pte_create(0xc0000000 >> RISCV_PGSHIFT, - PTE_R | PTE_W | PTE_X, 0); - - // Negative address space map at 0xffffffc000000000 - root_pt[0x100] = root_pt[0]; - root_pt[0x101] = root_pt[1]; - root_pt[0x102] = root_pt[2]; - root_pt[0x103] = root_pt[3]; - - mb(); - root_page_table = root_pt; - uintptr_t ptbr = ((uintptr_t) root_pt) >> RISCV_PGSHIFT; - write_csr(sptbr, ptbr); -} - -void initVirtualMemory(void) { - uintptr_t ms; - - ms = read_csr(mstatus); - ms = INSERT_FIELD(ms, MSTATUS_VM, VM_CHOICE); - write_csr(mstatus, ms); - ms = read_csr(mstatus); - - if (EXTRACT_FIELD(ms, MSTATUS_VM) != VM_CHOICE) { - printk(BIOS_DEBUG, "We don't have virtual memory...\n"); - return; - } else { - printk(BIOS_DEBUG, "-----------------------------\n"); - printk(BIOS_DEBUG, "Virtual memory status enabled\n"); - printk(BIOS_DEBUG, "-----------------------------\n"); - } - - // TODO: Figure out how to grab this from cbfs - // N.B. We used to map physical from 0x81000000, - // but since kernels need to be able to see the page tables - // created by firmware, we're going to map from start of RAM. - // All this is subject to change as we learn more. Much - // about RISCV is still in flux. - printk(BIOS_DEBUG, "Initializing virtual memory...\n"); - uintptr_t physicalStart = 0x80000000; - uintptr_t virtualStart = 0xffffffff80000000; - init_vm(virtualStart, physicalStart, (pte_t *)_pagetables); - mb(); - flush_tlb(); - -#if IS_ENABLED(CONFIG_DEBUG_PRINT_PAGE_TABLES) - printk(BIOS_DEBUG, "Finished initializing virtual memory, starting walk...\n"); - print_page_table(); -#else - printk(BIOS_DEBUG, "Finished initializing virtual memory\n"); -#endif -} - void mstatus_init(void) { uintptr_t ms = 0; -- To view, visit https://review.coreboot.org/23772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4e69d15f8ee540d2f98c342bc4ec0c00fb48def0 Gerrit-Change-Number: 23772 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2018