coreboot-gerrit December 2018

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Change in ...coreboot[master]: mb/google/hatch: Add EC trigger events and acpi configs
by Subrata Banik (Code Review) 21 Dec '18

21 Dec '18

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30281 ) Change subject: mb/google/hatch: Add EC trigger events and acpi configs ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/#/c/30281/7/src/mainboard/google/hatch/variants… File src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h: https://review.coreboot.org/#/c/30281/7/src/mainboard/google/hatch/variants… PS7, Line 79: #define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ > Ok, I have created bug 121306806 to track it we can add the required changes in this CL itself and call it out in commit msg https://review.coreboot.org/#/c/coreboot/+/26970/ -- To view, visit https://review.coreboot.org/c/coreboot/+/30281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a86f609c269cb59e546fc7ba4ba032e5ea8341a Gerrit-Change-Number: 30281 Gerrit-PatchSet: 7 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 21 Dec 2018 04:57:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aamir Bohra <aamir.bohra(a)intel.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch: Add SoC and EC asl files in DSDT
by Subrata Banik (Code Review) 21 Dec '18

21 Dec '18

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30282 ) Change subject: mb/google/hatch: Add SoC and EC asl files in DSDT ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/#/c/30282/8/src/mainboard/google/hatch/Kconfig File src/mainboard/google/hatch/Kconfig: https://review.coreboot.org/#/c/30282/8/src/mainboard/google/hatch/Kconfig@… PS8, Line 15: SOC_INTEL_COFFEELAKE > whl boards need to select the cfl soc thats because we don't have any WHL kconfig.. do we know CFL and WHL CPU Ids are same ? if yes then we are good else its not right way -- To view, visit https://review.coreboot.org/c/coreboot/+/30282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf1b1d7e34a7e863139c3583903f3b1e2cdc8da6 Gerrit-Change-Number: 30282 Gerrit-PatchSet: 8 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 21 Dec 2018 04:50:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch: Fixes to initial hatch mainboard checkin
by Subrata Banik (Code Review) 21 Dec '18

21 Dec '18

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30296 ) Change subject: mb/google/hatch: Fixes to initial hatch mainboard checkin ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/#/c/30296/7/src/mainboard/google/hatch/chromeos… File src/mainboard/google/hatch/chromeos.fmd: https://review.coreboot.org/#/c/30296/7/src/mainboard/google/hatch/chromeos… PS7, Line 4: SI_ME u can safely say to avoid having unused section there SI_ME@0x1000 0xFFF000 -- To view, visit https://review.coreboot.org/c/coreboot/+/30296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e311c68873f10f71314e44d3a714639a06dbee8 Gerrit-Change-Number: 30296 Gerrit-PatchSet: 7 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 21 Dec 2018 04:45:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch: Enable H1 TPM support over SPI interface
by Subrata Banik (Code Review) 21 Dec '18

21 Dec '18

Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30210 ) Change subject: mb/google/hatch: Enable H1 TPM support over SPI interface ...................................................................... mb/google/hatch: Enable H1 TPM support over SPI interface Add code support to enable H1 TPM interfaced to SOC on GSPI0. The TPM interrupt is mapped to GPP_C21. BUG=b:120914069 TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot Change-Id: Ib63a0b473f632d91745102ebd01993e8d65b9552 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> Reviewed-on: https://review.coreboot.org/c/30210 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/gpio.c 3 files changed, 71 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 7acfd09..1c0208f 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -10,14 +10,13 @@ select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_HAS_I2C_TPM_CR50 + select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 select SOC_INTEL_CANNONLAKE_MEMCFG_INIT select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK select SOC_INTEL_COFFEELAKE select SPD_READ_BY_WORD select SYSTEM_TYPE_LAPTOP - select TPM2 if BOARD_GOOGLE_BASEBOARD_HATCH @@ -29,6 +28,10 @@ select GBB_FLAG_FORCE_DEV_BOOT_LEGACY select GBB_FLAG_FORCE_MANUAL_RECOVERY +config DEVICETREE + string + default "variants/baseboard/devicetree.cb" + config DIMM_MAX int default 2 @@ -37,6 +40,9 @@ int default 512 +config DRIVER_TPM_SPI_BUS + default 0x1 + config GBB_HWID string depends on CHROMEOS @@ -62,18 +68,18 @@ int default 8 -config VARIANT_DIR - string - default "hatch" if BOARD_GOOGLE_HATCH - -config DEVICETREE - string - default "variants/baseboard/devicetree.cb" - config OVERRIDE_DEVICETREE string default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" if !BOARD_GOOGLE_HATCH +config TPM_TIS_ACPI_INTERRUPT + int + default 53 # GPE0_DW1_21 (GPP_C21) + +config VARIANT_DIR + string + default "hatch" if BOARD_GOOGLE_HATCH + config VBOOT select HAS_RECOVERY_MRC_CACHE select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 88df092..4fe0c4c 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -1,4 +1,31 @@ chip soc/intel/cannonlake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + # DW1 is used by: + # - GPP_C21 - H1_PCH_INT_ODL + register "gpe0_dw0" = "PMC_GPP_A" + register "gpe0_dw1" = "PMC_GPP_C" + register "gpe0_dw2" = "PMC_GPP_D" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + }" + device domain 0 on device pci 00.0 off end # Host Bridge device pci 02.0 off end # Integrated Graphics Device @@ -39,7 +66,14 @@ device pci 1d.4 off end # PCI Express Port 13 (x4) device pci 1e.0 off end # UART #0 device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 + device pci 1e.2 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)" + device spi 0 on end + end + end # GSPI #0 device pci 1e.3 off end # GSPI #1 device pci 1f.0 off end # LPC/eSPI device pci 1f.1 off end # P2SB diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 6f6b9d2..2517a58 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -19,6 +19,16 @@ #include <commonlib/helpers.h> static const struct pad_config gpio_table[] = { + /* H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, INVERT), }; const struct pad_config *__weak variant_gpio_table(size_t *num) @@ -29,6 +39,16 @@ /* GPIOs needed prior to ramstage. */ static const struct pad_config early_gpio_table[] = { + /* H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, INVERT), }; const struct pad_config *__weak variant_early_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/30210 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib63a0b473f632d91745102ebd01993e8d65b9552 Gerrit-Change-Number: 30210 Gerrit-PatchSet: 15 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/google/hatch: Clean up gpio definitions in hatch variant
by Subrata Banik (Code Review) 21 Dec '18

21 Dec '18

Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30291 ) Change subject: mb/google/hatch: Clean up gpio definitions in hatch variant ...................................................................... mb/google/hatch: Clean up gpio definitions in hatch variant This implementation cleans up gpio configuration functions and limit definition to baseboard only for now, until variant specfic overides are needed. BUG=b:120914069 TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot Change-Id: I563f6b97812b32d6e3d99e3df512dc112da78aea Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> Reviewed-on: https://review.coreboot.org/c/30291 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/hatch/ramstage.c M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h D src/mainboard/google/hatch/variants/hatch/Makefile.inc D src/mainboard/google/hatch/variants/hatch/gpio.c 5 files changed, 4 insertions(+), 72 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/hatch/ramstage.c b/src/mainboard/google/hatch/ramstage.c index 1ac6a29..d139eff 100644 --- a/src/mainboard/google/hatch/ramstage.c +++ b/src/mainboard/google/hatch/ramstage.c @@ -24,7 +24,7 @@ const struct pad_config *gpio_table; size_t num_gpios; - gpio_table = variant_base_gpio_table(&num_gpios); + gpio_table = variant_gpio_table(&num_gpios); gpio_configure_pads(gpio_table, num_gpios); } diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index d2efd48..6f6b9d2 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -21,24 +21,17 @@ static const struct pad_config gpio_table[] = { }; -const struct pad_config *__weak variant_base_gpio_table(size_t *num) +const struct pad_config *__weak variant_gpio_table(size_t *num) { *num = ARRAY_SIZE(gpio_table); return gpio_table; } -const struct pad_config *__weak variant_override_gpio_table(size_t *num) -{ - *num = 0; - return NULL; -} - /* GPIOs needed prior to ramstage. */ static const struct pad_config early_gpio_table[] = { }; -const struct pad_config *__weak -variant_early_gpio_table(size_t *num) +const struct pad_config *__weak variant_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h index 18f90488..90a52c0 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h @@ -22,10 +22,8 @@ /* The next set of functions return the gpio table and fill in the number of * entries for each table. */ -const struct pad_config *variant_base_gpio_table(size_t *num); -const struct pad_config *variant_override_gpio_table(size_t *num); +const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); -const struct pad_config *variant_sleep_gpio_table(size_t *num, int slp_typ); /* Return memory SKU for the board. */ size_t variant_memory_sku(void); @@ -33,8 +31,4 @@ /* Return ChromeOS gpio table and fill in number of entries. */ const struct cros_gpio *variant_cros_gpios(size_t *num); -/* Modify devictree settings during ramstage. */ -struct device; -void variant_update_devtree(struct device *dev); - #endif /* BASEBOARD_VARIANTS_H */ diff --git a/src/mainboard/google/hatch/variants/hatch/Makefile.inc b/src/mainboard/google/hatch/variants/hatch/Makefile.inc deleted file mode 100644 index d4d8537..0000000 --- a/src/mainboard/google/hatch/variants/hatch/Makefile.inc +++ /dev/null @@ -1,17 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright 2018 Google LLC -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -bootblock-y += gpio.c -ramstage-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/hatch/gpio.c b/src/mainboard/google/hatch/variants/hatch/gpio.c deleted file mode 100644 index 24535f5..0000000 --- a/src/mainboard/google/hatch/variants/hatch/gpio.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <commonlib/helpers.h> - -/* Pad configuration in ramstage */ -static const struct pad_config gpio_table[] = { -}; - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { -}; - -const struct pad_config *variant_base_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/30291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I563f6b97812b32d6e3d99e3df512dc112da78aea Gerrit-Change-Number: 30291 Gerrit-PatchSet: 6 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/google/hatch: Fixes to initial hatch mainboard checkin
by Shelley Chen (Code Review) 20 Dec '18

20 Dec '18

Hello Subrata Banik, Balaji Manigandan, Aamir Bohra, Rizwan Qureshi, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30296 to look at the new patch set (#7). Change subject: mb/google/hatch: Fixes to initial hatch mainboard checkin ...................................................................... mb/google/hatch: Fixes to initial hatch mainboard checkin Incorporating some feedback to initial hatch mainboard checking (CL:30169) that came in after the CL merged. BUG=b:20914069 BRANCH=None TEST=./util/abuild/abuild -p none -t google/hatch -x -a -v Change-Id: I4e311c68873f10f71314e44d3a714639a06dbee8 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/chromeos.c M src/mainboard/google/hatch/chromeos.fmd M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h D src/mainboard/google/hatch/variants/hatch/overridetree.cb 6 files changed, 17 insertions(+), 96 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/30296/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/30296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e311c68873f10f71314e44d3a714639a06dbee8 Gerrit-Change-Number: 30296 Gerrit-PatchSet: 7 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/broadwell: implement RMRR ACPI table
by Patrick Georgi (Code Review) 20 Dec '18

20 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30234 ) Change subject: soc/intel/broadwell: implement RMRR ACPI table ...................................................................... soc/intel/broadwell: implement RMRR ACPI table Modeled after Skylake implementation; uses duplicated intel common SA functions to get RMRR addresses Test: build/boot purism/librem13v1, observe IOMMU fully functional with intel_iommu=on kernel parameter Change-Id: I1a10a4f91b787b72f33150031b783d426148c25d Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/30234 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/include/soc/systemagent.h M src/soc/intel/broadwell/systemagent.c 3 files changed, 24 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 9c6bd9b..42d31c8 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -590,12 +590,20 @@ /* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */ if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten && !MCHBAR32(GFXVTBAR + 4)) { - const unsigned long tmp = current; + unsigned long tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_drhd_fixup(tmp, current); + + /* Add RMRR entry */ + tmp = current; + + current += acpi_create_dmar_rmrr(current, 0, + sa_get_gsm_base(), sa_get_tolud_base() - 1); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_rmrr_fixup(tmp, current); } /* VTVC0BAR has to be set, enabled, and in 32-bit space */ diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/soc/intel/broadwell/include/soc/systemagent.h index 92e79cc..f414581 100644 --- a/src/soc/intel/broadwell/include/soc/systemagent.h +++ b/src/soc/intel/broadwell/include/soc/systemagent.h @@ -137,4 +137,7 @@ /* System Agent identification */ u8 systemagent_revision(void); +uintptr_t sa_get_tolud_base(void); +uintptr_t sa_get_gsm_base(void); + #endif diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 8013979..e0d8b76 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -36,6 +36,18 @@ return pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID); } +uintptr_t sa_get_tolud_base(void) +{ + /* Bit 0 is lock bit, not part of address */ + return pci_read_config32(SA_DEV_ROOT, TOLUD) & ~1; +} + +uintptr_t sa_get_gsm_base(void) +{ + /* Bit 0 is lock bit, not part of address */ + return pci_read_config32(SA_DEV_ROOT, BGSM) & ~1; +} + static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { -- To view, visit https://review.coreboot.org/c/coreboot/+/30234 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a10a4f91b787b72f33150031b783d426148c25d Gerrit-Change-Number: 30234 Gerrit-PatchSet: 5 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: cpu/intel/common: decouple IA32_FEATURE_CONTROL lock from set_vmx()
by Patrick Georgi (Code Review) 20 Dec '18

20 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30229 ) Change subject: cpu/intel/common: decouple IA32_FEATURE_CONTROL lock from set_vmx() ...................................................................... cpu/intel/common: decouple IA32_FEATURE_CONTROL lock from set_vmx() Newer CPUs/SoCs need to configure other features via the IA32_FEATURE_CONTROL msr, such as SGX, which cannot be done if the msr is already locked. Create separate functions for setting the vmx flag and lock bit, and rename existing function to indicate that the lock bit will be set in addition to vmx flag (per Kconfig). This will allow Skylake/Kabylake (and others?) to use the common VMX code without breaking SGX, while ensuring no change in functionality to existing platforms which current set both together. Test: build/boot each affected platform, ensure no change in functionality Change-Id: Iee772fe87306b4729ca012cef8640d3858e2cb06 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/30229 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/intel/common/Kconfig M src/cpu/intel/common/common.h M src/cpu/intel/common/common_init.c M src/cpu/intel/fsp_model_406dx/model_406dx_init.c M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/intel/model_106cx/model_106cx_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/cpu/intel/model_6ex/model_6ex_init.c M src/cpu/intel/model_6fx/model_6fx_init.c M src/soc/intel/baytrail/cpu.c M src/soc/intel/braswell/cpu.c M src/soc/intel/broadwell/cpu.c 14 files changed, 46 insertions(+), 22 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved David Guckian: Looks good to me, but someone else must approve diff --git a/src/cpu/intel/common/Kconfig b/src/cpu/intel/common/Kconfig index 739333e..56bed22 100644 --- a/src/cpu/intel/common/Kconfig +++ b/src/cpu/intel/common/Kconfig @@ -7,9 +7,8 @@ bool "Enable VMX for virtualization" default y -config SET_VMX_LOCK_BIT - bool "Set lock bit after configuring VMX" - depends on ENABLE_VMX +config SET_IA32_FC_LOCK_BIT + bool "Set IA32_FEATURE_CONTROL lock bit" default y help Although the Intel manual says you must set the lock bit in addition diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h index 81c9f16..b9ac056 100644 --- a/src/cpu/intel/common/common.h +++ b/src/cpu/intel/common/common.h @@ -15,7 +15,9 @@ #ifndef _CPU_INTEL_COMMON_H #define _CPU_INTEL_COMMON_H -void set_vmx(void); +void set_vmx_and_lock(void); +void set_feature_ctrl_vmx(void); +void set_feature_ctrl_lock(void); /* * Init CPPC block with MSRs for Intel Enhanced Speed Step Technology. diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index 7dbbfda..9c0fcbb 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -21,12 +21,17 @@ #include <cpu/x86/msr.h> #include "common.h" -void set_vmx(void) +void set_vmx_and_lock(void) +{ + set_feature_ctrl_vmx(); + set_feature_ctrl_lock(); +} + +void set_feature_ctrl_vmx(void) { msr_t msr; uint32_t feature_flag; int enable = IS_ENABLED(CONFIG_ENABLE_VMX); - int lock = IS_ENABLED(CONFIG_SET_VMX_LOCK_BIT); feature_flag = cpu_get_feature_flags_ecx(); /* Check that the VMX is supported before reading or writing the MSR. */ @@ -38,10 +43,10 @@ msr = rdmsr(IA32_FEATURE_CONTROL); if (msr.lo & (1 << 0)) { - printk(BIOS_ERR, "VMX is locked, so %s will do nothing\n", + printk(BIOS_ERR, "IA32_FEATURE_CONTROL is locked, so %s will do nothing\n", __func__); - /* VMX locked. If we set it again we get an illegal - * instruction + /* IA32_FEATURE_CONTROL locked. If we set it again we get an + * illegal instruction */ return; } @@ -59,14 +64,32 @@ wrmsr(IA32_FEATURE_CONTROL, msr); + printk(BIOS_DEBUG, "VMX status: %s\n", + enable ? "enabled" : "disabled"); +} +void set_feature_ctrl_lock(void) +{ + msr_t msr; + int lock = IS_ENABLED(CONFIG_SET_IA32_FC_LOCK_BIT); + + msr = rdmsr(IA32_FEATURE_CONTROL); + + if (msr.lo & (1 << 0)) { + printk(BIOS_ERR, "IA32_FEATURE_CONTROL is locked, so %s will do nothing\n", + __func__); + /* IA32_FEATURE_CONTROL locked. If we set it again we get an + * illegal instruction + */ + return; + } + if (lock) { /* Set lock bit */ msr.lo |= (1 << 0); wrmsr(IA32_FEATURE_CONTROL, msr); } - printk(BIOS_DEBUG, "VMX status: %s, %s\n", - enable ? "enabled" : "disabled", + printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL status: %s\n", lock ? "locked" : "unlocked"); } diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c index 289305f..7994f0b 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c +++ b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c @@ -148,7 +148,7 @@ setup_lapic(); /* Set virtualization based on Kconfig option */ - set_vmx(); + set_vmx_and_lock(); /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 9d85960..aa77964 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -686,7 +686,7 @@ setup_lapic(); /* Set virtualization based on Kconfig option */ - set_vmx(); + set_vmx_and_lock(); /* Configure C States */ configure_c_states(); diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 7eb121e..dbb9631 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -296,7 +296,7 @@ init_timer(); /* Set virtualization based on Kconfig option */ - set_vmx(); + set_vmx_and_lock(); /* Configure C States */ configure_c_states(quad); diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 56598fa..a609aed 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -99,7 +99,7 @@ setup_lapic(); /* Set virtualization based on Kconfig option */ - set_vmx(); + set_vmx_and_lock(); /* Configure C States */ configure_c_states(); diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index 7ce516b..240bf50 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -333,7 +333,7 @@ setup_lapic(); /* Set virtualization based on Kconfig option */ - set_vmx(); + set_vmx_and_lock(); /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 27f56be..58aabdb 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -556,7 +556,7 @@ setup_lapic(); /* Set virtualization based on Kconfig option */ - set_vmx(); + set_vmx_and_lock(); /* Configure C States */ configure_c_states(); diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 5041dcd..78ece74 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -136,7 +136,7 @@ setup_lapic(); /* Set virtualization based on Kconfig option */ - set_vmx(); + set_vmx_and_lock(); /* Configure C States */ configure_c_states(); diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index c5659f3..9d11478 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -150,7 +150,7 @@ setup_lapic(); /* Set virtualization based on Kconfig option */ - set_vmx(); + set_vmx_and_lock(); /* Configure C States */ configure_c_states(); diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 6c37aa86..9526932 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -57,7 +57,7 @@ enable_turbo(); /* Set virtualization based on Kconfig option */ - set_vmx(); + set_vmx_and_lock(); /* Set core MSRs */ reg_script_run(core_msr_script); diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 9063c2a..12f34fb 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -62,7 +62,7 @@ enable_turbo(); /* Set virtualization based on Kconfig option */ - set_vmx(); + set_vmx_and_lock(); /* Set core MSRs */ reg_script_run(core_msr_script); diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 66ec345..eab6b00 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -581,7 +581,7 @@ setup_lapic(); /* Set virtualization based on Kconfig option */ - set_vmx(); + set_vmx_and_lock(); /* Configure C States */ configure_c_states(); -- To view, visit https://review.coreboot.org/c/coreboot/+/30229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee772fe87306b4729ca012cef8640d3858e2cb06 Gerrit-Change-Number: 30229 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: soc/amd/stoneyridge: Get rid of device_t
by Patrick Georgi (Code Review) 20 Dec '18

20 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30044 ) Change subject: soc/amd/stoneyridge: Get rid of device_t ...................................................................... soc/amd/stoneyridge: Get rid of device_t Use of device_t is deprecated. Change-Id: I6d6dce29591f134f64983387c3b268019d52a602 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/30044 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 88aa7db..7070d97 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -434,7 +434,7 @@ void configure_stoneyridge_i2c(void); void sb_clk_output_48Mhz(void); void sb_disable_4dw_burst(void); -void sb_enable(device_t dev); +void sb_enable(struct device *dev); void southbridge_final(void *chip_info); void southbridge_init(void *chip_info); void sb_lpc_port80(void); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 5aea825..f56123c 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -700,7 +700,7 @@ sb_print_pmxc0_status(); } -void sb_enable(device_t dev) +void sb_enable(struct device *dev) { printk(BIOS_DEBUG, "%s\n", __func__); } -- To view, visit https://review.coreboot.org/c/coreboot/+/30044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d6dce29591f134f64983387c3b268019d52a602 Gerrit-Change-Number: 30044 Gerrit-PatchSet: 9 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: Revert "mb/google/poppy/variants/nocturne: Add DMIC properties to ACP...
by Patrick Georgi (Code Review) 20 Dec '18

20 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30151 ) Change subject: Revert "mb/google/poppy/variants/nocturne: Add DMIC properties to ACPI DSD" ...................................................................... Revert "mb/google/poppy/variants/nocturne: Add DMIC properties to ACPI DSD" This reverts commit 999b916015ea0558e3821bdb51501b43a60b5ed6. The DMIC doesn't have an ACPI id. The patch which enables ACPI device with id DMIC may create conflict in the feature. Also the ACPI id "DMIC" doesn't comply with ACPI naming conventions. The issue for which the patch was introduced, is already addressed in kernel DMIC driver and the patches are upstreamed in to the Linux kernel. Change-Id: I42cb076700dcb5906599471bebfcd5b265b17644 Signed-off-by: Jenny TC <jenny.tc(a)intel.com> Reviewed-on: https://review.coreboot.org/c/30151 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/variants/nocturne/devicetree.cb 2 files changed, 1 insertion(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, but someone else must approve Nick Vaccaro: Looks good to me, approved diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 58c627c..789578f 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -3,7 +3,6 @@ def_bool n select BOARD_ROMSIZE_KB_16384 select DRIVERS_GENERIC_GPIO_KEYS - select DRIVERS_GENERIC_GENERIC select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select EC_GOOGLE_CHROMEEC diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 031c7ff..76b9773 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -468,18 +468,7 @@ end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on - chip drivers/generic/generic - register "hid" = ""DMIC"" - register "name" = ""DMIC"" - register "desc" = ""Generic DMIC"" - register "property_count" = "1" - register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[0].name" = ""modeswitch_delay_ms"" - register "property_list[0].integer" = "35" - device generic 0 on end - end - end # Intel HDA + device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE -- To view, visit https://review.coreboot.org/c/coreboot/+/30151 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42cb076700dcb5906599471bebfcd5b265b17644 Gerrit-Change-Number: 30151 Gerrit-PatchSet: 2 Gerrit-Owner: Jenny Tc <jenny.tc(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jenny Tc <jenny.tc(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit December 2018