Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30281 )
Change subject: mb/google/hatch: Add EC trigger events and acpi configs
......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/#/c/30281/7/src/mainboard/google/hatch/variants…
File src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h:
https://review.coreboot.org/#/c/30281/7/src/mainboard/google/hatch/variants…
PS7, Line 79: SIO_EC_ENABLE_PS2K
> Yes, I think this can be part of this CL since we are enabling ACPI configs for other EC ACPI device […]
i'm okay, even i'm okay to add tablet related flag if this is 2-in 1 design
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V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30296 )
Change subject: mb/google/hatch: Fixes to initial hatch mainboard checkin
......................................................................
Patch Set 8:
(3 comments)
https://review.coreboot.org/#/c/30296/6/src/mainboard/google/hatch/Kconfig
File src/mainboard/google/hatch/Kconfig:
https://review.coreboot.org/#/c/30296/6/src/mainboard/google/hatch/Kconfig@…
PS6, Line 5:
:
:
> Need it now for Trackpad and TPM
Done
https://review.coreboot.org/#/c/30296/7/src/mainboard/google/hatch/chromeos…
File src/mainboard/google/hatch/chromeos.fmd:
https://review.coreboot.org/#/c/30296/7/src/mainboard/google/hatch/chromeos…
PS7, Line 32:
> please adjust the subsequent sections' base and size so as to not leave any unmapped areas
Done
https://review.coreboot.org/#/c/30296/7/src/mainboard/google/hatch/chromeos…
PS7, Line 4: SI_ME
> u can safely say to avoid having unused section there […]
I have set SI_ALL=3MB and aligned the base and sizes.
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V Sowmya has uploaded a new patch set (#8) to the change originally created by Shelley Chen. ( https://review.coreboot.org/c/coreboot/+/30296 )
Change subject: mb/google/hatch: Fixes to initial hatch mainboard checkin
......................................................................
mb/google/hatch: Fixes to initial hatch mainboard checkin
Incorporating some feedback to initial hatch mainboard checking
(CL:30169) that came in after the CL merged.
Updated the chromeos.fmd with the following,
* SI_ALL = 3MB
* SI_BIOS = 16MB
BUG=b:20914069
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/hatch -x -a -v
Change-Id: I4e311c68873f10f71314e44d3a714639a06dbee8
Signed-off-by: Shelley Chen <shchen(a)google.com>
Signed-off-by: V Sowmya <v.sowmya(a)intel.com>
---
M src/mainboard/google/hatch/Kconfig
M src/mainboard/google/hatch/chromeos.c
M src/mainboard/google/hatch/chromeos.fmd
M src/mainboard/google/hatch/variants/baseboard/gpio.c
M src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h
D src/mainboard/google/hatch/variants/hatch/overridetree.cb
6 files changed, 29 insertions(+), 106 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/30296/8
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30047 )
Change subject: src: Get rid of device_t
......................................................................
Patch Set 3: Code-Review+1
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You-Cheng Syu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30351
Change subject: security/vboot: Add new hook function verstage_soc_init
......................................................................
security/vboot: Add new hook function verstage_soc_init
Some SoCs might have some common initialization steps need to be done.
Add a new hook function verstage_soc_init so that we don't have to
duplicate those code again and again for every board.
BRANCH=none
BUG=b:120588396
TEST=manually print some message to console in the new hook function
Change-Id: I31a43ae42f828a9439c03433cba19631b96408ff
Signed-off-by: You-Cheng Syu <youcheng(a)google.com>
---
M src/security/vboot/vboot_common.h
M src/security/vboot/verstage.c
2 files changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/30351/1
diff --git a/src/security/vboot/vboot_common.h b/src/security/vboot/vboot_common.h
index 61f5931..dc8286f 100644
--- a/src/security/vboot/vboot_common.h
+++ b/src/security/vboot/vboot_common.h
@@ -102,6 +102,7 @@
*/
void verstage_main(void);
void verstage_mainboard_init(void);
+void verstage_soc_init(void);
/* Check boot modes */
#if IS_ENABLED(CONFIG_VBOOT)
diff --git a/src/security/vboot/verstage.c b/src/security/vboot/verstage.c
index afd73f1..089ecb5 100644
--- a/src/security/vboot/verstage.c
+++ b/src/security/vboot/verstage.c
@@ -19,6 +19,11 @@
#include <program_loading.h>
#include <security/vboot/vboot_common.h>
+void __weak verstage_soc_init(void)
+{
+ /* Default empty implementation. */
+}
+
void __weak verstage_mainboard_init(void)
{
/* Default empty implementation. */
@@ -28,6 +33,7 @@
{
console_init();
exception_init();
+ verstage_soc_init();
verstage_mainboard_init();
if (IS_ENABLED(CONFIG_VBOOT_RETURN_FROM_VERSTAGE)) {
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Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30281 )
Change subject: mb/google/hatch: Add EC trigger events and acpi configs
......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/#/c/30281/7/src/mainboard/google/hatch/variants…
File src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h:
https://review.coreboot.org/#/c/30281/7/src/mainboard/google/hatch/variants…
PS7, Line 79: * __BASEBOARD_EC_H
> aamir have u added this line to enable PS2 keyboard like DE? […]
Yes, I think this can be part of this CL since we are enabling ACPI configs for other EC ACPI devices(ALS, PD device) also here, I'll update the commit message to highlight the same. Thoughts?
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