coreboot-gerrit December 2018

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Change in ...coreboot[master]: src/soc/intel/skylake/romstage/romstage_fsp20.c: Add weak CAR pre-con...
by Michał Żygowski (Code Review) 21 Dec '18

21 Dec '18

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30358 Change subject: src/soc/intel/skylake/romstage/romstage_fsp20.c: Add weak CAR pre-console init function ...................................................................... src/soc/intel/skylake/romstage/romstage_fsp20.c: Add weak CAR pre-console init function Add weak funtion before console initialization in romstage to allow mainboards initialize SuperIO for serial console for example. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I7a44ad626d97adbd20dee5d13325289c23c176ad --- M src/soc/intel/skylake/include/fsp20/soc/romstage.h M src/soc/intel/skylake/romstage/romstage_fsp20.c 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/30358/1 diff --git a/src/soc/intel/skylake/include/fsp20/soc/romstage.h b/src/soc/intel/skylake/include/fsp20/soc/romstage.h index 364bf52..b7bb604 100644 --- a/src/soc/intel/skylake/include/fsp20/soc/romstage.h +++ b/src/soc/intel/skylake/include/fsp20/soc/romstage.h @@ -20,6 +20,7 @@ #include <fsp/api.h> void mainboard_memory_init_params(FSPM_UPD *mupd); +void car_mainboard_pre_console_init(void); void systemagent_early_init(void); int smbus_read_byte(unsigned int device, unsigned int address); /* Board type */ diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 2a60158..09af24d 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -140,6 +140,7 @@ uintptr_t top_of_ram; struct chipset_power_state *ps; + car_mainboard_pre_console_init(); console_init(); /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ @@ -299,3 +300,8 @@ { /* Do nothing */ } + +__weak void car_mainboard_pre_console_init(void) +{ + /* Do nothing */ +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/30358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a44ad626d97adbd20dee5d13325289c23c176ad Gerrit-Change-Number: 30358 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: mainboard: Add Supermicro X10SLM+-F
by Tristan Corrick (Code Review) 21 Dec '18

21 Dec '18

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30357 Change subject: mainboard: Add Supermicro X10SLM+-F ...................................................................... mainboard: Add Supermicro X10SLM+-F This board runs well with coreboot. The documentation part of this commit lists what works and what doesn't. Tested with GRUB 2.02 as a payload, loading SeaBIOS which then boots FreeBSD 11.2. It has also been tested with GRUB directly booting Debian GNU/Linux 9.6 (kernel 4.9). Change-Id: I291573d4651bdffe24eb841033ea6189fcbf8502 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M Documentation/mainboard/index.md A Documentation/mainboard/supermicro/x10slm-f.md M MAINTAINERS A src/mainboard/supermicro/x10slm-f/Kconfig A src/mainboard/supermicro/x10slm-f/Kconfig.name A src/mainboard/supermicro/x10slm-f/acpi/ec.asl A src/mainboard/supermicro/x10slm-f/acpi/platform.asl A src/mainboard/supermicro/x10slm-f/acpi/superio.asl A src/mainboard/supermicro/x10slm-f/acpi_tables.c A src/mainboard/supermicro/x10slm-f/board_info.txt A src/mainboard/supermicro/x10slm-f/cmos.default A src/mainboard/supermicro/x10slm-f/cmos.layout A src/mainboard/supermicro/x10slm-f/devicetree.cb A src/mainboard/supermicro/x10slm-f/dsdt.asl A src/mainboard/supermicro/x10slm-f/gpio.h A src/mainboard/supermicro/x10slm-f/hda_verb.c A src/mainboard/supermicro/x10slm-f/mainboard.c A src/mainboard/supermicro/x10slm-f/romstage.c 18 files changed, 1,042 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/30357/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index f97e178..4e2b742 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -66,3 +66,7 @@ ## SiFive - [SiFive HiFive Unleashed](sifive/hifive-unleashed.md) + +## Supermicro + +- [X10SLM+-F](supermicro/x10slm-f.md) diff --git a/Documentation/mainboard/supermicro/x10slm-f.md b/Documentation/mainboard/supermicro/x10slm-f.md new file mode 100644 index 0000000..8d03429 --- /dev/null +++ b/Documentation/mainboard/supermicro/x10slm-f.md @@ -0,0 +1,203 @@ +# Supermicro X10SLM+-F + +This section details how to run coreboot on the [Supermicro X10SLM+-F]. + +## Required proprietary blobs + +```eval_rst +Please see :doc:`../../northbridge/intel/haswell/mrc.bin`. +``` + +## Building coreboot + +```eval_rst +If you haven't already, build the coreboot toolchain as described in +:doc:`../../lessons/lesson1`. +``` + +A fully working image should be possible so long as you have the +Haswell `mrc.bin` file. You can set the basic config with the following +commands. However, it is strongly advised to use `make menuconfig` +afterwards (or instead), so that you can see all of the settings. + +```bash +make distclean # Note: this will remove your current config, if it exists. +touch .config +./util/scripts/config --enable VENDOR_SUPERMICRO +./util/scripts/config --enable BOARD_SUPERMICRO_X10SLM_PLUS_F +./util/scripts/config --enable HAVE_MRC +make olddefconfig +``` + +If you don't plan on using coreboot's serial console to collect logs, +you might want to disable it at this point (`./util/scripts/config +--disable CONSOLE_SERIAL`). It should reduce the boot time by several +seconds. However, a more flexible method is to change the console log +level from within an OS using `util/nvramtool`, or with the `nvramcui` +payload. + +Now, run `make` to build the coreboot image. + +## Flashing coreboot + +```eval_rst +In addition to the information here, please see the +:doc:`../../flash_tutorial/index`. +``` + +### Internal programming + +Under the vendor firmware, the BIOS region of the flash chip is +write-protected. Additionally, the vendor flashing tool does not work +with a coreboot image. So, [external programming](#external-programming) +needs to be used when first installing coreboot. By default, coreboot is +not configured to write-protect the BIOS region, so internal programming +can be used thereafter. + +[flashrom] may be used to flash coreboot internally: + +```bash +sudo flashrom -p internal --ifd -i bios --noverify-all -w coreboot.rom +``` + +The use of `--noverify-all` is required since the Management Engine +region is not readable even by the host. + +### External programming + +The main firmware flash chip is an SOIC-8 package located near the CMOS +battery and SATA ports. It should come with a sticker attached that +states the firmware revision (e.g. "X10SLH 4.424"). The chip model is +an N25Q128A, and the datasheet can be found [here][N25Q128A]. + +As with [internal programming](#internal-programming), [flashrom] works +reliably: + +```bash +flashrom -p <your-programmer> --ifd -i bios -w coreboot.rom +``` + +For flashing to work, power to the board should be disconnected (ACPI +G3), and power should be supplied from the external programmer. There is +a diode attached to Vcc, so such flashing should not damage the board. +During testing, a single X10SLM+-F has been flashed dozens of times this +way without issue. + +## BMC (IPMI) + +This board has an ASPEED [AST2400], which has BMC functionality. The +BMC firmware resides in a 32 MiB SOIC-16 chip just above the [AST2400]. +This chip is an MX25L25635F, whose datasheet can be found +[here][MX25L25635F]. + +### Removing the BMC functionality + +The BMC functionality on this board can be removed. If you do not need +its features, removing the BMC functionality might increase security. +This topic has not been widely explored, and you should only **undertake +this process at your own risk.** + +There is a jumper labelled `JPB1` on the board that states the ability +to disable the BMC. Though, pins 1 and 2 are fixed together, keeping +the BMC enabled. It might be possible to disable the BMC by cutting the +connection between pins 1 and 2 (and then connecting pins 2 and 3). This +has not been tested so far. + +Another approach is to erase the entire BMC firmware chip. However, if +this is done, and the board's power cycled, the voltage changes on some +pins of the flash chip, **so it will be harder to flash it again!** + +To remove the firmware, connect an external programmer to the BMC +firmware chip. Vcc should **not** be connected via the external +programmer. The system should be turned off, but the power still +connected (ACPI S5). Then, erase the chip with [flashrom]. Power cycle +the board, and the BMC should no longer be active. + +If you erase the BMC firmware while using the **vendor BIOS**, you +will need to cut the connection between pins 1 and 2 of `JPB1`. The +system will stall for two minutes each time when booting, but it will +eventually start. There is no such delay when running coreboot. + +## ECC DRAM + +```eval_rst +ECC DRAM seems to work, but please see +:doc:`../../northbridge/intel/haswell/mrc.bin` +for caveats. +``` + +## Known issues + +- The x8 PCIe slots do not work, as the Haswell code is missing support. + The code to support it has been written, but it still needs to be + reviewed and merged. + +- Broadwell CPUs are not supported. They might work with minimal changes + to the code, but this has not been tested. + +- The PCH thermal sensor doesn't yet have a driver in coreboot, so it + can't be used for temperature readings. + +- There is no automatic, OS-independent fan control. This is because + the super I/O hardware monitor can only obtain valid CPU temperature + readings from the PECI agent, but the required driver doesn't exist + in coreboot. The `coretemp` driver can still be used for accurate CPU + temperature readings from an OS, and hence the OS can do fan control. + +## Untested + +- TPM +- PCIe x4 slot (it will almost certainly work) +- BMC (IPMI) functionality +- internal serial port +- chassis intrusion header +- SATA DOM header +- standby power header +- serial GPIO headers +- power supply SMBus header +- jumpers not otherwise mentioned +- LEDs + +## Working + +- USB +- S3 suspend/resume +- Gigabit Ethernet +- SATA +- external serial port +- VGA graphics +- disabling VGA graphics using the jumper +- hiding the AST2400 using the CMOS setting +- super I/O hardware monitor (see [Known issues](#known-issues)) +- initialisation with Haswell MRC version 1.6.1 build 2 +- flashrom under coreboot +- Wake-on-LAN +- front panel header +- internal buzzer + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| CPU | :doc:`../../northbridge/intel/haswell/index` | ++------------------+--------------------------------------------------+ +| PCH | Intel Lynx Point (C224) | ++------------------+--------------------------------------------------+ +| Super I/O | Nuvoton NCT6776 | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel SPS (server version of the ME) | ++------------------+--------------------------------------------------+ +| Coprocessor | ASPEED AST2400 | ++------------------+--------------------------------------------------+ +``` + +## Extra links + +- [Board manual] + +[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376 +[Board manual]: https://www.supermicro.com/manuals/motherboard/C224/MNL-1500.pdf +[flashrom]: https://flashrom.org/Flashrom +[MX25L25635F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L25635F.pdf +[N25Q128A]: https://www.micron.com/~/media/Documents/Products/Data%20Sheet/NOR%20Flash/… +[Supermicro X10SLM+-F]: https://www.supermicro.com/products/motherboard/xeon/c220/x10slm_-f.cfm diff --git a/MAINTAINERS b/MAINTAINERS index f90315e..fdecc25 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -378,6 +378,11 @@ F: src/mainboard/siemens/mc_bdx1/ F: src/mainboard/siemens/mc_tcu3/ +SUPERMICRO X10SLM+-F MAINBOARD +M: Tristan Corrick <tristan(a)corrick.kiwi> +S: Maintained +F: src/mainboard/supermicro/x10slm-f/ + AMD FAMILY10H & FAMILY15H (NON-AGESA) CPUS & NORTHBRIDGE M: Timothy Pearson <tpearson(a)raptorengineeringinc.com> S: Supported diff --git a/src/mainboard/supermicro/x10slm-f/Kconfig b/src/mainboard/supermicro/x10slm-f/Kconfig new file mode 100644 index 0000000..6bf0b2a --- /dev/null +++ b/src/mainboard/supermicro/x10slm-f/Kconfig @@ -0,0 +1,59 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_SUPERMICRO_X10SLM_PLUS_F + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select CPU_INTEL_HASWELL + select DRIVERS_ASPEED_AST2050 # Supports AST2400 too. + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6776 + select SUPERIO_NUVOTON_NCT6776_COM_A + select TSC_MONOTONIC_TIMER + +config CBFS_SIZE + hex + default 0xb00000 + +config MAINBOARD_DIR + string + default "supermicro/x10slm-f" + +config MAINBOARD_PART_NUMBER + string + default "X10SLM+-F" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x0803 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x15d9 + +config MAX_CPUS + int + default 8 + +endif diff --git a/src/mainboard/supermicro/x10slm-f/Kconfig.name b/src/mainboard/supermicro/x10slm-f/Kconfig.name new file mode 100644 index 0000000..a1965a3 --- /dev/null +++ b/src/mainboard/supermicro/x10slm-f/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SUPERMICRO_X10SLM_PLUS_F + bool "X10SLM+-F" diff --git a/src/mainboard/supermicro/x10slm-f/acpi/ec.asl b/src/mainboard/supermicro/x10slm-f/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/supermicro/x10slm-f/acpi/ec.asl diff --git a/src/mainboard/supermicro/x10slm-f/acpi/platform.asl b/src/mainboard/supermicro/x10slm-f/acpi/platform.asl new file mode 100644 index 0000000..adaf51a --- /dev/null +++ b/src/mainboard/supermicro/x10slm-f/acpi/platform.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK, 1) +{ + Return (Package() { 0, 0 }) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/supermicro/x10slm-f/acpi/superio.asl b/src/mainboard/supermicro/x10slm-f/acpi/superio.asl new file mode 100644 index 0000000..b12aabd --- /dev/null +++ b/src/mainboard/supermicro/x10slm-f/acpi/superio.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define NCT6776_SHOW_SP1 +#define NCT6776_SHOW_HWM + +#undef NCT6776_SHOW_KBC +#undef NCT6776_SHOW_PP +#undef NCT6776_SHOW_GPIO + +#include <superio/nuvoton/nct6776/acpi/superio.asl> diff --git a/src/mainboard/supermicro/x10slm-f/acpi_tables.c b/src/mainboard/supermicro/x10slm-f/acpi_tables.c new file mode 100644 index 0000000..a43b499 --- /dev/null +++ b/src/mainboard/supermicro/x10slm-f/acpi_tables.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/lynxpoint/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ +} diff --git a/src/mainboard/supermicro/x10slm-f/board_info.txt b/src/mainboard/supermicro/x10slm-f/board_info.txt new file mode 100644 index 0000000..e558429 --- /dev/null +++ b/src/mainboard/supermicro/x10slm-f/board_info.txt @@ -0,0 +1,7 @@ +Category: server +Board URL: https://www.supermicro.com/products/motherboard/xeon/c220/x10slm_-f.cfm +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2013 diff --git a/src/mainboard/supermicro/x10slm-f/cmos.default b/src/mainboard/supermicro/x10slm-f/cmos.default new file mode 100644 index 0000000..f404714 --- /dev/null +++ b/src/mainboard/supermicro/x10slm-f/cmos.default @@ -0,0 +1,5 @@ +boot_option=Fallback +debug_level=Debug +nmi=Enable +power_on_after_fail=Keep +hide_ast2400=Disable diff --git a/src/mainboard/supermicro/x10slm-f/cmos.layout b/src/mainboard/supermicro/x10slm-f/cmos.layout new file mode 100644 index 0000000..cce1f18 --- /dev/null +++ b/src/mainboard/supermicro/x10slm-f/cmos.layout @@ -0,0 +1,97 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 3 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 4 debug_level +#399 1 r 0 unused + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 5 power_on_after_fail + +# coreboot config options: mainboard +416 1 e 1 hide_ast2400 + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable + +2 0 Enable +2 1 Disable + +3 0 Fallback +3 1 Normal + +4 0 Emergency +4 1 Alert +4 2 Critical +4 3 Error +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew + +5 0 Disable +5 1 Enable +5 2 Keep + +# ----------------------------------------------------------------- +checksums + +checksum 392 423 984 diff --git a/src/mainboard/supermicro/x10slm-f/devicetree.cb b/src/mainboard/supermicro/x10slm-f/devicetree.cb new file mode 100644 index 0000000..434fb59 --- /dev/null +++ b/src/mainboard/supermicro/x10slm-f/devicetree.cb @@ -0,0 +1,133 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/haswell + + device cpu_cluster 0 on + chip cpu/intel/haswell + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + + device lapic 0 on end + device lapic 0xacac off end + end + end + + device domain 0 on + subsystemid 0x15d9 0x0803 inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PEG 10 + device pci 01.1 on end # PEG 11 + device pci 02.0 off end # IGD + device pci 03.0 off end # Mini-HD audio + + chip southbridge/intel/lynxpoint + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x8b" + register "pirqd_routing" = "0x8a" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x85" + + register "sata_ahci" = "1" + register "sata_port_map" = "0x3f" + + register "gen1_dec" = "0x00000295" # Super I/O HWM + + device pci 14.0 on end # xHCI controller + device pci 16.0 on end # Management Engine interface 1 + device pci 16.1 on end # Management Engine interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # EHCI controller 2 + device pci 1b.0 off end # HD audio controller + device pci 1c.0 on # PCIe root port 1 + device pci 00.0 on # ASPEED PCI-to-PCI bridge + device pci 00.0 on end # VGA controller + end + end + device pci 1c.1 off end # PCIe root port 2 + device pci 1c.2 on # PCIe root port 3 + device pci 00.0 on # Intel I210 Gigabit Ethernet + subsystemid 0x15d9 0x1533 + end + end + device pci 1c.3 on # PCIe root port 4 + device pci 00.0 on # Intel I210 Gigabit Ethernet + subsystemid 0x15d9 0x1533 + end + end + device pci 1c.4 on end # PCIe root port 5 + device pci 1c.5 off end # PCIe root port 6 + device pci 1c.6 off end # PCIe root port 7 + device pci 1c.7 off end # PCIe root port 8 + device pci 1d.0 on end # EHCI controller 1 + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # UART B + io 0x60 = 0x02f8 + irq 0x70 = 3 + end + device pnp 2e.5 off end # PS/2 KBC + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO8 + device pnp 2e.107 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO0 + device pnp 2e.208 off end # GPIOA + device pnp 2e.308 off end # GPIO base + device pnp 2e.109 off end # GPIO1 + device pnp 2e.209 off end # GPIO2 + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 off end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 off end # GPIO7 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep sleep + device pnp 2e.17 off end # GPIOA + end + end + device pci 1f.2 on end # SATA controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA controller 2 + device pci 1f.6 on end # PCH thermal sensor + end + end +end diff --git a/src/mainboard/supermicro/x10slm-f/dsdt.asl b/src/mainboard/supermicro/x10slm-f/dsdt.asl new file mode 100644 index 0000000..3a587b6 --- /dev/null +++ b/src/mainboard/supermicro/x10slm-f/dsdt.asl @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> + +DefinitionBlock("dsdt.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 0x20181220) +{ + #include "acpi/platform.asl" + #include <southbridge/intel/lynxpoint/acpi/platform.asl> + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } +} diff --git a/src/mainboard/supermicro/x10slm-f/gpio.h b/src/mainboard/supermicro/x10slm-f/gpio.h new file mode 100644 index 0000000..95a09b9 --- /dev/null +++ b/src/mainboard/supermicro/x10slm-f/gpio.h @@ -0,0 +1,220 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERMICRO_X10SLM_PLUS_F_GPIO_H +#define SUPERMICRO_X10SLM_PLUS_F_GPIO_H + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_OUTPUT, + .gpio2 = GPIO_DIR_OUTPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_OUTPUT, + .gpio7 = GPIO_DIR_OUTPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_HIGH, + .gpio1 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio7 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_HIGH, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio3 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio59 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio36 = GPIO_LEVEL_HIGH, + .gpio37 = GPIO_LEVEL_HIGH, + .gpio47 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio73 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio72 = GPIO_LEVEL_HIGH, + .gpio73 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; + +#endif /* SUPERMICRO_X10SLM_PLUS_F_GPIO_H */ diff --git a/src/mainboard/supermicro/x10slm-f/hda_verb.c b/src/mainboard/supermicro/x10slm-f/hda_verb.c new file mode 100644 index 0000000..0944532 --- /dev/null +++ b/src/mainboard/supermicro/x10slm-f/hda_verb.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = {}; +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/supermicro/x10slm-f/mainboard.c b/src/mainboard/supermicro/x10slm-f/mainboard.c new file mode 100644 index 0000000..8d0e3b0 --- /dev/null +++ b/src/mainboard/supermicro/x10slm-f/mainboard.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <option.h> +#include <stdint.h> +#include <types.h> + +/* + * Hiding the AST2400 might be desirable to reduce attack surface. + * + * The PCIe root port that the AST2400 is on is disabled, but the + * AST2400 itself likely remains in an enabled state. + * + * The AST2400 is also attached to the LPC. That interface does not get + * disabled. + */ +static void hide_ast2400(void) +{ + struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1c, 0)); + if (!dev) + return; + + /* + * Marking this device as disabled means that the southbridge code + * will properly disable the root port when it configures it later. + */ + dev->enabled = 0; + printk(BIOS_INFO, "The AST2400 is now set to be hidden.\n"); +} + +static void mainboard_enable(struct device *dev) +{ + u8 hide = 0; + + if (get_option(&hide, "hide_ast2400") == CB_SUCCESS && hide) + hide_ast2400(); +} + +struct chip_operations mainboard_ops = { + CHIP_NAME("X10SLM+-F") + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c new file mode 100644 index 0000000..3707290 --- /dev/null +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/intel/haswell/haswell.h> +#include <cpu/intel/romstage.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/pei_data.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <stdint.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> +#include "gpio.h" + +static const struct rcba_config_instruction rcba_config[] = { + RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), + RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)), + RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), + RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)), + RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)), + RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), + RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), + RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), + + RCBA_RMW_REG_32(FD, ~0UL, PCH_DISABLE_ALWAYS), + + RCBA_END_CONFIG, +}; + +void mainboard_config_superio(void) +{ + const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0); + const pnp_devfn_t SERIAL_DEV = PNP_DEV(0x2e, NCT6776_SP1); + const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI); + + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV); + + /* Select HWM/LED functions instead of floppy functions. */ + pnp_write_config(GLOBAL_PSEUDO_DEV, 0x1c, 0x03); + pnp_write_config(GLOBAL_PSEUDO_DEV, 0x24, 0x24); + + /* Power RAM in S3 and let the PCH handle power failure actions. */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x70); + + nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV); +} + +void mainboard_romstage_entry(unsigned long bist) +{ + struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = DEFAULT_PCIEXBAR, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = HPET_ADDR, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .system_type = 1, /* desktop/server */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, + .ec_present = 0, + .ddr_refresh_2x = 1, + .max_ddr3_freq = 1600, + .usb2_ports = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_INTERNAL }, + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, + { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, + { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + }, + .usb3_ports = { + /* Enable, OCn# */ + { 1, 1 }, + { 1, 1 }, + { 0, USB_OC_PIN_SKIP }, + { 0, USB_OC_PIN_SKIP }, + { 1, 3 }, + { 1, 3 }, + }, + }; + + struct romstage_params romstage_params = { + .pei_data = &pei_data, + .gpio_map = &mainboard_gpio_map, + .rcba_config = rcba_config, + .bist = bist, + }; + + romstage_common(&romstage_params); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/30357 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I291573d4651bdffe24eb841033ea6189fcbf8502 Gerrit-Change-Number: 30357 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Documentation/nb/intel: Add Haswell documentation
by Tristan Corrick (Code Review) 21 Dec '18

21 Dec '18

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30356 Change subject: Documentation/nb/intel: Add Haswell documentation ...................................................................... Documentation/nb/intel: Add Haswell documentation At the moment, this just gives some details on the MRC. Change-Id: I84e8ca2543b2e19b84a24f7d7032a4aedb6e9272 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M Documentation/mainboard/asrock/h81m-hds.md A Documentation/northbridge/intel/haswell/index.md A Documentation/northbridge/intel/haswell/mrc.bin.md M Documentation/northbridge/intel/index.md 4 files changed, 46 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/30356/1 diff --git a/Documentation/mainboard/asrock/h81m-hds.md b/Documentation/mainboard/asrock/h81m-hds.md index 0338aa1..460af8f 100644 --- a/Documentation/mainboard/asrock/h81m-hds.md +++ b/Documentation/mainboard/asrock/h81m-hds.md @@ -4,24 +4,10 @@ ## Required proprietary blobs -This board currently requires a proprietary blob in order to initialise -the RAM and a few other components. The blob largely consists of Intel's -Memory Reference Code (shortened to mrc), and is just under 200 KiB -in size. It is also known as a system agent binary. Unfortunately, -it is not currently possible to distribute this as part of coreboot. -However, the mrc can be obtained from a Haswell Chromebook firmware -image, and you might find one online. The mrc from a ChromeOS image can -be extracted with the following command. If extracting from a "standard" -coreboot image, omit `-r RO_SECTION`. - -```bash -cbfstool coreboot.rom extract -f mrc.bin -n mrc.bin -r RO_SECTION +```eval_rst +Please see :doc:`../../northbridge/intel/haswell/mrc.bin`. ``` -Now, place mrc.bin in the root of the coreboot directory. -Alternatively, place it anywhere you want, and set `MRC_FILE` to its -location when building coreboot. - ## Building coreboot A fully working image should be possible just by setting your MAC diff --git a/Documentation/northbridge/intel/haswell/index.md b/Documentation/northbridge/intel/haswell/index.md new file mode 100644 index 0000000..3eb8059 --- /dev/null +++ b/Documentation/northbridge/intel/haswell/index.md @@ -0,0 +1,8 @@ +# Intel Haswell documentation + +This section describes the Intel Haswell architecture as it relates to +coreboot. + +## Proprietary blobs + +- [mrc.bin](mrc.bin.md) diff --git a/Documentation/northbridge/intel/haswell/mrc.bin.md b/Documentation/northbridge/intel/haswell/mrc.bin.md new file mode 100644 index 0000000..e27e9d6 --- /dev/null +++ b/Documentation/northbridge/intel/haswell/mrc.bin.md @@ -0,0 +1,35 @@ +# mrc.bin + +All Haswell boards supported by coreboot currently require a proprietary +blob in order to initialise the DRAM and a few other components. The +blob, named `mrc.bin`, largely consists of Intel's memory reference code +(MRC), but it has been tailored specifically for Chrome OS. It is just +under 200 KiB in size. Another name for `mrc.bin` is the system agent +binary. + +Having a replacement for `mrc.bin` using native coreboot code is very +much desired, but it is not an easy task. + +## Obtaining mrc.bin + +Unfortunately, it is not currently possible to distribute `mrc.bin` as +part of coreboot. Though, it can be obtained from a Haswell Chromebook +or Chromebox firmware image, and you might find one online. `mrc.bin` +can be extracted with the following command. If extracting from a +"standard" coreboot image, omit `-r RO_SECTION`. + +```bash +cbfstool coreboot.rom extract -f mrc.bin -n mrc.bin -r RO_SECTION +``` + +Now, place `mrc.bin` in the root of the coreboot directory. +Alternatively, place `mrc.bin` anywhere you want, and set `MRC_FILE` to +its location when building coreboot. + +## ECC DRAM + +When `mrc.bin` has finished executing, ECC is active on the channels +populated with ECC DIMMs. However, `mrc.bin` was tailored specifically +for Haswell Chromebooks and Chomeboxes, none of which support ECC DRAM. +While ECC likely functions correctly, it is advised to further validate +the correct operation of ECC if data integrity is absolutely critical. diff --git a/Documentation/northbridge/intel/index.md b/Documentation/northbridge/intel/index.md index 6cca1da..da7634b 100644 --- a/Documentation/northbridge/intel/index.md +++ b/Documentation/northbridge/intel/index.md @@ -4,4 +4,5 @@ ## Platforms +- [Haswell](haswell/index.md) - [Sandy Bridge](sandybridge/index.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/30356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84e8ca2543b2e19b84a24f7d7032a4aedb6e9272 Gerrit-Change-Number: 30356 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/aspeed/ast: Select `MAINBOARD_HAS_NATIVE_VGA_INIT`
by Tristan Corrick (Code Review) 21 Dec '18

21 Dec '18

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30355 Change subject: drivers/aspeed/ast: Select `MAINBOARD_HAS_NATIVE_VGA_INIT` ...................................................................... drivers/aspeed/ast: Select `MAINBOARD_HAS_NATIVE_VGA_INIT` Any board that uses the AST driver will have support for native graphics init. So, select the option in the driver instead of every board. Change-Id: I2bf42c168d1ffdda11857854889b74953abd7e40 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/drivers/aspeed/ast2050/Kconfig M src/mainboard/asus/kcma-d8/Kconfig M src/mainboard/asus/kgpe-d16/Kconfig 3 files changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/30355/1 diff --git a/src/drivers/aspeed/ast2050/Kconfig b/src/drivers/aspeed/ast2050/Kconfig index 715def8..337b181 100644 --- a/src/drivers/aspeed/ast2050/Kconfig +++ b/src/drivers/aspeed/ast2050/Kconfig @@ -2,3 +2,4 @@ bool select DRIVERS_ASPEED_AST_COMMON select HAVE_VGA_TEXT_FRAMEBUFFER + select MAINBOARD_HAS_NATIVE_VGA_INIT diff --git a/src/mainboard/asus/kcma-d8/Kconfig b/src/mainboard/asus/kcma-d8/Kconfig index 229b5ac..7d66707 100644 --- a/src/mainboard/asus/kcma-d8/Kconfig +++ b/src/mainboard/asus/kcma-d8/Kconfig @@ -31,7 +31,6 @@ select DRIVERS_I2C_W83795 select DRIVERS_ASPEED_AST2050 select MAINBOARD_FORCE_NATIVE_VGA_INIT - select MAINBOARD_HAS_NATIVE_VGA_INIT config MAINBOARD_DIR string diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig index d87d926..efdade8 100644 --- a/src/mainboard/asus/kgpe-d16/Kconfig +++ b/src/mainboard/asus/kgpe-d16/Kconfig @@ -32,7 +32,6 @@ select DRIVERS_I2C_W83795 select DRIVERS_ASPEED_AST2050 select MAINBOARD_FORCE_NATIVE_VGA_INIT - select MAINBOARD_HAS_NATIVE_VGA_INIT config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/30355 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2bf42c168d1ffdda11857854889b74953abd7e40 Gerrit-Change-Number: 30355 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/mainboard/pcengines/apu1: Enable LPC TPM
by Michał Żygowski (Code Review) 21 Dec '18

21 Dec '18

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30354 Change subject: src/mainboard/pcengines/apu1: Enable LPC TPM ...................................................................... src/mainboard/pcengines/apu1: Enable LPC TPM PC Engines apu1 has a 20 pin LPC header that allows connection of external TPM module. Add necessary Kconfig option and devicetree entry for TPM. Change-Id: Ic9f3d41c6e8346a12553386b9c00de6b8fd21abd Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/mainboard/pcengines/apu1/Kconfig M src/mainboard/pcengines/apu1/devicetree.cb 2 files changed, 32 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/30354/1 diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index 9d42159..07aaa8c 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -31,6 +31,7 @@ select BOARD_ROMSIZE_KB_2048 select GENERIC_SPD_BIN select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS + select MAINBOARD_HAS_LPC_TPM config MAINBOARD_DIR string diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb index 72e89c0..acdabd1 100644 --- a/src/mainboard/pcengines/apu1/devicetree.cb +++ b/src/mainboard/pcengines/apu1/devicetree.cb @@ -43,35 +43,38 @@ device pci 14.1 off end # IDE 0x439c device pci 14.2 off end # HDA 0x4383 device pci 14.3 on # LPC 0x439d - chip superio/nuvoton/nct5104d - register "irq_trigger_type" = "0" - device pnp 2e.0 off end - device pnp 2e.2 on - io 0x60 = 0x3f8 - irq 0x70 = 4 + chip superio/nuvoton/nct5104d + register "irq_trigger_type" = "0" + device pnp 2e.0 off end + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.10 off + # UART C is conditionally turned on + io 0x60 = 0x3e8 + irq 0x70 = 4 + end + device pnp 2e.11 off + # UART D is conditionally turned on + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 2e.8 off end + device pnp 2e.f off end + # GPIO0 and GPIO1 are conditionally turned on + device pnp 2e.007 off end + device pnp 2e.107 off end + device pnp 2e.607 off end + device pnp 2e.e off end end - device pnp 2e.3 on - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.10 off - # UART C is conditionally turned on - io 0x60 = 0x3e8 - irq 0x70 = 4 - end - device pnp 2e.11 off - # UART D is conditionally turned on - io 0x60 = 0x2e8 - irq 0x70 = 3 - end - device pnp 2e.8 off end - device pnp 2e.f off end - # GPIO0 and GPIO1 are conditionally turned on - device pnp 2e.007 off end - device pnp 2e.107 off end - device pnp 2e.607 off end - device pnp 2e.e off end - end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end # LPC TPM end #LPC device pci 14.4 on end # PCIB 0x4384 always active; pins remapped to gpio by disconnect_pcib = 1 device pci 14.5 off end # OHCI FS/LS USB -- To view, visit https://review.coreboot.org/c/coreboot/+/30354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9f3d41c6e8346a12553386b9c00de6b8fd21abd Gerrit-Change-Number: 30354 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: crossgcc: Update IASL and EXPAT versions
by HAOUAS Elyes (Code Review) 21 Dec '18

21 Dec '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30313 to look at the new patch set (#4). Change subject: crossgcc: Update IASL and EXPAT versions ...................................................................... crossgcc: Update IASL and EXPAT versions Update: * IASL to version 20181213 changes in this version: https://acpica.org/node/163 * EXPAT to version 2.2.6: changes in this version: https://github.com/libexpat/libexpat/blob/R_2_2_6/expat/Changes Change-Id: Ib67cf26497a0c2c2a364741675b13e4ce0190e41 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc R util/crossgcc/patches/acpica-unix2-20181213_iasl.patch D util/crossgcc/sum/acpica-unix2-20181003.tar.gz.cksum A util/crossgcc/sum/acpica-unix2-20181213.tar.gz.cksum D util/crossgcc/sum/expat-2.2.5.tar.bz2.cksum A util/crossgcc/sum/expat-2.2.6.tar.bz2.cksum 6 files changed, 15 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/30313/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/30313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib67cf26497a0c2c2a364741675b13e4ce0190e41 Gerrit-Change-Number: 30313 Gerrit-PatchSet: 4 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/fsp_broadwell_de/acpi: Fix wrong table checksum
by Patrick Rudolph (Code Review) 21 Dec '18

21 Dec '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30353 Change subject: soc/intel/fsp_broadwell_de/acpi: Fix wrong table checksum ...................................................................... soc/intel/fsp_broadwell_de/acpi: Fix wrong table checksum Fix the following warning shown in dmesg: "ACPI BIOS Warning (bug): Incorrect checksum in table [FACP]" The table checksum was wrong as it was calculated twice and with the second time the checksum field wasn't set to zero. Change-Id: I375354bf3e95ebdac3b0dad43659d72c6ab3175a Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/fsp_broadwell_de/acpi.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/30353/1 diff --git a/src/soc/intel/fsp_broadwell_de/acpi.c b/src/soc/intel/fsp_broadwell_de/acpi.c index 15ea5ec..728850d 100644 --- a/src/soc/intel/fsp_broadwell_de/acpi.c +++ b/src/soc/intel/fsp_broadwell_de/acpi.c @@ -309,8 +309,6 @@ fadt->x_gpe1_blk.access_size = 0; fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; fadt->x_gpe1_blk.addrh = 0x00; - - header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); } static unsigned long acpi_fill_dmar(unsigned long current) -- To view, visit https://review.coreboot.org/c/coreboot/+/30353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I375354bf3e95ebdac3b0dad43659d72c6ab3175a Gerrit-Change-Number: 30353 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: 3rdparty/blobs: Update for current Intel microcode
by Martin Kepplinger (Code Review) 21 Dec '18

21 Dec '18

Martin Kepplinger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30081 ) Change subject: 3rdparty/blobs: Update for current Intel microcode ...................................................................... Patch Set 2: Hey, why wasn't this included for the 4.9 release? This is quite a reasonable and important update. Was this overlooked or are there serious objections, despite already merged in the blobs repo? thanks! Anyways, 4.10 isn't that far away :) -- To view, visit https://review.coreboot.org/c/coreboot/+/30081 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09a41a8269cfdf8953bac10c9630922192851e73 Gerrit-Change-Number: 30081 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Kepplinger <martink(a)posteo.de> Gerrit-Comment-Date: Fri, 21 Dec 2018 10:04:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch: Fixes to initial hatch mainboard checkin
by Aamir Bohra (Code Review) 21 Dec '18

21 Dec '18

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30296 ) Change subject: mb/google/hatch: Fixes to initial hatch mainboard checkin ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/#/c/30296/8/src/mainboard/google/hatch/variants… File src/mainboard/google/hatch/variants/baseboard/gpio.c: https://review.coreboot.org/#/c/30296/8/src/mainboard/google/hatch/variants… PS8, Line 30: /* H1_PCH_INT_ODL */ : PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, INVERT), : /* PCH_WP_OD */ : PAD_CFG_GPI(GPP_C20, NONE, DEEP), : /* EC_IN_RW_OD */ : PAD_CFG_GPI(GPP_C22, NONE, DEEP), : }; order? -- To view, visit https://review.coreboot.org/c/coreboot/+/30296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e311c68873f10f71314e44d3a714639a06dbee8 Gerrit-Change-Number: 30296 Gerrit-PatchSet: 8 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 21 Dec 2018 09:51:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch: Fixes to initial hatch mainboard checkin
by Subrata Banik (Code Review) 21 Dec '18

21 Dec '18

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30296 ) Change subject: mb/google/hatch: Fixes to initial hatch mainboard checkin ...................................................................... Patch Set 8: Code-Review+1 Just want to double confirm if image can be opened using FIT -- To view, visit https://review.coreboot.org/c/coreboot/+/30296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e311c68873f10f71314e44d3a714639a06dbee8 Gerrit-Change-Number: 30296 Gerrit-PatchSet: 8 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 21 Dec 2018 09:28:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2018