HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30046 )
Change subject: src/northbridge: Get rid of device_t
......................................................................
Patch Set 3:
> Would it possible to add a checkpatch rule to prevent new
> occurrences of device_t ?
or maybe review/merge the 2 remaining changes, this way, Jenkins will not be happy if some one use device_t.
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EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30350 )
Change subject: mb/google/sarien: Disable pcie interface for wwan
......................................................................
Patch Set 1: Code-Review+1
It worked at Taipei side.
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HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30046 )
Change subject: src/northbridge: Get rid of device_t
......................................................................
Patch Set 3:
Would it possible to add a checkpatch rule to prevent new occurrences of device_t ?
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Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30282 )
Change subject: mb/google/hatch: Add SoC and EC asl files in DSDT
......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/#/c/30282/8/src/mainboard/google/hatch/Kconfig
File src/mainboard/google/hatch/Kconfig:
https://review.coreboot.org/#/c/30282/8/src/mainboard/google/hatch/Kconfig@…
PS8, Line 15: SOC_INTEL_COFFEELAKE
> thats because we don't have any WHL kconfig.. […]
Yes. The CPU IDs are not same, some of the PCH Ips are same and for rest support id added here:
https://review.coreboot.org/c/coreboot/+/27519https://review.coreboot.org/c/coreboot/+/28111
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Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30350
Change subject: mb/google/sarien: Disable pcie interface for wwan
......................................................................
mb/google/sarien: Disable pcie interface for wwan
WWAN chip support 3 interfaces as pci express, USB 2.0 and USB 3.0, the
usgae of Sarien choose to only use USB interface but not over pci
express, so totally disable pci express root port 12.
BUG=b:1246720
TEST=Boot up into OS with WWAN attached, cold boot and warm boot 10
cyles can still device can be listed under lsusb.
Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com>
Change-Id: Ic4da393c0c0d903848111e1c037c2730c86afa7d
---
M src/mainboard/google/sarien/variants/arcada/devicetree.cb
M src/mainboard/google/sarien/variants/sarien/devicetree.cb
2 files changed, 2 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/30350/1
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index a8bb342..52840de 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -86,11 +86,6 @@
register "PcieClkSrcUsage[1]" = "10"
register "PcieClkSrcClkReq[1]" = "1"
- # PCIe port 12 for M.2 3042
- register "PcieRpEnable[11]" = "1"
- register "PcieClkSrcUsage[3]" = "11"
- register "PcieClkSrcClkReq[3]" = "3"
-
# PCIe port 13 for M.2 2280 SSD
register "PcieRpEnable[12]" = "1"
register "PcieClkSrcUsage[4]" = "12"
@@ -240,7 +235,7 @@
device pci 1d.0 on end # PCI Express Port 9
device pci 1d.1 on end # PCI Express Port 10
device pci 1d.2 on end # PCI Express Port 11
- device pci 1d.3 on end # PCI Express Port 12
+ device pci 1d.3 off end # PCI Express Port 12
device pci 1d.4 on end # PCI Express Port 13 (x4)
device pci 1e.0 off end # UART #0
device pci 1e.1 off end # UART #1
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index c24cd02..47abadc 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -95,11 +95,6 @@
register "PcieClkSrcUsage[1]" = "9"
register "PcieClkSrcClkReq[1]" = "1"
- # PCIe port 12 for M.2 3042
- register "PcieRpEnable[11]" = "1"
- register "PcieClkSrcUsage[0]" = "11"
- register "PcieClkSrcClkReq[0]" = "0"
-
# PCIe port 13 for M.2 2280 SSD
register "PcieRpEnable[12]" = "1"
register "PcieClkSrcUsage[2]" = "12"
@@ -259,7 +254,7 @@
device pci 1d.0 on end # PCI Express Port 9
device pci 1d.1 on end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
- device pci 1d.3 on end # PCI Express Port 12
+ device pci 1d.3 off end # PCI Express Port 12
device pci 1d.4 on end # PCI Express Port 13 (x4)
device pci 1e.0 off end # UART #0
device pci 1e.1 off end # UART #1
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