November 2018 - coreboot-gerrit

Change in ...coreboot[master]: arch/x86/Kconfig: move MAX_REBOOT_CNT option
by Nico Huber (Code Review) 01 Dec '18

01 Dec '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29979 ) Change subject: arch/x86/Kconfig: move MAX_REBOOT_CNT option ...................................................................... Patch Set 2: (1 comment) Currently, you can't set wrong values. That's a feature I'd like to have maintained. Everything below the currently defined defaults is wrong. In other words, this option was hidden on purpose. You can add another option for instance and take the minimum of both or something like that. But you mustn't lower it. https://review.coreboot.org/#/c/29979/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29979/1//COMMIT_MSG@11 PS1, Line 11: > It only adds the entry, so you don't have to change it in the config file by hand. […] It's not about complete reboots. If you'd set it to 2 you might get false fallbacks (because a single reboot can result in coreboot resetting again, without anything failing). -- To view, visit https://review.coreboot.org/c/coreboot/+/29979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice26e2ef349f1172b564edc14f1012c33546a93c Gerrit-Change-Number: 29979 Gerrit-PatchSet: 2 Gerrit-Owner: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-Reviewer: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Fri, 30 Nov 2018 23:59:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Program HD Audio SVID/SSID
by Lijian Zhao (Code Review) 01 Dec '18

01 Dec '18

Hello Jairaj Arava, Patrick Rudolph, Pratikkumar V Prajapati, Subrata Banik, Sathyanarayana Nujella, build bot (Jenkins), Krzysztof M Sywula, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29651 to look at the new patch set (#5). Change subject: soc/intel/cannonlake: Program HD Audio SVID/SSID ...................................................................... soc/intel/cannonlake: Program HD Audio SVID/SSID Realtek Codec kernel driver requires PCH HD Audio controller to have subystem vendor id and subsystem device id matched with verb table. So program same values to make it working. BUG=b:119058355,b:119054586 TEST=Boot up on Sarien board and check with kernel driver dmesg to see ALC3204 or ALC3254. Change-Id: I25e22313fd99479f1a2f68636a2eab83126ca488 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/fsp_params.c A src/soc/intel/cannonlake/include/soc/hda_ssid.h 3 files changed, 65 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/29651/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/29651 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25e22313fd99479f1a2f68636a2eab83126ca488 Gerrit-Change-Number: 29651 Gerrit-PatchSet: 5 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/cannonlake: Program HD Audio SVID/SSID
by Nico Huber (Code Review) 01 Dec '18

01 Dec '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29651 ) Change subject: soc/intel/cannonlake: Program HD Audio SVID/SSID ...................................................................... Patch Set 3: Is this just setting subsystem ids of a PCI device? These should be set in the devicetree and no blob needed. If yes, this seems backwards. Shouldn't we set the id of the PCI device first and when configuring the codec take the id of the PCI device? -- To view, visit https://review.coreboot.org/c/coreboot/+/29651 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25e22313fd99479f1a2f68636a2eab83126ca488 Gerrit-Change-Number: 29651 Gerrit-PatchSet: 3 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Fri, 30 Nov 2018 23:49:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Program HD Audio SVID/SSID
by Lijian Zhao (Code Review) 01 Dec '18

01 Dec '18

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29651 ) Change subject: soc/intel/cannonlake: Program HD Audio SVID/SSID ...................................................................... Patch Set 4: > Patch Set 1: > > Could we do this at the SOC level? > > If we had a Kconfig entry in the SOC that allowed the mainboard to define an HDA codec device ID then the SOC level code could have this structure (filled with CONFIG_SUBSYSTEM_VENDOR_ID and something like CONFIG_HDA_CODEC_ID) and pass it to FSP if HDA is enabled. Done, moved to SOC level and add HDA_CODEC_ID -- To view, visit https://review.coreboot.org/c/coreboot/+/29651 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25e22313fd99479f1a2f68636a2eab83126ca488 Gerrit-Change-Number: 29651 Gerrit-PatchSet: 4 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 23:49:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Program HD Audio SVID/SSID
by Lijian Zhao (Code Review) 01 Dec '18

01 Dec '18

Hello Jairaj Arava, Patrick Rudolph, Pratikkumar V Prajapati, Subrata Banik, Sathyanarayana Nujella, build bot (Jenkins), Krzysztof M Sywula, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29651 to look at the new patch set (#4). Change subject: soc/intel/cannonlake: Program HD Audio SVID/SSID ...................................................................... soc/intel/cannonlake: Program HD Audio SVID/SSID Realtek Codec kernel driver requires PCH HD Audio controller to have subystem vendor id and subsystem device id matched with verb table. So program same values to make it working. BUG=b:119058355,b:119054586 TEST=Boot up on Sarien board and check with kernel driver dmesg to see ALC3204 or ALC3254. Change-Id: I25e22313fd99479f1a2f68636a2eab83126ca488 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/fsp_params.c A src/soc/intel/cannonlake/include/soc/hda_ssid.h 3 files changed, 65 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/29651/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/29651 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25e22313fd99479f1a2f68636a2eab83126ca488 Gerrit-Change-Number: 29651 Gerrit-PatchSet: 4 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/cannonlake: Program HD Audio SVID/SSID
by Lijian Zhao (Code Review) 01 Dec '18

01 Dec '18

Hello Jairaj Arava, Patrick Rudolph, Pratikkumar V Prajapati, Subrata Banik, Sathyanarayana Nujella, build bot (Jenkins), Krzysztof M Sywula, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29651 to look at the new patch set (#3). Change subject: soc/intel/cannonlake: Program HD Audio SVID/SSID ...................................................................... soc/intel/cannonlake: Program HD Audio SVID/SSID Realtek Codec kernel driver requires PCH HD Audio controller to have subystem vendor id and subsystem device id matched with verb table. So program same values to make it working. BUG=b:119058355,b:119054586 TEST=Boot up on Sarien board and check with kernel driver dmesg to see ALC3204 or ALC3254. Change-Id: I25e22313fd99479f1a2f68636a2eab83126ca488 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/fsp_params.c A src/soc/intel/cannonlake/include/soc/hda_ssid.h 3 files changed, 62 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/29651/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/29651 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25e22313fd99479f1a2f68636a2eab83126ca488 Gerrit-Change-Number: 29651 Gerrit-PatchSet: 3 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/cannonlake: Program HD Audio SVID/SSID
by Lijian Zhao (Code Review) 01 Dec '18

01 Dec '18

Hello Jairaj Arava, Pratikkumar V Prajapati, Subrata Banik, Sathyanarayana Nujella, build bot (Jenkins), Krzysztof M Sywula, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29651 to look at the new patch set (#2). Change subject: soc/intel/cannonlake: Program HD Audio SVID/SSID ...................................................................... soc/intel/cannonlake: Program HD Audio SVID/SSID Realtek Codec kernel driver requires PCH HD Audio controller to have subystem vendor id and subsystem device id matched with verb table. So program same values to make it working. BUG=b:119058355,b:119054586 TEST=Boot up on Sarien board and check with kernel driver dmesg to see ALC3204 or ALC3254. Change-Id: I25e22313fd99479f1a2f68636a2eab83126ca488 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/google/sarien/ramstage.c M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/fsp_params.c A src/soc/intel/cannonlake/include/soc/hda_ssid.h 4 files changed, 63 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/29651/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29651 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25e22313fd99479f1a2f68636a2eab83126ca488 Gerrit-Change-Number: 29651 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/google/{zoombini, sarien}: Use common CPU ACPI code
by Duncan Laurie (Code Review) 30 Nov '18

30 Nov '18

Duncan Laurie has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29755 ) Change subject: mb/google/{zoombini,sarien}: Use common CPU ACPI code ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/29755 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief3de0c8061fd1a985fecbc355062eb23d046d6d Gerrit-Change-Number: 29755 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: soc/intel/cannonlake: Remove CPU ACPI code
by Duncan Laurie (Code Review) 30 Nov '18

30 Nov '18

Duncan Laurie has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29756 ) Change subject: soc/intel/cannonlake: Remove CPU ACPI code ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/29756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id526dc503f278b5cf3a8ce5ccec6f751aa777df0 Gerrit-Change-Number: 29756 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: ec/google/wilco: Turn camera power on
by Duncan Laurie (Code Review) 30 Nov '18

30 Nov '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29987 Change subject: ec/google/wilco: Turn camera power on ...................................................................... ec/google/wilco: Turn camera power on Send the EC command required to turn the camera power on and verify that it shows up on the USB bus. Change-Id: I9e9ba712a11cef85cde91ac21a4b6b5090ef58dc Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/ec/google/wilco/chip.c M src/ec/google/wilco/commands.h 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/29987/1 diff --git a/src/ec/google/wilco/chip.c b/src/ec/google/wilco/chip.c index e1f468d..a9caaec 100644 --- a/src/ec/google/wilco/chip.c +++ b/src/ec/google/wilco/chip.c @@ -69,6 +69,9 @@ /* Enable WiFi radio */ wilco_ec_radio_control(RADIO_WIFI, 1); + + /* Turn on camera power */ + wilco_ec_send(KB_CAMERA, CAMERA_ON); } static void wilco_ec_resource(struct device *dev, int index, diff --git a/src/ec/google/wilco/commands.h b/src/ec/google/wilco/commands.h index 0989b20..752e19b 100644 --- a/src/ec/google/wilco/commands.h +++ b/src/ec/google/wilco/commands.h @@ -32,6 +32,8 @@ KB_SAVE = 0x2f, /* Restore PS/2 data after S3 resume */ KB_RESTORE = 0x30, + /* Manage the EC control of camera power */ + KB_CAMERA = 0x33, /* Retrieve information about the EC */ KB_EC_INFO = 0x38, /* Set ACPI mode on or off */ @@ -67,6 +69,11 @@ RADIO_WIFI = 0x02, }; +enum ec_camera { + CAMERA_ON = 0, + CAMERA_OFF +}; + /** * wilco_ec_radio_control() - Control wireless radios. * @ec_radio: Wireless radio type. -- To view, visit https://review.coreboot.org/c/coreboot/+/29987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e9ba712a11cef85cde91ac21a4b6b5090ef58dc Gerrit-Change-Number: 29987 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B group
by Furquan Shaikh (Code Review) 30 Nov '18

30 Nov '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29872 ) Change subject: mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B group ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2332b0eb7a2f74e8178b95a23c8ac2091027a071 Gerrit-Change-Number: 29872 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 22:25:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B group
by Furquan Shaikh (Code Review) 30 Nov '18

30 Nov '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29872 ) Change subject: mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B group ...................................................................... Patch Set 2: > Patch Set 2: Code-Review+1 > > my test result is same as shelley now by > correct the HW re-work > > Would you help to +2 ? > We need it to build the EVT Does APIC_INVERT fail for you too? -- To view, visit https://review.coreboot.org/c/coreboot/+/29872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2332b0eb7a2f74e8178b95a23c8ac2091027a071 Gerrit-Change-Number: 29872 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Fri, 30 Nov 2018 22:24:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: ACPI: Rename FADT model and set it to zero
by HAOUAS Elyes (Code Review) 30 Nov '18

30 Nov '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29986 Change subject: ACPI: Rename FADT model and set it to zero ...................................................................... ACPI: Rename FADT model and set it to zero INT_MODEL defined in ACPI 1.0 and renamed to reserved in upper versions. The value for this field is zero but 1 is allowed to maintain compatibility with ACPI 1.0. So set this value to zero as we are using ACPI upper than 1.0 Change-Id: I910ead4e5618c958a7989f4c309a3a4bb938e31a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/include/arch/acpi.h M src/mainboard/aopen/dxplplusu/fadt.c M src/mainboard/emulation/qemu-q35/acpi_tables.c M src/mainboard/google/auron/fadt.c M src/mainboard/google/cyan/fadt.c M src/mainboard/google/jecht/fadt.c M src/mainboard/google/rambi/fadt.c M src/mainboard/intel/harcuvar/fadt.c M src/mainboard/intel/strago/fadt.c M src/mainboard/intel/wtm2/fadt.c M src/mainboard/lenovo/t400/fadt.c M src/mainboard/lenovo/x200/fadt.c M src/mainboard/purism/librem_bdw/fadt.c M src/mainboard/roda/rk9/fadt.c M src/mainboard/scaleway/tagada/fadt.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/fsp_broadwell_de/acpi.c M src/southbridge/amd/agesa/hudson/fadt.c M src/southbridge/amd/cimx/sb800/fadt.c M src/southbridge/amd/pi/hudson/fadt.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/fsp_rangeley/acpi.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c 26 files changed, 26 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/29986/1 diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index cd86e83..b766465 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -489,7 +489,7 @@ struct acpi_table_header header; u32 firmware_ctrl; u32 dsdt; - u8 model; /* Eliminated in ACPI 2.0. Platforms should set + u8 reserved; /* Eliminated in ACPI 2.0. Platforms should set * this field to zero but field values of one * are also allowed to maintain compatibility * with ACPI 1.0. diff --git a/src/mainboard/aopen/dxplplusu/fadt.c b/src/mainboard/aopen/dxplplusu/fadt.c index b78a3ed..b6c3d9e 100644 --- a/src/mainboard/aopen/dxplplusu/fadt.c +++ b/src/mainboard/aopen/dxplplusu/fadt.c @@ -45,7 +45,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; + fadt->reserved = 0; fadt->preferred_pm_profile = 0; /* PM_MOBILE; */ fadt->sci_int = 0x9; diff --git a/src/mainboard/emulation/qemu-q35/acpi_tables.c b/src/mainboard/emulation/qemu-q35/acpi_tables.c index 5a36cb1..736b0db 100644 --- a/src/mainboard/emulation/qemu-q35/acpi_tables.c +++ b/src/mainboard/emulation/qemu-q35/acpi_tables.c @@ -57,7 +57,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 0x00; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_MOBILE; fadt->sci_int = 0x9; fadt->smi_cmd = 0; diff --git a/src/mainboard/google/auron/fadt.c b/src/mainboard/google/auron/fadt.c index 9ee5c95..e614ce4 100644 --- a/src/mainboard/google/auron/fadt.c +++ b/src/mainboard/google/auron/fadt.c @@ -32,7 +32,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_MOBILE; fadt->x_firmware_ctl_l = (unsigned long)facs; diff --git a/src/mainboard/google/cyan/fadt.c b/src/mainboard/google/cyan/fadt.c index 7455d4b..3087dd9 100644 --- a/src/mainboard/google/cyan/fadt.c +++ b/src/mainboard/google/cyan/fadt.c @@ -32,7 +32,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_MOBILE; fadt->x_firmware_ctl_l = (unsigned long)facs; diff --git a/src/mainboard/google/jecht/fadt.c b/src/mainboard/google/jecht/fadt.c index 9ee5c95..e614ce4 100644 --- a/src/mainboard/google/jecht/fadt.c +++ b/src/mainboard/google/jecht/fadt.c @@ -32,7 +32,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_MOBILE; fadt->x_firmware_ctl_l = (unsigned long)facs; diff --git a/src/mainboard/google/rambi/fadt.c b/src/mainboard/google/rambi/fadt.c index d02609b..01b6add 100644 --- a/src/mainboard/google/rambi/fadt.c +++ b/src/mainboard/google/rambi/fadt.c @@ -31,7 +31,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_MOBILE; fadt->x_firmware_ctl_l = (unsigned long)facs; diff --git a/src/mainboard/intel/harcuvar/fadt.c b/src/mainboard/intel/harcuvar/fadt.c index 9f41f64..bc47c59 100644 --- a/src/mainboard/intel/harcuvar/fadt.c +++ b/src/mainboard/intel/harcuvar/fadt.c @@ -36,7 +36,7 @@ fadt->firmware_ctrl = (unsigned long)facs; fadt->dsdt = (unsigned long)dsdt; - fadt->model = 1; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER; fadt->x_firmware_ctl_l = (unsigned long)facs; diff --git a/src/mainboard/intel/strago/fadt.c b/src/mainboard/intel/strago/fadt.c index e0e7d44..a8ed861 100644 --- a/src/mainboard/intel/strago/fadt.c +++ b/src/mainboard/intel/strago/fadt.c @@ -32,7 +32,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_MOBILE; fadt->x_firmware_ctl_l = (unsigned long)facs; diff --git a/src/mainboard/intel/wtm2/fadt.c b/src/mainboard/intel/wtm2/fadt.c index 6f1553c..b3351d9 100644 --- a/src/mainboard/intel/wtm2/fadt.c +++ b/src/mainboard/intel/wtm2/fadt.c @@ -31,7 +31,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_MOBILE; fadt->x_firmware_ctl_l = (unsigned long)facs; diff --git a/src/mainboard/lenovo/t400/fadt.c b/src/mainboard/lenovo/t400/fadt.c index 5596115..3175c7d 100644 --- a/src/mainboard/lenovo/t400/fadt.c +++ b/src/mainboard/lenovo/t400/fadt.c @@ -35,7 +35,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 0x00; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_MOBILE; fadt->sci_int = 0x9; fadt->smi_cmd = APM_CNT; diff --git a/src/mainboard/lenovo/x200/fadt.c b/src/mainboard/lenovo/x200/fadt.c index 5596115..3175c7d 100644 --- a/src/mainboard/lenovo/x200/fadt.c +++ b/src/mainboard/lenovo/x200/fadt.c @@ -35,7 +35,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 0x00; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_MOBILE; fadt->sci_int = 0x9; fadt->smi_cmd = APM_CNT; diff --git a/src/mainboard/purism/librem_bdw/fadt.c b/src/mainboard/purism/librem_bdw/fadt.c index fbce9d7..147937b 100644 --- a/src/mainboard/purism/librem_bdw/fadt.c +++ b/src/mainboard/purism/librem_bdw/fadt.c @@ -31,7 +31,7 @@ fadt->firmware_ctrl = (u32)facs; fadt->dsdt = (u32)dsdt; - fadt->model = 1; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_MOBILE; fadt->x_firmware_ctl_l = (u32)facs; diff --git a/src/mainboard/roda/rk9/fadt.c b/src/mainboard/roda/rk9/fadt.c index 5596115..3175c7d 100644 --- a/src/mainboard/roda/rk9/fadt.c +++ b/src/mainboard/roda/rk9/fadt.c @@ -35,7 +35,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 0x00; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_MOBILE; fadt->sci_int = 0x9; fadt->smi_cmd = APM_CNT; diff --git a/src/mainboard/scaleway/tagada/fadt.c b/src/mainboard/scaleway/tagada/fadt.c index 9f41f64..bc47c59 100644 --- a/src/mainboard/scaleway/tagada/fadt.c +++ b/src/mainboard/scaleway/tagada/fadt.c @@ -36,7 +36,7 @@ fadt->firmware_ctrl = (unsigned long)facs; fadt->dsdt = (unsigned long)dsdt; - fadt->model = 1; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER; fadt->x_firmware_ctl_l = (unsigned long)facs; diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 645aff4..cb4f95d 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -86,7 +86,7 @@ fadt->firmware_ctrl = (u32) facs; fadt->dsdt = (u32) dsdt; - fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ + fadt->reserved = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = FADT_PM_PROFILE; fadt->sci_int = 9; /* IRQ 09 - ACPI SCI */ diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index 2640a80..2abc7ca 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -198,7 +198,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ + fadt->reserved = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = config->fadt_pm_profile; /* unknown is default */ /* System Management */ diff --git a/src/soc/intel/fsp_broadwell_de/acpi.c b/src/soc/intel/fsp_broadwell_de/acpi.c index d5bee64..370279c 100644 --- a/src/soc/intel/fsp_broadwell_de/acpi.c +++ b/src/soc/intel/fsp_broadwell_de/acpi.c @@ -176,7 +176,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ + fadt->reserved = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = 0; fadt->sci_int = acpi_sci_irq(); diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c index e8483a0..20af86e 100644 --- a/src/southbridge/amd/agesa/hudson/fadt.c +++ b/src/southbridge/amd/agesa/hudson/fadt.c @@ -65,7 +65,7 @@ else fadt->dsdt = (uintptr_t)dsdt; - fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ + fadt->reserved = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = FADT_PM_PROFILE; fadt->sci_int = 9; /* HUDSON - IRQ 09 - ACPI SCI */ diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c index 15e05c3..5313b7d 100644 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ b/src/southbridge/amd/cimx/sb800/fadt.c @@ -69,7 +69,7 @@ else fadt->dsdt = (uintptr_t)dsdt; - fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ + fadt->reserved = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = FADT_PM_PROFILE; fadt->sci_int = 9; /* HUDSON 1 - IRQ 09 - ACPI SCI */ fadt->smi_cmd = 0; /* disable system management mode */ diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index c2d5d19..0a6bc77 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -57,7 +57,7 @@ fadt->firmware_ctrl = (u32) facs; fadt->dsdt = (u32) dsdt; - fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ + fadt->reserved = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = FADT_PM_PROFILE; fadt->sci_int = 9; /* HUDSON - IRQ 09 - ACPI SCI */ diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 7ae538e..efbe688 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -743,7 +743,7 @@ u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; int c2_latency; - fadt->model = 1; + fadt->reserved = 0; fadt->sci_int = 0x9; fadt->smi_cmd = APM_CNT; diff --git a/src/southbridge/intel/fsp_rangeley/acpi.c b/src/southbridge/intel/fsp_rangeley/acpi.c index efe5412..be5595d 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi.c +++ b/src/southbridge/intel/fsp_rangeley/acpi.c @@ -58,7 +58,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ + fadt->reserved = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = config->fadt_pm_profile; /* unknown is default */ /* System Management */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 7dcec50..db49180 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -576,7 +576,7 @@ fadt->mon_alrm = 0x00; fadt->century = 0x32; - fadt->model = 1; + fadt->reserved = 0; fadt->sci_int = 0x9; fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index ba79e73..6ad6929 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -589,7 +589,7 @@ fadt->mon_alrm = 0x00; fadt->century = 0x32; - fadt->model = 1; + fadt->reserved = 0; fadt->sci_int = 0x9; fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index e5cbc59..455c785 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -652,7 +652,7 @@ u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; int c2_latency; - fadt->model = 1; + fadt->reserved = 0; fadt->sci_int = 0x9; fadt->smi_cmd = APM_CNT; -- To view, visit https://review.coreboot.org/c/coreboot/+/29986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I910ead4e5618c958a7989f4c309a3a4bb938e31a Gerrit-Change-Number: 29986 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: Makefile.inc: Avoid race condition when using 'make -j<N>'
by Nico Huber (Code Review) 30 Nov '18

30 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29984 ) Change subject: Makefile.inc: Avoid race condition when using 'make -j<N>' ...................................................................... Patch Set 1: I guess the the now earlier triggered build of `conf` could still col- lide with the one triggered by the oldconfig rule in Makefile. So add the same dependency to the other rule, too? -- To view, visit https://review.coreboot.org/c/coreboot/+/29984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie93eda567f88ca08c97df7e70cdff5b07442747d Gerrit-Change-Number: 29984 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Fri, 30 Nov 2018 20:15:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: src: Remove not used variable
by HAOUAS Elyes (Code Review) 30 Nov '18

30 Nov '18

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29917 ) Change subject: src: Remove not used variable ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/#/c/29917/11/src/northbridge/intel/x4x/early_in… File src/northbridge/intel/x4x/early_init.c: https://review.coreboot.org/#/c/29917/11/src/northbridge/intel/x4x/early_in… PS11, Line 227: reg32 = RCBA32(0x2010); is it needed to read RCBA 0x2010 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 11 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 20:09:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: mb/google/sarien: Program HD Audio SVID/SSID
by Lijian Zhao (Code Review) 30 Nov '18

30 Nov '18

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29651 ) Change subject: mb/google/sarien: Program HD Audio SVID/SSID ...................................................................... Patch Set 1: > Patch Set 1: > > Could we do this at the SOC level? > > If we had a Kconfig entry in the SOC that allowed the mainboard to define an HDA codec device ID then the SOC level code could have this structure (filled with CONFIG_SUBSYSTEM_VENDOR_ID and something like CONFIG_HDA_CODEC_ID) and pass it to FSP if HDA is enabled. Sure, thought about that before that sounds better. -- To view, visit https://review.coreboot.org/c/coreboot/+/29651 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25e22313fd99479f1a2f68636a2eab83126ca488 Gerrit-Change-Number: 29651 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 19:29:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: src/(device/lib/soc): Remove unused variables
by Richard Spiegel (Code Review) 30 Nov '18

30 Nov '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29985 Change subject: src/(device/lib/soc): Remove unused variables ...................................................................... src/(device/lib/soc): Remove unused variables When building grunt with flags set to detect variables that get a value but then are unused, there are 7 instances that causes error (unused variable). In most cases it's enough to simply remove the variable. In one instance, the variable is used to receive the return of a function. For this instance, add a debug print that will use it. On another instance, the variable will be used depending on build options, so the variable must only be created and set if this build option is set. BUG=b:120260448 TEST=Build and boot grunt. Change-Id: I0d00fb6a42db20afb34c76b9445a741a57096ead Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/device/dram/ddr3.c M src/lib/selfboot.c M src/soc/amd/common/block/pi/def_callouts.c M src/soc/amd/stoneyridge/lpc.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/southbridge.c 6 files changed, 9 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/29985/1 diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index f27fdcb..1f5b7eb 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -136,7 +136,10 @@ u8 reg8; u32 mtb; /* medium time base */ u32 ftb; /* fine time base */ - unsigned int val, param; + unsigned int val; +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) + unsigned int param; +#endif ret = SPD_STATUS_OK; @@ -173,7 +176,9 @@ printram(" Invalid number of memory banks\n"); ret = SPD_STATUS_INVALID_FIELD; } +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) param = 1 << (val + 3); +#endif printram(" Banks : %u\n", param); /* SDRAM capacity */ capacity_shift = reg8 & 0x0f; diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 9c52cd6..f1c2ba4 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -144,9 +144,9 @@ { uint8_t *dest; size_t memsz; - struct cbfs_payload_segment *first_segment, *seg, segment; + struct cbfs_payload_segment *seg, segment; - for (first_segment = seg = cbfssegs;; ++seg) { + for (seg = cbfssegs;; ++seg) { printk(BIOS_DEBUG, "Checking segment from ROM address 0x%p\n", seg); cbfs_decode_payload_segment(&segment, seg); dest = (uint8_t *)(uintptr_t)segment.load_addr; diff --git a/src/soc/amd/common/block/pi/def_callouts.c b/src/soc/amd/common/block/pi/def_callouts.c index 0fffaf3..693c7c5 100644 --- a/src/soc/amd/common/block/pi/def_callouts.c +++ b/src/soc/amd/common/block/pi/def_callouts.c @@ -116,10 +116,8 @@ { AGESA_STATUS Status; uintptr_t ResetType; - AMD_CONFIG_PARAMS *StdHeader; ResetType = Data; - StdHeader = ConfigPtr; /* * This should perform the RESET based upon the ResetType, but coreboot diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c index 317574b..efc948d 100644 --- a/src/soc/amd/stoneyridge/lpc.c +++ b/src/soc/amd/stoneyridge/lpc.c @@ -145,6 +145,7 @@ /* Allocate ACPI NVS in CBMEM */ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); + printk(BIOS_DEBUG, "ACPI GNVS at %p\n", gnvs); } static void lpc_set_resources(struct device *dev) diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 749eefe..94242da 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -226,12 +226,9 @@ acpi_header_t *ssdt; acpi_header_t *alib; acpi_header_t *ivrs; - acpi_hest_t *hest; - acpi_bert_t *bert; /* HEST */ current = ALIGN(current, 8); - hest = (acpi_hest_t *)current; acpi_write_hest((void *)current, acpi_fill_hest); acpi_add_table(rsdp, (void *)current); current += ((acpi_header_t *)current)->length; @@ -249,7 +246,6 @@ printk(BIOS_ERR, "Error: Can't find BERT storage area\n"); } else { current = ALIGN(current, 8); - bert = (acpi_bert_t *)current; acpi_write_bert((void *)current, (uintptr_t)rgn, size); acpi_add_table(rsdp, (void *)current); current += ((acpi_header_t *)current)->length; diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 6157e50..bbebf6c 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -217,13 +217,10 @@ */ int sb_find_wideio_range(uint16_t start, uint16_t size) { - uint32_t enable_register; int i, index = WIDEIO_RANGE_ERROR; uint16_t end, current_size, start_wideio, end_wideio; end = start + size; - enable_register = pci_read_config32(SOC_LPC_DEV, - LPC_IO_OR_MEM_DECODE_ENABLE); for (i = 0; i < TOTAL_WIDEIO_PORTS; i++) { current_size = sb_wideio_size(i); if (current_size == 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/29985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d00fb6a42db20afb34c76b9445a741a57096ead Gerrit-Change-Number: 29985 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src: Remove not used variable
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29917 ) Change subject: src: Remove not used variable ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/#/c/29917/11/src/cpu/amd/family_10h-family_15h/… File src/cpu/amd/family_10h-family_15h/init_cpus.c: https://review.coreboot.org/#/c/29917/11/src/cpu/amd/family_10h-family_15h/… PS11, Line 1061: if ((get_option(&nvram, "cpu_c_states") == CB_SUCCESS) && line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 11 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 16:31:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src: Remove not used variable
by HAOUAS Elyes (Code Review) 30 Nov '18

30 Nov '18

Hello Patrick Rudolph, Huang Jin, Julius Werner, Angel Pons, York Yang, Philipp Deppenwiese, build bot (Jenkins), Damien Zammit, David Guckian, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29917 to look at the new patch set (#11). Change subject: src: Remove not used variable ...................................................................... src: Remove not used variable Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm64/boot.c M src/cpu/amd/family_10h-family_15h/init_cpus.c M src/device/dram/ddr3.c M src/drivers/spi/sst.c M src/lib/selfboot.c M src/northbridge/amd/amdmct/mct/mct_d.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/haswell/raminit.c M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/intel/x4x/early_init.c M src/northbridge/via/vx900/raminit_ddr3.c M src/soc/amd/stoneyridge/southbridge.c M src/soc/cavium/common/bootblock.c M src/soc/intel/fsp_baytrail/romstage/romstage.c M src/soc/intel/fsp_broadwell_de/romstage/romstage.c M src/soc/intel/quark/i2c.c M src/southbridge/amd/common/amd_pci_util.c M src/southbridge/intel/fsp_rangeley/romstage.c M src/southbridge/intel/i82371eb/fadt.c 22 files changed, 25 insertions(+), 88 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/29917/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 11 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: src: Remove not used variable
by HAOUAS Elyes (Code Review) 30 Nov '18

30 Nov '18

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29917 ) Change subject: src: Remove not used variable ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/#/c/29917/10/src/northbridge/intel/x4x/early_in… File src/northbridge/intel/x4x/early_init.c: https://review.coreboot.org/#/c/29917/10/src/northbridge/intel/x4x/early_in… PS10, Line 227: reg32 = RCBA32(0x2010); is it needed to read RCBA32(0x2010) ? -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 10 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 16:23:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src: Remove not used variable
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29917 ) Change subject: src: Remove not used variable ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/#/c/29917/10/src/cpu/amd/family_10h-family_15h/… File src/cpu/amd/family_10h-family_15h/init_cpus.c: https://review.coreboot.org/#/c/29917/10/src/cpu/amd/family_10h-family_15h/… PS10, Line 1061: if ((get_option(&nvram, "cpu_c_states") == CB_SUCCESS) && line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 10 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 16:00:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src: Remove not used variable
by HAOUAS Elyes (Code Review) 30 Nov '18

30 Nov '18

Hello Patrick Rudolph, Huang Jin, Julius Werner, Angel Pons, York Yang, Philipp Deppenwiese, build bot (Jenkins), Damien Zammit, David Guckian, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29917 to look at the new patch set (#10). Change subject: src: Remove not used variable ...................................................................... src: Remove not used variable Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm64/boot.c M src/cpu/amd/family_10h-family_15h/init_cpus.c M src/device/dram/ddr3.c M src/drivers/spi/sst.c M src/lib/selfboot.c M src/northbridge/amd/amdmct/mct/mct_d.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/haswell/raminit.c M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/intel/x4x/early_init.c M src/northbridge/via/vx900/raminit_ddr3.c M src/soc/amd/stoneyridge/southbridge.c M src/soc/cavium/common/bootblock.c M src/soc/intel/fsp_baytrail/romstage/romstage.c M src/soc/intel/fsp_broadwell_de/romstage/romstage.c M src/soc/intel/quark/i2c.c M src/southbridge/amd/common/amd_pci_util.c M src/southbridge/intel/fsp_rangeley/romstage.c M src/southbridge/intel/i82371eb/fadt.c 22 files changed, 25 insertions(+), 87 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/29917/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 10 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: Crash Test
by HAOUAS Elyes (Code Review) 30 Nov '18

30 Nov '18

HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29926 ) Change subject: Crash Test ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/29926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3dde296ab4b84add8a8ab6a3bb5ecb65da2c158 Gerrit-Change-Number: 29926 Gerrit-PatchSet: 9 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: src/arch/x86/acpi.c: Update ACPI table revision
by HAOUAS Elyes (Code Review) 30 Nov '18

30 Nov '18

Hello Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29579 to look at the new patch set (#3). Change subject: src/arch/x86/acpi.c: Update ACPI table revision ...................................................................... src/arch/x86/acpi.c: Update ACPI table revision Change-Id: I22020bd156536ee8f23a267d7c7b2d7af6c7cfeb Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/acpi.c 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/29579/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/29579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22020bd156536ee8f23a267d7c7b2d7af6c7cfeb Gerrit-Change-Number: 29579 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: Makefile.inc: Avoid race condition when using 'make -j<N>'
by Jonathan Neuschäfer (Code Review) 30 Nov '18

30 Nov '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29984 Change subject: Makefile.inc: Avoid race condition when using 'make -j<N>' ...................................................................... Makefile.inc: Avoid race condition when using 'make -j<N>' When building coreboot from scratch with 'make -j4', I sometimes see this error: CREATE build/mainboard/emulation/qemu-riscv/cbfs-file.wblRgZ.out (from /.../coreboot/.config) HOSTCC cbfstool/cbfstool (link) make[1]: execvp: build/util/kconfig/conf: Permission denied make[1]: *** [/.../coreboot/util/kconfig/Makefile:92: savedefconfig] Error 127 It happens, I think, because the rule generated by cbfs-files-processor-defconfig runs 'make savedefconfig', which builds build/util/kconfig/conf, and something also builds it, at the same time. Fix this case, by making this rule depend on $(objutil)/kconfig/conf. Change-Id: Ie93eda567f88ca08c97df7e70cdff5b07442747d Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/29984/1 diff --git a/Makefile.inc b/Makefile.inc index aaae7bc..6a702a2 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -287,7 +287,7 @@ # arg1: input # arg2: output cbfs-files-processor-defconfig= \ - $(eval $(2): $(1) $(obj)/build.h; \ + $(eval $(2): $(1) $(obj)/build.h $(objutil)/kconfig/conf; \ +printf " CREATE $(2) (from $(1))\n"; \ printf "\# This image was built using coreboot " > $(2).tmp && \ grep "\<COREBOOT_VERSION\>" $(obj)/build.h |cut -d\" -f2 >> $(2).tmp && \ -- To view, visit https://review.coreboot.org/c/coreboot/+/29984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie93eda567f88ca08c97df7e70cdff5b07442747d Gerrit-Change-Number: 29984 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: arch/x86/Kconfig: move MAX_REBOOT_CNT option
by Marcello Sylvester Bauer (Code Review) 30 Nov '18

30 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29979 to look at the new patch set (#2). Change subject: arch/x86/Kconfig: move MAX_REBOOT_CNT option ...................................................................... arch/x86/Kconfig: move MAX_REBOOT_CNT option Move the MAX_REBOOT_CNT option to arch/x86/Kconfig, to make it in the menuconfig reachable. This simplifies the change of this option. Change-Id: Ice26e2ef349f1172b564edc14f1012c33546a93c Signed-off-by: Marcello Sylvester Bauer <info(a)marcellobauer.com> --- M src/Kconfig M src/arch/x86/Kconfig 2 files changed, 10 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/29979/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice26e2ef349f1172b564edc14f1012c33546a93c Gerrit-Change-Number: 29979 Gerrit-PatchSet: 2 Gerrit-Owner: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-Reviewer: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: arch/x86/Kconfig: move MAX_REBOOT_CNT option
by Marcello Sylvester Bauer (Code Review) 30 Nov '18

30 Nov '18

Marcello Sylvester Bauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29979 ) Change subject: arch/x86/Kconfig: move MAX_REBOOT_CNT option ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/29979/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29979/1//COMMIT_MSG@11 PS1, Line 11: > Use case? […] It only adds the entry, so you don't have to change it in the config file by hand. In my case I would rather fallback after 2 failed reboots, but also values up to 15 are possible. https://review.coreboot.org/#/c/29979/1/src/arch/x86/Kconfig File src/arch/x86/Kconfig: https://review.coreboot.org/#/c/29979/1/src/arch/x86/Kconfig@274 PS1, Line 274: 0 > 0 would mean every boot has failed? Never use the normal path? true. it will be changed to 1. -- To view, visit https://review.coreboot.org/c/coreboot/+/29979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice26e2ef349f1172b564edc14f1012c33546a93c Gerrit-Change-Number: 29979 Gerrit-PatchSet: 1 Gerrit-Owner: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-Reviewer: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Fri, 30 Nov 2018 15:27:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in ...coreboot[master]: src: Remove not used variable
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29917 ) Change subject: src: Remove not used variable ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/#/c/29917/9/src/cpu/amd/family_10h-family_15h/i… File src/cpu/amd/family_10h-family_15h/init_cpus.c: https://review.coreboot.org/#/c/29917/9/src/cpu/amd/family_10h-family_15h/i… PS9, Line 1062: if (!!nvram) { suspect code indent for conditional statements (32, 32) -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 9 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 15:26:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src: Remove not used variable
by HAOUAS Elyes (Code Review) 30 Nov '18

30 Nov '18

Hello Patrick Rudolph, Huang Jin, Julius Werner, Angel Pons, York Yang, Philipp Deppenwiese, build bot (Jenkins), Damien Zammit, David Guckian, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29917 to look at the new patch set (#9). Change subject: src: Remove not used variable ...................................................................... src: Remove not used variable Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm64/boot.c M src/cpu/amd/family_10h-family_15h/init_cpus.c M src/device/dram/ddr3.c M src/drivers/spi/sst.c M src/lib/selfboot.c M src/northbridge/amd/amdmct/mct/mct_d.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/haswell/raminit.c M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/intel/x4x/early_init.c M src/northbridge/via/vx900/raminit_ddr3.c M src/soc/amd/stoneyridge/southbridge.c M src/soc/cavium/common/bootblock.c M src/soc/intel/fsp_baytrail/romstage/romstage.c M src/soc/intel/fsp_broadwell_de/romstage/romstage.c M src/soc/intel/quark/i2c.c M src/southbridge/amd/common/amd_pci_util.c M src/southbridge/intel/fsp_rangeley/romstage.c M src/southbridge/intel/i82371eb/fadt.c 22 files changed, 26 insertions(+), 87 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/29917/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 9 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: src: Remove not used variable
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29917 ) Change subject: src: Remove not used variable ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/#/c/29917/8/src/cpu/amd/family_10h-family_15h/i… File src/cpu/amd/family_10h-family_15h/init_cpus.c: https://review.coreboot.org/#/c/29917/8/src/cpu/amd/family_10h-family_15h/i… PS8, Line 1061: if ((get_option(&nvram, "cpu_c_states") == CB_SUCCESS) && line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 8 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 15:06:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src: Remove not used variable
by HAOUAS Elyes (Code Review) 30 Nov '18

30 Nov '18

Hello Patrick Rudolph, Huang Jin, Julius Werner, Angel Pons, York Yang, Philipp Deppenwiese, build bot (Jenkins), Damien Zammit, David Guckian, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29917 to look at the new patch set (#8). Change subject: src: Remove not used variable ...................................................................... src: Remove not used variable Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm64/boot.c M src/cpu/amd/family_10h-family_15h/init_cpus.c M src/device/dram/ddr3.c M src/drivers/spi/sst.c M src/lib/selfboot.c M src/northbridge/amd/amdmct/mct/mct_d.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/haswell/raminit.c M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/via/vx900/raminit_ddr3.c M src/soc/cavium/common/bootblock.c M src/soc/intel/fsp_baytrail/romstage/romstage.c M src/soc/intel/fsp_broadwell_de/romstage/romstage.c M src/soc/intel/quark/i2c.c M src/southbridge/amd/common/amd_pci_util.c M src/southbridge/intel/fsp_rangeley/romstage.c M src/southbridge/intel/i82371eb/fadt.c 19 files changed, 21 insertions(+), 68 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/29917/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 8 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: arch/x86/Kconfig: move MAX_REBOOT_CNT option
by Nico Huber (Code Review) 30 Nov '18

30 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29979 ) Change subject: arch/x86/Kconfig: move MAX_REBOOT_CNT option ...................................................................... Patch Set 1: (2 comments) The current per platform defaults should be enforced as minimum, it won't work reliable otherwise because some reboots triggered by coreboot itself are expected. https://review.coreboot.org/#/c/29979/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29979/1//COMMIT_MSG@11 PS1, Line 11: Use case? What does it fix? https://review.coreboot.org/#/c/29979/1/src/arch/x86/Kconfig File src/arch/x86/Kconfig: https://review.coreboot.org/#/c/29979/1/src/arch/x86/Kconfig@274 PS1, Line 274: 0 0 would mean every boot has failed? Never use the normal path? -- To view, visit https://review.coreboot.org/c/coreboot/+/29979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice26e2ef349f1172b564edc14f1012c33546a93c Gerrit-Change-Number: 29979 Gerrit-PatchSet: 1 Gerrit-Owner: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Fri, 30 Nov 2018 15:03:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src: Remove not used variable
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29917 ) Change subject: src: Remove not used variable ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/#/c/29917/7/src/cpu/amd/family_10h-family_15h/i… File src/cpu/amd/family_10h-family_15h/init_cpus.c: https://review.coreboot.org/#/c/29917/7/src/cpu/amd/family_10h-family_15h/i… PS7, Line 1062: if (!!nvram) { suspect code indent for conditional statements (32, 32) -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 7 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 14:57:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/intel/lynxpoint: Allow the flash chip to be write-protected
by Nico Huber (Code Review) 30 Nov '18

30 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29977 ) Change subject: sb/intel/lynxpoint: Allow the flash chip to be write-protected ...................................................................... Patch Set 1: > While technically correct I don't see why we need to duplicate code and > Kconfig options. Can you move the bd82x6x code to sb/intel/common and > just use that instead ? +1 -- To view, visit https://review.coreboot.org/c/coreboot/+/29977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I781082b1ed507b00815d1e85aec3e56ae5a4bef2 Gerrit-Change-Number: 29977 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 14:56:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src: Remove not used variable
by HAOUAS Elyes (Code Review) 30 Nov '18

30 Nov '18

Hello Patrick Rudolph, Julius Werner, Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29917 to look at the new patch set (#7). Change subject: src: Remove not used variable ...................................................................... src: Remove not used variable Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm64/boot.c M src/cpu/amd/family_10h-family_15h/init_cpus.c M src/device/dram/ddr3.c M src/drivers/spi/sst.c M src/lib/selfboot.c M src/northbridge/amd/amdmct/mct/mct_d.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/haswell/raminit.c M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/via/vx900/raminit_ddr3.c M src/soc/cavium/common/bootblock.c M src/soc/intel/fsp_baytrail/romstage/romstage.c M src/soc/intel/fsp_broadwell_de/romstage/romstage.c M src/soc/intel/quark/i2c.c M src/southbridge/amd/common/amd_pci_util.c M src/southbridge/intel/fsp_rangeley/romstage.c M src/southbridge/intel/i82371eb/fadt.c 19 files changed, 22 insertions(+), 68 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/29917/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 7 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: Documentation: gerrit guidelines: Adopt the new topic syntax
by Jonathan Neuschäfer (Code Review) 30 Nov '18

30 Nov '18

Jonathan Neuschäfer has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/29983 ) Change subject: Documentation: gerrit guidelines: Adopt the new topic syntax ...................................................................... Documentation: gerrit guidelines: Adopt the new topic syntax When the old syntax is used, gerrit now respends with: remote: WARNING: deprecated topic syntax. Use %topic=TOPIC instead Change-Id: I002bfc3e9c4b348379337bc386d3bdefb307679d Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M Documentation/getting_started/gerrit_guidelines.md 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/29983/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29983 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I002bfc3e9c4b348379337bc386d3bdefb307679d Gerrit-Change-Number: 29983 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: Documentation: gerrit guidelines: Adopt the new topic syntax
by Jonathan Neuschäfer (Code Review) 30 Nov '18

30 Nov '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29983 Change subject: Documentation: gerrit guidelines: Adopt the new topic syntax ...................................................................... Documentation: gerrit guidelines: Adopt the new topic syntax Change-Id: I002bfc3e9c4b348379337bc386d3bdefb307679d Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M Documentation/getting_started/gerrit_guidelines.md 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/29983/1 diff --git a/Documentation/getting_started/gerrit_guidelines.md b/Documentation/getting_started/gerrit_guidelines.md index 9210c84..77edaf2 100644 --- a/Documentation/getting_started/gerrit_guidelines.md +++ b/Documentation/getting_started/gerrit_guidelines.md @@ -151,7 +151,7 @@ the patch and clicking on the icon next to the topic line. Topics can also be set when you push the patches into gerrit. For example, to push a set of commits with the the i915-kernel-x60 set, use the command: - git push origin HEAD:refs/for/master/i915-kernel-x60 + git push origin HEAD:refs/for/master%topic=i915-kernel-x60 * If one of your patches isn't ready to be merged, make sure it's obvious that you don't feel it's ready for merge yet. The preferred way to show -- To view, visit https://review.coreboot.org/c/coreboot/+/29983 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I002bfc3e9c4b348379337bc386d3bdefb307679d Gerrit-Change-Number: 29983 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: qcs405 [temp]: Combine BB with QC-Sec for ROM boot
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29973 ) Change subject: qcs405 [temp]: Combine BB with QC-Sec for ROM boot ...................................................................... Patch Set 2: (39 comments) https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py File util/qualcomm/createxbl.py: https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@25 PS2, Line 25: # 09/04/15 et Added -x and -d to embed xbl_sec ELF trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@68 PS2, Line 68: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@84 PS2, Line 84: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@103 PS2, Line 103: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@113 PS2, Line 113: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@121 PS2, Line 121: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@144 PS2, Line 144: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@164 PS2, Line 164: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@172 PS2, Line 172: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@192 PS2, Line 192: header_format = 'reg' trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@223 PS2, Line 223: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@231 PS2, Line 231: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@232 PS2, Line 232: # Create hash table trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@235 PS2, Line 235: target_hash, trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@237 PS2, Line 237: secure_type = image_header_secflag) trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@245 PS2, Line 245: target_hash_hd, trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@254 PS2, Line 254: # Add the hash segment into the ELF trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@272 PS2, Line 272: def merge_elfs(env, trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@284 PS2, Line 284: mbn_tools.preprocess_elf_file(elf_in_file_name1) trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@289 PS2, Line 289: mbn_tools.preprocess_elf_file(elf_in_file_name2) trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@290 PS2, Line 290: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@294 PS2, Line 294: mbn_tools.preprocess_elf_file(elf_in_file_xbl_sec) trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@325 PS2, Line 325: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@364 PS2, Line 364: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@400 PS2, Line 400: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@477 PS2, Line 477: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@512 PS2, Line 512: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@614 PS2, Line 614: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@618 PS2, Line 618: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@621 PS2, Line 621: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@640 PS2, Line 640: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@674 PS2, Line 674: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@675 PS2, Line 675: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@681 PS2, Line 681: inp_data_offset = 0 trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@682 PS2, Line 682: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@689 PS2, Line 689: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@706 PS2, Line 706: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/createxbl.py@708 PS2, Line 708: trailing whitespace https://review.coreboot.org/#/c/29973/2/util/qualcomm/mbn_tools.py File util/qualcomm/mbn_tools.py: https://review.coreboot.org/#/c/29973/2/util/qualcomm/mbn_tools.py@1167 PS2, Line 1167: # Check if a shifting is required to accomodate for the hash segment. 'accomodate' may be misspelled - perhaps 'accommodate'? -- To view, visit https://review.coreboot.org/c/coreboot/+/29973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief4d92214cdc7ec06e90b0c7e73c11b6d6deddb9 Gerrit-Change-Number: 29973 Gerrit-PatchSet: 2 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Fri, 30 Nov 2018 14:09:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: qcs405: Add blsp spi driver and enable SPI-NOR
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29968 ) Change subject: qcs405: Add blsp spi driver and enable SPI-NOR ...................................................................... Patch Set 2: (95 comments) https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/clock.c File src/soc/qualcomm/qcs405/clock.c: https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/clock.c@206 PS2, Line 206: clock_enable_vote(REG(GCC_BLSP1_AHB_CBCR), code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/clock.c@206 PS2, Line 206: clock_enable_vote(REG(GCC_BLSP1_AHB_CBCR), please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/clock.c@207 PS2, Line 207: REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE), code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/clock.c@207 PS2, Line 207: REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE), please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/clock.c@208 PS2, Line 208: BLSP2_AHB_CLK_ENA); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/clock.c@208 PS2, Line 208: BLSP2_AHB_CLK_ENA); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/include/soc… File src/soc/qualcomm/qcs405/include/soc/qup.h: https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 161: unsigned clk_frequency; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 162: unsigned src_frequency; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 164: unsigned initialized; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 173: unsigned data_len; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 178: unsigned size; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c File src/soc/qualcomm/qcs405/spi.c: https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@63 PS2, Line 63: {0},{0},{0},{0}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@63 PS2, Line 63: {0},{0},{0},{0}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@63 PS2, Line 63: {0},{0},{0},{0}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@64 PS2, Line 64: /* BLSP5 registers for SPI interface */ code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@65 PS2, Line 65: { code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@65 PS2, Line 65: { please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@66 PS2, Line 66: BLSP5_SPI_CONFIG_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@66 PS2, Line 66: BLSP5_SPI_CONFIG_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@67 PS2, Line 67: BLSP5_SPI_IO_CONTROL_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@67 PS2, Line 67: BLSP5_SPI_IO_CONTROL_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@68 PS2, Line 68: BLSP5_SPI_ERROR_FLAGS_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@68 PS2, Line 68: BLSP5_SPI_ERROR_FLAGS_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@69 PS2, Line 69: BLSP5_SPI_ERROR_FLAGS_EN_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@69 PS2, Line 69: BLSP5_SPI_ERROR_FLAGS_EN_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@70 PS2, Line 70: BLSP5_QUP_CONFIG_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@70 PS2, Line 70: BLSP5_QUP_CONFIG_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@71 PS2, Line 71: BLSP5_QUP_ERROR_FLAGS_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@71 PS2, Line 71: BLSP5_QUP_ERROR_FLAGS_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@72 PS2, Line 72: BLSP5_QUP_ERROR_FLAGS_EN_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@72 PS2, Line 72: BLSP5_QUP_ERROR_FLAGS_EN_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@73 PS2, Line 73: BLSP5_QUP_OPERATIONAL_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@73 PS2, Line 73: BLSP5_QUP_OPERATIONAL_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@74 PS2, Line 74: BLSP5_QUP_IO_MODES_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@74 PS2, Line 74: BLSP5_QUP_IO_MODES_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@75 PS2, Line 75: BLSP5_QUP_STATE_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@75 PS2, Line 75: BLSP5_QUP_STATE_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@76 PS2, Line 76: BLSP5_QUP_INPUT_FIFOc_REG(0), code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@76 PS2, Line 76: BLSP5_QUP_INPUT_FIFOc_REG(0), please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@77 PS2, Line 77: BLSP5_QUP_OUTPUT_FIFOc_REG(0), code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@77 PS2, Line 77: BLSP5_QUP_OUTPUT_FIFOc_REG(0), please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@78 PS2, Line 78: BLSP5_QUP_MX_INPUT_COUNT_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@78 PS2, Line 78: BLSP5_QUP_MX_INPUT_COUNT_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@79 PS2, Line 79: BLSP5_QUP_MX_OUTPUT_COUNT_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@79 PS2, Line 79: BLSP5_QUP_MX_OUTPUT_COUNT_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@80 PS2, Line 80: BLSP5_QUP_SW_RESET_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@80 PS2, Line 80: BLSP5_QUP_SW_RESET_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@81 PS2, Line 81: 0, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@81 PS2, Line 81: 0, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@82 PS2, Line 82: 0, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@82 PS2, Line 82: 0, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@83 PS2, Line 83: BLSP5_QUP_OPERATIONAL_MASK, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@83 PS2, Line 83: BLSP5_QUP_OPERATIONAL_MASK, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@84 PS2, Line 84: BLSP5_SPI_DEASSERT_WAIT_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@84 PS2, Line 84: BLSP5_SPI_DEASSERT_WAIT_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@85 PS2, Line 85: }, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@85 PS2, Line 85: }, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@273 PS2, Line 273: SPI_IO_CTRL_NO_TRI_STATE | SPI_IO_CTRL_MX_CS_MODE); line over 80 characters https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@310 PS2, Line 310: switch(slave->bus) { switch and case should be at the same indent https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@310 PS2, Line 310: switch(slave->bus) { space required before the open parenthesis '(' https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@311 PS2, Line 311: case 5: code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@311 PS2, Line 311: case 5: please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@313 PS2, Line 313: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@313 PS2, Line 313: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@313 PS2, Line 313: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@314 PS2, Line 314: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@314 PS2, Line 314: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@314 PS2, Line 314: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@315 PS2, Line 315: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@315 PS2, Line 315: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@315 PS2, Line 315: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@316 PS2, Line 316: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@316 PS2, Line 316: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@316 PS2, Line 316: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@318 PS2, Line 318: break; code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@318 PS2, Line 318: break; please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@319 PS2, Line 319: default: code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@320 PS2, Line 320: printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); line over 80 characters https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@320 PS2, Line 320: printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@320 PS2, Line 320: printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@321 PS2, Line 321: break; code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@321 PS2, Line 321: break; please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@322 PS2, Line 322: } code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@322 PS2, Line 322: } please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@354 PS2, Line 354: } void function return statements are not generally useful https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@428 PS2, Line 428: } void function return statements are not generally useful https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@684 PS2, Line 684: "or chipselect\n", bus); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@684 PS2, Line 684: "or chipselect\n", bus); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@713 PS2, Line 713: static int xfer_vectors(const struct spi_slave *slave, open brace '{' following function definitions go on the next line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@714 PS2, Line 714: struct spi_op vectors[], size_t count) code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@714 PS2, Line 714: struct spi_op vectors[], size_t count) please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@715 PS2, Line 715: { please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@716 PS2, Line 716: return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@716 PS2, Line 716: return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/2/src/soc/qualcomm/qcs405/spi.c@717 PS2, Line 717: } please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/29968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I340eb3bf77b25fe3502d4b29ef4bf7c06b282c02 Gerrit-Change-Number: 29968 Gerrit-PatchSet: 2 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Fri, 30 Nov 2018 14:08:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qclib: Add qclib support
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29967 ) Change subject: qclib: Add qclib support ...................................................................... Patch Set 2: (14 comments) https://review.coreboot.org/#/c/29967/2/src/soc/qualcomm/qcs405/qclib_execu… File src/soc/qualcomm/qcs405/qclib_execute.c: https://review.coreboot.org/#/c/29967/2/src/soc/qualcomm/qcs405/qclib_execu… PS2, Line 35: int (*doit)(void *, void *); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/29967/2/src/soc/qualcomm/qcs405/qclib_execu… PS2, Line 35: int (*doit)(void *, void *); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/29967/2/src/soc/qualcomm/qcs405/qclib_execu… PS2, Line 43: struct prog pmic = code indent should use tabs where possible https://review.coreboot.org/#/c/29967/2/src/soc/qualcomm/qcs405/qclib_execu… PS2, Line 43: struct prog pmic = please, no spaces at the start of a line https://review.coreboot.org/#/c/29967/2/src/soc/qualcomm/qcs405/qclib_execu… PS2, Line 44: PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX PMIC_NAME); code indent should use tabs where possible https://review.coreboot.org/#/c/29967/2/src/soc/qualcomm/qcs405/qclib_execu… PS2, Line 44: PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX PMIC_NAME); please, no spaces at the start of a line https://review.coreboot.org/#/c/29967/2/src/soc/qualcomm/qcs405/qclib_execu… PS2, Line 52: if (prog_locate(&pmic)) code indent should use tabs where possible https://review.coreboot.org/#/c/29967/2/src/soc/qualcomm/qcs405/qclib_execu… PS2, Line 52: if (prog_locate(&pmic)) please, no spaces at the start of a line https://review.coreboot.org/#/c/29967/2/src/soc/qualcomm/qcs405/qclib_execu… PS2, Line 53: goto fail; code indent should use tabs where possible https://review.coreboot.org/#/c/29967/2/src/soc/qualcomm/qcs405/qclib_execu… PS2, Line 53: goto fail; please, no spaces at the start of a line https://review.coreboot.org/#/c/29967/2/src/soc/qualcomm/qcs405/qclib_execu… PS2, Line 55: if (cbfs_prog_stage_load(&pmic)) code indent should use tabs where possible https://review.coreboot.org/#/c/29967/2/src/soc/qualcomm/qcs405/qclib_execu… PS2, Line 55: if (cbfs_prog_stage_load(&pmic)) please, no spaces at the start of a line https://review.coreboot.org/#/c/29967/2/src/soc/qualcomm/qcs405/qclib_execu… PS2, Line 56: goto fail; code indent should use tabs where possible https://review.coreboot.org/#/c/29967/2/src/soc/qualcomm/qcs405/qclib_execu… PS2, Line 56: goto fail; please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/29967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07 Gerrit-Change-Number: 29967 Gerrit-PatchSet: 2 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Fri, 30 Nov 2018 14:08:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: Coreboot: Add support for USB host mode for mistral platform
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29966 ) Change subject: Coreboot: Add support for USB host mode for mistral platform ...................................................................... Patch Set 2: (4 comments) https://review.coreboot.org/#/c/29966/2/src/soc/qualcomm/qcs405/usb.c File src/soc/qualcomm/qcs405/usb.c: https://review.coreboot.org/#/c/29966/2/src/soc/qualcomm/qcs405/usb.c@137 PS2, Line 137: write8(&dwc3->usb2_phy_dig->override_x0, dwc3->board_data->parameter_override_x0); line over 80 characters https://review.coreboot.org/#/c/29966/2/src/soc/qualcomm/qcs405/usb.c@138 PS2, Line 138: write8(&dwc3->usb2_phy_dig->override_x1, dwc3->board_data->parameter_override_x1); line over 80 characters https://review.coreboot.org/#/c/29966/2/src/soc/qualcomm/qcs405/usb.c@139 PS2, Line 139: write8(&dwc3->usb2_phy_dig->override_x2, dwc3->board_data->parameter_override_x2); line over 80 characters https://review.coreboot.org/#/c/29966/2/src/soc/qualcomm/qcs405/usb.c@140 PS2, Line 140: write8(&dwc3->usb2_phy_dig->override_x3, dwc3->board_data->parameter_override_x3); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35ec549b49b9789389c80843f6103e7243d52aac Gerrit-Change-Number: 29966 Gerrit-PatchSet: 2 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Fri, 30 Nov 2018 14:08:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405: Add blsp uart driver
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29964 ) Change subject: qcs405: Add blsp uart driver ...................................................................... Patch Set 2: (25 comments) https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/include/soc… File src/soc/qualcomm/qcs405/include/soc/cdp.h: https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 36: unsigned smem_get_board_machtype(void); Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 89: SPI_CS_0 , space prohibited before that ',' (ctx:WxE) https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 119: unsigned count; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 124: unsigned base; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 126: unsigned is_macsec; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 127: unsigned mac_pwr0; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 128: unsigned mac_pwr1; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 129: unsigned mac_conn_to_phy; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 172: unsigned int get_board_index(unsigned machid); Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 173: void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count); Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/include/soc… File src/soc/qualcomm/qcs405/include/soc/iomap.h: https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 49: #define writel_i(v,a) write32((void *)a, v) space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/uart.c File src/soc/qualcomm/qcs405/uart.c: https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/uart.c@50 PS2, Line 50: unsigned blsp_uart; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/uart.c@54 PS2, Line 54: void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count) Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/uart.c@56 PS2, Line 56: int i; code indent should use tabs where possible https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/uart.c@56 PS2, Line 56: int i; please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/uart.c@58 PS2, Line 58: for (i = 0; i < count; i++) { code indent should use tabs where possible https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/uart.c@58 PS2, Line 58: for (i = 0; i < count; i++) { please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/uart.c@59 PS2, Line 59: gpio_configure(gpio->gpio, gpio->func, code indent should use tabs where possible https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/uart.c@59 PS2, Line 59: gpio_configure(gpio->gpio, gpio->func, please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/uart.c@60 PS2, Line 60: gpio->pull, gpio->drvstr, gpio->enable); code indent should use tabs where possible https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/uart.c@60 PS2, Line 60: gpio->pull, gpio->drvstr, gpio->enable); please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/uart.c@61 PS2, Line 61: gpio++; code indent should use tabs where possible https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/uart.c@61 PS2, Line 61: gpio++; please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/uart.c@62 PS2, Line 62: } code indent should use tabs where possible https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/uart.c@62 PS2, Line 62: } please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/29964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9626c68eadead8b8ec5ffbc08cab7b0ec36478f Gerrit-Change-Number: 29964 Gerrit-PatchSet: 2 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Fri, 30 Nov 2018 14:07:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405:Add SPI_RAM_SIMULATION support for QCS405
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29959 ) Change subject: qcs405:Add SPI_RAM_SIMULATION support for QCS405 ...................................................................... Patch Set 2: (6 comments) https://review.coreboot.org/#/c/29959/2/src/soc/qualcomm/qcs405/flash_contr… File src/soc/qualcomm/qcs405/flash_controller.c: https://review.coreboot.org/#/c/29959/2/src/soc/qualcomm/qcs405/flash_contr… PS2, Line 37: static int ram_read(const struct spi_flash *flash, u32 addr, size_t len, void *buf) line over 80 characters https://review.coreboot.org/#/c/29959/2/src/soc/qualcomm/qcs405/flash_contr… PS2, Line 68: { that open brace { should be on the previous line https://review.coreboot.org/#/c/29959/2/src/soc/qualcomm/qcs405/flash_contr… PS2, Line 78: static char name[] = "ram_flash"; static char array declaration should probably be static const char https://review.coreboot.org/#/c/29959/2/src/soc/qualcomm/qcs405/flash_contr… PS2, Line 80: printk(BIOS_INFO, "[%s]..CONFIG_QC_SOC_SIMULATE\n", __FUNCTION__); __func__ should be used instead of gcc specific __FUNCTION__ https://review.coreboot.org/#/c/29959/2/src/soc/qualcomm/qcs405/flash_contr… PS2, Line 82: printk(BIOS_INFO, "[%s]..ram_flash\n", __FUNCTION__); __func__ should be used instead of gcc specific __FUNCTION__ https://review.coreboot.org/#/c/29959/2/src/soc/qualcomm/qcs405/mmu.c File src/soc/qualcomm/qcs405/mmu.c: https://review.coreboot.org/#/c/29959/2/src/soc/qualcomm/qcs405/mmu.c@40 PS2, Line 40: mmu_config_range((void *)0x80000000, 0x40000000, MA_MEM | MA_NS | MA_RW); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I895315a995cbbd5e6a7a305e48476f0d0f583cfe Gerrit-Change-Number: 29959 Gerrit-PatchSet: 2 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Fri, 30 Nov 2018 14:07:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405: Add GPIO API
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29955 ) Change subject: qcs405: Add GPIO API ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29955/2/src/soc/qualcomm/qcs405/include/soc… File src/soc/qualcomm/qcs405/include/soc/gpio.h: https://review.coreboot.org/#/c/29955/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 90: #define PIN(index, tlmm, func1, func2, func3, func4, func5, func6, func7) \ Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/c/coreboot/+/29955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85ce9007c545b44371c4704a0456774d0eff12a8 Gerrit-Change-Number: 29955 Gerrit-PatchSet: 2 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Fri, 30 Nov 2018 14:06:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/intel/lynxpoint: Allow the flash chip to be write-protected
by Patrick Rudolph (Code Review) 30 Nov '18

30 Nov '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29977 ) Change subject: sb/intel/lynxpoint: Allow the flash chip to be write-protected ...................................................................... Patch Set 1: While technically correct I don't see why we need to duplicate code and Kconfig options. Can you move the bd82x6x code to sb/intel/common and just use that instead ? -- To view, visit https://review.coreboot.org/c/coreboot/+/29977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I781082b1ed507b00815d1e85aec3e56ae5a4bef2 Gerrit-Change-Number: 29977 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 14:05:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: soc/qualcomm/qcs405: Add MMU support
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29950 ) Change subject: soc/qualcomm/qcs405: Add MMU support ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29950/2/src/soc/qualcomm/qcs405/mmu.c File src/soc/qualcomm/qcs405/mmu.c: https://review.coreboot.org/#/c/29950/2/src/soc/qualcomm/qcs405/mmu.c@22 PS2, Line 22: void qcs405_mmu_init() Bad function definition - void qcs405_mmu_init() should probably be void qcs405_mmu_init(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/29950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c6353be2c0379ec94f91223805762a2286de06d Gerrit-Change-Number: 29950 Gerrit-PatchSet: 2 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Fri, 30 Nov 2018 14:05:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405: Add bl31 stage and elf
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29981 Change subject: qcs405: Add bl31 stage and elf ...................................................................... qcs405: Add bl31 stage and elf Change-Id: I967c0b78a3561574609bf8332a22838c85e43429 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/arch/arm64/Makefile.inc M src/soc/qualcomm/qcs405/Kconfig M src/soc/qualcomm/qcs405/Makefile.inc A src/soc/qualcomm/qcs405/bl31_plat_params.c A src/soc/qualcomm/qcs405/include/soc/bl31_plat_params.h M src/soc/qualcomm/qcs405/include/soc/memlayout.ld M src/soc/qualcomm/qcs405/include/soc/symbols.h 7 files changed, 124 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/29981/1 diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 6bb7196..bf2f01b 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -157,6 +157,8 @@ ifeq ($(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE),y) +ifneq ($(CONFIG_SOC_QUALCOMM_QCS405),y) + ifeq ($(CONFIG_ARM64_BL31_EXTERNAL_FILE),"") BL31_SOURCE := $(top)/3rdparty/arm-trusted-firmware @@ -235,6 +237,8 @@ endif # CONFIG_ARM64_USE_SECURE_OS +endif # CONFIG_SOC_QUALCOMM_QCS405 + endif # CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE endif # CONFIG_ARCH_RAMSTAGE_ARM64 diff --git a/src/soc/qualcomm/qcs405/Kconfig b/src/soc/qualcomm/qcs405/Kconfig index 29960d4..6704d79 100644 --- a/src/soc/qualcomm/qcs405/Kconfig +++ b/src/soc/qualcomm/qcs405/Kconfig @@ -6,6 +6,7 @@ select ARCH_RAMSTAGE_ARMV8_64 select ARCH_ROMSTAGE_ARMV8_64 select ARCH_VERSTAGE_ARMV8_64 + select ARM64_USE_ARM_TRUSTED_FIRMWARE select BOOTBLOCK_CONSOLE select GENERIC_GPIO_LIB select GENERIC_UDELAY diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index 40dcb9b..a5f9779 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -41,6 +41,7 @@ ramstage-y += rpm_load_reset.c ramstage-y += usb.c ramstage-y += flash_controller.c +ramstage-y += bl31_plat_params.c ################################################################################ @@ -86,6 +87,18 @@ endif ################################################################################ + +BL31_FILE := $(QCS405_BLOB)/bl31.elf +bl31_file := $(shell ls $(BL31_FILE)) +ifneq (,$(findstring $(BL31_FILE),$(bl31_file))) + BL31_CBFS := $(CONFIG_CBFS_PREFIX)/bl31 + $(BL31_CBFS)-file := $(BL31_FILE) + $(BL31_CBFS)-type := payload + $(BL31_CBFS)-compression := none + cbfs-files-y += $(BL31_CBFS) +endif +################################################################################ + QC_SEC_FILE := $(QCS405_BLOB)/qc_sec.mbn qc_sec_file := $(shell ls $(QC_SEC_FILE)) ifneq (,$(findstring $(QC_SEC_FILE),$(qc_sec_file))) diff --git a/src/soc/qualcomm/qcs405/bl31_plat_params.c b/src/soc/qualcomm/qcs405/bl31_plat_params.c new file mode 100644 index 0000000..68a3c14 --- /dev/null +++ b/src/soc/qualcomm/qcs405/bl31_plat_params.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arm_tf.h> +#include <assert.h> +#include <cbmem.h> +#include <soc/bl31_plat_params.h> + +static struct bl31_plat_param *plat_params; + +void register_bl31_param(struct bl31_plat_param *param) +{ + param->next = plat_params; + plat_params = param; +} + +void *soc_get_bl31_plat_params(bl31_params_t *bl31_params) +{ + static struct bl31_u64_param cbtable_param = { + .h = { .type = PARAM_COREBOOT_TABLE, }, + }; + if (!cbtable_param.value) { + cbtable_param.value = (uint64_t)cbmem_find(CBMEM_ID_CBTABLE); + if (cbtable_param.value) + register_bl31_param(&cbtable_param.h); + } + return plat_params; +} diff --git a/src/soc/qualcomm/qcs405/include/soc/bl31_plat_params.h b/src/soc/qualcomm/qcs405/include/soc/bl31_plat_params.h new file mode 100644 index 0000000..d7a8e28 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/bl31_plat_params.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __BL31_PLAT_PARAMS_H__ +#define __BL31_PLAT_PARAMS_H__ + +#if 0 +#include <arm-trusted-firmware/plat/qti/common/inc/qti_plat_params.h> +#else +/* param type */ +enum { + PARAM_NONE = 0, + PARAM_COREBOOT_TABLE, +}; + +/* common header for all plat parameter type */ +struct bl31_plat_param { + uint64_t type; + void *next; +}; + +struct bl31_u64_param { + struct bl31_plat_param h; + uint64_t value; +}; +#endif + +void register_bl31_param(struct bl31_plat_param *param); + +#endif/* __BL31_PLAT_PARAMS_H__ */ diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld index 9e7df11..46d4673 100644 --- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld +++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld @@ -51,6 +51,7 @@ REGION(qclib, 0x8C6a000, 0x80000, 4096) //REGION(dcb, 0x8CEa000, 0x4000, 4096) REGION(pmic, 0x8CED000, 0x10000, 4096) + REGION(el3_stack_canary, 0x8CFD000, 0x8, 0x10) BSRAM_END(0x8D80000) DRAM_START(0x80000000) diff --git a/src/soc/qualcomm/qcs405/include/soc/symbols.h b/src/soc/qualcomm/qcs405/include/soc/symbols.h index 74ba170..28b93f9 100644 --- a/src/soc/qualcomm/qcs405/include/soc/symbols.h +++ b/src/soc/qualcomm/qcs405/include/soc/symbols.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef _SOC_QUALCOMM_QCS405_SYMBOLS_H_ -#define _SOC_QUALCOMM_QCS405_SYMBOLS_H_ +#ifndef _SOC_QUALCOMM_SDM845_SYMBOLS_H_ +#define _SOC_QUALCOMM_SDM845_SYMBOLS_H_ #include <types.h> @@ -42,4 +42,24 @@ extern u8 _erpm[]; #define _rpm_size (_erpm - _rpm) -#endif // _SOC_QUALCOMM_QCS405_SYMBOLS_H_ +extern u8 _el3_stack_canary[]; +extern u8 _eel3_stack_canary[]; +#define _el3_stack_canary_size (_eel3_stack_canary - _el3_stack_canary) + +extern u8 _ddr_training[]; +extern u8 _eddr_training[]; +#define _ddr_training_size (_eddr_training - _ddr_training) + +extern u8 _qclib_serial_log[]; +extern u8 _eqclib_serial_log[]; +#define _qclib_serial_log_size (_eqclib_serial_log - _qclib_serial_log) + +extern u8 _limits_cfg[]; +extern u8 _elimits_cfg[]; +#define _limits_cfg_size (_elimits_cfg - _limits_cfg) + +extern u8 _ddr_information[]; +extern u8 _eddr_information[]; +#define _ddr_information_size (_eddr_information - _ddr_information) + +#endif // _SOC_QUALCOMM_SDM845_SYMBOLS_H_ -- To view, visit https://review.coreboot.org/c/coreboot/+/29981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I967c0b78a3561574609bf8332a22838c85e43429 Gerrit-Change-Number: 29981 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/lynxpoint: Make the finalise handler common
by Patrick Rudolph (Code Review) 30 Nov '18

30 Nov '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29975 ) Change subject: sb/intel/lynxpoint: Make the finalise handler common ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/29975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13b581a2219288019a4e0c9e618db3ac7c3c15ab Gerrit-Change-Number: 29975 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 14:01:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: src: Remove not used variable
by Patrick Rudolph (Code Review) 30 Nov '18

30 Nov '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29917 ) Change subject: src: Remove not used variable ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 6 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 13:59:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: MAINTAINERS: Add Philipp Hug as reviewer for RISC-V
by Jonathan Neuschäfer (Code Review) 30 Nov '18

30 Nov '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29980 Change subject: MAINTAINERS: Add Philipp Hug as reviewer for RISC-V ...................................................................... MAINTAINERS: Add Philipp Hug as reviewer for RISC-V Philipp has been reviewing and writing RISC-V-related code for a while. Change-Id: I3f2d3a61f66343a6e0350909edfe466d2ee6c089 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M MAINTAINERS 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/29980/1 diff --git a/MAINTAINERS b/MAINTAINERS index 3df572c..40b4911 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -136,6 +136,7 @@ RISC-V ARCHITECTURE M: Ronald Minnich <rminnich(a)gmail.com> M: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> +R: Philipp Hug <philipp(a)hug.cx> S: Maintained F: src/arch/riscv/ F: src/soc/sifive/ -- To view, visit https://review.coreboot.org/c/coreboot/+/29980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f2d3a61f66343a6e0350909edfe466d2ee6c089 Gerrit-Change-Number: 29980 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src: Remove not used variable
by HAOUAS Elyes (Code Review) 30 Nov '18

30 Nov '18

Hello Patrick Rudolph, Julius Werner, Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29917 to look at the new patch set (#6). Change subject: src: Remove not used variable ...................................................................... src: Remove not used variable Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm64/boot.c M src/device/dram/ddr3.c M src/drivers/spi/sst.c M src/lib/selfboot.c M src/northbridge/intel/haswell/raminit.c M src/southbridge/amd/common/amd_pci_util.c M src/southbridge/intel/i82371eb/fadt.c 7 files changed, 6 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/29917/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 6 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B group
by Ren Kuo (Code Review) 30 Nov '18

30 Nov '18

Ren Kuo has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29872 ) Change subject: mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B group ...................................................................... Patch Set 2: Code-Review+1 my test result is same as shelley now by correct the HW re-work Would you help to +2 ? We need it to build the EVT -- To view, visit https://review.coreboot.org/c/coreboot/+/29872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2332b0eb7a2f74e8178b95a23c8ac2091027a071 Gerrit-Change-Number: 29872 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Fri, 30 Nov 2018 13:05:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: Crash Test
by HAOUAS Elyes (Code Review) 30 Nov '18

30 Nov '18

HAOUAS Elyes has restored this change. ( https://review.coreboot.org/c/coreboot/+/29926 ) Change subject: Crash Test ...................................................................... Restored for test -- To view, visit https://review.coreboot.org/c/coreboot/+/29926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3dde296ab4b84add8a8ab6a3bb5ecb65da2c158 Gerrit-Change-Number: 29926 Gerrit-PatchSet: 5 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: restore

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Change in ...coreboot[master]: broadcom: Remove SoC and board support
by HAOUAS Elyes (Code Review) 30 Nov '18

30 Nov '18

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29905 ) Change subject: broadcom: Remove SoC and board support ...................................................................... Patch Set 4: maybe a missing file: payloads/libpayload/configs/config.purin ? -- To view, visit https://review.coreboot.org/c/coreboot/+/29905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I148dd7eb0192d396cb69bc26c4062f88a764771a Gerrit-Change-Number: 29905 Gerrit-PatchSet: 4 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 30 Nov 2018 12:34:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/soc/intel/braswell: Remove disabled LPE acpi code
by Frans Hendriks (Code Review) 30 Nov '18

30 Nov '18

Hello Patrick Rudolph, build bot (Jenkins), Hannah Williams, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29414 to look at the new patch set (#4). Change subject: src/soc/intel/braswell: Remove disabled LPE acpi code ...................................................................... src/soc/intel/braswell: Remove disabled LPE acpi code The ACPI code for LPE device was included regardless of the availability of the LPE controller. Move the LPE ACPI code to seperate SSDT and hide it when LPE is disabled. BUG=N/A TEST=Intel CherryHill CRB Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/mainboard/google/cyan/Makefile.inc M src/mainboard/google/cyan/acpi/codec_maxim.asl M src/mainboard/google/cyan/acpi/codec_realtek.asl A src/mainboard/google/cyan/acpi/jack_board.asl A src/mainboard/google/cyan/acpi/jack_detect.asl A src/mainboard/google/cyan/ssdtlpe.asl A src/mainboard/google/cyan/variants/banon/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/celes/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/cyan/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/edgar/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/kefka/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/reks/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/relm/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/setzer/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/terra/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/ultima/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/wizpig/include/variant/acpi/lpe.asl M src/mainboard/intel/strago/Makefile.inc M src/mainboard/intel/strago/acpi/mainboard.asl A src/mainboard/intel/strago/ssdtlpe.asl M src/soc/intel/braswell/acpi/southcluster.asl M src/soc/intel/braswell/include/soc/acpi.h M src/soc/intel/braswell/lpe.c 23 files changed, 393 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/29414/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/29414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73 Gerrit-Change-Number: 29414 Gerrit-PatchSet: 4 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: arch/x86/Kconfig: move MAX_REBOOT_CNT option
by Marcello Sylvester Bauer (Code Review) 30 Nov '18

30 Nov '18

Marcello Sylvester Bauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29979 Change subject: arch/x86/Kconfig: move MAX_REBOOT_CNT option ...................................................................... arch/x86/Kconfig: move MAX_REBOOT_CNT option Move the MAX_REBOOT_CNT option to arch/x86/Kconfig, to make it in the menuconfig reachable. This simplifies the change of this option. Change-Id: Ice26e2ef349f1172b564edc14f1012c33546a93c Signed-off-by: Marcello Sylvester Bauer <info(a)marcellobauer.com> --- M src/Kconfig M src/arch/x86/Kconfig 2 files changed, 10 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/29979/1 diff --git a/src/Kconfig b/src/Kconfig index 62a7a92..812e83e 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1085,14 +1085,6 @@ help Internal option that controls whether we compile in register scripts. -config MAX_REBOOT_CNT - int - default 3 - help - Internal option that sets the maximum number of bootblock executions allowed - with the normal image enabled before assuming the normal image is defective - and switching to the fallback image. - config CREATE_BOARD_CHECKLIST bool default n diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 7c8371e..0bbd0b0 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -268,6 +268,16 @@ default "bootblock_simple.c" if BOOTBLOCK_SIMPLE default "bootblock_normal.c" if BOOTBLOCK_NORMAL +config MAX_REBOOT_CNT + int "Max reboot count" + default 3 + range 0 15 + depends on BOOTBLOCK_NORMAL + help + Sets the maximum number of bootblock executions allowed with the + normal image enabled before assuming the normal image is defective + and switching to the fallback image. + config SKIP_MAX_REBOOT_CNT_CLEAR bool "Do not clear reboot count after successful boot" depends on BOOTBLOCK_NORMAL -- To view, visit https://review.coreboot.org/c/coreboot/+/29979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice26e2ef349f1172b564edc14f1012c33546a93c Gerrit-Change-Number: 29979 Gerrit-PatchSet: 1 Gerrit-Owner: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cbmem: Enable AArch64 support
by Ádám Kallai (Code Review) 30 Nov '18

30 Nov '18

Ádám Kallai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29978 Change subject: cbmem: Enable AArch64 support ...................................................................... cbmem: Enable AArch64 support TEST=on Chromebook Kevin with 64bit userland, it works well. Change-Id: If16065000214c6cff9c14a14c5b5f44faca38153 Signed-off-by: Adam Kallai <kadam(a)inf.u-szeged.hu> --- M util/cbmem/cbmem.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/29978/1 diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 90ad55e..8e73d9c 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -1123,7 +1123,7 @@ exit(exit_code); } -#ifdef __arm__ +#if defined(__arm__) || defined(__aarch64__) static void dt_update_cells(const char *name, int *addr_cells_ptr, int *size_cells_ptr) { @@ -1236,7 +1236,7 @@ closedir(dir); return ret; } -#endif /* __arm__ */ +#endif /* defined(__arm__) || defined(__aarch64__) */ int main(int argc, char** argv) { @@ -1339,7 +1339,7 @@ return 1; } -#ifdef __arm__ +#if defined(__arm__) || defined(__aarch64__) int addr_cells, size_cells; char *coreboot_node = dt_find_compat("/proc/device-tree", "coreboot", &addr_cells, &size_cells); -- To view, visit https://review.coreboot.org/c/coreboot/+/29978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If16065000214c6cff9c14a14c5b5f44faca38153 Gerrit-Change-Number: 29978 Gerrit-PatchSet: 1 Gerrit-Owner: Ádám Kallai <kadam(a)inf.u-szeged.hu> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien/variants/sarien: Enable melf touchscreen
by Chris Zhou (Code Review) 30 Nov '18

30 Nov '18

Chris Zhou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29830 ) Change subject: mb/google/sarien/variants/sarien: Enable melf touchscreen ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29830/2/src/mainboard/google/sarien/variant… File src/mainboard/google/sarien/variants/sarien/devicetree.cb: https://review.coreboot.org/#/c/29830/2/src/mainboard/google/sarien/variant… PS2, Line 124: GPP_B13 > There does not seem to be a dedicated touchscreen reset pin, this is PLTRST and doesn't seem like wh […] According schematic, the reset_gpio is connected with PLTRST. Please see issue 119799550 #5(https://partnerissuetracker.corp.google.com/issues/119799550#comment5). -- To view, visit https://review.coreboot.org/c/coreboot/+/29830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I926c988c141628ae2d98206f9eb615d06357a366 Gerrit-Change-Number: 29830 Gerrit-PatchSet: 2 Gerrit-Owner: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Crystal Lin <crystal_lin(a)compal.corp-partner.google.com> Gerrit-CC: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Fri, 30 Nov 2018 10:43:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/vboot: Fix remaining measured boot issues
by Philipp Deppenwiese (Code Review) 30 Nov '18

30 Nov '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29840 ) Change subject: security/vboot: Fix remaining measured boot issues ...................................................................... security/vboot: Fix remaining measured boot issues Makes vboot measured boot mode available for all boards. * Increase Tegra210 and Rockchip3228 SRAM for romstage/verstage. * Add missing files for Intel apollolake and AMD stoneyridge as TPM driver target. Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/29840 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/soc/amd/stoneyridge/Makefile.inc M src/soc/intel/apollolake/Makefile.inc M src/soc/nvidia/tegra210/include/soc/memlayout.ld M src/soc/rockchip/rk3288/include/soc/memlayout.ld 4 files changed, 14 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Julius Werner: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index c54b652..a53984e 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -87,6 +87,7 @@ postcar-y += ramtop.c postcar-y += sb_util.c postcar-y += nb_util.c +postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c ramstage-y += BiosCallOuts.c ramstage-y += i2c.c diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 6168f86..19ebe7c 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -75,6 +75,7 @@ postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += heci.c postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += reset.c postcar-$(CONFIG_UART_DEBUG) += uart.c +postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += gspi.c verstage-y += car.c verstage-y += i2c.c diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout.ld b/src/soc/nvidia/tegra210/include/soc/memlayout.ld index c1c581b..d807c06 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout.ld @@ -28,18 +28,18 @@ SECTIONS { SRAM_START(0x40000000) - PRERAM_CBMEM_CONSOLE(0x40000000, 8K) - PRERAM_CBFS_CACHE(0x40002000, 36K) - VBOOT2_WORK(0x4000B000, 12K) + PRERAM_CBMEM_CONSOLE(0x40000000, 4K) + PRERAM_CBFS_CACHE(0x40001000, 36K) + VBOOT2_WORK(0x4000A000, 12K) #if ENV_ARM64 - STACK(0x4000E000, 3K) + STACK(0x4000D000, 3K) #else /* AVP gets a separate stack to avoid any chance of handoff races. */ - STACK(0x4000EC00, 3K) + STACK(0x4000DC00, 3K) #endif - TIMESTAMP(0x4000F800, 2K) - BOOTBLOCK(0x40010000, 28K) - VERSTAGE(0x40017000, 64K) - ROMSTAGE(0x40027000, 100K) + TIMESTAMP(0x4000E800, 2K) + BOOTBLOCK(0x4000F000, 28K) + VERSTAGE(0x40016000, 64K) + ROMSTAGE(0x40026000, 104K) SRAM_END(0x40040000) DRAM_START(0x80000000) diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld index fc3758b..6320fad 100644 --- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld @@ -31,9 +31,9 @@ SRAM_START(0xFF700000) TTB(0xFF700000, 16K) BOOTBLOCK(0xFF704004, 20K - 4) - PRERAM_CBMEM_CONSOLE(0xFF709000, 3K) - VBOOT2_WORK(0xFF709C00, 12K) - OVERLAP_VERSTAGE_ROMSTAGE(0xFF70CC00, 41K) + PRERAM_CBMEM_CONSOLE(0xFF709000, 2K) + VBOOT2_WORK(0xFF709800, 12K) + OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C800, 42K) PRERAM_CBFS_CACHE(0xFF717000, 1K) TIMESTAMP(0xFF717400, 0x180) STACK(0xFF717580, 3K - 0x180) -- To view, visit https://review.coreboot.org/c/coreboot/+/29840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82 Gerrit-Change-Number: 29840 Gerrit-PatchSet: 18 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: cpu/intel/fsp_model_406dx: Drop dead microcode reference
by David Guckian (Code Review) 30 Nov '18

30 Nov '18

David Guckian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29931 ) Change subject: cpu/intel/fsp_model_406dx: Drop dead microcode reference ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/29931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia724262a526fe960c17ae4b248acfa42fc342331 Gerrit-Change-Number: 29931 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 10:26:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: broadcom: Remove SoC and board support
by Philipp Deppenwiese (Code Review) 30 Nov '18

30 Nov '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29905 ) Change subject: broadcom: Remove SoC and board support ...................................................................... broadcom: Remove SoC and board support The reason for this code cleanup is the legacy Google Purin board which isn't available anymore and AFAIK never made it into the stores. * Remove broadcom cygnus SoC support * Remove /util/broadcom tool * Remove Google Purin mainboard * Remove MAINTAINERS entries Change-Id: I148dd7eb0192d396cb69bc26c4062f88a764771a Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/29905 Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Documentation/util.md M MAINTAINERS M Makefile.inc D src/mainboard/google/purin/Kconfig D src/mainboard/google/purin/Kconfig.name D src/mainboard/google/purin/Makefile.inc D src/mainboard/google/purin/board_info.txt D src/mainboard/google/purin/boardid.c D src/mainboard/google/purin/bootblock.c D src/mainboard/google/purin/chromeos.c D src/mainboard/google/purin/chromeos.fmd D src/mainboard/google/purin/devicetree.cb D src/mainboard/google/purin/mainboard.c D src/mainboard/google/purin/memlayout.ld D src/mainboard/google/purin/reset.c D src/soc/broadcom/Kconfig D src/soc/broadcom/cygnus/Kconfig D src/soc/broadcom/cygnus/Makefile.inc D src/soc/broadcom/cygnus/bootblock.c D src/soc/broadcom/cygnus/cbmem.c D src/soc/broadcom/cygnus/ddr_init.c D src/soc/broadcom/cygnus/ddr_init_table.c D src/soc/broadcom/cygnus/gpio.c D src/soc/broadcom/cygnus/hw_init.c D src/soc/broadcom/cygnus/i2c.c D src/soc/broadcom/cygnus/include/soc/addressmap.h D src/soc/broadcom/cygnus/include/soc/config.h D src/soc/broadcom/cygnus/include/soc/cygnus.h D src/soc/broadcom/cygnus/include/soc/cygnus_types.h D src/soc/broadcom/cygnus/include/soc/ddr_bist.h D src/soc/broadcom/cygnus/include/soc/gpio.h D src/soc/broadcom/cygnus/include/soc/halapis/ddr_regs.h D src/soc/broadcom/cygnus/include/soc/hw_init.h D src/soc/broadcom/cygnus/include/soc/i2c.h D src/soc/broadcom/cygnus/include/soc/memlayout.ld D src/soc/broadcom/cygnus/include/soc/ns16550.h D src/soc/broadcom/cygnus/include/soc/reg_utils.h D src/soc/broadcom/cygnus/include/soc/sdram.h D src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h D src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_reg_access.h D src/soc/broadcom/cygnus/include/soc/shmoo_and28/shmoo_and28.h D src/soc/broadcom/cygnus/include/soc/shmoo_and28/ydc_ddr_bist.h D src/soc/broadcom/cygnus/include/soc/tz.h D src/soc/broadcom/cygnus/iomux.c D src/soc/broadcom/cygnus/ns16550.c D src/soc/broadcom/cygnus/phy_reg_access.c D src/soc/broadcom/cygnus/romstage.c D src/soc/broadcom/cygnus/sdram.c D src/soc/broadcom/cygnus/shmoo_and28.c D src/soc/broadcom/cygnus/soc.c D src/soc/broadcom/cygnus/spi.c D src/soc/broadcom/cygnus/timer.c D src/soc/broadcom/cygnus/tz.c D src/soc/broadcom/cygnus/usb.c D src/soc/broadcom/cygnus/ydc_ddr_bist.c M util/README.md D util/broadcom/Makefile.inc D util/broadcom/description.md D util/broadcom/khmacsha256 D util/broadcom/secimage/Makefile D util/broadcom/secimage/Makefile.inc D util/broadcom/secimage/crypto.c D util/broadcom/secimage/io.c D util/broadcom/secimage/misc.c D util/broadcom/secimage/sbi.c D util/broadcom/secimage/secimage.h D util/broadcom/secimage/test/data/expected/binary.xxdump D util/broadcom/secimage/test/data/input/binary.xxdump D util/broadcom/secimage/test/data/input/configfile.xxdump D util/broadcom/secimage/test/data/input/hmac_binary_key.xxdump D util/broadcom/secimage/test/hmac.sh D util/broadcom/unauth.cfg M util/testing/Makefile.inc 73 files changed, 1 insertion(+), 29,729 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve -- To view, visit https://review.coreboot.org/c/coreboot/+/29905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I148dd7eb0192d396cb69bc26c4062f88a764771a Gerrit-Change-Number: 29905 Gerrit-PatchSet: 4 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: MAINTAINERS: Add myself as a maintainer
by Philipp Deppenwiese (Code Review) 30 Nov '18

30 Nov '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29913 ) Change subject: MAINTAINERS: Add myself as a maintainer ...................................................................... MAINTAINERS: Add myself as a maintainer Add myself as a maintainer for legacy Intel-based ChromeOS devices for which I provide coreboot images as a comminuty member, and as a maintainer for Purism devices in a professional capacity. Change-Id: I70df3b9e4e36c2e5d73f8888fe0ec220aa8a91b7 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/29913 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M MAINTAINERS 1 file changed, 25 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/MAINTAINERS b/MAINTAINERS index ad94bc1..8ff21a8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -193,6 +193,20 @@ S: Supported F: src/mainboard/google/panther/ +GOOGLE MAINBOARDS (Intel-based, legacy/inactive) +M: Matt DeVillier <MrChromebox(a)gmail.com> +S: Maintained +F: src/mainboard/google/auron/ +F: src/mainboard/google/beltino/ +F: src/mainboard/google/butterfly/ +F: src/mainboard/google/cyan/ +F: src/mainboard/google/glados/ +F: src/mainboard/google/jecht/ +F: src/mainboard/google/link/ +F: src/mainboard/google/parrot/ +F: src/mainboard/google/slippy/ +F: src/mainboard/google/stout/ + OCP MAINBOARDS M: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> M: Patrick Rudolph <patrick.rudolph(a)9elements.com> @@ -207,6 +221,17 @@ F: src/mainboard/opencellular/rotundu/ F: src/mainboard/opencellular/elgon/ +PURISM MAINBOARDS +M: Matt DeVillier <matt.devillier(a)puri.sm> +S: Supported +F: src/mainboard/purism + +SAMSUNG CHROMEOS MAINBOARDS +M: Matt DeVillier <MrChromebox(a)gmail.com> +S: Maintained +F: src/mainboard/samsung/lumpy/ +F: src/mainboard/samsung/stumpy/ + INTEL MINNOWBOARD MAX MAINBOARD M: Huang Jin <huang.jin(a)intel.com> M: York Yang <york.yang(a)intel.com> -- To view, visit https://review.coreboot.org/c/coreboot/+/29913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70df3b9e4e36c2e5d73f8888fe0ec220aa8a91b7 Gerrit-Change-Number: 29913 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: LinuxBoot: fix initramfs xz compression
by Philipp Deppenwiese (Code Review) 30 Nov '18

30 Nov '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29935 ) Change subject: LinuxBoot: fix initramfs xz compression ...................................................................... LinuxBoot: fix initramfs xz compression Add the flag '--check=crc32' to the xz compression to use CRC32 for the integrity check. The linux kernel does not support CRC64 for integrity checks, which is the default flag on most xz applications. Change-Id: I738bd99ef22aa053dc198df5595e1878069de13e Signed-off-by: Marcello Sylvester Bauer <info(a)marcellobauer.com> Reviewed-on: https://review.coreboot.org/c/29935 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M payloads/external/LinuxBoot/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved diff --git a/payloads/external/LinuxBoot/Makefile b/payloads/external/LinuxBoot/Makefile index 8016095..a67b16a 100644 --- a/payloads/external/LinuxBoot/Makefile +++ b/payloads/external/LinuxBoot/Makefile @@ -39,7 +39,7 @@ initramfs_compressed: initramfs ifeq ($(CONFIG_LINUXBOOT_INITRAMFS_COMPRESSION_XZ),y) - xz --keep --force --lzma2=dict=1MiB $(top)/$(CONFIG_LINUXBOOT_INITRAMFS) + xz --keep --force --check=crc32 --lzma2=dict=1MiB $(top)/$(CONFIG_LINUXBOOT_INITRAMFS) endif ifeq ($(CONFIG_LINUXBOOT_COMPILE_KERNEL),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/29935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I738bd99ef22aa053dc198df5595e1878069de13e Gerrit-Change-Number: 29935 Gerrit-PatchSet: 2 Gerrit-Owner: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: LinuxBoot: fix initramfs xz compression
by Philipp Deppenwiese (Code Review) 30 Nov '18

30 Nov '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29935 ) Change subject: LinuxBoot: fix initramfs xz compression ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I738bd99ef22aa053dc198df5595e1878069de13e Gerrit-Change-Number: 29935 Gerrit-PatchSet: 1 Gerrit-Owner: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 10:24:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405 [temp]: Combine BB with QC-Sec for ROM boot
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29973 ) Change subject: qcs405 [temp]: Combine BB with QC-Sec for ROM boot ...................................................................... Patch Set 1: (39 comments) https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py File util/qualcomm/createxbl.py: https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@25 PS1, Line 25: # 09/04/15 et Added -x and -d to embed xbl_sec ELF trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@68 PS1, Line 68: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@84 PS1, Line 84: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@103 PS1, Line 103: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@113 PS1, Line 113: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@121 PS1, Line 121: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@144 PS1, Line 144: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@164 PS1, Line 164: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@172 PS1, Line 172: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@192 PS1, Line 192: header_format = 'reg' trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@223 PS1, Line 223: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@231 PS1, Line 231: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@232 PS1, Line 232: # Create hash table trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@235 PS1, Line 235: target_hash, trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@237 PS1, Line 237: secure_type = image_header_secflag) trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@245 PS1, Line 245: target_hash_hd, trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@254 PS1, Line 254: # Add the hash segment into the ELF trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@272 PS1, Line 272: def merge_elfs(env, trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@284 PS1, Line 284: mbn_tools.preprocess_elf_file(elf_in_file_name1) trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@289 PS1, Line 289: mbn_tools.preprocess_elf_file(elf_in_file_name2) trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@290 PS1, Line 290: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@294 PS1, Line 294: mbn_tools.preprocess_elf_file(elf_in_file_xbl_sec) trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@325 PS1, Line 325: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@364 PS1, Line 364: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@400 PS1, Line 400: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@477 PS1, Line 477: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@512 PS1, Line 512: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@614 PS1, Line 614: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@618 PS1, Line 618: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@621 PS1, Line 621: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@640 PS1, Line 640: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@674 PS1, Line 674: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@675 PS1, Line 675: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@681 PS1, Line 681: inp_data_offset = 0 trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@682 PS1, Line 682: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@689 PS1, Line 689: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@706 PS1, Line 706: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/createxbl.py@708 PS1, Line 708: trailing whitespace https://review.coreboot.org/#/c/29973/1/util/qualcomm/mbn_tools.py File util/qualcomm/mbn_tools.py: https://review.coreboot.org/#/c/29973/1/util/qualcomm/mbn_tools.py@1167 PS1, Line 1167: # Check if a shifting is required to accomodate for the hash segment. 'accomodate' may be misspelled - perhaps 'accommodate'? -- To view, visit https://review.coreboot.org/c/coreboot/+/29973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief4d92214cdc7ec06e90b0c7e73c11b6d6deddb9 Gerrit-Change-Number: 29973 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 10:17:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: qcs405: Add blsp spi driver and enable SPI-NOR
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29968 ) Change subject: qcs405: Add blsp spi driver and enable SPI-NOR ...................................................................... Patch Set 1: (95 comments) https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/clock.c File src/soc/qualcomm/qcs405/clock.c: https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/clock.c@206 PS1, Line 206: clock_enable_vote(REG(GCC_BLSP1_AHB_CBCR), code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/clock.c@206 PS1, Line 206: clock_enable_vote(REG(GCC_BLSP1_AHB_CBCR), please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/clock.c@207 PS1, Line 207: REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE), code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/clock.c@207 PS1, Line 207: REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE), please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/clock.c@208 PS1, Line 208: BLSP2_AHB_CLK_ENA); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/clock.c@208 PS1, Line 208: BLSP2_AHB_CLK_ENA); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/include/soc… File src/soc/qualcomm/qcs405/include/soc/qup.h: https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/include/soc… PS1, Line 161: unsigned clk_frequency; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/include/soc… PS1, Line 162: unsigned src_frequency; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/include/soc… PS1, Line 164: unsigned initialized; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/include/soc… PS1, Line 173: unsigned data_len; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/include/soc… PS1, Line 178: unsigned size; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c File src/soc/qualcomm/qcs405/spi.c: https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@63 PS1, Line 63: {0},{0},{0},{0}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@63 PS1, Line 63: {0},{0},{0},{0}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@63 PS1, Line 63: {0},{0},{0},{0}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@64 PS1, Line 64: /* BLSP5 registers for SPI interface */ code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@65 PS1, Line 65: { code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@65 PS1, Line 65: { please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@66 PS1, Line 66: BLSP5_SPI_CONFIG_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@66 PS1, Line 66: BLSP5_SPI_CONFIG_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@67 PS1, Line 67: BLSP5_SPI_IO_CONTROL_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@67 PS1, Line 67: BLSP5_SPI_IO_CONTROL_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@68 PS1, Line 68: BLSP5_SPI_ERROR_FLAGS_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@68 PS1, Line 68: BLSP5_SPI_ERROR_FLAGS_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@69 PS1, Line 69: BLSP5_SPI_ERROR_FLAGS_EN_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@69 PS1, Line 69: BLSP5_SPI_ERROR_FLAGS_EN_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@70 PS1, Line 70: BLSP5_QUP_CONFIG_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@70 PS1, Line 70: BLSP5_QUP_CONFIG_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@71 PS1, Line 71: BLSP5_QUP_ERROR_FLAGS_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@71 PS1, Line 71: BLSP5_QUP_ERROR_FLAGS_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@72 PS1, Line 72: BLSP5_QUP_ERROR_FLAGS_EN_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@72 PS1, Line 72: BLSP5_QUP_ERROR_FLAGS_EN_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@73 PS1, Line 73: BLSP5_QUP_OPERATIONAL_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@73 PS1, Line 73: BLSP5_QUP_OPERATIONAL_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@74 PS1, Line 74: BLSP5_QUP_IO_MODES_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@74 PS1, Line 74: BLSP5_QUP_IO_MODES_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@75 PS1, Line 75: BLSP5_QUP_STATE_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@75 PS1, Line 75: BLSP5_QUP_STATE_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@76 PS1, Line 76: BLSP5_QUP_INPUT_FIFOc_REG(0), code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@76 PS1, Line 76: BLSP5_QUP_INPUT_FIFOc_REG(0), please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@77 PS1, Line 77: BLSP5_QUP_OUTPUT_FIFOc_REG(0), code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@77 PS1, Line 77: BLSP5_QUP_OUTPUT_FIFOc_REG(0), please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@78 PS1, Line 78: BLSP5_QUP_MX_INPUT_COUNT_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@78 PS1, Line 78: BLSP5_QUP_MX_INPUT_COUNT_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@79 PS1, Line 79: BLSP5_QUP_MX_OUTPUT_COUNT_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@79 PS1, Line 79: BLSP5_QUP_MX_OUTPUT_COUNT_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@80 PS1, Line 80: BLSP5_QUP_SW_RESET_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@80 PS1, Line 80: BLSP5_QUP_SW_RESET_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@81 PS1, Line 81: 0, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@81 PS1, Line 81: 0, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@82 PS1, Line 82: 0, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@82 PS1, Line 82: 0, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@83 PS1, Line 83: BLSP5_QUP_OPERATIONAL_MASK, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@83 PS1, Line 83: BLSP5_QUP_OPERATIONAL_MASK, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@84 PS1, Line 84: BLSP5_SPI_DEASSERT_WAIT_REG, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@84 PS1, Line 84: BLSP5_SPI_DEASSERT_WAIT_REG, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@85 PS1, Line 85: }, code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@85 PS1, Line 85: }, please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@273 PS1, Line 273: SPI_IO_CTRL_NO_TRI_STATE | SPI_IO_CTRL_MX_CS_MODE); line over 80 characters https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@310 PS1, Line 310: switch(slave->bus) { switch and case should be at the same indent https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@310 PS1, Line 310: switch(slave->bus) { space required before the open parenthesis '(' https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@311 PS1, Line 311: case 5: code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@311 PS1, Line 311: case 5: please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@313 PS1, Line 313: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@313 PS1, Line 313: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@313 PS1, Line 313: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@314 PS1, Line 314: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@314 PS1, Line 314: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@314 PS1, Line 314: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@315 PS1, Line 315: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@315 PS1, Line 315: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@315 PS1, Line 315: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@316 PS1, Line 316: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@316 PS1, Line 316: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@316 PS1, Line 316: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@318 PS1, Line 318: break; code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@318 PS1, Line 318: break; please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@319 PS1, Line 319: default: code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@320 PS1, Line 320: printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); line over 80 characters https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@320 PS1, Line 320: printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@320 PS1, Line 320: printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@321 PS1, Line 321: break; code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@321 PS1, Line 321: break; please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@322 PS1, Line 322: } code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@322 PS1, Line 322: } please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@354 PS1, Line 354: } void function return statements are not generally useful https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@428 PS1, Line 428: } void function return statements are not generally useful https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@684 PS1, Line 684: "or chipselect\n", bus); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@684 PS1, Line 684: "or chipselect\n", bus); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@713 PS1, Line 713: static int xfer_vectors(const struct spi_slave *slave, open brace '{' following function definitions go on the next line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@714 PS1, Line 714: struct spi_op vectors[], size_t count) code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@714 PS1, Line 714: struct spi_op vectors[], size_t count) please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@715 PS1, Line 715: { please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@716 PS1, Line 716: return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); code indent should use tabs where possible https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@716 PS1, Line 716: return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); please, no spaces at the start of a line https://review.coreboot.org/#/c/29968/1/src/soc/qualcomm/qcs405/spi.c@717 PS1, Line 717: } please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/29968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I340eb3bf77b25fe3502d4b29ef4bf7c06b282c02 Gerrit-Change-Number: 29968 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 10:17:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qclib: Add qclib support
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29967 ) Change subject: qclib: Add qclib support ...................................................................... Patch Set 1: (14 comments) https://review.coreboot.org/#/c/29967/1/src/soc/qualcomm/qcs405/qclib_execu… File src/soc/qualcomm/qcs405/qclib_execute.c: https://review.coreboot.org/#/c/29967/1/src/soc/qualcomm/qcs405/qclib_execu… PS1, Line 35: int (*doit)(void *, void *); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/29967/1/src/soc/qualcomm/qcs405/qclib_execu… PS1, Line 35: int (*doit)(void *, void *); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/29967/1/src/soc/qualcomm/qcs405/qclib_execu… PS1, Line 43: struct prog pmic = code indent should use tabs where possible https://review.coreboot.org/#/c/29967/1/src/soc/qualcomm/qcs405/qclib_execu… PS1, Line 43: struct prog pmic = please, no spaces at the start of a line https://review.coreboot.org/#/c/29967/1/src/soc/qualcomm/qcs405/qclib_execu… PS1, Line 44: PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX PMIC_NAME); code indent should use tabs where possible https://review.coreboot.org/#/c/29967/1/src/soc/qualcomm/qcs405/qclib_execu… PS1, Line 44: PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX PMIC_NAME); please, no spaces at the start of a line https://review.coreboot.org/#/c/29967/1/src/soc/qualcomm/qcs405/qclib_execu… PS1, Line 52: if (prog_locate(&pmic)) code indent should use tabs where possible https://review.coreboot.org/#/c/29967/1/src/soc/qualcomm/qcs405/qclib_execu… PS1, Line 52: if (prog_locate(&pmic)) please, no spaces at the start of a line https://review.coreboot.org/#/c/29967/1/src/soc/qualcomm/qcs405/qclib_execu… PS1, Line 53: goto fail; code indent should use tabs where possible https://review.coreboot.org/#/c/29967/1/src/soc/qualcomm/qcs405/qclib_execu… PS1, Line 53: goto fail; please, no spaces at the start of a line https://review.coreboot.org/#/c/29967/1/src/soc/qualcomm/qcs405/qclib_execu… PS1, Line 55: if (cbfs_prog_stage_load(&pmic)) code indent should use tabs where possible https://review.coreboot.org/#/c/29967/1/src/soc/qualcomm/qcs405/qclib_execu… PS1, Line 55: if (cbfs_prog_stage_load(&pmic)) please, no spaces at the start of a line https://review.coreboot.org/#/c/29967/1/src/soc/qualcomm/qcs405/qclib_execu… PS1, Line 56: goto fail; code indent should use tabs where possible https://review.coreboot.org/#/c/29967/1/src/soc/qualcomm/qcs405/qclib_execu… PS1, Line 56: goto fail; please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/29967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07 Gerrit-Change-Number: 29967 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 10:17:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: Coreboot: Add support for USB host mode for mistral platform
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29966 ) Change subject: Coreboot: Add support for USB host mode for mistral platform ...................................................................... Patch Set 1: (4 comments) https://review.coreboot.org/#/c/29966/1/src/soc/qualcomm/qcs405/usb.c File src/soc/qualcomm/qcs405/usb.c: https://review.coreboot.org/#/c/29966/1/src/soc/qualcomm/qcs405/usb.c@137 PS1, Line 137: write8(&dwc3->usb2_phy_dig->override_x0, dwc3->board_data->parameter_override_x0); line over 80 characters https://review.coreboot.org/#/c/29966/1/src/soc/qualcomm/qcs405/usb.c@138 PS1, Line 138: write8(&dwc3->usb2_phy_dig->override_x1, dwc3->board_data->parameter_override_x1); line over 80 characters https://review.coreboot.org/#/c/29966/1/src/soc/qualcomm/qcs405/usb.c@139 PS1, Line 139: write8(&dwc3->usb2_phy_dig->override_x2, dwc3->board_data->parameter_override_x2); line over 80 characters https://review.coreboot.org/#/c/29966/1/src/soc/qualcomm/qcs405/usb.c@140 PS1, Line 140: write8(&dwc3->usb2_phy_dig->override_x3, dwc3->board_data->parameter_override_x3); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35ec549b49b9789389c80843f6103e7243d52aac Gerrit-Change-Number: 29966 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 10:16:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405: Add blsp uart driver
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29964 ) Change subject: qcs405: Add blsp uart driver ...................................................................... Patch Set 1: (25 comments) https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/include/soc… File src/soc/qualcomm/qcs405/include/soc/cdp.h: https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/include/soc… PS1, Line 36: unsigned smem_get_board_machtype(void); Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/include/soc… PS1, Line 89: SPI_CS_0 , space prohibited before that ',' (ctx:WxE) https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/include/soc… PS1, Line 119: unsigned count; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/include/soc… PS1, Line 124: unsigned base; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/include/soc… PS1, Line 126: unsigned is_macsec; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/include/soc… PS1, Line 127: unsigned mac_pwr0; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/include/soc… PS1, Line 128: unsigned mac_pwr1; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/include/soc… PS1, Line 129: unsigned mac_conn_to_phy; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/include/soc… PS1, Line 172: unsigned int get_board_index(unsigned machid); Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/include/soc… PS1, Line 173: void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count); Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/include/soc… File src/soc/qualcomm/qcs405/include/soc/iomap.h: https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/include/soc… PS1, Line 49: #define writel_i(v,a) write32((void *)a, v) space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/uart.c File src/soc/qualcomm/qcs405/uart.c: https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/uart.c@50 PS1, Line 50: unsigned blsp_uart; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/uart.c@54 PS1, Line 54: void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count) Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/uart.c@56 PS1, Line 56: int i; code indent should use tabs where possible https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/uart.c@56 PS1, Line 56: int i; please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/uart.c@58 PS1, Line 58: for (i = 0; i < count; i++) { code indent should use tabs where possible https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/uart.c@58 PS1, Line 58: for (i = 0; i < count; i++) { please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/uart.c@59 PS1, Line 59: gpio_configure(gpio->gpio, gpio->func, code indent should use tabs where possible https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/uart.c@59 PS1, Line 59: gpio_configure(gpio->gpio, gpio->func, please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/uart.c@60 PS1, Line 60: gpio->pull, gpio->drvstr, gpio->enable); code indent should use tabs where possible https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/uart.c@60 PS1, Line 60: gpio->pull, gpio->drvstr, gpio->enable); please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/uart.c@61 PS1, Line 61: gpio++; code indent should use tabs where possible https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/uart.c@61 PS1, Line 61: gpio++; please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/uart.c@62 PS1, Line 62: } code indent should use tabs where possible https://review.coreboot.org/#/c/29964/1/src/soc/qualcomm/qcs405/uart.c@62 PS1, Line 62: } please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/29964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9626c68eadead8b8ec5ffbc08cab7b0ec36478f Gerrit-Change-Number: 29964 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 10:16:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405:Add SPI_RAM_SIMULATION support for QCS405
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29959 ) Change subject: qcs405:Add SPI_RAM_SIMULATION support for QCS405 ...................................................................... Patch Set 1: (6 comments) https://review.coreboot.org/#/c/29959/1/src/soc/qualcomm/qcs405/flash_contr… File src/soc/qualcomm/qcs405/flash_controller.c: https://review.coreboot.org/#/c/29959/1/src/soc/qualcomm/qcs405/flash_contr… PS1, Line 37: static int ram_read(const struct spi_flash *flash, u32 addr, size_t len, void *buf) line over 80 characters https://review.coreboot.org/#/c/29959/1/src/soc/qualcomm/qcs405/flash_contr… PS1, Line 68: { that open brace { should be on the previous line https://review.coreboot.org/#/c/29959/1/src/soc/qualcomm/qcs405/flash_contr… PS1, Line 78: static char name[] = "ram_flash"; static char array declaration should probably be static const char https://review.coreboot.org/#/c/29959/1/src/soc/qualcomm/qcs405/flash_contr… PS1, Line 80: printk(BIOS_INFO, "[%s]..CONFIG_QC_SOC_SIMULATE\n", __FUNCTION__); __func__ should be used instead of gcc specific __FUNCTION__ https://review.coreboot.org/#/c/29959/1/src/soc/qualcomm/qcs405/flash_contr… PS1, Line 82: printk(BIOS_INFO, "[%s]..ram_flash\n", __FUNCTION__); __func__ should be used instead of gcc specific __FUNCTION__ https://review.coreboot.org/#/c/29959/1/src/soc/qualcomm/qcs405/mmu.c File src/soc/qualcomm/qcs405/mmu.c: https://review.coreboot.org/#/c/29959/1/src/soc/qualcomm/qcs405/mmu.c@40 PS1, Line 40: mmu_config_range((void *)0x80000000, 0x40000000, MA_MEM | MA_NS | MA_RW); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I895315a995cbbd5e6a7a305e48476f0d0f583cfe Gerrit-Change-Number: 29959 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 10:15:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405: Add GPIO API
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29955 ) Change subject: qcs405: Add GPIO API ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29955/1/src/soc/qualcomm/qcs405/include/soc… File src/soc/qualcomm/qcs405/include/soc/gpio.h: https://review.coreboot.org/#/c/29955/1/src/soc/qualcomm/qcs405/include/soc… PS1, Line 90: #define PIN(index, tlmm, func1, func2, func3, func4, func5, func6, func7) \ Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/c/coreboot/+/29955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85ce9007c545b44371c4704a0456774d0eff12a8 Gerrit-Change-Number: 29955 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 10:15:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/qualcomm/qcs405: Add MMU support
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29950 ) Change subject: soc/qualcomm/qcs405: Add MMU support ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29950/1/src/soc/qualcomm/qcs405/mmu.c File src/soc/qualcomm/qcs405/mmu.c: https://review.coreboot.org/#/c/29950/1/src/soc/qualcomm/qcs405/mmu.c@22 PS1, Line 22: void qcs405_mmu_init() Bad function definition - void qcs405_mmu_init() should probably be void qcs405_mmu_init(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/29950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c6353be2c0379ec94f91223805762a2286de06d Gerrit-Change-Number: 29950 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 10:15:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/intel/lynxpoint: Allow the flash chip to be write-protected
by Tristan Corrick (Code Review) 30 Nov '18

30 Nov '18

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29977 Change subject: sb/intel/lynxpoint: Allow the flash chip to be write-protected ...................................................................... sb/intel/lynxpoint: Allow the flash chip to be write-protected This patch is based on the bd82x6x code. Lynx Point uses the same register locations and layout for flash protection. Tested on an ASRock H81M-HDS. When write-protection is configured, flashrom reports all flash regions as read-only, and does not manage to alter the contents of the flash chip. Change-Id: I781082b1ed507b00815d1e85aec3e56ae5a4bef2 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/southbridge/intel/lynxpoint/Kconfig M src/southbridge/intel/lynxpoint/finalize.c 2 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/29977/1 diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 5b06c4b..0690972 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -59,6 +59,20 @@ If you set this option to y, the serial IRQ machine will be operated in continuous mode. +config SPI_FLASH_WRITE_PROTECT + bool "Write-protect the SPI flash during chipset lockdown" + help + Select this if you want the entire firmware flash chip to be + write-protected during chipset lockdown. This can provide a + security benefit, as malware will not be able to write to the + flash chip. However, it is important to note that ALL writes + and erases are blocked, so you will not be able to update + coreboot using flashrom's internal programmer. + + If you have configured coreboot not to run the chipset lockdown + (see `INTEL_CHIPSET_LOCKDOWN`), then the payload must initiate + the lockdown in order for this setting to take effect. + config ME_MBP_CLEAR_LATE bool "Defer wait for ME MBP Cleared" default y diff --git a/src/southbridge/intel/lynxpoint/finalize.c b/src/southbridge/intel/lynxpoint/finalize.c index 590a245..3971874 100644 --- a/src/southbridge/intel/lynxpoint/finalize.c +++ b/src/southbridge/intel/lynxpoint/finalize.c @@ -32,6 +32,13 @@ RCBA32(0x3898) = SPI_OPMENU_LOWER; RCBA32(0x389c) = SPI_OPMENU_UPPER; + if (IS_ENABLED(CONFIG_SPI_FLASH_WRITE_PROTECT)) { + int i; + for (i = 0; i <= 4; i++) + SPIBAR32(0x74 + i * 4) = + SPIBAR32(0x54 + i * 4) | (1UL << 31); + } + /* Lock SPIBAR */ RCBA32_OR(0x3804, (1 << 15)); -- To view, visit https://review.coreboot.org/c/coreboot/+/29977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I781082b1ed507b00815d1e85aec3e56ae5a4bef2 Gerrit-Change-Number: 29977 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/lynxpoint: Ensure the finalise handler is called
by Tristan Corrick (Code Review) 30 Nov '18

30 Nov '18

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29976 Change subject: sb/intel/lynxpoint: Ensure the finalise handler is called ...................................................................... sb/intel/lynxpoint: Ensure the finalise handler is called The finalise handler is not called during S3 resume when using the `BS_PAYLOAD_BOOT` approach. So, adopt the `lpc_final` approach used by bd82x6x and others. Tested on an ASRock H81M-HDS. The finalise handler is now called on the normal boot path, and during S3 resume. Change-Id: I9766a8dcbcb38420e937c810d252fef071851e92 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/smi.c 2 files changed, 8 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/29976/1 diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index ca850c0..fe5bce8 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -967,6 +967,13 @@ return current; } +static void lpc_final(struct device *dev) +{ + if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && (acpi_is_wakeup_s3() || + IS_ENABLED(CONFIG_INTEL_CHIPSET_LOCKDOWN))) { + outb(APM_CNT_FINALIZE, APM_CNT); + } +} static struct pci_operations pci_ops = { .set_subsystem = set_subsystem, @@ -981,6 +988,7 @@ .acpi_name = lpc_acpi_name, .write_acpi_tables = southbridge_write_acpi_tables, .init = lpc_init, + .final = lpc_final, .enable = pch_lpc_enable, .scan_bus = scan_lpc_bus, .ops_pci = &pci_ops, diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 5dab05c..cf70d21 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -118,17 +118,3 @@ "d" (APM_CNT) ); } - -/* - * Finalize system before payload boot if INTEL_CHIPSET_LOCKDOWN=y - */ -#if IS_ENABLED(CONFIG_INTEL_CHIPSET_LOCKDOWN) - -static void finalize_boot(void *unused) -{ - outb(APM_CNT_FINALIZE, APM_CNT); -} - -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL); - -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/29976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9766a8dcbcb38420e937c810d252fef071851e92 Gerrit-Change-Number: 29976 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/lynxpoint: Make the finalise handler common
by Tristan Corrick (Code Review) 30 Nov '18

30 Nov '18

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29975 Change subject: sb/intel/lynxpoint: Make the finalise handler common ...................................................................... sb/intel/lynxpoint: Make the finalise handler common The ASRock H81M-HDS doesn't implement a finalise handler. To fix this, and reduce code duplication in the process, make a common implementation. There should be no functional change to boards with existing finalise handlers, since the code is identical among them and the new, common implementation. Tested on an ASRock H81M-HDS. The finalise handler works. Change-Id: I13b581a2219288019a4e0c9e618db3ac7c3c15ab Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/mainboard/google/beltino/smihandler.c M src/mainboard/google/slippy/smihandler.c M src/mainboard/intel/baskingridge/mainboard_smi.c M src/southbridge/intel/lynxpoint/smihandler.c 4 files changed, 15 insertions(+), 60 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/29975/1 diff --git a/src/mainboard/google/beltino/smihandler.c b/src/mainboard/google/beltino/smihandler.c index 3d9324d..074a3e9 100644 --- a/src/mainboard/google/beltino/smihandler.c +++ b/src/mainboard/google/beltino/smihandler.c @@ -27,29 +27,6 @@ #include <superio/ite/it8772f/it8772f.h> #include "onboard.h" -static int mainboard_finalized = 0; - -int mainboard_smi_apmc(u8 apmc) -{ - switch (apmc) { - case APM_CNT_FINALIZE: - if (mainboard_finalized) { - printk(BIOS_DEBUG, "SMI#: Already finalized\n"); - return 0; - } - - intel_pch_finalize_smm(); - intel_northbridge_haswell_finalize_smm(); - intel_cpu_haswell_finalize_smm(); - - mainboard_finalized = 1; - break; - default: - break; - } - return 0; -} - void mainboard_smi_sleep(u8 slp_typ) { switch (slp_typ) { diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c index 3480147..bab764a 100644 --- a/src/mainboard/google/slippy/smihandler.c +++ b/src/mainboard/google/slippy/smihandler.c @@ -119,24 +119,9 @@ while (google_chromeec_get_event() != 0); } - -static int mainboard_finalized = 0; - int mainboard_smi_apmc(u8 apmc) { switch (apmc) { - case APM_CNT_FINALIZE: - if (mainboard_finalized) { - printk(BIOS_DEBUG, "SMI#: Already finalized\n"); - return 0; - } - - intel_pch_finalize_smm(); - intel_northbridge_haswell_finalize_smm(); - intel_cpu_haswell_finalize_smm(); - - mainboard_finalized = 1; - break; case APM_CNT_ACPI_ENABLE: google_chromeec_set_smi_mask(0); /* Clear all pending events */ diff --git a/src/mainboard/intel/baskingridge/mainboard_smi.c b/src/mainboard/intel/baskingridge/mainboard_smi.c index 229085d..0fd0639 100644 --- a/src/mainboard/intel/baskingridge/mainboard_smi.c +++ b/src/mainboard/intel/baskingridge/mainboard_smi.c @@ -46,25 +46,3 @@ break; } } - - -static int mainboard_finalized = 0; - -int mainboard_smi_apmc(u8 apmc) -{ - switch (apmc) { - case APM_CNT_FINALIZE: - if (mainboard_finalized) { - printk(BIOS_DEBUG, "SMI#: Already finalized\n"); - return 0; - } - - intel_pch_finalize_smm(); - intel_northbridge_haswell_finalize_smm(); - intel_cpu_haswell_finalize_smm(); - - mainboard_finalized = 1; - break; - } - return 0; -} diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 87848c2..bdda6dd 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -25,6 +25,8 @@ #include <elog.h> #include <halt.h> #include <pc80/mc146818rtc.h> +#include <northbridge/intel/haswell/haswell.h> +#include <cpu/intel/haswell/haswell.h> #include "pch.h" #include "nvs.h" @@ -270,11 +272,24 @@ { u8 reg8; em64t101_smm_state_save_area_t *state; + static int mainboard_finalized = 0; /* Emulate B2 register as the FADT / Linux expects it */ reg8 = inb(APM_CNT); switch (reg8) { + case APM_CNT_FINALIZE: + if (mainboard_finalized) { + printk(BIOS_DEBUG, "SMI#: Already finalized\n"); + return; + } + + intel_pch_finalize_smm(); + intel_northbridge_haswell_finalize_smm(); + intel_cpu_haswell_finalize_smm(); + + mainboard_finalized = 1; + break; case APM_CNT_CST_CONTROL: /* Calling this function seems to cause * some kind of race condition in Linux -- To view, visit https://review.coreboot.org/c/coreboot/+/29975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13b581a2219288019a4e0c9e618db3ac7c3c15ab Gerrit-Change-Number: 29975 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: qcs405 [temp]: HACK HACK for commit id for VBOOT project
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29974 Change subject: qcs405 [temp]: HACK HACK for commit id for VBOOT project ...................................................................... qcs405 [temp]: HACK HACK for commit id for VBOOT project This pacth is needed for having control over the vboot project checked out. Change-Id: I1fd040619eb996164e50705fcf16547571e99f99 Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/29974/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index 392211f..356d5f1 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 392211f0358919d510179ad399d8f056180e652e +Subproject commit 356d5f1c866655af435400da91ecb6010f96ceb9 -- To view, visit https://review.coreboot.org/c/coreboot/+/29974 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fd040619eb996164e50705fcf16547571e99f99 Gerrit-Change-Number: 29974 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

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Change in ...coreboot[master]: qcs405 [temp]: Combine BB with QC-Sec for ROM boot
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29973 Change subject: qcs405 [temp]: Combine BB with QC-Sec for ROM boot ...................................................................... qcs405 [temp]: Combine BB with QC-Sec for ROM boot Some of the changes in this patch are part of the SDM845 upstream patches. Those will be needed until the sdm845 patches are merged. After that the remaining delta would have to be patched out and pushed separately. TEST=build & run Change-Id: Ief4d92214cdc7ec06e90b0c7e73c11b6d6deddb9 Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/arch/arm64/armv8/cpu.S M src/soc/qualcomm/ipq40xx/Kconfig M src/soc/qualcomm/ipq40xx/mbn_header.h M src/soc/qualcomm/ipq806x/Makefile.inc M src/soc/qualcomm/ipq806x/mbn_header.h M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/sdm845/Makefile.inc R util/qualcomm/createxbl.py M util/qualcomm/description.md R util/qualcomm/ipqheader.py R util/qualcomm/mbn_tools.py R util/qualcomm/mbncat.py A util/qualcomm/qgpt.py M util/qualcomm/scripts/cmm/debug_cb_405.cmm M util/qualcomm/scripts/cmm/debug_cb_845.cmm M util/qualcomm/scripts/cmm/debug_cb_common.cmm M util/qualcomm/scripts/cmm/pbl32_to_bootblock64_jump.cmm 17 files changed, 483 insertions(+), 224 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/29973/1 diff --git a/src/arch/arm64/armv8/cpu.S b/src/arch/arm64/armv8/cpu.S index d3fd9d3..038e711 100644 --- a/src/arch/arm64/armv8/cpu.S +++ b/src/arch/arm64/armv8/cpu.S @@ -148,7 +148,7 @@ 2: stp x0, x0, [x1], #16 cmp x1, x2 - bne 2b + ble 2b /* Initialize stack with sentinel value to later check overflow. */ ldr x2, =0xdeadbeefdeadbeef diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig index 2cfcd2d..849d306 100644 --- a/src/soc/qualcomm/ipq40xx/Kconfig +++ b/src/soc/qualcomm/ipq40xx/Kconfig @@ -48,7 +48,7 @@ config SBL_UTIL_PATH depends on USE_BLOBS string "Path for utils to combine SBL_ELF and bootblock" - default "util/ipqheader" + default "util/qualcomm" help Path for utils to combine SBL_ELF and bootblock diff --git a/src/soc/qualcomm/ipq40xx/mbn_header.h b/src/soc/qualcomm/ipq40xx/mbn_header.h index cedcf12..a48de1c 100644 --- a/src/soc/qualcomm/ipq40xx/mbn_header.h +++ b/src/soc/qualcomm/ipq40xx/mbn_header.h @@ -18,7 +18,7 @@ #include <types.h> -/* QCA firmware blob header gleaned from util/ipqheader/ipqheader.py */ +/* QCA firmware blob header gleaned from util/qualcomm/ipqheader.py */ struct mbn_header { u32 mbn_type; diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 8a428b2..1fd134a 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -62,14 +62,14 @@ # Add MBN header to allow SBL3 to start coreboot bootblock $(objcbfs)/bootblock.mbn: $(objcbfs)/bootblock.raw.bin @printf " ADD MBN $(subst $(obj)/,,$(@))\n" - ./util/ipqheader/ipqheader.py $(call loadaddr,bootblock) $< $@.tmp + ./util/qualcomm/ipqheader.py $(call loadaddr,bootblock) $< $@.tmp @mv $@.tmp $@ # Create a complete bootblock which will start up the system $(objcbfs)/bootblock.bin: $(call strip_quotes,$(CONFIG_SBL_BLOB)) \ $(objcbfs)/bootblock.mbn @printf " MBNCAT $(subst $(obj)/,,$(@))\n" - @util/ipqheader/mbncat.py -o $@.tmp $^ + @util/qualcomm/mbncat.py -o $@.tmp $^ @mv $@.tmp $@ endif diff --git a/src/soc/qualcomm/ipq806x/mbn_header.h b/src/soc/qualcomm/ipq806x/mbn_header.h index 1e6a32f..c7b38d3 100644 --- a/src/soc/qualcomm/ipq806x/mbn_header.h +++ b/src/soc/qualcomm/ipq806x/mbn_header.h @@ -18,7 +18,7 @@ #include <types.h> -/* Qualcomm firmware blob header gleaned from util/ipqheader/ipqheader.py */ +/* Qualcomm firmware blob header gleaned from util/qualcomm/ipqheader.py */ struct mbn_header { u32 mbn_type; diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index 47ec7ca..40dcb9b 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -90,7 +90,7 @@ qc_sec_file := $(shell ls $(QC_SEC_FILE)) ifneq (,$(findstring $(QC_SEC_FILE),$(qc_sec_file))) $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.elf - @util/qualcomm/createxbl.py -f $(objcbfs)/bootblock.elf \ + @python util/qualcomm/createxbl.py -f $(objcbfs)/bootblock.elf \ -x $(QC_SEC_FILE) -o $(objcbfs)/merged_bb_qcsec.mbn \ -a 64 -d 32 -c 32 ifeq ($(CONFIG_QC_FLASH_SIMULATE_SDCARD),y) diff --git a/src/soc/qualcomm/sdm845/Makefile.inc b/src/soc/qualcomm/sdm845/Makefile.inc index 507d913..6f3f3bf 100644 --- a/src/soc/qualcomm/sdm845/Makefile.inc +++ b/src/soc/qualcomm/sdm845/Makefile.inc @@ -31,8 +31,22 @@ CPPFLAGS_common += -Isrc/soc/qualcomm/sdm845/include +SDM845_BLOB := $(top)/3rdparty/blobs/soc/qualcomm/sdm845 + +################################################################################ +QC_SEC_FILE := $(SDM845_BLOB)/qc_sec.mbn +qc_sec_file := $(shell ls $(QC_SEC_FILE)) +ifneq (,$(findstring $(QC_SEC_FILE),$(qc_sec_file))) +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.elf + @util/qualcomm/createxbl.py -f $(objcbfs)/bootblock.elf \ + -x $(QC_SEC_FILE) -o $(objcbfs)/merged_bb_qcsec.mbn \ + -a 64 -d 64 -c 64 + @util/qualcomm/qgpt.py $(objcbfs)/merged_bb_qcsec.mbn \ + $(objcbfs)/bootblock.bin +else $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin @printf "Generating: $(subst $(obj)/,,$(@))\n" cp $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin +endif endif diff --git a/util/ipqheader/createxbl.py b/util/qualcomm/createxbl.py similarity index 87% rename from util/ipqheader/createxbl.py rename to util/qualcomm/createxbl.py index 1efd8ba..655b0ec 100755 --- a/util/ipqheader/createxbl.py +++ b/util/qualcomm/createxbl.py @@ -1,4 +1,3 @@ -#!/usr/bin/env python2 #============================================================================ # #/** @file createxbl.py @@ -6,32 +5,9 @@ # GENERAL DESCRIPTION # Concatentates XBL segments into one ELF image # -# Copyright (c) 2016, The Linux Foundation. All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# * Redistributions in binary form must reproduce the above -# copyright notice, this list of conditions and the following -# disclaimer in the documentation and/or other materials provided -# with the distribution. -# * Neither the name of The Linux Foundation nor the names of its -# contributors may be used to endorse or promote products derived -# from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED -# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT -# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -# BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -# OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -# IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# Copyright 2014-2016 by QUALCOMM Technologies, Incorporated. +# All Rights Reserved. +# QUALCOMM Proprietary/GTDR # #**/ # @@ -44,7 +20,9 @@ # # when who what, where, why # -------- --- ------------------------------------------------------ -# 09/04/15 et Added -x and -d to embed xbl_sec ELF +# 04/16/16 et Appended path to import correct mbn_tools +# 11/09/15 plc Update pflag for xblsec segment +# 09/04/15 et Added -x and -d to embed xbl_sec ELF # 02/11/15 ck Fixed missing elf type check in ZI OOB feature # 11/04/14 ck Updated calls to mbn_tools functions # 10/22/14 ck Added -z option to remove out of bounds ZI segments when converting from 64 to 32 @@ -60,15 +38,19 @@ import os import sys import shutil + +# Add path to mbn_tools +sys.path.append(os.path.join(os.path.dirname(os.path.abspath(__file__)), + 'sectools','sectools','features','isc','parsegen')) import mbn_tools -PAGE_SIZE = 4096 -SEGMENT_ALIGN = 16 -ELF32_HDR_SIZE = 52 -ELF32_PHDR_SIZE = 32 -ELF64_HDR_SIZE = 64 -ELF64_PHDR_SIZE = 56 - +PAGE_SIZE = 4096 +SEGMENT_ALIGN = 16 +ELF32_HDR_SIZE = 52 +ELF32_PHDR_SIZE = 32 +ELF64_HDR_SIZE = 64 +ELF64_PHDR_SIZE = 56 +SEGMENT_ALIGN_4K = 4096 ############################################################################## # main @@ -83,7 +65,7 @@ parser.add_option("-s", "--second_filepath", action="store", type="string", dest="elf_inp_file2", help="Second ELF file to merge.") - + parser.add_option("-x", "--xbl_sec_filepath", action="store", type="string", dest="elf_inp_xbl_sec", help="Second ELF file to merge.") @@ -99,7 +81,7 @@ parser.add_option("-b", "--second_elf_arch", action="store", type="string", dest="elf_2_arch", help="Second ELF file architecture. '32' or '64'") - + parser.add_option("-d", "--xbl_sec_elf_arch", action="store", type="string", dest="elf_xbl_sec_arch", help="xbl_sec file architecture. '32' or '64'") @@ -118,7 +100,7 @@ help="Removes ZI segments that have addresses greater" + \ " than 32 bits when converting from a 64 to 32 bit ELF") - + (options, args) = parser.parse_args() if not options.elf_inp_file1: parser.error('First ELF filename not given') @@ -128,7 +110,7 @@ if not options.elf_1_arch: parser.error('First ELF architecture not given') - + if (not options.elf_1_arch == '64') and (not options.elf_1_arch == '32'): parser.error('Invalid First ELF architecture given') @@ -136,7 +118,7 @@ if options.elf_inp_file2: if (not options.elf_2_arch == '64') and (not options.elf_2_arch == '32'): parser.error('Invalid Second ELF architecture given') - + # Only evaluate elf_xbl_sec_arch if file is given if options.elf_inp_xbl_sec: if (not options.elf_xbl_sec_arch == '64') and (not options.elf_xbl_sec_arch == '32'): @@ -159,7 +141,7 @@ elf_inp_file2 = options.elf_inp_file2 else: elf_inp_file2 = "" - + # Do same for xbl_sec elf_inp_xbl_sec = options.elf_inp_xbl_sec if options.elf_inp_xbl_sec else "" @@ -179,7 +161,7 @@ is_elf2_64_bit = False else: is_elf2_64_bit = False - + if options.elf_inp_xbl_sec: if options.elf_xbl_sec_arch == '64': is_elf_xbl_sec_64_bit = True @@ -187,7 +169,7 @@ is_elf_xbl_sec_64_bit = False else: is_elf_xbl_sec_64_bit = False - + # If output ELF arch is given then set is_out_elf_64_bit accordingly. # If not then default to be input1's setting if options.elf_out_arch: @@ -207,7 +189,7 @@ mbn_type = 'elf' - header_format = 'reg' + header_format = 'reg' gen_dict['IMAGE_KEY_IMAGE_ID'] = mbn_tools.ImageType.APPSBL_IMG #gen_dict['IMAGE_KEY_IMAGE_SOURCE'] = 0 #gen_dict['IMAGE_KEY_IMAGE_DEST'] = 0 @@ -224,9 +206,9 @@ target_nonsec = target_base + "_combined_hash.mbn" - #print "Input file 1:", elf_inp_file1 - #print "Input file 2:", elf_inp_file2 - #print "Output file:", binary_out + print "Input file 1:", elf_inp_file1 + print "Input file 2:", elf_inp_file2 + print "Output file:", binary_out merge_elfs([], elf_inp_file1, @@ -238,7 +220,7 @@ is_elf_xbl_sec_64_bit, is_out_elf_64_bit, zi_oob_enabled) - + # Hash the image if user did not explicitly say not to if options.hash_image: @@ -246,21 +228,21 @@ shutil.move(merged_elf, binary_out) else: shutil.copy(merged_elf, source_elf) - - # Create hash table + + # Create hash table rv = mbn_tools.pboot_gen_elf([], source_elf, - target_hash, + target_hash, elf_out_file_name = target_phdr_elf, - secure_type = image_header_secflag) + secure_type = image_header_secflag) if rv: raise RuntimeError, "Failed to run pboot_gen_elf" # Create hash table header - rv = mbn_tools.image_header([], + rv = mbn_tools.image_header(os.environ, gen_dict, target_hash, - target_hash_hd, + target_hash_hd, image_header_secflag, elf_file_name = source_elf) if rv: @@ -269,7 +251,7 @@ files_to_cat_in_order = [target_hash_hd, target_hash] mbn_tools.concat_files (target_nonsec, files_to_cat_in_order) - # Add the hash segment into the ELF + # Add the hash segment into the ELF mbn_tools.pboot_add_hash([], target_phdr_elf, target_nonsec, @@ -287,7 +269,7 @@ ############################################################################## # merge_elfs ############################################################################## -def merge_elfs(env, +def merge_elfs(env, elf_in_file_name1, elf_in_file_name2, elf_in_file_xbl_sec, @@ -299,17 +281,17 @@ zi_oob_enabled): [elf_header1, phdr_table1] = \ - mbn_tools.preprocess_elf_file(elf_in_file_name1) + mbn_tools.preprocess_elf_file(elf_in_file_name1) # Check to make sure second file path exists before using if elf_in_file_name2 != "": [elf_header2, phdr_table2] = \ - mbn_tools.preprocess_elf_file(elf_in_file_name2) - + mbn_tools.preprocess_elf_file(elf_in_file_name2) + # Check to make sure xbl_sec file path exists before using if elf_in_file_xbl_sec != "": [elf_headerxblsec, phdr_tablexblsec] = \ - mbn_tools.preprocess_elf_file(elf_in_file_xbl_sec) + mbn_tools.preprocess_elf_file(elf_in_file_xbl_sec) # Open Files elf_in_fp1 = mbn_tools.OPEN(elf_in_file_name1, "rb") @@ -340,7 +322,7 @@ else: phdr_total_size += elf_header2.e_phnum * ELF32_PHDR_SIZE phdr_total_count += elf_header2.e_phnum - + # Account for xbl_sec header if included if elf_in_file_xbl_sec != "": phdr_total_count += 1 @@ -379,7 +361,7 @@ '\x00' + \ '\x00' + \ ('\x00' * 7)) - + # Address needs to be verified that it is not greater than 32 bits # as it is possible to go from a 64 bit elf to 32. if (elf_header1.e_entry > 0xFFFFFFFF): @@ -415,7 +397,7 @@ phdr_total_count = phdr_total_count - 1 # Do not include xbl_sec in above calculation # xbl_sec is to be treated as a single blob - + # Now it is ok to populate the ELF header and write it out out_elf_header.e_phnum = phdr_total_count @@ -492,9 +474,9 @@ exit() new_phdr.p_align = curr_phdr.p_align - - #print "i=",i - #print "phdr_offset=", phdr_offset + + print "i=",i + print "phdr_offset=", phdr_offset # update output file location to next phdr location elf_out_fp.seek(phdr_offset) @@ -502,15 +484,12 @@ phdr_offset += out_elf_header.e_phentsize inp_data_offset = curr_phdr.p_offset # used to read data from input file - -# print "inp_data_offset=" -# print inp_data_offset -# -# print "curr_phdr.p_offset=" -# print curr_phdr.p_offset -# -# print "curr_phdr.p_filesz=" -# print curr_phdr.p_filesz + print "inp_data_offset=" + print inp_data_offset + print "curr_phdr.p_offset=" + print curr_phdr.p_offset + print "curr_phdr.p_filesz=" + print curr_phdr.p_filesz # output current phdr if is_out_elf_64_bit == False: @@ -525,8 +504,14 @@ new_phdr.p_offset, new_phdr.p_filesz) + # Update segment alignment value if applicable + if new_phdr.p_align == SEGMENT_ALIGN_4K: + local_align = SEGMENT_ALIGN + else: + local_align = new_phdr.p_align + # update data segment offset to be aligned after previous segment - segment_offset += roundup(new_phdr.p_filesz, SEGMENT_ALIGN); + segment_offset += roundup(new_phdr.p_filesz, local_align); elf_in_fp1.close() # Output second elf data if applicable @@ -590,9 +575,10 @@ exit() new_phdr.p_align = curr_phdr.p_align - -# print "i=",i -# print "phdr_offset=", phdr_offset + print "i" + print i + print "phdr_offset=" + print phdr_offset # update output file location to next phdr location elf_out_fp.seek(phdr_offset) @@ -600,15 +586,12 @@ phdr_offset += out_elf_header.e_phentsize inp_data_offset = curr_phdr.p_offset # used to read data from input file - -# print "inp_data_offset=" -# print inp_data_offset -# -# print "curr_phdr.p_offset=" -# print curr_phdr.p_offset -# -# print "curr_phdr.p_filesz=" -# print curr_phdr.p_filesz + print "inp_data_offset=" + print inp_data_offset + print "curr_phdr.p_offset=" + print curr_phdr.p_offset + print "curr_phdr.p_filesz=" + print curr_phdr.p_filesz # output current phdr if is_out_elf_64_bit == False: @@ -623,28 +606,38 @@ new_phdr.p_offset, new_phdr.p_filesz) + # Update segment alignment value if applicable + if new_phdr.p_align == SEGMENT_ALIGN_4K: + local_align = SEGMENT_ALIGN + else: + local_align = new_phdr.p_align + # update data segment offset to be aligned after previous segment - segment_offset += roundup(new_phdr.p_filesz, SEGMENT_ALIGN); + segment_offset += roundup(new_phdr.p_filesz, local_align); elf_in_fp2.close() - + # Embed xbl_sec image if provided if elf_in_file_xbl_sec != "": - + # Scan pheaders in xbl_sec for segment that contains entry point address entry_seg_offset = -1 entry_addr = elf_headerxblsec.e_entry + start_addr = -1 for i in range(elf_headerxblsec.e_phnum): phdr = phdr_tablexblsec[i] - max_addr = phdr.p_vaddr + phdr.p_memsz + max_addr = phdr.p_vaddr + phdr.p_memsz - 1 if phdr.p_vaddr <= entry_addr <= max_addr: entry_seg_offset = phdr.p_offset + start_addr = phdr.p_vaddr break if entry_seg_offset == -1: print "Error: Failed to find entry point in any segment!" exit() # magical equation for program header's phys and virt addr - phys_virt_addr = entry_addr - entry_seg_offset - + # phys_virt_addr = entry_addr - entry_seg_offset + phys_virt_addr = start_addr - entry_seg_offset + print "entry_addr " + str(hex(entry_addr)) + "entry_seg_offset " + str(hex(start_addr)) + "phys_virt_addr " + str(hex(phys_virt_addr)) + if is_out_elf_64_bit: # Converting from 32 to 64 elf requires no data size validation new_phdr = mbn_tools.Elf64_Phdr('\0' * ELF64_PHDR_SIZE) @@ -654,7 +647,7 @@ new_phdr.p_paddr = phys_virt_addr new_phdr.p_filesz = os.path.getsize(elf_in_file_xbl_sec) new_phdr.p_memsz = new_phdr.p_filesz - new_phdr.p_flags = 0x5 + new_phdr.p_flags = 0x5 | (mbn_tools.MI_PBT_SWAPPED_SEGMENT << mbn_tools.MI_PBT_FLAG_SEGMENT_TYPE_SHIFT); new_phdr.p_align = 0x1000 else: # Converting from 64 to 32 elf requires data size validation @@ -663,7 +656,7 @@ new_phdr = mbn_tools.Elf32_Phdr('\0' * ELF32_PHDR_SIZE) new_phdr.p_type = 0x1 # new_phdr.p_offset = segment_offset - new_phdr.p_flags = 0x5 + new_phdr.p_flags = 0x5 | (mbn_tools.MI_PBT_SWAPPED_SEGMENT << mbn_tools.MI_PBT_FLAG_SEGMENT_TYPE_SHIFT); new_phdr.p_align = 0x1000 if phys_virt_addr > 0xFFFFFFFF: @@ -678,22 +671,22 @@ exit() new_phdr.p_filesz = os.path.getsize(elf_in_file_xbl_sec) new_phdr.p_memsz = new_phdr.p_filesz - - + + # update output file location to next phdr location elf_out_fp.seek(phdr_offset) # increment phdr_offset to next location phdr_offset += out_elf_header.e_phentsize # Copy entire xbl_sec file, so start from byte 0 - inp_data_offset = 0 - + inp_data_offset = 0 + # Output xbl_sec's phdr elf_in_file_xbl_sec if is_out_elf_64_bit == False: elf_out_fp.write(mbn_tools.Elf32_Phdr.getPackedData(new_phdr)) else: elf_out_fp.write(mbn_tools.Elf64_Phdr.getPackedData(new_phdr)) - + # Copy the ENTIRE xbl_sec image bytes_written = mbn_tools.file_copy_offset(elf_in_fpxblsec, inp_data_offset, @@ -702,10 +695,17 @@ new_phdr.p_filesz) # update data segment offset to be aligned after previous segment # Not necessary, unless appending more pheaders after this point - segment_offset += roundup(new_phdr.p_filesz, SEGMENT_ALIGN); + # Update segment alignment value if applicable + if new_phdr.p_align == SEGMENT_ALIGN_4K: + local_align = SEGMENT_ALIGN + else: + local_align = new_phdr.p_align + + segment_offset += roundup(new_phdr.p_filesz, local_align); + elf_in_fpxblsec.close() - + elf_out_fp.close() return 0 diff --git a/util/qualcomm/description.md b/util/qualcomm/description.md old mode 100644 new mode 100755 diff --git a/util/ipqheader/ipqheader.py b/util/qualcomm/ipqheader.py similarity index 100% rename from util/ipqheader/ipqheader.py rename to util/qualcomm/ipqheader.py diff --git a/util/ipqheader/mbn_tools.py b/util/qualcomm/mbn_tools.py similarity index 94% rename from util/ipqheader/mbn_tools.py rename to util/qualcomm/mbn_tools.py index c66afda..a144b23 100755 --- a/util/ipqheader/mbn_tools.py +++ b/util/qualcomm/mbn_tools.py @@ -1,38 +1,15 @@ -#!/usr/bin/env python2 +#============================================================================== +# +# Copyright (c) 2010-2013,2017 Qualcomm Technologies, Inc. +# All Rights Reserved. +# Confidential and Proprietary - Qualcomm Technologies, Inc. +# #=============================================================================== # # MBN TOOLS # # GENERAL DESCRIPTION # Contains all MBN Utilities for image generation -# -# Copyright (c) 2016, The Linux Foundation. All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# * Redistributions in binary form must reproduce the above -# copyright notice, this list of conditions and the following -# disclaimer in the documentation and/or other materials provided -# with the distribution. -# * Neither the name of The Linux Foundation nor the names of its -# contributors may be used to endorse or promote products derived -# from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED -# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT -# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -# BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -# OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -# IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# #------------------------------------------------------------------------------- # EDIT HISTORY FOR FILE # @@ -52,13 +29,12 @@ # 10/20/11 dxiang Clean up #=============================================================================== -import stat -import csv -import itertools -import struct -import os -import shutil +import copy import hashlib +import os +import re +import shutil +import struct #---------------------------------------------------------------------------- # GLOBAL VARIABLES BEGIN @@ -311,7 +287,7 @@ 1) 'X's | char * | string | 'X' bytes 2) H | unsigned short | integer | 2 bytes 3) I | unsigned int | integer | 4 bytes - + 4) Q | unsigned long | integer | 8 bytes """ #---------------------------------------------------------------------------- @@ -989,6 +965,12 @@ boot_header.cert_chain_ptr = image_dest + code_size + signature_size boot_header.cert_chain_size = cert_chain_size + # If platform image integrity check is enabled + if 'USES_PLATFORM_IMAGE_INTEGRITY_CHECK' in env: + boot_header.flash_parti_ver = 5 # version + boot_header.image_src = 0 # sig_size_qti + boot_header.image_dest_ptr = 0 # cert_chain_size_qti + # If preamble is required, output the preamble file and update the boot_header if requires_preamble is True: boot_header = image_preamble(gen_dict, preamble_file_name, boot_header, num_of_pages) @@ -1005,14 +987,16 @@ # pboot_gen_elf #---------------------------------------------------------------------------- def pboot_gen_elf(env, elf_in_file_name, - hash_out_file_name, - elf_out_file_name, - secure_type = 'non_secure', - hash_seg_max_size = None, - last_phys_addr = None, - append_xml_hdr = False, - is_sha256_algo = True, - cert_chain_size_in = CERT_CHAIN_ONEROOT_MAXSIZE): + hash_out_file_name, + elf_out_file_name, + secure_type='non_secure', + hash_seg_max_size=None, + last_phys_addr=None, + append_xml_hdr=False, + is_sha256_algo=True, + cert_chain_size_in=CERT_CHAIN_ONEROOT_MAXSIZE, + hash_pageseg_as_segment=False): + global MI_PROG_BOOT_DIGEST_SIZE if (is_sha256_algo is True): MI_PROG_BOOT_DIGEST_SIZE = 32 @@ -1090,26 +1074,41 @@ off = seg_offset + seg_size - while seg_offset < off: + # Add a single hash table entry for pageable segment + if hash_pageseg_as_segment: + elf_in_fp.seek(seg_offset) + fbuf = elf_in_fp.read(seg_size) - if seg_offset < ELF_BLOCK_ALIGN: - hash_size = seg_offset - else: - hash_size = ELF_BLOCK_ALIGN + if MI_PBT_CHECK_FLAG_TYPE(curr_phdr.p_flags) is True: + hash = generate_hash(fbuf, is_sha256_algo) + else: + hash = '\0' * MI_PROG_BOOT_DIGEST_SIZE - elf_in_fp.seek(seg_offset) - fbuf = elf_in_fp.read(hash_size) + # Write hash to file + hash_out_fp.write(hash) + hashtable_size += MI_PROG_BOOT_DIGEST_SIZE + # Add a hash table entry for each block of pageable segment + else: + while seg_offset < off: - if MI_PBT_CHECK_FLAG_TYPE(curr_phdr.p_flags) is True: - hash = generate_hash(fbuf, is_sha256_algo) - else: - hash = '\0' * MI_PROG_BOOT_DIGEST_SIZE + if seg_offset < ELF_BLOCK_ALIGN: + hash_size = seg_offset + else: + hash_size = ELF_BLOCK_ALIGN - # Write hash to file - hash_out_fp.write(hash) + elf_in_fp.seek(seg_offset) + fbuf = elf_in_fp.read(hash_size) - hashtable_size += MI_PROG_BOOT_DIGEST_SIZE - seg_offset += ELF_BLOCK_ALIGN + if MI_PBT_CHECK_FLAG_TYPE(curr_phdr.p_flags) is True: + hash = generate_hash(fbuf, is_sha256_algo) + else: + hash = '\0' * MI_PROG_BOOT_DIGEST_SIZE + + # Write hash to file + hash_out_fp.write(hash) + + hashtable_size += MI_PROG_BOOT_DIGEST_SIZE + seg_offset += ELF_BLOCK_ALIGN # Copy the hash entry for all that are PAGED segments and those that are not the PHDR type. This is for # backward tool compatibility where some images are generated using older exe tools. @@ -1165,15 +1164,15 @@ bytes_to_pad = ELF_BLOCK_ALIGN - pad_hash_segment hash_seg_end = hash_tbl_end_addr + bytes_to_pad - # Check if a shifting is required to accommodate for the hash segment. + # Check if a shifting is required to accomodate for the hash segment. # Get the minimum offset by going through the program headers. # Note that the program headers in the input file do not contain # the dummy program header for ELF + Program header, and the # program header for the hashtable. - min_offset = phdr_table[0].p_offset + min_offset = hash_seg_end #start with the minimum needed for i in range(num_phdrs): curr_phdr = phdr_table[i] - if curr_phdr.p_offset < min_offset: + if curr_phdr.p_offset < min_offset and (curr_phdr.p_type != PHDR_TYPE): # discard entry of type PHDR which will have offset=0: min_offset = curr_phdr.p_offset if min_offset < hash_seg_end: @@ -1443,6 +1442,11 @@ [elf_header, phdr_table] = preprocess_elf_file(elf_in_file_name) segment_list = readSCL(scl_file_name, env['GLOBAL_DICT']) + if 'USES_FEATURE_DYNAMIC_LOADING' in env: + sub = 1 + else: + sub = 0 + if elf_header.e_ident[ELFINFO_CLASS_INDEX] == ELFINFO_CLASS_64: curr_phdr = Elf64_Phdr('\0' * ELF64_PHDR_SIZE) # Offset into program header where the p_flags field is stored @@ -1456,14 +1460,14 @@ elf_in_fp = OPEN(elf_in_file_name, "r+") # Check for corresponding number of segments - if len(segment_list) is not elf_header.e_phnum: + if len(segment_list) is not (elf_header.e_phnum -sub): raise RuntimeError, 'SCL file and ELF file have different number of segments!' # Go to the start of the p_flag entry in the first program header file_offset = elf_header.e_phoff + phdr_flag_off # Change each program header flag in the ELF file based off the SCL file - for i in range(elf_header.e_phnum): + for i in range(elf_header.e_phnum -sub): # Seek to correct location and create new p_flag value elf_in_fp.seek(file_offset) curr_phdr = phdr_table[i] @@ -1810,8 +1814,8 @@ # Get file names for 'cust' and 'targ' auto-generated files inside 'build/ms' cust_h = env.subst('CUST${BUILD_ID}.H').lower() targ_h = env.subst('TARG${BUILD_ID}.H').lower() - cust_file_name = str(env.FindFile(cust_h, "${INC_ROOT}/build/ms")) - targ_file_name = str(env.FindFile(targ_h, "${INC_ROOT}/build/ms")) + cust_file_name = str(env.FindFile(cust_h, "${INC_ROOT}/build/ms").abspath) + targ_file_name = str(env.FindFile(targ_h, "${INC_ROOT}/build/ms").abspath) # Check that files are present if (os.path.exists(cust_file_name) is True) and \ @@ -1834,45 +1838,36 @@ raise RuntimeError, "At least 1 file must be specified as an input" global_dict = {} - Fields = ["Define", "Key", "Value"] # For each input file for i in range(len(args)): + with open(args[i]) as fp: + for line in fp: + temp = re.findall('\#define[ ]+(\w+)([ ]+[^\n]+)*', line.strip()) + if (1 == len(temp)): + k, v = temp[0] + k = k.strip() + v = v.strip() + if 0 == len(v): + # If value pair is empty string, assume feature definition is true + global_dict[k] = 'yes' + continue - template_file_path = args[i] - instream = OPEN(template_file_path, 'r') - # Tokenize each line with a white space - values = csv.DictReader(instream, Fields, delimiter=" ") + if global_dict is not None and len(global_dict.keys()) > 0: + # Check for and handle text replacements as we parse + all_keys = copy.copy(global_dict.keys()) + all_keys.sort(key=lambda x: len(x), reverse=True) + for x in all_keys: + v = v.replace(x, str(global_dict[x])) - for values in itertools.izip(values): - new_entry = values[0] - # Verify the parsed tokens - if (new_entry['Define'] == '#define') and \ - (new_entry['Key'] != None) and \ - (new_entry['Value'] != None): + # Attempt to evaluate value + try: + v = eval(v) + # Catch exceptions and do not evaluate + except: + pass - new_key = new_entry['Key'].strip() - new_value = new_entry['Value'].strip() - - # If value pair is empty string, assume feature definition is true - if new_value == '': - new_value = 'yes' - - # Check for and handle text replacements as we parse - if global_dict is not None and len(global_dict.keys()) > 0: - for key in global_dict: - new_value = new_value.replace(key, str(global_dict.get(key))) - - # Attempt to evaluate value - try: - new_value = eval(new_value) - # Catch exceptions and do not evaluate - except: - pass - - # Add to global dictionary - global_dict[new_key] = new_value - instream.close() + global_dict[k] = v return global_dict @@ -2224,25 +2219,25 @@ #generate new file for appending target data + required MCs file = open(target, "ab") + filedata_till_128kb = filedata[0:VIRTUAL_BLOCK_SIZE] + filedata_after_128kb = filedata[VIRTUAL_BLOCK_SIZE:length] + + a = str(hex(FLASH_CODE_WORD)) + mc1 = chr(int(a[8:10],16)) + chr(int(a[6:8],16)) + chr(int(a[4:6],16)) + chr(int(a[2:4],16)) + + b = str(hex(MAGIC_NUM)) + mc2 = chr(int(b[8:10],16)) + chr(int(b[6:8],16)) + chr(int(b[4:6],16)) + chr(int(b[2:4],16)) + + c = str(hex(SBL_VIRTUAL_BLOCK_MAGIC_NUM)) + mc3 = chr(int(c[8:10],16)) + chr(int(c[6:8],16)) + chr(int(c[4:6],16)) + chr(int(c[2:4],16)) + while length > VIRTUAL_BLOCK_SIZE: + file.write(filedata_till_128kb) + filedata = mc1 + mc2 + mc3 + filedata_after_128kb + length = len(filedata) filedata_till_128kb = filedata[0:VIRTUAL_BLOCK_SIZE] filedata_after_128kb = filedata[VIRTUAL_BLOCK_SIZE:length] - a = str(hex(FLASH_CODE_WORD)) - mc1 = chr(int(a[8:10],16)) + chr(int(a[6:8],16)) + chr(int(a[4:6],16)) + chr(int(a[2:4],16)) - - b = str(hex(MAGIC_NUM)) - mc2 = chr(int(b[8:10],16)) + chr(int(b[6:8],16)) + chr(int(b[4:6],16)) + chr(int(b[2:4],16)) - - c = str(hex(SBL_VIRTUAL_BLOCK_MAGIC_NUM)) - mc3 = chr(int(c[8:10],16)) + chr(int(c[6:8],16)) + chr(int(c[4:6],16)) + chr(int(c[2:4],16)) - - MC_inserted_data = filedata_till_128kb + mc1 + mc2 + mc3 - file.write(MC_inserted_data) - - filedata = filedata_after_128kb - length = len(filedata) - #copy the leftover data (<128KB) in output file if length > 0: file.write(filedata) @@ -2313,3 +2308,4 @@ #---------------------------------------------------------------------------- # HELPER FUNCTIONS END #---------------------------------------------------------------------------- + diff --git a/util/ipqheader/mbncat.py b/util/qualcomm/mbncat.py similarity index 100% rename from util/ipqheader/mbncat.py rename to util/qualcomm/mbncat.py diff --git a/util/qualcomm/qgpt.py b/util/qualcomm/qgpt.py new file mode 100755 index 0000000..596ec54 --- /dev/null +++ b/util/qualcomm/qgpt.py @@ -0,0 +1,249 @@ +#!/usr/bin/python +#============================================================================ +# +#/** @file qgpt.py +# +# GENERAL DESCRIPTION +# Generates QCom GPT header for wrapping Bootblock +# +# Copyright (c) 2018, The Linux Foundation. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above +# copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided +# with the distribution. +# * Neither the name of The Linux Foundation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS +# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +# BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +# OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +# IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +#**/ +# + +import os +import math +import random +import re +import struct +import sys +import tempfile + +from binascii import crc32 +from optparse import OptionParser +from types import * + + +def UpdateMBR(options, GPTBlobBuffer): + i = 0x1BE + GPTBlobBuffer[i + 0] = 0x00 # not bootable + GPTBlobBuffer[i + 1] = 0x00 # head + GPTBlobBuffer[i + 2] = 0x01 # sector + GPTBlobBuffer[i + 3] = 0x00 # cylinder + GPTBlobBuffer[i + 4] = 0xEE # type + GPTBlobBuffer[i + 5] = 0xFF # head + GPTBlobBuffer[i + 6] = 0xFF # sector + GPTBlobBuffer[i + 7] = 0xFF # cylinder + GPTBlobBuffer[i + 8:i + 8 + 4] = [0x01, 0x00, 0x00, 0x00] + + GPTBlobBuffer[i + 12:i + 16] = [0x00, 0x0f, 0x00, 0x00] + + # magic byte for MBR partitioning - always at this location regardless of + # options.sector + GPTBlobBuffer[510:512] = [0x55, 0xAA] + return i + + +def UpdatePartitionEntry(options, GPTBlobBuffer): + + i = 2 * options.sector_size + # GUID of Boot Block + GPTBlobBuffer[i:i + 16] = [0x2c, 0xba, 0xa0, 0xde, 0xdd, 0xcb, 0x05, 0x48, + 0xb4, 0xf9, 0xf4, 0x28, 0x25, 0x1c, 0x3e, 0x98] + i += 16 + + #This is to set Unique Partition GUID. Below Hex Value is : 00ChezaBootblock00 + UniquePartitionGUID = 0x6b636f6c62746f6f42617a65684300 + + for b in range(16): + GPTBlobBuffer[i] = ((UniquePartitionGUID >> (b * 8)) & 0xFF) + i += 1 + + # LBA of BootBlock Start Content + GPTBlobBuffer[i:i + 8] = [0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00] + i += 8 + + # End LBA of BootBlock Content + GPTBlobBuffer[i] = options.end_lba & 0xFF + GPTBlobBuffer[i+1] = (options.end_lba>>8) & 0xFF + GPTBlobBuffer[i+2] = (options.end_lba>>16) & 0xFF + GPTBlobBuffer[i+3] = (options.end_lba>>24) & 0xFF + GPTBlobBuffer[i+4] = (options.end_lba>>32) & 0xFF + GPTBlobBuffer[i+5] = (options.end_lba>>40) & 0xFF + GPTBlobBuffer[i+6] = (options.end_lba>>48) & 0xFF + GPTBlobBuffer[i+7] = (options.end_lba>>56) & 0xFF + i += 8 + + # Attributes + GPTBlobBuffer[i:i + 8] = [0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00] + i += 8 + + # Lable + GPTBlobBuffer[i:i + 17] = [0x62, 0x00, 0x6f, 0x00, 0x6f, 0x00, 0x74, 0x00, + 0x62, 0x00, 0x6c, 0x00, 0x6f, 0x00, 0x63, 0x00, 0x6b] + + return i + +def UpdateGPTHeader(options, GPTBlobBuffer): + + i = options.sector_size + # Signature and Revision and HeaderSize i.e. "EFI PART" and 00 00 01 00 + # and 5C 00 00 00 + GPTBlobBuffer[i:i + 16] = [0x45, 0x46, 0x49, 0x20, 0x50, 0x41, 0x52, 0x54, + 0x00, 0x00, 0x01, 0x00, 0x5C, 0x00, 0x00, 0x00] + i += 16 + + # CRC is zeroed out till calculated later + GPTBlobBuffer[i:i + 4] = [0x00, 0x00, 0x00, 0x00] + i += 4 + + # Reserved, set to 0 + GPTBlobBuffer[i:i + 4] = [0x00, 0x00, 0x00, 0x00] + i += 4 + + # Current LBA + GPTBlobBuffer[i:i + 8] = [0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00] + i += 8 + + # Backup LBA, No Backup Gpt Used + GPTBlobBuffer[i:i + 8] = [0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00] + i += 8 + + # First Usuable LBA (qc_sec + bootblock location) + GPTBlobBuffer[i:i + 8] = [0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00] + i += 8 + + # Last Usuable LBA (qc_sec + bootblock end location) + GPTBlobBuffer[i] = options.end_lba & 0xFF + GPTBlobBuffer[i+1] = (options.end_lba>>8) & 0xFF + GPTBlobBuffer[i+2] = (options.end_lba>>16) & 0xFF + GPTBlobBuffer[i+3] = (options.end_lba>>24) & 0xFF + GPTBlobBuffer[i+4] = (options.end_lba>>32) & 0xFF + GPTBlobBuffer[i+5] = (options.end_lba>>40) & 0xFF + GPTBlobBuffer[i+6] = (options.end_lba>>48) & 0xFF + GPTBlobBuffer[i+7] = (options.end_lba>>56) & 0xFF + i += 8 + + # GUID + GPTBlobBuffer[i:i + 16] = [0x32,0x1B,0x10,0x98,0xE2,0xBB,0xF2,0x4B, + 0xA0,0x6E,0x2B,0xB3,0x3D,0x00,0x0C,0x20] + i += 16 + + # Partition Table Entry LBA + GPTBlobBuffer[i:i + 8] = [0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00] + i += 8 + + # Number of Partition Entries + GPTBlobBuffer[i:i + 4] = [0x01, 0x00, 0x00, 0x00] + i += 4 + + # Size of One Partition Entry + GPTBlobBuffer[i:i + 4] = [0x80, 0x00, 0x00, 0x00] + i += 4 + + # CRC of Partition Entry + + PartEntry = GPTBlobBuffer[options.sector_size*2:options.sector_size*2 + 128] + CalcEntryCRC = crc32(''.join(struct.pack("B", x) for x in PartEntry)) + + GPTBlobBuffer[i] = CalcEntryCRC & 0xFF + GPTBlobBuffer[i+1] = (CalcEntryCRC>>8) & 0xFF + GPTBlobBuffer[i+2] = (CalcEntryCRC>>16) & 0xFF + GPTBlobBuffer[i+3] = (CalcEntryCRC>>24) & 0xFF + i += 4 + + # CRC of Partition Table Header + GPTHeader = GPTBlobBuffer[options.sector_size:options.sector_size + 92] + CalcEntryCRC = crc32(''.join(struct.pack("B", x) for x in GPTHeader)) + i = options.sector_size + 16 + + GPTBlobBuffer[i] = CalcEntryCRC & 0xFF + GPTBlobBuffer[i+1] = (CalcEntryCRC>>8) & 0xFF + GPTBlobBuffer[i+2] = (CalcEntryCRC>>16) & 0xFF + GPTBlobBuffer[i+3] = (CalcEntryCRC>>24) & 0xFF + + return i + + +def openfile(name, perm): + try: + f = open(name, perm) + except: + print("could not open path {0}".format(name)) + print("Do you have read permissions on the path?") + sys.exit(1) + return f + + +if __name__ == '__main__': + usage = 'usage: %prog [OPTIONS] INFILE OUTFILE\n\n' + \ + 'Packages IMAGE in a GPT format.' + parser = OptionParser(usage) + parser.add_option('-s', type="int", dest='sector_size', default=4096, + help='Sector size in bytes [Default:4096(4KB)]', + metavar='SIZE') + + (options, args) = parser.parse_args() + if len(args) != 2: + print("Invalid arguments! Exiting...\n") + parser.print_help() + sys.exit(1) + + if options.sector_size != 4096 and options.sector_size != 512: + print("Invalid Sector Size") + sys.exit(1) + + options.inputfile = args[0] + options.outputfile = args[1] + + try: + statinfo = os.stat(options.inputfile) + except OSError as err: + print('OS Error: {0}'.format(err)) + sys.exit(1) + + # 3(MBR+GPT+PART_ENTRY) + 1(if the input file size is not perfect division of sector size) + options.end_lba = (statinfo.st_size/options.sector_size)+4 + + + GPTBlobBuffer = [0] * (options.sector_size*3) #Size of MBR+GPT+PART_ENTRY + + UpdateMBR(options, GPTBlobBuffer) + + UpdatePartitionEntry(options, GPTBlobBuffer) + + UpdateGPTHeader(options, GPTBlobBuffer) + + fin = openfile(options.inputfile, 'r+') + fout = openfile(options.outputfile, 'wb') + for b in GPTBlobBuffer: + fout.write(struct.pack("B", b)) + bb_buffer = fin.read(statinfo.st_size) + fout.write(bb_buffer) + fout.close() + fin.close() diff --git a/util/qualcomm/scripts/cmm/debug_cb_405.cmm b/util/qualcomm/scripts/cmm/debug_cb_405.cmm old mode 100644 new mode 100755 diff --git a/util/qualcomm/scripts/cmm/debug_cb_845.cmm b/util/qualcomm/scripts/cmm/debug_cb_845.cmm old mode 100644 new mode 100755 diff --git a/util/qualcomm/scripts/cmm/debug_cb_common.cmm b/util/qualcomm/scripts/cmm/debug_cb_common.cmm old mode 100644 new mode 100755 diff --git a/util/qualcomm/scripts/cmm/pbl32_to_bootblock64_jump.cmm b/util/qualcomm/scripts/cmm/pbl32_to_bootblock64_jump.cmm old mode 100644 new mode 100755 -- To view, visit https://review.coreboot.org/c/coreboot/+/29973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief4d92214cdc7ec06e90b0c7e73c11b6d6deddb9 Gerrit-Change-Number: 29973 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: qcs405 [temp]: REMOVE HACK HACK depthcharge/vboot
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29972 Change subject: qcs405 [temp]: REMOVE HACK HACK depthcharge/vboot ...................................................................... qcs405 [temp]: REMOVE HACK HACK depthcharge/vboot Change-Id: Ia520e50d359018ef0a1342d1c98bee8521986139 --- M payloads/external/depthcharge/Makefile A payloads/external/depthcharge/depthcharge 2 files changed, 7 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/29972/1 diff --git a/payloads/external/depthcharge/Makefile b/payloads/external/depthcharge/Makefile index c1993e4..0411c8f 100644 --- a/payloads/external/depthcharge/Makefile +++ b/payloads/external/depthcharge/Makefile @@ -37,7 +37,7 @@ $(project_dir): @echo " Cloning $(project_name) from Git" - @git clone $(project_git_repo) $(project_name) + #@git clone $(project_git_repo) $(project_name) fetch: $(project_dir) @cd $(project_dir); \ @@ -45,7 +45,7 @@ if [ $$? -ne 0 ] || \ [ "$(TAG-y)" = "origin/master" ]; then \ echo " Fetching new commits from the $(project_name) git repo"; \ - git fetch; fi + fi # Check out the requested version of the tree # Don't write a file for master branch so the latest remote version is always used @@ -54,9 +54,9 @@ echo " Checking out $(project_name) revision $(TAG-y)" rm -f $(project_dir)/.version_* cd $(project_dir); \ - git checkout master; \ - git branch -D coreboot 2>/dev/null; \ - git checkout -b coreboot $(TAG-y) + echo git1 \ + echo git2 \ + echo git3 ifneq ($(DEPTHCHARGE_MASTER),y) touch $(project_dir)/.version_$(TAG-y) endif @@ -92,7 +92,7 @@ rm -rf $(output_dir) distclean: - rm -rf $(project_dir) + rm -rf $(output_dir) print-repo-info: echo "$(project_git_repo) $(project_dir)" diff --git a/payloads/external/depthcharge/depthcharge b/payloads/external/depthcharge/depthcharge new file mode 120000 index 0000000..ecdeb4a --- /dev/null +++ b/payloads/external/depthcharge/depthcharge @@ -0,0 +1 @@ +../../../../depthcharge/ \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/29972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia520e50d359018ef0a1342d1c98bee8521986139 Gerrit-Change-Number: 29972 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: qcs405: Clear bss for bootblock
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29971 Change subject: qcs405: Clear bss for bootblock ...................................................................... qcs405: Clear bss for bootblock Looks like bss is not zero cleared, resulting in unintialized section to have junk data values. So clear it up before jumping to 'C' code. Change-Id: I1b751ced2c948f45a7b365b695eb95869dfcdc29 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/arch/arm64/armv8/cpu.S 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/29971/1 diff --git a/src/arch/arm64/armv8/cpu.S b/src/arch/arm64/armv8/cpu.S index 935f1fe..d3fd9d3 100644 --- a/src/arch/arm64/armv8/cpu.S +++ b/src/arch/arm64/armv8/cpu.S @@ -141,6 +141,15 @@ dsb sy isb + /* Finally clear the bss here */ + ldr x1, =_bss + ldr x2, =_ebss + mov x0, #0 +2: + stp x0, x0, [x1], #16 + cmp x1, x2 + bne 2b + /* Initialize stack with sentinel value to later check overflow. */ ldr x2, =0xdeadbeefdeadbeef ldr x0, =_stack -- To view, visit https://review.coreboot.org/c/coreboot/+/29971 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b751ced2c948f45a7b365b695eb95869dfcdc29 Gerrit-Change-Number: 29971 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: Mistral: QCS405: Added RPM support
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29970 Change subject: Mistral: QCS405: Added RPM support ...................................................................... Mistral: QCS405: Added RPM support This pacth adds support to read RPM image from 3rdparty/blobs and load it. It takes RPM out of reset. Change-Id: I17f491f0a4bd0dce7522b7e80e1bac97ec18b945 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/include/soc/clock.h M src/soc/qualcomm/qcs405/include/soc/memlayout.ld A src/soc/qualcomm/qcs405/include/soc/rpm.h M src/soc/qualcomm/qcs405/include/soc/symbols.h M src/soc/qualcomm/qcs405/mmu.c A src/soc/qualcomm/qcs405/rpm_load_reset.c M src/soc/qualcomm/qcs405/soc.c 9 files changed, 105 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/29970/1 diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index ee68751..47ec7ca 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -38,6 +38,7 @@ ramstage-y += gpio.c ramstage-y += clock.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c +ramstage-y += rpm_load_reset.c ramstage-y += usb.c ramstage-y += flash_controller.c @@ -74,6 +75,17 @@ endif ################################################################################ +RPM_FILE := $(QCS405_BLOB)/rpm.mbn +rpm_file := $(shell ls $(RPM_FILE)) +ifneq (,$(findstring $(RPM_FILE),$(rpm_file))) + RPM_CBFS := $(CONFIG_CBFS_PREFIX)/rpm + $(RPM_CBFS)-file := $(RPM_FILE) + $(RPM_CBFS)-type := payload + $(RPM_CBFS)-compression := $(CBFS_COMPRESS_FLAG) + cbfs-files-y += $(RPM_CBFS) +endif + +################################################################################ QC_SEC_FILE := $(QCS405_BLOB)/qc_sec.mbn qc_sec_file := $(shell ls $(QC_SEC_FILE)) ifneq (,$(findstring $(QC_SEC_FILE),$(qc_sec_file))) diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index f26face..a129613 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -175,6 +175,13 @@ return 0; } +void clock_reset_rpm(void) +{ + /* Bring RPM out of RESET */ + + clrbits_le32(REG(GCC_APSS_MISC), BIT(RPM_RESET_REMOVAL)); +} + int clock_reset_bcr(void *bcr_addr, bool reset) { struct qcs405_bcr *bcr = bcr_addr; diff --git a/src/soc/qualcomm/qcs405/include/soc/clock.h b/src/soc/qualcomm/qcs405/include/soc/clock.h index d02ecd7..2736133 100644 --- a/src/soc/qualcomm/qcs405/include/soc/clock.h +++ b/src/soc/qualcomm/qcs405/include/soc/clock.h @@ -16,6 +16,8 @@ #define __SOC_QUALCOMM_QCS405_CLOCK_H__ #define GCC_APCS_CLOCK_BRANCH_ENA_VOTE 0x01845004 +#define GCC_APSS_MISC 0x1860000 +#define RPM_RESET_REMOVAL 0 #define GCC_BLSP1_UART0_BASE 0x180600C #define GCC_BLSP1_UART1_BASE 0x1802044 @@ -143,7 +145,7 @@ }; void clock_init(void); -void clock_reset_aop(void); +void clock_reset_rpm(void); int clock_configure_qspi(uint32_t hz); int clock_reset_bcr(void *bcr_addr, bool reset); diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld index 8566f9f..9e7df11 100644 --- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld +++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld @@ -24,8 +24,16 @@ #define BSRAM_START(addr) SYMBOL(bsram, addr) #define BSRAM_END(addr) SYMBOL(ebsram, addr) +/* RPM : 0x0B000000 - 0x0B100000 */ +#define RPMSRAM_START(addr) SYMBOL(rpmsram, addr) +#define RPMSRAM_END(addr) SYMBOL(rpmsram, addr) + SECTIONS { + RPMSRAM_START(0x00200000) + REGION(rpm, 0x00200000, 0xA4000, 0x0) + RPMSRAM_END(0x02A4000) + SSRAM_START(0x8600000) SSRAM_END(0x8608000) diff --git a/src/soc/qualcomm/qcs405/include/soc/rpm.h b/src/soc/qualcomm/qcs405/include/soc/rpm.h new file mode 100644 index 0000000..e83253f --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/rpm.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_QCS405_RPM_H__ +#define _SOC_QUALCOMM_QCS405_RPM_H__ + +void rpm_fw_load_reset(void); + +#endif // _SOC_QUALCOMM_QCS405_RPM_H__ diff --git a/src/soc/qualcomm/qcs405/include/soc/symbols.h b/src/soc/qualcomm/qcs405/include/soc/symbols.h index 447b7ae..74ba170 100644 --- a/src/soc/qualcomm/qcs405/include/soc/symbols.h +++ b/src/soc/qualcomm/qcs405/include/soc/symbols.h @@ -38,4 +38,8 @@ extern u8 _epmic[]; #define _pmic_size (_epmic - _pmic) +extern u8 _rpm[]; +extern u8 _erpm[]; +#define _rpm_size (_erpm - _rpm) + #endif // _SOC_QUALCOMM_QCS405_SYMBOLS_H_ diff --git a/src/soc/qualcomm/qcs405/mmu.c b/src/soc/qualcomm/qcs405/mmu.c index ecae39f..1cf4a36 100644 --- a/src/soc/qualcomm/qcs405/mmu.c +++ b/src/soc/qualcomm/qcs405/mmu.c @@ -28,6 +28,7 @@ mmu_config_range((void *)_ssram, _ssram_size, MA_MEM | MA_S | MA_RW); mmu_config_range((void *)_bsram, _bsram_size, MA_MEM | MA_S | MA_RW); mmu_config_range((void *)0x80000000, 0x40000000, MA_MEM | MA_S | MA_RW); + mmu_config_range((void *)_rpm, _rpm_size, MA_MEM | MA_NS | MA_RW); mmu_enable(); } @@ -35,4 +36,5 @@ void qcs405_mmu_dram_config_c(void) { mmu_config_range((void *)0x80000000, 0x40000000, MA_MEM | MA_NS | MA_RW); + mmu_config_range((void *)_rpm, _rpm_size, MA_MEM | MA_NS | MA_RW); } diff --git a/src/soc/qualcomm/qcs405/rpm_load_reset.c b/src/soc/qualcomm/qcs405/rpm_load_reset.c new file mode 100644 index 0000000..d0dac3f --- /dev/null +++ b/src/soc/qualcomm/qcs405/rpm_load_reset.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <arch/cache.h> +#include <cbfs.h> +#include <halt.h> +#include <console/console.h> +#include <timestamp.h> +#include <soc/mmu.h> +#include <soc/rpm.h> +#include <soc/clock.h> + +void rpm_fw_load_reset(void) +{ + bool rpm_fw_entry; + + struct prog rpm_fw_prog = + PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/rpm"); + printk(BIOS_DEBUG, "\nNIT:PROG_INIT for /rpm has happened.\n"); + + if (prog_locate(&rpm_fw_prog)) + die("SOC image: RPM_FW not found"); + printk(BIOS_DEBUG, "\nNIT:PROG_LOCATE for /rpm has happened.\n"); + + rpm_fw_entry = selfload(&rpm_fw_prog); + if (!rpm_fw_entry) + die("SOC image: RPM load failed"); + printk(BIOS_DEBUG, "\nNIT:SELF_LOAD of rpm has happened.\n"); + + clock_reset_rpm(); + + printk(BIOS_DEBUG, "\nSOC:RPM brought out of reset.\n"); +} diff --git a/src/soc/qualcomm/qcs405/soc.c b/src/soc/qualcomm/qcs405/soc.c index 3de3c02..9be1bdc 100644 --- a/src/soc/qualcomm/qcs405/soc.c +++ b/src/soc/qualcomm/qcs405/soc.c @@ -18,6 +18,7 @@ #include <timestamp.h> #include <soc/mmu.h> #include <soc/symbols.h> +#include <soc/rpm.h> static void soc_read_resources(device_t dev) { @@ -28,7 +29,7 @@ static void soc_init(device_t dev) { - + rpm_fw_load_reset(); } static struct device_operations soc_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/29970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17f491f0a4bd0dce7522b7e80e1bac97ec18b945 Gerrit-Change-Number: 29970 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: qcs405: memlayout: Make bootblock 64k aligned
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29969 Change subject: qcs405: memlayout: Make bootblock 64k aligned ...................................................................... qcs405: memlayout: Make bootblock 64k aligned The qc_sec in qcs405 excepts that bootblock to be 64k aligned. So adjust the memlayout accordingly. Change-Id: I1599242bb5158477318867508c72dc14f1244b00 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/arch/arm64/armv8/bootblock.S M src/soc/qualcomm/qcs405/include/soc/memlayout.ld 2 files changed, 15 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/29969/1 diff --git a/src/arch/arm64/armv8/bootblock.S b/src/arch/arm64/armv8/bootblock.S index e5758bc..7dc8b0f 100644 --- a/src/arch/arm64/armv8/bootblock.S +++ b/src/arch/arm64/armv8/bootblock.S @@ -23,7 +23,9 @@ ENTRY(_start) /* Initialize PSTATE, SCTLR and caches to clean state, set up stack. */ - bl arm64_init_cpu + ldr x15, =arm64_init_cpu + blr x15 - bl main + ldr x15, =main + blr x15 ENDPROC(_start) diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld index dadbbe8..8566f9f 100644 --- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld +++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld @@ -31,17 +31,17 @@ BSRAM_START(0x8C00000) REGION(fw_reserved2, 0x8C00000, 0x16000, 4096) - OVERLAP_VERSTAGE_ROMSTAGE(0x8C16000, 100K) - BOOTBLOCK(0x8C2F000, 40K) - TTB(0x8C39000, 56K) - VBOOT2_WORK(0x8C47000, 16K) - STACK(0x8C4B000, 16K) - TIMESTAMP(0x8C4F000, 1K) - PRERAM_CBMEM_CONSOLE(0x8C4F400, 32K) - PRERAM_CBFS_CACHE(0x8C57400, 70K) - //REGION(bsram_unused, 0x8C68C00, 0xA2400, 0x100) - REGION(qclib, 0x8C69000, 0x80000, 4096) - REGION(dcb, 0x8CE9000, 0x4000, 4096) + OVERLAP_VERSTAGE_ROMSTAGE(0x8C16000, 104K) + BOOTBLOCK(0x8C30000, 40K) + TTB(0x8C3a000, 56K) + VBOOT2_WORK(0x8C48000, 16K) + STACK(0x8C4c000, 16K) + TIMESTAMP(0x8C50000, 1K) + PRERAM_CBMEM_CONSOLE(0x8C50400, 32K) + PRERAM_CBFS_CACHE(0x8C58400, 70K) + //REGION(bsram_unused, 0x8C69C00, 0xA2400, 0x100) + REGION(qclib, 0x8C6a000, 0x80000, 4096) + //REGION(dcb, 0x8CEa000, 0x4000, 4096) REGION(pmic, 0x8CED000, 0x10000, 4096) BSRAM_END(0x8D80000) -- To view, visit https://review.coreboot.org/c/coreboot/+/29969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1599242bb5158477318867508c72dc14f1244b00 Gerrit-Change-Number: 29969 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: qcs405: Add blsp spi driver and enable SPI-NOR
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29968 Change subject: qcs405: Add blsp spi driver and enable SPI-NOR ...................................................................... qcs405: Add blsp spi driver and enable SPI-NOR Add the blsp spi driver required for qcs405 and also enable the support for WINBOND spi-nor flash Change-Id: I340eb3bf77b25fe3502d4b29ef4bf7c06b282c02 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/mainboard/google/mistral/Kconfig M src/soc/qualcomm/qcs405/Kconfig M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/include/soc/mmu.h A src/soc/qualcomm/qcs405/include/soc/qup.h A src/soc/qualcomm/qcs405/include/soc/spi.h M src/soc/qualcomm/qcs405/spi.c 8 files changed, 1,138 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/29968/1 diff --git a/src/mainboard/google/mistral/Kconfig b/src/mainboard/google/mistral/Kconfig index f8e8ac7..b614a37 100644 --- a/src/mainboard/google/mistral/Kconfig +++ b/src/mainboard/google/mistral/Kconfig @@ -10,6 +10,8 @@ select COMMON_CBFS_SPI_WRAPPER select SOC_QUALCOMM_QCS405 select SPI_FLASH + select SPI_FLASH_GIGADEVICE + select SPI_FLASH_WINBOND select MAINBOARD_HAS_CHROMEOS select MISSING_BOARD_RESET diff --git a/src/soc/qualcomm/qcs405/Kconfig b/src/soc/qualcomm/qcs405/Kconfig index b24dc9e..29960d4 100644 --- a/src/soc/qualcomm/qcs405/Kconfig +++ b/src/soc/qualcomm/qcs405/Kconfig @@ -21,9 +21,13 @@ select VBOOT_OPROM_MATTERS select VBOOT_STARTS_IN_BOOTBLOCK -config QC_SOC_SIMULATE - bool - prompt "Build for Early Simulation Environment" - default y +config QCS405_BLSP_SPI + bool + default y + prompt "Build Flash Using SPI-NOR" + +config BOOT_DEVICE_SPI_FLASH_BUS + int + default 5 endif diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index 5e255e2..ee68751 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -9,14 +9,14 @@ bootblock-y += gpio.c bootblock-y += clock.c bootblock-$(CONFIG_DRIVERS_UART) += uart.c -bootblock-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c +bootblock-y += flash_controller.c ################################################################################ verstage-y += spi.c verstage-y += timer.c verstage-y += gpio.c verstage-$(CONFIG_DRIVERS_UART) += uart.c -verstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c +verstage-y += flash_controller.c ################################################################################ romstage-y += spi.c @@ -26,9 +26,9 @@ romstage-y += clock.c romstage-y += mmu.c romstage-$(CONFIG_DRIVERS_UART) += uart.c -romstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c romstage-y += usb.c romstage-y += qclib_execute.c +romstage-y+= flash_controller.c ################################################################################ ramstage-y += soc.c @@ -38,8 +38,8 @@ ramstage-y += gpio.c ramstage-y += clock.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c -ramstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c ramstage-y += usb.c +ramstage-y += flash_controller.c ################################################################################ diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index 6307259..f26face 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -203,6 +203,8 @@ clock_configure(blsp2_qup0_spi_clk, spi_cfg, 50000000, ARRAY_SIZE(spi_cfg)); clock_enable(REG(GCC_BLSP2_QUP0_SPI_APPS_CBCR)); - + clock_enable_vote(REG(GCC_BLSP1_AHB_CBCR), + REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE), + BLSP2_AHB_CLK_ENA); } diff --git a/src/soc/qualcomm/qcs405/include/soc/mmu.h b/src/soc/qualcomm/qcs405/include/soc/mmu.h index 7bf024f..bb8aa30 100644 --- a/src/soc/qualcomm/qcs405/include/soc/mmu.h +++ b/src/soc/qualcomm/qcs405/include/soc/mmu.h @@ -19,8 +19,8 @@ #define DRAMSIZE1GB 0x40000000 void qcs405_mmu_init(void); -#ifdef CONFIG_QC_SOC_SIMULATE +//#ifdef CONFIG_QC_SOC_SIMULATE void qcs405_mmu_dram_config_c(void); -#endif +//#endif #endif // _SOC_QUALCOMM_QCS405_MMU_H_ diff --git a/src/soc/qualcomm/qcs405/include/soc/qup.h b/src/soc/qualcomm/qcs405/include/soc/qup.h new file mode 100644 index 0000000..211b44e --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/qup.h @@ -0,0 +1,230 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 - 2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __QUP_H__ +#define __QUP_H__ + + +/* QUP block registers */ +#define QUP_CONFIG 0x000 +#define QUP_STATE 0x004 +#define QUP_IO_MODES 0x008 +#define QUP_SW_RESET 0x00C +#define QUP_TRANSFER_CANCEL 0x014 +#define QUP_OPERATIONAL 0x018 +#define QUP_ERROR_FLAGS 0x01C +#define QUP_ERROR_FLAGS_EN 0x020 +#define QUP_TEST_CTRL 0x024 +#define QUP_OPERATIONAL_MASK 0x028 +#define QUP_HW_VERSION 0x030 +#define QUP_MX_OUTPUT_COUNT 0x100 +#define QUP_MX_OUTPUT_CNT_CURRENT 0x104 +#define QUP_OUTPUT_DEBUG 0x108 +#define QUP_OUTPUT_FIFO_WORD_CNT 0x10C +#define QUP_OUTPUT_FIFO 0x110 +#define QUP_OUTPUT_FIFO_SIZE 64 /* bytes */ +#define QUP_MX_WRITE_COUNT 0x150 +#define QUP_MX_WRITE_CNT_CURRENT 0x154 +#define QUP_MX_INPUT_COUNT 0x200 +#define QUP_MX_INPUT_CNT_CURRENT 0x204 +#define QUP_MX_READ_COUNT 0x208 +#define QUP_MX_READ_CNT_CURRENT 0x20C +#define QUP_INPUT_DEBUG 0x210 +#define QUP_INPUT_FIFO_WORD_CNT 0x214 +#define QUP_INPUT_FIFO 0x218 +#define QUP_INPUT_FIFO_SIZE 64 /* bytes */ +#define QUP_I2C_MASTER_CLK_CTL 0x400 +#define QUP_I2C_MASTER_STATUS 0x404 +#define QUP_I2C_MASTER_CONFIG 0x408 +#define QUP_I2C_MASTER_BUS_CLEAR 0x40C +#define QUP_I2C_MASTER_LOCAL_ID 0x410 +#define QUP_I2C_MASTER_COMMAND 0x414 + +#define OUTPUT_FIFO_FULL (1<<6) +#define INPUT_FIFO_NOT_EMPTY (1<<5) +#define OUTPUT_FIFO_NOT_EMPTY (1<<4) +#define INPUT_SERVICE_FLAG (1<<9) +#define OUTPUT_SERVICE_FLAG (1<<8) +#define QUP_UNPACK_EN (1<<14) +#define QUP_PACK_EN (1<<15) +#define QUP_OUTPUT_BIT_SHIFT_EN (1<<16) + +#define QUP_MODE_MASK (0x03) +#define QUP_OUTPUT_MODE_SHFT (10) +#define QUP_INPUT_MODE_SHFT (12) + +#define QUP_FS_DIVIDER_MASK (0xFF) + +#define QUP_APP_CLK_ON_EN (1 << 12) +#define QUP_CORE_CLK_ON_EN (1 << 13) +#define QUP_MINI_CORE_PROTO_SHFT (8) +#define QUP_MINI_CORE_PROTO_MASK (0x0F) + +/* Mini-core states */ +#define QUP_STATE_RESET 0x0 +#define QUP_STATE_RUN 0x1 +#define QUP_STATE_PAUSE 0x3 +#define QUP_STATE_VALID (1<<2) +#define QUP_STATE_MASK 0x3 +#define QUP_STATE_VALID_MASK (1<<2) + +/* Tags for output FIFO */ +#define QUP_I2C_1CLK_NOOP_SEQ 0x1 /*MSB 8-bit NOP, LSB 8-bits 1 clk.*/ +#define QUP_I2C_START_SEQ (0x1 << 8) +#define QUP_I2C_DATA_SEQ (0x2 << 8) +#define QUP_I2C_STOP_SEQ (0x3 << 8) +#define QUP_I2C_RECV_SEQ (0x4 << 8) + +/* Tags for input FIFO */ +#define QUP_I2C_MIDATA_SEQ (0x5 << 8) +#define QUP_I2C_MISTOP_SEQ (0x6 << 8) +#define QUP_I2C_MINACK_SEQ (0x7 << 8) + +#define QUP_I2C_ADDR(x) ((x & 0xFF) << 1) +#define QUP_I2C_DATA(x) (x & 0xFF) +#define QUP_I2C_MI_TAG(x) (x & 0xFF00) +#define QUP_I2C_SLAVE_READ (0x1) + +/*Bit vals for I2C_MASTER_CLK_CTL register */ +#define QUP_HS_DIVIDER_SHFT (8) +#define QUP_DIVIDER_MIN_VAL (0x3) + +/* Bit masks for I2C_MASTER_STATUS register */ +#define QUP_I2C_INVALID_READ_SEQ (1 << 25) +#define QUP_I2C_INVALID_READ_ADDR (1 << 24) +#define QUP_I2C_INVALID_TAG (1 << 23) +#define QUP_I2C_FAILED_MASK (0x3 << 6) +#define QUP_I2C_INVALID_WRITE (1 << 5) +#define QUP_I2C_ARB_LOST (1 << 4) +#define QUP_I2C_PACKET_NACK (1 << 3) +#define QUP_I2C_BUS_ERROR (1 << 2) + +typedef enum { + QUP_SUCCESS = 0, + QUP_ERR_BAD_PARAM, + QUP_ERR_STATE_SET, + QUP_ERR_TIMEOUT, + QUP_ERR_UNSUPPORTED, + QUP_ERR_I2C_FAILED, + QUP_ERR_I2C_ARB_LOST, + QUP_ERR_I2C_BUS_ERROR, + QUP_ERR_I2C_INVALID_SLAVE_ADDR, + QUP_ERR_XFER_FAIL, + QUP_ERR_I2C_NACK, + QUP_ERR_I2C_INVALID_WRITE, + QUP_ERR_I2C_INVALID_TAG, + QUP_ERR_UNDEFINED, +} qup_return_t; + +typedef enum { + QUP_MINICORE_SPI = 1, + QUP_MINICORE_I2C_MASTER, + QUP_MINICORE_I2C_SLAVE +} qup_protocol_t; + +typedef enum { + QUP_MODE_FIFO = 0, + QUP_MODE_BLOCK, + QUP_MODE_DATAMOVER, +} qup_mode_t; + +typedef struct { + qup_protocol_t protocol; + unsigned clk_frequency; + unsigned src_frequency; + qup_mode_t mode; + unsigned initialized; +} qup_config_t; + +typedef struct { + qup_protocol_t protocol; + union { + struct { + uint8_t addr; + uint8_t *data; + unsigned data_len; + } iic; + struct { + void *in; + void *out; + unsigned size; + } spi; + } p; +} qup_data_t; + +/* + * Initialize BLSP QUP block for FIFO I2C transfers. + * id[IN]: BLSP for which QUP is to be initialized. + * config_ptr[IN]: configurations parameters for the QUP. + * + * return: QUP_SUCCESS, if initialization succeeds. + */ +qup_return_t qup_init(blsp_qup_id_t id, const qup_config_t *config_ptr); + +/* + * Set QUP state to run, pause, reset. + * id[IN]: BLSP block for which QUP state is to be set. + * state[IN]: New state to transition to. + * + * return: QUP_SUCCESS, if state transition succeeds. + */ +qup_return_t qup_set_state(blsp_qup_id_t id, uint32_t state); + +/* + * Reset the status bits set during an i2c transfer. + * id[IN]: BLSP block for which i2c status bits are to be cleared. + * + * return: QUP_SUCCESS, if status bits are cleared successfully. + */ +qup_return_t qup_reset_i2c_master_status(blsp_qup_id_t id); + +/* + * Send data to the peripheral on the bus. + * id[IN]: BLSP block for which data is to be sent. + * p_tx_obj[IN]: Data to be sent to the slave on the bus. + * stop_seq[IN]: When set to non-zero QUP engine sends i2c stop sequnce. + * + * return: QUP_SUCCESS, when data is sent successfully to the peripheral. + */ +qup_return_t qup_send_data(blsp_qup_id_t id, qup_data_t *p_tx_obj, + uint8_t stop_seq); + +/* + * Receive data from peripheral on the bus. + * id[IN]: BLSP block from which data is to be received. + * p_tx_obj[IN]: length of data to be received, slave address. + * [OUT]: buffer filled with data from slave. + * + * return: QUP_SUCCESS, when data is received successfully. + */ +qup_return_t qup_recv_data(blsp_qup_id_t id, qup_data_t *p_tx_obj); + +#endif //__QUP_H__ diff --git a/src/soc/qualcomm/qcs405/include/soc/spi.h b/src/soc/qualcomm/qcs405/include/soc/spi.h new file mode 100644 index 0000000..5da709f --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/spi.h @@ -0,0 +1,189 @@ +/* + * Register definitions for the IPQ BLSP SPI Controller + * + * Copyright (c) 2012 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _IPQ40XX_SPI_H_ +#define _IPQ40XX_SPI_H_ + +#include <soc/iomap.h> +#include <soc/qup.h> +#include <spi-generic.h> + +#define BLSP0_QUP_REG_BASE ((void *)0x78b5000u) +#define BLSP5_QUP_REG_BASE ((void *)0x7af5000u) + +#define BLSP0_SPI_CONFIG_REG (BLSP0_QUP_REG_BASE + 0x00000300) +#define BLSP5_SPI_CONFIG_REG (BLSP5_QUP_REG_BASE + 0x00000300) + +#define BLSP0_SPI_IO_CONTROL_REG (BLSP0_QUP_REG_BASE + 0x00000304) +#define BLSP5_SPI_IO_CONTROL_REG (BLSP5_QUP_REG_BASE + 0x00000304) + +#define BLSP0_SPI_ERROR_FLAGS_REG (BLSP0_QUP_REG_BASE + 0x00000308) +#define BLSP5_SPI_ERROR_FLAGS_REG (BLSP5_QUP_REG_BASE + 0x00000308) + +#define BLSP0_SPI_DEASSERT_WAIT_REG (BLSP0_QUP_REG_BASE + 0x00000310) +#define BLSP5_SPI_DEASSERT_WAIT_REG (BLSP5_QUP_REG_BASE + 0x00000310) +#define BLSP0_SPI_ERROR_FLAGS_EN_REG (BLSP0_QUP_REG_BASE + 0x0000030c) +#define BLSP5_SPI_ERROR_FLAGS_EN_REG (BLSP5_QUP_REG_BASE + 0x0000030c) + +#define BLSP0_QUP_CONFIG_REG (BLSP0_QUP_REG_BASE + 0x00000000) +#define BLSP5_QUP_CONFIG_REG (BLSP5_QUP_REG_BASE + 0x00000000) + +#define BLSP0_QUP_ERROR_FLAGS_REG (BLSP0_QUP_REG_BASE + 0x0000001c) +#define BLSP5_QUP_ERROR_FLAGS_REG (BLSP5_QUP_REG_BASE + 0x0000001c) + +#define BLSP0_QUP_ERROR_FLAGS_EN_REG (BLSP0_QUP_REG_BASE + 0x00000020) +#define BLSP5_QUP_ERROR_FLAGS_EN_REG (BLSP5_QUP_REG_BASE + 0x00000020) + +#define BLSP0_QUP_OPERATIONAL_MASK (BLSP0_QUP_REG_BASE + 0x00000028) +#define BLSP5_QUP_OPERATIONAL_MASK (BLSP5_QUP_REG_BASE + 0x00000028) + +#define BLSP0_QUP_OPERATIONAL_REG (BLSP0_QUP_REG_BASE + 0x00000018) +#define BLSP5_QUP_OPERATIONAL_REG (BLSP5_QUP_REG_BASE + 0x00000018) + +#define BLSP0_QUP_IO_MODES_REG (BLSP0_QUP_REG_BASE + 0x00000008) +#define BLSP5_QUP_IO_MODES_REG (BLSP5_QUP_REG_BASE + 0x00000008) + +#define BLSP0_QUP_STATE_REG (BLSP0_QUP_REG_BASE + 0x00000004) +#define BLSP5_QUP_STATE_REG (BLSP5_QUP_REG_BASE + 0x00000004) + +#define BLSP0_QUP_INPUT_FIFOc_REG(c) \ + (BLSP0_QUP_REG_BASE + 0x00000218 + 4 * (c)) +#define BLSP5_QUP_INPUT_FIFOc_REG(c) \ + (BLSP5_QUP_REG_BASE + 0x00000218 + 4 * (c)) + +#define BLSP0_QUP_OUTPUT_FIFOc_REG(c) \ + (BLSP0_QUP_REG_BASE + 0x00000110 + 4 * (c)) +#define BLSP5_QUP_OUTPUT_FIFOc_REG(c) \ + (BLSP5_QUP_REG_BASE + 0x00000110 + 4 * (c)) + +#define BLSP0_QUP_MX_INPUT_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000200) +#define BLSP5_QUP_MX_INPUT_COUNT_REG (BLSP5_QUP_REG_BASE + 0x00000200) + +#define BLSP0_QUP_MX_OUTPUT_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000100) +#define BLSP5_QUP_MX_OUTPUT_COUNT_REG (BLSP5_QUP_REG_BASE + 0x00000100) + +#define BLSP0_QUP_SW_RESET_REG (BLSP0_QUP_REG_BASE + 0x0000000c) +#define BLSP5_QUP_SW_RESET_REG (BLSP5_QUP_REG_BASE + 0x0000000c) + +#define QUP_CONFIG_MINI_CORE_MSK (0x0F << 8) +#define QUP_CONFIG_MINI_CORE_SPI (1 << 8) +#define QUP_CONF_INPUT_MSK (1 << 7) +#define QUP_CONF_INPUT_ENA (0 << 7) +#define QUP_CONF_NO_INPUT (1 << 7) +#define QUP_CONF_OUTPUT_MSK (1 << 6) +#define QUP_CONF_OUTPUT_ENA (0 << 6) +#define QUP_CONF_NO_OUTPUT (1 << 6) +#define QUP_CONF_N_MASK 0x1F +#define QUP_CONF_N_SPI_8_BIT_WORD 0x07 + +#define SPI_CONFIG_INPUT_FIRST (1 << 9) +#define SPI_CONFIG_INPUT_FIRST_BACK (0 << 9) +#define SPI_CONFIG_LOOP_BACK_MSK (1 << 8) +#define SPI_CONFIG_NO_LOOP_BACK (0 << 8) +#define SPI_CONFIG_NO_SLAVE_OPER_MSK (1 << 5) +#define SPI_CONFIG_NO_SLAVE_OPER (0 << 5) + +#define SPI_IO_CTRL_CLK_ALWAYS_ON (0 << 9) +#define SPI_IO_CTRL_MX_CS_MODE (1 << 8) +#define SPI_IO_CTRL_NO_TRI_STATE (1 << 0) +#define SPI_IO_CTRL_FORCE_CS_MSK (1 << 11) +#define SPI_IO_CTRL_FORCE_CS_EN (1 << 11) +#define SPI_IO_CTRL_FORCE_CS_DIS (0 << 11) +#define SPI_IO_CTRL_CLOCK_IDLE_HIGH (1 << 10) + +#define QUP_IO_MODES_OUTPUT_BIT_SHIFT_MSK (1 << 16) +#define QUP_IO_MODES_OUTPUT_BIT_SHIFT_EN (1 << 16) +#define QUP_IO_MODES_INPUT_MODE_MSK (0x03 << 12) +#define QUP_IO_MODES_INPUT_BLOCK_MODE (0x01 << 12) +#define QUP_IO_MODES_OUTPUT_MODE_MSK (0x03 << 10) +#define QUP_IO_MODES_OUTPUT_BLOCK_MODE (0x01 << 10) + +#define SPI_INPUT_BLOCK_SIZE 4 +#define SPI_OUTPUT_BLOCK_SIZE 4 + +#define MAX_COUNT_SIZE 0xffff + +#define SPI_CORE_RESET 0 +#define SPI_CORE_RUNNING 1 +#define SPI_MODE0 0 +#define SPI_MODE1 1 +#define SPI_MODE2 2 +#define SPI_MODE3 3 +#define BLSP0_SPI 0 +#define BLSP5_SPI 5 + +struct blsp_spi { + void *spi_config; + void *io_control; + void *error_flags; + void *error_flags_en; + void *qup_config; + void *qup_error_flags; + void *qup_error_flags_en; + void *qup_operational; + void *qup_io_modes; + void *qup_state; + void *qup_input_fifo; + void *qup_output_fifo; + void *qup_mx_input_count; + void *qup_mx_output_count; + void *qup_sw_reset; + void *qup_ns_reg; + void *qup_md_reg; + void *qup_op_mask; + void *qup_deassert_wait; +}; + + +#define SUCCESS 0 + +#define DUMMY_DATA_VAL 0 +#define TIMEOUT_CNT 100 + +#define ETIMEDOUT -10 +#define EINVAL -11 +#define EIO -12 + +/* MX_INPUT_COUNT and MX_OUTPUT_COUNT are 16-bits. Zero has a special meaning + * (count function disabled) and does not hold significance in the count. */ +#define MAX_PACKET_COUNT ((64 * KiB) - 1) + + +struct ipq_spi_slave { + struct spi_slave slave; + const struct blsp_spi *regs; + unsigned int mode; + unsigned int initialized; + unsigned long freq; + int allocated; +}; + +#endif /* _IPQ40XX_SPI_H_ */ diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c index 73e538e..7801be8 100644 --- a/src/soc/qualcomm/qcs405/spi.c +++ b/src/soc/qualcomm/qcs405/spi.c @@ -1,71 +1,736 @@ /* - * This file is part of the coreboot project. + * Copyright (c) 2012 The Linux Foundation. All rights reserved. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include <spi-generic.h> +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <gpio.h> +#include <soc/iomap.h> +#include <soc/spi.h> +#include <stdlib.h> +#include <string.h> #include <spi_flash.h> -#if IS_ENABLED(CONFIG_QC_SOC_SIMULATE) - -extern int spi_simulate_ram_flash_probe(const struct spi_slave *spi, - struct spi_flash *flash); - -static const struct spi_ctrlr spi_ctrlr = { - .flash_probe = spi_simulate_ram_flash_probe, -}; - -const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { +static const struct blsp_spi spi_reg[] = { + /* BLSP0 registers for SPI interface */ { - .ctrlr = &spi_ctrlr, - .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, - .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, - } + BLSP0_SPI_CONFIG_REG, + BLSP0_SPI_IO_CONTROL_REG, + BLSP0_SPI_ERROR_FLAGS_REG, + BLSP0_SPI_ERROR_FLAGS_EN_REG, + BLSP0_QUP_CONFIG_REG, + BLSP0_QUP_ERROR_FLAGS_REG, + BLSP0_QUP_ERROR_FLAGS_EN_REG, + BLSP0_QUP_OPERATIONAL_REG, + BLSP0_QUP_IO_MODES_REG, + BLSP0_QUP_STATE_REG, + BLSP0_QUP_INPUT_FIFOc_REG(0), + BLSP0_QUP_OUTPUT_FIFOc_REG(0), + BLSP0_QUP_MX_INPUT_COUNT_REG, + BLSP0_QUP_MX_OUTPUT_COUNT_REG, + BLSP0_QUP_SW_RESET_REG, + 0, + 0, + BLSP0_QUP_OPERATIONAL_MASK, + BLSP0_SPI_DEASSERT_WAIT_REG, + }, + {0},{0},{0},{0}, + /* BLSP5 registers for SPI interface */ + { + BLSP5_SPI_CONFIG_REG, + BLSP5_SPI_IO_CONTROL_REG, + BLSP5_SPI_ERROR_FLAGS_REG, + BLSP5_SPI_ERROR_FLAGS_EN_REG, + BLSP5_QUP_CONFIG_REG, + BLSP5_QUP_ERROR_FLAGS_REG, + BLSP5_QUP_ERROR_FLAGS_EN_REG, + BLSP5_QUP_OPERATIONAL_REG, + BLSP5_QUP_IO_MODES_REG, + BLSP5_QUP_STATE_REG, + BLSP5_QUP_INPUT_FIFOc_REG(0), + BLSP5_QUP_OUTPUT_FIFOc_REG(0), + BLSP5_QUP_MX_INPUT_COUNT_REG, + BLSP5_QUP_MX_OUTPUT_COUNT_REG, + BLSP5_QUP_SW_RESET_REG, + 0, + 0, + BLSP5_QUP_OPERATIONAL_MASK, + BLSP5_SPI_DEASSERT_WAIT_REG, + }, + }; -#else +static int check_bit_state(void *reg_addr, int mask, + int val, int us_delay) +{ + unsigned int count = TIMEOUT_CNT; + + while ((read32(reg_addr) & mask) != val) { + count--; + if (count == 0) + return -ETIMEDOUT; + udelay(us_delay); + } + + return SUCCESS; +} + +/* + * Check whether QUPn State is valid + */ +static int check_qup_state_valid(struct ipq_spi_slave *ds) +{ + + return check_bit_state(ds->regs->qup_state, QUP_STATE_VALID_MASK, + QUP_STATE_VALID, 1); + +} + +/* + * Configure QUPn Core state + */ +static int config_spi_state(struct ipq_spi_slave *ds, unsigned int state) +{ + uint32_t val; + int ret = SUCCESS; + + ret = check_qup_state_valid(ds); + if (ret != SUCCESS) + return ret; + + switch (state) { + case QUP_STATE_RUN: + /* Set the state to RUN */ + val = ((read32(ds->regs->qup_state) & ~QUP_STATE_MASK) + | QUP_STATE_RUN); + write32(ds->regs->qup_state, val); + ret = check_qup_state_valid(ds); + break; + case QUP_STATE_RESET: + /* Set the state to RESET */ + val = ((read32(ds->regs->qup_state) & ~QUP_STATE_MASK) + | QUP_STATE_RESET); + write32(ds->regs->qup_state, val); + ret = check_qup_state_valid(ds); + break; + default: + printk(BIOS_ERR, "unsupported QUP SPI state : %d\n", state); + ret = -EINVAL; + break; + } + + return ret; +} + +/* + * Set QUPn SPI Mode + */ +static void spi_set_mode(struct ipq_spi_slave *ds, unsigned int mode) +{ + unsigned int clk_idle_state; + unsigned int input_first_mode; + uint32_t val; + + switch (mode) { + case SPI_MODE0: + clk_idle_state = 0; + input_first_mode = SPI_CONFIG_INPUT_FIRST; + break; + case SPI_MODE1: + clk_idle_state = 0; + input_first_mode = 0; + break; + case SPI_MODE2: + clk_idle_state = 1; + input_first_mode = SPI_CONFIG_INPUT_FIRST; + break; + case SPI_MODE3: + clk_idle_state = 1; + input_first_mode = 0; + break; + default: + printk(BIOS_ERR, "unsupported spi mode : %d\n", mode); + return; + } + + + val = read32(ds->regs->spi_config); + val |= input_first_mode; + write32(ds->regs->spi_config, val); + + val = read32(ds->regs->io_control); + if (clk_idle_state) + val |= SPI_IO_CTRL_CLOCK_IDLE_HIGH; + else + val &= ~SPI_IO_CTRL_CLOCK_IDLE_HIGH; + + write32(ds->regs->io_control, val); +} + +/* + * Reset entire QUP and all mini cores + */ +static void spi_reset(struct ipq_spi_slave *ds) +{ + write32(ds->regs->qup_sw_reset, 0x1); + udelay(5); + check_qup_state_valid(ds); +} + +static struct ipq_spi_slave spi_slave_pool[2]; + +static struct ipq_spi_slave *to_ipq_spi(const struct spi_slave *slave) +{ + struct ipq_spi_slave *ds; + size_t i; + + for (i = 0; i < ARRAY_SIZE(spi_slave_pool); i++) { + ds = spi_slave_pool + i; + + if (!ds->allocated) + continue; + + if ((ds->slave.bus == slave->bus) && + (ds->slave.cs == slave->cs)) + return ds; + } + + return NULL; +} + +/* + * BLSP QUPn SPI Hardware Initialisation + */ +static int spi_hw_init(struct ipq_spi_slave *ds) +{ + int ret; + + ds->initialized = 0; + + /* QUPn module configuration */ + spi_reset(ds); + + /* Set the QUPn state */ + ret = config_spi_state(ds, QUP_STATE_RESET); + if (ret) + return ret; + + /* + * Configure Mini core to SPI core with Input Output enabled, + * SPI master, N = 8 bits + */ + clrsetbits_le32(ds->regs->qup_config, QUP_CONFIG_MINI_CORE_MSK | + QUP_CONF_INPUT_MSK | + QUP_CONF_OUTPUT_MSK | + QUP_CONF_N_MASK, + QUP_CONFIG_MINI_CORE_SPI | + QUP_CONF_INPUT_ENA | + QUP_CONF_OUTPUT_ENA | + QUP_CONF_N_SPI_8_BIT_WORD); + + /* + * Configure Input first SPI protocol, + * SPI master mode and no loopback + */ + clrsetbits_le32(ds->regs->spi_config, SPI_CONFIG_LOOP_BACK_MSK | + SPI_CONFIG_NO_SLAVE_OPER_MSK, + SPI_CONFIG_NO_LOOP_BACK | + SPI_CONFIG_NO_SLAVE_OPER); + + /* + * Configure SPI IO Control Register + * CLK_ALWAYS_ON = 0 + * MX_CS_MODE = 0 + * NO_TRI_STATE = 1 + */ + write32(ds->regs->io_control, SPI_IO_CTRL_CLK_ALWAYS_ON | + SPI_IO_CTRL_NO_TRI_STATE | SPI_IO_CTRL_MX_CS_MODE); + + /* + * Configure SPI IO Modes. + * OUTPUT_BIT_SHIFT_EN = 1 + * INPUT_MODE = Block Mode + * OUTPUT MODE = Block Mode + */ + clrsetbits_le32(ds->regs->qup_io_modes, + QUP_IO_MODES_OUTPUT_BIT_SHIFT_MSK | + QUP_IO_MODES_INPUT_MODE_MSK | + QUP_IO_MODES_OUTPUT_MODE_MSK, + QUP_IO_MODES_OUTPUT_BIT_SHIFT_EN | + QUP_IO_MODES_INPUT_BLOCK_MODE | + QUP_IO_MODES_OUTPUT_BLOCK_MODE); + + spi_set_mode(ds, ds->mode); + + /* Disable Error mask */ + write32(ds->regs->error_flags_en, 0); + write32(ds->regs->qup_error_flags_en, 0); + + write32(ds->regs->qup_deassert_wait, 0); + + ds->initialized = 1; + + return SUCCESS; +} static int spi_ctrlr_claim_bus(const struct spi_slave *slave) { - return 0; + struct ipq_spi_slave *ds = to_ipq_spi(slave); + unsigned int ret; + + ret = spi_hw_init(ds); + if (ret) + return -EIO; + switch(slave->bus) { + case 5: + + gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); + gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); + gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); + gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); + + break; + default: + printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); + break; + } + + + return SUCCESS; } static void spi_ctrlr_release_bus(const struct spi_slave *slave) { + struct ipq_spi_slave *ds = to_ipq_spi(slave); + /* Reset the SPI hardware */ + spi_reset(ds); + ds->initialized = 0; } -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytes_out, void *din, size_t bytes_in) +static void write_force_cs(const struct spi_slave *slave, int assert) { + struct ipq_spi_slave *ds = to_ipq_spi(slave); +#if 0 + io = read32(ds->regs->io_control); + + io &= ~(3 << 2); + write32(ds->regs->io_control, io); +#else + if (assert) + clrsetbits_le32(ds->regs->io_control, + SPI_IO_CTRL_FORCE_CS_MSK, SPI_IO_CTRL_FORCE_CS_EN); + else + clrsetbits_le32(ds->regs->io_control, + SPI_IO_CTRL_FORCE_CS_MSK, SPI_IO_CTRL_FORCE_CS_DIS); +#endif + return; +} + +/* + * Function to write data to OUTPUT FIFO + */ +static void spi_write_byte(struct ipq_spi_slave *ds, unsigned char data) +{ + /* Wait for space in the FIFO */ + while ((read32(ds->regs->qup_operational) & OUTPUT_FIFO_FULL)) + udelay(1); + + /* Write the byte of data */ + write32(ds->regs->qup_output_fifo, data); +} + +/* + * Function to read data from Input FIFO + */ +static unsigned char spi_read_byte(struct ipq_spi_slave *ds) +{ + /* Wait for Data in FIFO */ + while (!(read32(ds->regs->qup_operational) & INPUT_FIFO_NOT_EMPTY)) + udelay(1); + + /* Read a byte of data */ + return read32(ds->regs->qup_input_fifo) & 0xff; +} + +/* + * Function to check wheather Input or Output FIFO + * has data to be serviced + */ +static int check_fifo_status(void *reg_addr) +{ + unsigned int count = TIMEOUT_CNT; + unsigned int status_flag; + unsigned int val; + + do { + val = read32(reg_addr); + count--; + if (count == 0) + return -ETIMEDOUT; + status_flag = ((val & OUTPUT_SERVICE_FLAG) | + (val & INPUT_SERVICE_FLAG)); + } while (!status_flag); + + return SUCCESS; +} + +/* + * Function to configure Input and Output enable/disable + */ +static void enable_io_config(struct ipq_spi_slave *ds, + uint32_t write_cnt, uint32_t read_cnt) +{ + + if (write_cnt) { + clrsetbits_le32(ds->regs->qup_config, + QUP_CONF_OUTPUT_MSK, QUP_CONF_OUTPUT_ENA); + } else { + clrsetbits_le32(ds->regs->qup_config, + QUP_CONF_OUTPUT_MSK, QUP_CONF_NO_OUTPUT); + } + + if (read_cnt) { + clrsetbits_le32(ds->regs->qup_config, + QUP_CONF_INPUT_MSK, QUP_CONF_INPUT_ENA); + } else { + clrsetbits_le32(ds->regs->qup_config, + QUP_CONF_INPUT_MSK, QUP_CONF_NO_INPUT); + } + + return; +} + +/* + * Function to read bytes number of data from the Input FIFO + */ +static int __blsp_spi_read(struct ipq_spi_slave *ds, u8 *data_buffer, + unsigned int bytes) +{ + uint32_t val; + unsigned int i; + unsigned int fifo_count; + int ret = SUCCESS; + int state_config; + + /* Configure no of bytes to read */ + state_config = config_spi_state(ds, QUP_STATE_RESET); + if (state_config) + return state_config; + + /* Configure input and output enable */ + enable_io_config(ds, 0, bytes); + + write32(ds->regs->qup_mx_input_count, bytes); + + state_config = config_spi_state(ds, QUP_STATE_RUN); + if (state_config) + return state_config; + + while (bytes) { + ret = check_fifo_status(ds->regs->qup_operational); + if (ret != SUCCESS) + goto out; + + val = read32(ds->regs->qup_operational); + if (val & INPUT_SERVICE_FLAG) { + /* + * acknowledge to hw that software will + * read input data + */ + val &= INPUT_SERVICE_FLAG; + write32(ds->regs->qup_operational, val); + + fifo_count = ((bytes > SPI_INPUT_BLOCK_SIZE) ? + SPI_INPUT_BLOCK_SIZE : bytes); + + for (i = 0; i < fifo_count; i++) { + *data_buffer = spi_read_byte(ds); + data_buffer++; + bytes--; + } + } + } + +out: + /* + * Put the SPI Core back in the Reset State + * to end the transfer + */ + (void)config_spi_state(ds, QUP_STATE_RESET); + return ret; +} + +static int blsp_spi_read(struct ipq_spi_slave *ds, u8 *data_buffer, + unsigned int bytes) +{ + int length, ret; + + while (bytes) { + length = (bytes < MAX_COUNT_SIZE) ? bytes : MAX_COUNT_SIZE; + + ret = __blsp_spi_read(ds, data_buffer, length); + if (ret != SUCCESS) + return ret; + + data_buffer += length; + bytes -= length; + } + return 0; } +/* + * Function to write data to the Output FIFO + */ +static int __blsp_spi_write(struct ipq_spi_slave *ds, const u8 *cmd_buffer, + unsigned int bytes) +{ + uint32_t val; + unsigned int i; + unsigned int write_len = bytes; + unsigned int read_len = 3; //bytes; hack for now + unsigned int fifo_count; + int ret = SUCCESS; + int state_config; + + state_config = config_spi_state(ds, QUP_STATE_RESET); + if (state_config) + return state_config; + + /* No of bytes to be written in Output FIFO */ + write32(ds->regs->qup_mx_output_count, bytes); + write32(ds->regs->qup_mx_input_count, bytes); + state_config = config_spi_state(ds, QUP_STATE_RUN); + if (state_config) + return state_config; + + /* Configure input and output enable */ + enable_io_config(ds, write_len, read_len); + + /* + * read_len considered to ensure that we read the dummy data for the + * write we performed. This is needed to ensure with WR-RD transaction + * to get the actual data on the subsequent read cycle that happens + */ + while (write_len || read_len) { + + ret = check_fifo_status(ds->regs->qup_operational); + if (ret != SUCCESS) + goto out; + + val = read32(ds->regs->qup_operational); + if (val & OUTPUT_SERVICE_FLAG) { + /* + * acknowledge to hw that software will write + * expected output data + */ + val &= OUTPUT_SERVICE_FLAG; + write32(ds->regs->qup_operational, val); + + if (write_len > SPI_OUTPUT_BLOCK_SIZE) + fifo_count = SPI_OUTPUT_BLOCK_SIZE; + else + fifo_count = write_len; + + for (i = 0; i < fifo_count; i++) { + /* Write actual data to output FIFO */ + spi_write_byte(ds, *cmd_buffer); + cmd_buffer++; + write_len--; + } + } + if (val & INPUT_SERVICE_FLAG) { + /* + * acknowledge to hw that software + * will read input data + */ + val &= INPUT_SERVICE_FLAG; + write32(ds->regs->qup_operational, val); + + if (read_len > SPI_INPUT_BLOCK_SIZE) + fifo_count = SPI_INPUT_BLOCK_SIZE; + else + fifo_count = read_len; + + for (i = 0; i < fifo_count; i++) { + /* Read dummy data for the data written */ + (void)spi_read_byte(ds); + + /* Decrement the read count after reading the + * dummy data from the device. This is to make + * sure we read dummy data before we write the + * data to fifo + */ + read_len--; + } + } + } + +out: + /* + * Put the SPI Core back in the Reset State + * to end the transfer + */ + (void)config_spi_state(ds, QUP_STATE_RESET); + + return ret; +} + +static int blsp_spi_write(struct ipq_spi_slave *ds, u8 *cmd_buffer, + unsigned int bytes) +{ + int length, ret; + + while (bytes) { + length = (bytes < MAX_COUNT_SIZE) ? bytes : MAX_COUNT_SIZE; + + ret = __blsp_spi_write(ds, cmd_buffer, length); + if (ret != SUCCESS) + return ret; + + cmd_buffer += length; + bytes -= length; + } + + return 0; +} + +/* + * This function is invoked with either tx_buf or rx_buf. + * Calling this function with both null does a chip select change. + */ +static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes) +{ + struct ipq_spi_slave *ds = to_ipq_spi(slave); + u8 *txp = (u8 *)dout; + u8 *rxp = (u8 *)din; + int ret; + +#if 0 + /* Driver implementation does not support full duplex. */ + if (dout && din) + return -1; +#endif + ret = config_spi_state(ds, QUP_STATE_RESET); + if (ret != SUCCESS) + return ret; + + write_force_cs(slave, 1); + + if (dout != NULL) { + ret = blsp_spi_write(ds, txp, (unsigned int) out_bytes); + if (ret != SUCCESS) + goto out; + } + + if (din != NULL) { + ret = blsp_spi_read(ds, rxp, in_bytes); + if (ret != SUCCESS) + goto out; + } + +out: + write_force_cs(slave, 0); + + /* + * Put the SPI Core back in the Reset State + * to end the transfer + */ + (void)config_spi_state(ds, QUP_STATE_RESET); + + return ret; +} + +static int spi_ctrlr_setup(const struct spi_slave *slave) +{ + struct ipq_spi_slave *ds = NULL; + int i; + unsigned int bus = slave->bus; + unsigned int cs = slave->cs; + + if ((bus < BLSP0_SPI) || (bus > BLSP5_SPI) + || ((bus == BLSP0_SPI) && (cs > 2)) + || ((bus == BLSP5_SPI) && (cs > 0))) { + printk(BIOS_ERR, + "SPI error: unsupported bus %d (Supported busses 0, 1 and 2) " + "or chipselect\n", bus); + return -1; + } + + for (i = 0; i < ARRAY_SIZE(spi_slave_pool); i++) { + if (spi_slave_pool[i].allocated) + continue; + ds = spi_slave_pool + i; + + ds->slave.bus = bus; + ds->slave.cs = cs; + ds->regs = &spi_reg[bus]; + + /* + * TODO(vbendeb): + * hardcoded frequency and mode - we might need to find a way + * to configure this + */ + ds->freq = 10000000; + ds->mode = SPI_MODE0; + ds->allocated = 1; + + return 0; + } + + printk(BIOS_ERR, "SPI error: all %d pools busy\n", i); + return -1; +} + +static int xfer_vectors(const struct spi_slave *slave, + struct spi_op vectors[], size_t count) + { + return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); + } + static const struct spi_ctrlr spi_ctrlr = { + .setup = spi_ctrlr_setup, .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, - .xfer = spi_ctrlr_xfer, - .max_xfer_size = 65535, + //.xfer = spi_ctrlr_xfer, + .xfer_vector = xfer_vectors, + .max_xfer_size = MAX_PACKET_COUNT, }; const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { .ctrlr = &spi_ctrlr, - .bus_start = 0, - .bus_end = 0, + .bus_start = BLSP5_SPI, + .bus_end = BLSP5_SPI, }, }; -#endif - const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); -- To view, visit https://review.coreboot.org/c/coreboot/+/29968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I340eb3bf77b25fe3502d4b29ef4bf7c06b282c02 Gerrit-Change-Number: 29968 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: qclib: Add qclib support
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29967 Change subject: qclib: Add qclib support ...................................................................... qclib: Add qclib support Add qclib support to configure pmic, clocks, DDR Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/mainboard/google/mistral/mainboard.c M src/mainboard/google/mistral/romstage.c M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/include/soc/memlayout.ld A src/soc/qualcomm/qcs405/include/soc/qclib.h M src/soc/qualcomm/qcs405/include/soc/symbols.h M src/soc/qualcomm/qcs405/mmu.c A src/soc/qualcomm/qcs405/qclib_execute.c 8 files changed, 247 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/29967/1 diff --git a/src/mainboard/google/mistral/mainboard.c b/src/mainboard/google/mistral/mainboard.c index 7201874..f4fc31e 100644 --- a/src/mainboard/google/mistral/mainboard.c +++ b/src/mainboard/google/mistral/mainboard.c @@ -18,12 +18,14 @@ #include <timestamp.h> #include <soc/usb.h> +#if 0 static struct usb_board_data usb0_board_data = { .parameter_override_x0 = 0x63, .parameter_override_x1 = 0x03, .parameter_override_x0 = 0x1d, .parameter_override_x1 = 0x03, }; +#endif static struct usb_board_data usb1_board_data = { .parameter_override_x0 = 0x63, @@ -35,7 +37,7 @@ static void setup_usb(void) { /* Setting Primarty usb controller */ - setup_usb_host(HSUSB_SS_PORT_0, &usb0_board_data); + //setup_usb_host(HSUSB_SS_PORT_0, &usb0_board_data); /* Setting secondary usb controller */ setup_usb_host(HSUSB_HS_PORT_1, &usb1_board_data); diff --git a/src/mainboard/google/mistral/romstage.c b/src/mainboard/google/mistral/romstage.c index 31e5113..e53f485 100644 --- a/src/mainboard/google/mistral/romstage.c +++ b/src/mainboard/google/mistral/romstage.c @@ -21,19 +21,18 @@ #include <timestamp.h> #include <arch/stages.h> #include <soc/usb.h> +#include <soc/qclib.h> -#ifdef CONFIG_QC_SOC_SIMULATE extern void qcs405_mmu_dram_config_c(void); -#endif void platform_romstage_main(void) { + /* QCLib: DDR init & train */ + qclib_load_and_run(); + /* * Do DWC3 core and phy reset. Kick these resets off early * so they get atleast 1msec to settle. */ reset_usb(HSUSB_SS_PORT_0); reset_usb(HSUSB_HS_PORT_1); -#ifdef CONFIG_QC_SOC_SIMULATE - qcs405_mmu_dram_config_c(); -#endif } diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index c174cae..5e255e2 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -28,6 +28,7 @@ romstage-$(CONFIG_DRIVERS_UART) += uart.c romstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c romstage-y += usb.c +romstage-y += qclib_execute.c ################################################################################ ramstage-y += soc.c @@ -51,6 +52,28 @@ cp $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin ################################################################################ +QCLIB_FILE := $(QCS405_BLOB)/QcLib.elf +qclib_file := $(shell ls $(QCLIB_FILE)) +ifneq (,$(findstring $(QCLIB_FILE),$(qclib_file))) + QCLIB_CBFS := $(CONFIG_CBFS_PREFIX)/qclib + $(QCLIB_CBFS)-file := $(QCLIB_FILE) + $(QCLIB_CBFS)-type := stage + $(QCLIB_CBFS)-compression := none + cbfs-files-y += $(QCLIB_CBFS) +endif + +################################################################################ +PMIC_FILE := $(QCS405_BLOB)/pmic.elf +pmic_file := $(shell ls $(PMIC_FILE)) +ifneq (,$(findstring $(PMIC_FILE),$(pmic_file))) + PMIC_CBFS := $(CONFIG_CBFS_PREFIX)/pmiccfg + $(PMIC_CBFS)-file := $(PMIC_FILE) + $(PMIC_CBFS)-type := stage + $(PMIC_CBFS)-compression := none + cbfs-files-y += $(PMIC_CBFS) +endif + +################################################################################ QC_SEC_FILE := $(QCS405_BLOB)/qc_sec.mbn qc_sec_file := $(shell ls $(QC_SEC_FILE)) ifneq (,$(findstring $(QC_SEC_FILE),$(qc_sec_file))) diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld index 03c6edb..dadbbe8 100644 --- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld +++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld @@ -30,8 +30,8 @@ SSRAM_END(0x8608000) BSRAM_START(0x8C00000) - OVERLAP_VERSTAGE_ROMSTAGE(0x8C00000, 100K) - REGION(fw_reserved2, 0x8C19000, 0x16000, 4096) + REGION(fw_reserved2, 0x8C00000, 0x16000, 4096) + OVERLAP_VERSTAGE_ROMSTAGE(0x8C16000, 100K) BOOTBLOCK(0x8C2F000, 40K) TTB(0x8C39000, 56K) VBOOT2_WORK(0x8C47000, 16K) @@ -39,10 +39,10 @@ TIMESTAMP(0x8C4F000, 1K) PRERAM_CBMEM_CONSOLE(0x8C4F400, 32K) PRERAM_CBFS_CACHE(0x8C57400, 70K) - REGION(bsram_unused, 0x8C68C00, 0xA2400, 0x100) -/* REGION(qclib, 0x8D0B000, 0x80000, 4096) - REGION(dcb, 0x8D8B000, 0x4000, 4096) - REGION(pmic, 0x8D8F000, 0xA000, 4096)*/ + //REGION(bsram_unused, 0x8C68C00, 0xA2400, 0x100) + REGION(qclib, 0x8C69000, 0x80000, 4096) + REGION(dcb, 0x8CE9000, 0x4000, 4096) + REGION(pmic, 0x8CED000, 0x10000, 4096) BSRAM_END(0x8D80000) DRAM_START(0x80000000) diff --git a/src/soc/qualcomm/qcs405/include/soc/qclib.h b/src/soc/qualcomm/qcs405/include/soc/qclib.h new file mode 100644 index 0000000..b6a681e --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/qclib.h @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_QCS405_QCLIB_H__ +#define _SOC_QUALCOMM_QCS405_QCLIB_H__ + +#include <fmap.h> + +/* coreboot & QCLib I/F definitions */ + +/* TE_NAME (table entry name) */ +#define TE_NAME_LENGTH 24 /* length (bytes) of name field */ +#define TE_DDR_INFORMATION "ddr_information" +#define TE_DCB_SETTINGS "dcb_settings" +#define TE_PMIC_SETTINGS "pmic_settings" +#define TE_DDR_TRAINING_DATA "ddr_training_data" +#define TE_LIMITS_CFG_DATA "limits_cfg_data" +#define TE_QCLIB_LOG_BUFFER "qclib_log_buffer" + +#if IS_ENABLED(CONFIG_QC_SDI_ENABLE) +#define TE_QCSDI "qcsdi" +#endif + +/* TE_INDEX (table entry index) */ +/* te_index_ddr_information must be first index + This allows DDR mmu configuration to occcur first + in case other write operations require DDR access */ +enum te_index { + te_index_ddr_information, /* 00 */ + te_index_dcb, /* 01 */ + te_index_pmic, /* 02 */ + te_index_ddr_training, /* 03 */ + te_index_limits_cfg, /* 04 */ + te_index_qclib_log_buffer, /* 05 */ + + /* add new entries above */ +#if IS_ENABLED(CONFIG_QC_SDI_ENABLE) + te_index_qcsdi, /* ALWAYS LAST */ +#endif + te_index_last +}; + +/* BA_BMASK_VALUES (blob_attributes bit mask values) */ +#define BA_BMASK_SAVE_TO_STORAGE 0x00000001 + +struct qclib_cb_if_table_entry { + const char name[TE_NAME_LENGTH]; /* 0x00 TE_NAME */ + uint64_t blob_address; /* 0x18 blob addr in SRAM */ + uint32_t size; /* 0x20 blob size in SRAM */ + uint32_t blob_attributes; /* 0x24 BA_BMASK_VALUES */ +}; + +/* GA_BMASK_VALUES (global_attributes bit mask values) */ +#define GA_BMASK_ENABLE_SOC_DEBUG_FLOW 0x00000001 +#define GA_BMASK_ENABLE_UART_LOGGING 0x00000002 + +#define INTERFACE_VERSION 0x00000001 +#define MAX_NUMBER_OF_ENTRIES 16 + +#define QCLIB_MAGIC_NUMBER 0x51434C49425F4342 /* QCLIB_CB */ + +struct qclib_cb_if_table_header { + uint64_t magic; /* 0x00 */ + uint32_t version; /* 0x08 */ + uint32_t num_entries; /* 0x0C */ + uint32_t max_entries; /* 0x10 */ + uint32_t global_attributes; /* 0x14 */ + uint64_t reserved; /* 0x18 */ + struct qclib_cb_if_table_entry te[MAX_NUMBER_OF_ENTRIES]; /* 0x20 */ +}; + +/* fmap_region[] table index */ +enum fmap_region_index { + fmap_ddr_region, + fmap_limits_cfg, + fmap_region_max +}; + +/* Region Device for Data in Flash */ +struct fmap_region { + struct region_device dev; + size_t size; + bool dev_valid; + enum te_index index; + char fmap_name[TE_NAME_LENGTH]; +}; + +void qclib_load_and_run(void); + +#endif // _SOC_QUALCOMM_QCS405_QCLIB_H_ diff --git a/src/soc/qualcomm/qcs405/include/soc/symbols.h b/src/soc/qualcomm/qcs405/include/soc/symbols.h index f7cdc8d..447b7ae 100644 --- a/src/soc/qualcomm/qcs405/include/soc/symbols.h +++ b/src/soc/qualcomm/qcs405/include/soc/symbols.h @@ -30,4 +30,12 @@ extern u8 _edram_reserved[]; #define _dram_reserved_size (_edram_reserved - _dram_reserved) +extern u8 _dcb[]; +extern u8 _edcb[]; +#define _dcb_size (_edcb - _dcb) + +extern u8 _pmic[]; +extern u8 _epmic[]; +#define _pmic_size (_epmic - _pmic) + #endif // _SOC_QUALCOMM_QCS405_SYMBOLS_H_ diff --git a/src/soc/qualcomm/qcs405/mmu.c b/src/soc/qualcomm/qcs405/mmu.c index bebca24..ecae39f 100644 --- a/src/soc/qualcomm/qcs405/mmu.c +++ b/src/soc/qualcomm/qcs405/mmu.c @@ -27,16 +27,12 @@ MA_DEV | MA_S | MA_RW); mmu_config_range((void *)_ssram, _ssram_size, MA_MEM | MA_S | MA_RW); mmu_config_range((void *)_bsram, _bsram_size, MA_MEM | MA_S | MA_RW); -#ifdef CONFIG_QC_SOC_SIMULATE mmu_config_range((void *)0x80000000, 0x40000000, MA_MEM | MA_S | MA_RW); -#endif mmu_enable(); } -#ifdef CONFIG_QC_SOC_SIMULATE void qcs405_mmu_dram_config_c(void) { mmu_config_range((void *)0x80000000, 0x40000000, MA_MEM | MA_NS | MA_RW); } -#endif diff --git a/src/soc/qualcomm/qcs405/qclib_execute.c b/src/soc/qualcomm/qcs405/qclib_execute.c new file mode 100644 index 0000000..917a04c --- /dev/null +++ b/src/soc/qualcomm/qcs405/qclib_execute.c @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <arch/cache.h> +#include <arch/mmu.h> +#include <cbfs.h> +#include <halt.h> +#include <console/console.h> +#include <timestamp.h> +#include <soc/mmu.h> +#include <soc/qclib.h> +#include <soc/symbols.h> + +#define PMIC_NAME "/pmiccfg" +#define DCB_NAME "/dcb" +#define QCLIB_NAME "/qclib" + +#define PBL_DATA_PTR 0x8c101a0 //0x14810188 + +void qclib_load_and_run(void) +{ + int (*doit)(void *, void *); + void *arg; + int ret_code; + struct mmu_context pre_qclib_mmu_context; + + struct prog qclib = + PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX QCLIB_NAME); + + struct prog pmic = + PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX PMIC_NAME); + + /* Attempt to load PMICCFG Blob */ +#if 0 + if (!cbfs_boot_load_file(CONFIG_CBFS_PREFIX PMIC_NAME, + _pmic, _pmic_size, CBFS_TYPE_RAW)) + goto fail; +#else + if (prog_locate(&pmic)) + goto fail; + + if (cbfs_prog_stage_load(&pmic)) + goto fail; +#endif + /* Attempt to load DCB Blob */ +// if (!cbfs_boot_load_file(CONFIG_CBFS_PREFIX DCB_NAME, +// _dcb, _dcb_size, CBFS_TYPE_RAW)) +// goto fail; + + /* Attempt to load QCLib elf */ + if (prog_locate(&qclib)) + goto fail; + + if (cbfs_prog_stage_load(&qclib)) + goto fail; + + prog_set_entry(&qclib, qclib.entry, (void *)PBL_DATA_PTR); + + printk(BIOS_DEBUG, "\n\n\nQCLib is about to Initialize PMIC and DDR\n"); + printk(BIOS_DEBUG, "Jumping to QCLib code at %p(%p)\n", + prog_entry(&qclib), prog_entry_arg(&qclib)); + + doit = prog_entry(&qclib); + arg = prog_entry_arg(&qclib); + + /* back-up mmu context before disabling mmu and executing qclib */ + mmu_save_context(&pre_qclib_mmu_context); + /* disable mmu before jumping to qclib. mmu_disable also + flushes and invalidates caches before disabling mmu. */ + mmu_disable(); + + ret_code = doit(arg, NULL); + printk(BIOS_DEBUG, "QCLib completed\n\n\n"); + + /* Before returning, QCLib flushes cache and disables mmu. + Explicitly disable mmu (flush, invalidate and disable mmu) + before re-enabling mmu with backed-up mmu context */ + mmu_disable(); + mmu_restore_context(&pre_qclib_mmu_context); + mmu_enable(); + + qcs405_mmu_dram_config_c(); + return; + +fail: + die("Couldn't run QCLib.\n"); +} + -- To view, visit https://review.coreboot.org/c/coreboot/+/29967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07 Gerrit-Change-Number: 29967 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: Coreboot: Add support for USB host mode for mistral platform
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29966 Change subject: Coreboot: Add support for USB host mode for mistral platform ...................................................................... Coreboot: Add support for USB host mode for mistral platform Add required changes for USB host mode working on mistral platform for USB disk enumeration. Change-Id: I35ec549b49b9789389c80843f6103e7243d52aac Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Vijayavardhan Vennapusa <vvreddy(a)partner-android.googlesource.com> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/mainboard/google/mistral/mainboard.c M src/mainboard/google/mistral/romstage.c M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/include/soc/addressmap.h M src/soc/qualcomm/qcs405/include/soc/clock.h M src/soc/qualcomm/qcs405/include/soc/iomap.h A src/soc/qualcomm/qcs405/include/soc/usb.h A src/soc/qualcomm/qcs405/usb.c 8 files changed, 370 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/29966/1 diff --git a/src/mainboard/google/mistral/mainboard.c b/src/mainboard/google/mistral/mainboard.c index c249a32..7201874 100644 --- a/src/mainboard/google/mistral/mainboard.c +++ b/src/mainboard/google/mistral/mainboard.c @@ -16,10 +16,34 @@ #include <device/device.h> #include <bootblock_common.h> #include <timestamp.h> +#include <soc/usb.h> + +static struct usb_board_data usb0_board_data = { + .parameter_override_x0 = 0x63, + .parameter_override_x1 = 0x03, + .parameter_override_x0 = 0x1d, + .parameter_override_x1 = 0x03, +}; + +static struct usb_board_data usb1_board_data = { + .parameter_override_x0 = 0x63, + .parameter_override_x1 = 0x03, + .parameter_override_x0 = 0x1d, + .parameter_override_x1 = 0x03, +}; + +static void setup_usb(void) +{ + /* Setting Primarty usb controller */ + setup_usb_host(HSUSB_SS_PORT_0, &usb0_board_data); + + /* Setting secondary usb controller */ + setup_usb_host(HSUSB_HS_PORT_1, &usb1_board_data); +} static void mainboard_init(device_t dev) { - + setup_usb(); } static void mainboard_enable(device_t dev) diff --git a/src/mainboard/google/mistral/romstage.c b/src/mainboard/google/mistral/romstage.c index 71968fc..31e5113 100644 --- a/src/mainboard/google/mistral/romstage.c +++ b/src/mainboard/google/mistral/romstage.c @@ -20,12 +20,19 @@ #include <console/console.h> #include <timestamp.h> #include <arch/stages.h> +#include <soc/usb.h> #ifdef CONFIG_QC_SOC_SIMULATE extern void qcs405_mmu_dram_config_c(void); #endif void platform_romstage_main(void) { + /* + * Do DWC3 core and phy reset. Kick these resets off early + * so they get atleast 1msec to settle. + */ + reset_usb(HSUSB_SS_PORT_0); + reset_usb(HSUSB_HS_PORT_1); #ifdef CONFIG_QC_SOC_SIMULATE qcs405_mmu_dram_config_c(); #endif diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index 57d59f8..c174cae 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -27,6 +27,7 @@ romstage-y += mmu.c romstage-$(CONFIG_DRIVERS_UART) += uart.c romstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c +romstage-y += usb.c ################################################################################ ramstage-y += soc.c @@ -37,6 +38,7 @@ ramstage-y += clock.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c +ramstage-y += usb.c ################################################################################ diff --git a/src/soc/qualcomm/qcs405/include/soc/addressmap.h b/src/soc/qualcomm/qcs405/include/soc/addressmap.h index 435b680..696bc42 100644 --- a/src/soc/qualcomm/qcs405/include/soc/addressmap.h +++ b/src/soc/qualcomm/qcs405/include/soc/addressmap.h @@ -23,4 +23,12 @@ #define TLMM_NORTH_TILE_BASE 0x1300000 #define TLMM_SOUTH_TILE_BASE 0x1000000 +/* USB BASE ADDRESS */ +#define USB_HOST0_DWC3_BASE 0x758C100 +#define USB3_USB30_QSCRATCH_BASE 0x7678800 +#define USB2_FEMTO_PHY_PRI_BASE 0x007A000 + +#define USB_HOST1_DWC3_BASE 0x78CC100 +#define USB2_USB30_QSCRATCH_BASE 0x79B8800 +#define USB2_FEMTO_PHY_SEC_BASE 0x007C000 #endif /* __SOC_QUALCOMM_QCS405_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/qcs405/include/soc/clock.h b/src/soc/qualcomm/qcs405/include/soc/clock.h index aa8bbe5..d02ecd7 100644 --- a/src/soc/qualcomm/qcs405/include/soc/clock.h +++ b/src/soc/qualcomm/qcs405/include/soc/clock.h @@ -65,10 +65,10 @@ /** * USB BCR registers */ -#define GCC_USB_HS_PHY_CFG_AHB_BCR 0x1841038 +#define GCC_USB_HS_PHY_CFG_AHB_BCR 0x180000C #define GCC_USB_HS_BCR 0x1841000 #define GCC_USB_30_BCR 0x1839000 -#define GCC_USB2A_PHY_BCR 0x1841028 +#define GCC_USB2A_PHY_BCR 0x180000C #define GCC_USB2_HS_PHY_ONLY_BCR 0x1841034 #define GCC_QUSB2_PHY_BCR 0x184103C diff --git a/src/soc/qualcomm/qcs405/include/soc/iomap.h b/src/soc/qualcomm/qcs405/include/soc/iomap.h index 2a7a148..571c62f 100644 --- a/src/soc/qualcomm/qcs405/include/soc/iomap.h +++ b/src/soc/qualcomm/qcs405/include/soc/iomap.h @@ -99,14 +99,6 @@ #define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 * (x)) #define GPIO_IN_OUT_ADDR(x) (GPIO_CONFIG_ADDR(x) + 4) -/* Yes, this is not a typo... host2 is actually mapped before host1. */ -#define USB_HOST2_XHCI_BASE 0x10000000 -#define USB_HOST2_DWC3_BASE 0x1000C100 -#define USB_HOST2_PHY_BASE 0x100F8800 -#define USB_HOST1_XHCI_BASE 0x11000000 -#define USB_HOST1_DWC3_BASE 0x1100C100 -#define USB_HOST1_PHY_BASE 0x110F8800 - #define UART1_DM_BASE ((void *)0x078af000) #define UART2_DM_BASE ((void *)0x078B1000) diff --git a/src/soc/qualcomm/qcs405/include/soc/usb.h b/src/soc/qualcomm/qcs405/include/soc/usb.h new file mode 100644 index 0000000..80674bb --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/usb.h @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2018 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <types.h> + +#ifndef _QCS405_USB_H_ +#define _QCS405_USB_H_ + +/* QSCRATCH_GENERAL_CFG register bit offset */ +#define PIPE_UTMI_CLK_SEL BIT(0) +#define PIPE3_PHYSTATUS_SW BIT(3) +#define PIPE_UTMI_CLK_DIS BIT(8) + +/* Global USB3 Control Registers */ +#define DWC3_GUSB3PIPECTL_DELAYP1TRANS BIT(18) +#define DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX BIT(27) +#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) +#define DWC3_GCTL_PRTCAP_OTG 3 +#define DWC3_GCTL_PRTCAP_HOST 1 + +/* Global USB2 PHY Configuration Register */ +#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10) +#define DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) +#define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3) +#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) +#define USBTRDTIM_UTMI_8_BIT 9 +#define UTMI_PHYIF_8_BIT 0 + +#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) +#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) +#define DWC3_GCTL_DISSCRAMBLE (1 << 3) +#define DWC3_GCTL_U2EXIT_LFPS (1 << 2) +#define DWC3_GCTL_DSBLCLKGTNG (1 << 0) + +/* USB2 PHY register values */ +#define USB2PHY_TCSR_CTRL 0x01 +#define USB2PHY_REFCLK_CTRL 0x0d +#define USB2PHY_UTMI_CTRL5 0x12 +#define USB2PHY_PARAMETER_OVERRIDE_X0 0x63 +#define USB2PHY_PARAMETER_OVERRIDE_X1 0x03 +#define USB2PHY_PARAMETER_OVERRIDE_X2 0x1d +#define USB2PHY_PARAMETER_OVERRIDE_X3 0x03 +#define USB2PHY_HS_PHY_CTRL1 0x23 +#define QUSB2PHY_HS_PHY_CTRL_COMMON0 0x08 +#define QUSB2PHY_HS_PHY_CTRL_COMMON1 0xdc +#define USB2PHY_HS_PHY_CTRL2 0xe0 + +struct usb_board_data { + /* Register values going to override from the boardfile */ + u8 parameter_override_x0; + u8 parameter_override_x1; + u8 parameter_override_x2; + u8 parameter_override_x3; +}; + +enum usb_port { + HSUSB_SS_PORT_0, + HSUSB_HS_PORT_1, +}; + +void setup_usb_host(enum usb_port port, struct usb_board_data *data); +/* Call reset_ before setup_ */ +void reset_usb(enum usb_port port); + +#endif /* _QCS405_USB_H_ */ diff --git a/src/soc/qualcomm/qcs405/usb.c b/src/soc/qualcomm/qcs405/usb.c new file mode 100644 index 0000000..67574cf --- /dev/null +++ b/src/soc/qualcomm/qcs405/usb.c @@ -0,0 +1,250 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2018 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <lib.h> +#include <stdlib.h> +#include <console/console.h> +#include <delay.h> +#include <soc/usb.h> +#include <soc/clock.h> +#include <soc/addressmap.h> +#include <timer.h> + +struct usb_qscratch { + u8 rsvd0[8]; + u32 *qscratch_cfg_reg; + +}; +check_member(usb_qscratch, qscratch_cfg_reg, 0x08); + +struct usb_usb2_phy_dig { + u8 rsvd1[116]; + u32 utmi_ctrl5; + u32 ctrl_common0; + u32 ctrl_common1; + u8 rsvd2[12]; + u32 phy_ctrl1; + u32 phy_ctrl2; + u8 rsvd3; + u32 override_x0; + u32 override_x1; + u32 override_x2; + u32 override_x3; + u8 rsvd4[24]; + u32 tcsr_ctrl; + u8 rsvd5[36]; + u32 refclk_ctrl; +}; +check_member(usb_usb2_phy_dig, utmi_ctrl5, 0x74); +check_member(usb_usb2_phy_dig, phy_ctrl1, 0x8C); +check_member(usb_usb2_phy_dig, override_x0, 0x98); +check_member(usb_usb2_phy_dig, tcsr_ctrl, 0xC0); +check_member(usb_usb2_phy_dig, refclk_ctrl, 0xE8); + +struct usb_dwc3 { + u32 sbuscfg0; + u32 sbuscfg1; + u32 txthrcfg; + u32 rxthrcfg; + u32 ctl; + u32 pmsts; + u32 sts; + u32 uctl1; + u32 snpsid; + u32 gpio; + u32 uid; + u32 uctl; + u64 buserraddr; + u64 prtbimap; + u8 reserved1[32]; + u32 dbgfifospace; + u32 dbgltssm; + u32 dbglnmcc; + u32 dbgbmu; + u32 dbglspmux; + u32 dbglsp; + u32 dbgepinfo0; + u32 dbgepinfo1; + u64 prtbimap_hs; + u64 prtbimap_fs; + u8 reserved2[112]; + u32 usb2phycfg; + u8 reserved3[60]; + u32 usb2i2cctl; + u8 reserved4[60]; + u32 usb2phyacc; + u8 reserved5[60]; + u32 usb3pipectl; + u8 reserved6[60]; +}; +check_member(usb_dwc3, usb3pipectl, 0x1c0); + +struct usb_dwc3_cfg { + struct usb_dwc3 *usb_host_dwc3; + struct usb_usb2_phy_dig *usb2_phy_dig; + struct usb_qscratch *usb_qscratch_reg; + u32 *usb2_phy_bcr; + u32 *usb2_phy_por_bcr; + u32 *usb3_bcr; + struct usb_board_data *board_data; +}; + +static struct usb_dwc3_cfg usb_host_base[2] = { + [HSUSB_SS_PORT_0] = { + .usb_host_dwc3 = (void *)USB_HOST0_DWC3_BASE, + .usb2_phy_dig = (void *)USB2_FEMTO_PHY_PRI_BASE, + .usb2_phy_bcr = (void *)GCC_USB_HS_PHY_CFG_AHB_BCR, + .usb2_phy_por_bcr = (void *)GCC_USB2A_PHY_BCR, + .usb3_bcr = (void *)GCC_USB_30_BCR, + .usb_qscratch_reg = (void *)USB3_USB30_QSCRATCH_BASE, + }, + [HSUSB_HS_PORT_1] = { + .usb_host_dwc3 = (void *)USB_HOST1_DWC3_BASE, + .usb2_phy_dig = (void *)USB2_FEMTO_PHY_SEC_BASE, + .usb2_phy_bcr = (void *)GCC_QUSB2_PHY_BCR, + .usb2_phy_por_bcr = (void *)GCC_USB2_HS_PHY_ONLY_BCR, + .usb3_bcr = (void *)GCC_USB_HS_BCR, + .usb_qscratch_reg = (void *)USB2_USB30_QSCRATCH_BASE, + }, +}; + +void reset_usb(enum usb_port port) +{ + struct usb_dwc3_cfg *dwc3 = &usb_host_base[port]; + + /* Put Core in Reset */ + printk(BIOS_INFO, "Starting DWC3 reset for USB%d\n", port); + + /* Assert Core reset */ + clock_reset_bcr(dwc3->usb3_bcr, 1); +} + +static void usb2_phy_override_phy_params(struct usb_dwc3_cfg *dwc3) +{ + write8(&dwc3->usb2_phy_dig->override_x0, dwc3->board_data->parameter_override_x0); + write8(&dwc3->usb2_phy_dig->override_x1, dwc3->board_data->parameter_override_x1); + write8(&dwc3->usb2_phy_dig->override_x2, dwc3->board_data->parameter_override_x2); + write8(&dwc3->usb2_phy_dig->override_x3, dwc3->board_data->parameter_override_x3); +} + +static void hs_usb_phy_init(struct usb_dwc3_cfg *dwc3) +{ + write8(&dwc3->usb2_phy_dig->tcsr_ctrl, USB2PHY_TCSR_CTRL); + write8(&dwc3->usb2_phy_dig->refclk_ctrl, USB2PHY_REFCLK_CTRL); + write8(&dwc3->usb2_phy_dig->utmi_ctrl5, USB2PHY_UTMI_CTRL5); + write8(&dwc3->usb2_phy_dig->override_x0, USB2PHY_PARAMETER_OVERRIDE_X0); + write8(&dwc3->usb2_phy_dig->override_x1, USB2PHY_PARAMETER_OVERRIDE_X1); + write8(&dwc3->usb2_phy_dig->override_x2, USB2PHY_PARAMETER_OVERRIDE_X2); + write8(&dwc3->usb2_phy_dig->override_x3, USB2PHY_PARAMETER_OVERRIDE_X3); + + if (dwc3->board_data) + /* Overridw board specific PHY tuning values */ + usb2_phy_override_phy_params(dwc3); + + write8(&dwc3->usb2_phy_dig->phy_ctrl1, USB2PHY_HS_PHY_CTRL1); + write8(&dwc3->usb2_phy_dig->ctrl_common0, QUSB2PHY_HS_PHY_CTRL_COMMON0); + write8(&dwc3->usb2_phy_dig->ctrl_common1, QUSB2PHY_HS_PHY_CTRL_COMMON1); + write8(&dwc3->usb2_phy_dig->phy_ctrl2, USB2PHY_HS_PHY_CTRL2); + udelay(20); + write8(&dwc3->usb2_phy_dig->utmi_ctrl5, 0x10); + write8(&dwc3->usb2_phy_dig->phy_ctrl2, 0x60); +} + +static void setup_dwc3(struct usb_dwc3 *dwc3) +{ + /* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */ + clrsetbits_le32(&dwc3->usb3pipectl, + DWC3_GUSB3PIPECTL_DELAYP1TRANS, + DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX); + + clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK | + DWC3_GCTL_DISSCRAMBLE), + DWC3_GCTL_U2EXIT_LFPS | DWC3_GCTL_DSBLCLKGTNG); + + /* configure controller in Host mode */ + clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)), + DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_HOST)); + printk(BIOS_INFO, "Configure USB in Host mode\n"); +} + +/* Initialization of DWC3 Core and PHY */ +void setup_usb_host(enum usb_port port, struct usb_board_data *board_data) +{ + struct usb_dwc3_cfg *dwc3 = &usb_host_base[port]; + u32 val; + + printk(BIOS_INFO, "Setting up USB HOST%d controller.\n", port); + + dwc3->board_data = board_data; + + /* Clear core reset. */ + clock_reset_bcr(dwc3->usb3_bcr, 0); + + + if (port == HSUSB_SS_PORT_0) { + /* Set PHY reset. */ + setbits_le32(&dwc3->usb2_phy_bcr, BIT(1)); + udelay(15); + /* Clear PHY reset. */ + clrbits_le32(&dwc3->usb2_phy_bcr, BIT(1)); + } else { + clock_reset_bcr(dwc3->usb2_phy_bcr, 1); + udelay(15); + clock_reset_bcr(dwc3->usb2_phy_bcr, 0); + } + udelay(100); + + /* Initialize PHYs */ + hs_usb_phy_init(dwc3); + + if (port == HSUSB_SS_PORT_0) { + /* Set PHY POR reset. */ + setbits_le32(&dwc3->usb2_phy_por_bcr, BIT(0)); + val = read8(&dwc3->usb2_phy_dig->ctrl_common0); + val &= ~(0x4); + write8(&dwc3->usb2_phy_dig->ctrl_common0, val); + udelay(20); + /* Clear PHY POR reset. */ + clrbits_le32(&dwc3->usb2_phy_por_bcr, BIT(0)); + } else { + clock_reset_bcr(dwc3->usb2_phy_por_bcr, 1); + val = read8(&dwc3->usb2_phy_dig->ctrl_common0); + val &= ~(0x4); + write8(&dwc3->usb2_phy_dig->ctrl_common0, val); + udelay(20); + clock_reset_bcr(dwc3->usb2_phy_por_bcr, 0); + } + udelay(100); + + setup_dwc3(dwc3->usb_host_dwc3); + + /* + * Below sequence is used when dwc3 operates without + * SSPHY and only HS/FS/LS modes are supported. + */ + + /* Configure dwc3 to use UTMI clock as PIPE clock not present */ + setbits_le32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg, + PIPE_UTMI_CLK_DIS); + udelay(2); + setbits_le32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg, + PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW); + udelay(3); + clrbits_le32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg, + PIPE_UTMI_CLK_DIS); + + printk(BIOS_INFO, "DWC3 and PHY setup finished\n"); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/29966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35ec549b49b9789389c80843f6103e7243d52aac Gerrit-Change-Number: 29966 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: libpayload: Fix uart driver for qcs405 support
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29965 Change subject: libpayload: Fix uart driver for qcs405 support ...................................................................... libpayload: Fix uart driver for qcs405 support Change-Id: Ied54cf5dd13e9ab752533ad07e9ea906f41060b8 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M payloads/libpayload/drivers/serial/ipq40xx.c 1 file changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/29965/1 diff --git a/payloads/libpayload/drivers/serial/ipq40xx.c b/payloads/libpayload/drivers/serial/ipq40xx.c index 52d71b8..6ffa3f9 100644 --- a/payloads/libpayload/drivers/serial/ipq40xx.c +++ b/payloads/libpayload/drivers/serial/ipq40xx.c @@ -269,7 +269,7 @@ #define MSM_BOOT_UART_DM_E_RX_NOT_READY 5 #define UART1_DM_BASE ((void *)0x078af000) -#define UART2_DM_BASE ((void *)0x078b0000) +#define UART2_DM_BASE ((void *)0x078b1000) enum { BLSP1_UART1, @@ -288,8 +288,8 @@ * board/qcom/ipq40xx_cdp/ipq40xx_board_param.h */ static const uart_params_t uart_board_param = { - .uart_dm_base = UART1_DM_BASE, - .blsp_uart = BLSP1_UART1, + .uart_dm_base = UART2_DM_BASE, + .blsp_uart = BLSP1_UART2, }; #define write32(addr, val) writel(val, addr) @@ -558,6 +558,8 @@ if (!sc_ptr) return; + msm_boot_uart_dm_init(uart_board_param.uart_dm_base); + consin.havekey = serial_havechar; consin.getchar = serial_getchar; -- To view, visit https://review.coreboot.org/c/coreboot/+/29965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied54cf5dd13e9ab752533ad07e9ea906f41060b8 Gerrit-Change-Number: 29965 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: qcs405: Add blsp uart driver
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29964 Change subject: qcs405: Add blsp uart driver ...................................................................... qcs405: Add blsp uart driver Change-Id: Id9626c68eadead8b8ec5ffbc08cab7b0ec36478f Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Prudhvi Yarlagadda<pyarlaga(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Makefile.inc A src/soc/qualcomm/qcs405/include/soc/blsp.h A src/soc/qualcomm/qcs405/include/soc/cdp.h A src/soc/qualcomm/qcs405/include/soc/iomap.h A src/soc/qualcomm/qcs405/include/soc/ipq_uart.h A src/soc/qualcomm/qcs405/uart.c 6 files changed, 976 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/29964/1 diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index 58a62fa..57d59f8 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -8,14 +8,14 @@ bootblock-y += timer.c bootblock-y += gpio.c bootblock-y += clock.c -bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c +bootblock-$(CONFIG_DRIVERS_UART) += uart.c bootblock-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c ################################################################################ verstage-y += spi.c verstage-y += timer.c verstage-y += gpio.c -verstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c +verstage-$(CONFIG_DRIVERS_UART) += uart.c verstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c ################################################################################ @@ -25,7 +25,7 @@ romstage-y += gpio.c romstage-y += clock.c romstage-y += mmu.c -romstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c +romstage-$(CONFIG_DRIVERS_UART) += uart.c romstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c ################################################################################ @@ -35,7 +35,7 @@ ramstage-y += timer.c ramstage-y += gpio.c ramstage-y += clock.c -ramstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c +ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c ################################################################################ diff --git a/src/soc/qualcomm/qcs405/include/soc/blsp.h b/src/soc/qualcomm/qcs405/include/soc/blsp.h new file mode 100644 index 0000000..ce74e56 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/blsp.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2011-2012 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef __BLSP_H_ +#define __BLSP_H_ + +typedef enum { + BLSP_QUP_ID_0, + BLSP_QUP_ID_1, + BLSP_QUP_ID_2, + BLSP_QUP_ID_3, +} blsp_qup_id_t; + +typedef enum { + BLSP_SUCCESS = 0, + BLSP_ID_ERROR, + BLSP_ERROR, + BLSP_UNSUPPORTED +} blsp_return_t; + +typedef enum { + BLSP_PROTO_I2C_UIM = 1, + BLSP_PROTO_I2C_ONLY, + BLSP_PROTO_SPI_ONLY, + BLSP_PROTO_UART_FLOW_CTL, + BLSP_PROTO_UIM, + BLSP_PROTO_I2C_UART, +} blsp_protocol_t; + +blsp_return_t blsp_i2c_init(blsp_qup_id_t id); +int blsp_i2c_init_board(blsp_qup_id_t id); + +#endif diff --git a/src/soc/qualcomm/qcs405/include/soc/cdp.h b/src/soc/qualcomm/qcs405/include/soc/cdp.h new file mode 100644 index 0000000..ca9e996 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/cdp.h @@ -0,0 +1,175 @@ +/* + * Copyright (c) 2012 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _IPQ40XX_CDP_H_ +#define _IPQ40XX_CDP_H_ + +#include <types.h> + +unsigned smem_get_board_machtype(void); + +typedef enum { + PHY_INTERFACE_MODE_MII, + PHY_INTERFACE_MODE_GMII, + PHY_INTERFACE_MODE_SGMII, + PHY_INTERFACE_MODE_QSGMII, + PHY_INTERFACE_MODE_TBI, + PHY_INTERFACE_MODE_RMII, + PHY_INTERFACE_MODE_RGMII, + PHY_INTERFACE_MODE_RGMII_ID, + PHY_INTERFACE_MODE_RGMII_RXID, + PHY_INTERFACE_MODE_RGMII_TXID, + PHY_INTERFACE_MODE_RTBI, + PHY_INTERFACE_MODE_XGMII, + PHY_INTERFACE_MODE_NONE /* Must be last */ +} phy_interface_t; + +typedef struct { + gpio_t gpio; + unsigned int func; + unsigned int dir; + unsigned int pull; + unsigned int drvstr; + unsigned int enable; +} gpio_func_data_t; + +typedef struct { + unsigned int m_value; + unsigned int n_value; + unsigned int d_value; +} uart_clk_mnd_t; + +/* SPI Mode */ + +typedef enum { + NOR_SPI_MODE_0, + NOR_SPI_MODE_1, + NOR_SPI_MODE_2, + NOR_SPI_MODE_3, +} spi_mode; + +/* SPI GSBI Bus number */ + +typedef enum { + GSBI_BUS_5 = 0, + GSBI_BUS_6, + GSBI_BUS_7, +} spi_gsbi_bus_num; + +/* SPI Chip selects */ + +typedef enum { + SPI_CS_0 , + SPI_CS_1, + SPI_CS_2, + SPI_CS_3, +} spi_cs; + +/* Flash Types */ + +typedef enum { + ONLY_NAND, + ONLY_NOR, + NAND_NOR, + NOR_MMC, +} flash_desc; + +#define NO_OF_DBG_UART_GPIOS 2 + +#define SPI_NOR_FLASH_VENDOR_MICRON 0x1 +#define SPI_NOR_FLASH_VENDOR_SPANSION 0x2 + +/* SPI parameters */ + +typedef struct { + spi_mode mode; + spi_gsbi_bus_num bus_number; + spi_cs chip_select; + int vendor; +} spinorflash_params_t; + +typedef struct { + unsigned count; + uint8_t addr[7]; +} ipq_gmac_phy_addr_t; + +typedef struct { + unsigned base; + int unit; + unsigned is_macsec; + unsigned mac_pwr0; + unsigned mac_pwr1; + unsigned mac_conn_to_phy; + phy_interface_t phy; + ipq_gmac_phy_addr_t phy_addr; +} ipq_gmac_board_cfg_t; + +#define IPQ_GMAC_NMACS 4 + +enum gale_board_id { + BOARD_ID_GALE_PROTO = 0, + BOARD_ID_GALE_EVT = 1, + BOARD_ID_GALE_EVT2_0 = 2, + BOARD_ID_GALE_EVT2_1 = 6, + BOARD_ID_GALE_EVT3 = 5, +}; + +/* Board specific parameters */ +typedef struct { +#if 0 + unsigned int gmac_gpio_count; + gpio_func_data_t *gmac_gpio; + ipq_gmac_board_cfg_t gmac_cfg[IPQ_GMAC_NMACS]; + flash_desc flashdesc; + spinorflash_params_t flash_param; +#endif +} __packed board_ipq40xx_params_t; + +extern board_ipq40xx_params_t *gboard_param; + +#if 0 +static inline int gmac_cfg_is_valid(ipq_gmac_board_cfg_t *cfg) +{ + /* + * 'cfg' is valid if and only if + * unit number is non-negative and less than IPQ_GMAC_NMACS. + * 'cfg' pointer lies within the array range of + * board_ipq40xx_params_t->gmac_cfg[] + */ + return ((cfg >= &gboard_param->gmac_cfg[0]) && + (cfg < &gboard_param->gmac_cfg[IPQ_GMAC_NMACS]) && + (cfg->unit >= 0) && (cfg->unit < IPQ_GMAC_NMACS)); +} +#endif + +unsigned int get_board_index(unsigned machid); +void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count); + +#endif /* _IPQ40XX_CDP_H_ */ diff --git a/src/soc/qualcomm/qcs405/include/soc/iomap.h b/src/soc/qualcomm/qcs405/include/soc/iomap.h new file mode 100644 index 0000000..2a7a148 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/iomap.h @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2012 - 2013, 2015 The Linux Foundation. All rights reserved. + * + * Copyright (c) 2008, Google Inc. + * All rights reserved. + * + * Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Google, Inc. nor the names of its contributors + * may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef __SOC_QUALCOMM_IPQ40XX_IOMAP_H_ +#define __SOC_QUALCOMM_IPQ40XX_IOMAP_H_ + +#include <arch/io.h> +#include <soc/cdp.h> +#include <soc/blsp.h> + +/* Typecast to allow integers being passed as address + This needs to be included because vendor code is not compliant with our + macros for read/write. Hence, special macros for readl_i and writel_i are + included to do this in one place for all occurrences in vendor code + */ +#define readl_i(a) read32((const void *)(a)) +#define writel_i(v,a) write32((void *)a, v) +#define clrsetbits_le32_i(addr, clear, set) \ + clrsetbits_le32(((void *)(addr)), (clear), (set)) + +#define GCC_CLK_CTL_REG ((void *)0x01800000u) +#define MSM_CLK_CTL_BASE GCC_CLK_CTL_REG +#define GCC_CLK_BRANCH_ENA (GCC_CLK_CTL_REG + 0x6000) +#define IMEM_AXI (1 << 17) +#define SYS_NOC_APSS_AHB (1 << 16) +#define BIMC_AXI_M0 (1 << 15) +#define APSS_AHB (1 << 14) +#define APSS_AXI (1 << 13) +#define MPM_AHB (1 << 12) +#define GMEM_SYS_NOC_AXI (1 << 11) +#define BLSP1_AHB (1 << 10) +#define BLSP1_SLEEP (1 << 9) +#define PRNG_AHB (1 << 8) +#define BOOT_ROM_AHB (1 << 7) +#define MSG_RAM_AHB (1 << 6) +#define TLMM_AHB (1 << 5) +#define TLMM (1 << 4) +#define SPMI_PCNOC_AHB (1 << 3) +#define CRYPTO (1 << 2) +#define CRYPTO_AXI (1 << 1) +#define CRYPTO_AHB (1 << 0) + +#define GCC_BLSP1_QUP1_I2C_APPS_CBCR (MSM_CLK_CTL_BASE + 0x2008) +#define GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR (MSM_CLK_CTL_BASE + 0x200c) +#define GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR (MSM_CLK_CTL_BASE + 0x2010) +#define GCC_BLSP1_QUP2_I2C_APPS_CBCR (MSM_CLK_CTL_BASE + 0x3010) +#define GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR (MSM_CLK_CTL_BASE + 0x3000) +#define GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR (MSM_CLK_CTL_BASE + 0x3004) + +#define GCNT_GLOBAL_CTRL_BASE ((void *)0x004a0000u) +#define GCNT_CNTCR (GCNT_GLOBAL_CTRL_BASE + 0x1000) +#define GCNT_GLB_CNTCV_LO (GCNT_GLOBAL_CTRL_BASE + 0x1008) +#define GCNT_GLB_CNTCV_HI (GCNT_GLOBAL_CTRL_BASE + 0x100c) +#define GCNT_CNTCV_LO (GCNT_GLOBAL_CTRL_BASE + 0x2000) +#define GCNT_CNTCV_HI (GCNT_GLOBAL_CTRL_BASE + 0x2004) + +#define GCNT_PSHOLD ((void *)0x004AB000u) + +/* RPM interface constants */ +#define RPM_INT ((void *)0x63020) +#define RPM_INT_ACK ((void *)0x63060) +#define RPM_SIGNAL_COOKIE ((void *)0x47C20) +#define RPM_SIGNAL_ENTRY ((void *)0x47C24) +#define RPM_FW_MAGIC_NUM 0x4D505242 + +#define TLMM_BASE_ADDR ((void *)0x01000000) +#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 * (x)) +#define GPIO_IN_OUT_ADDR(x) (GPIO_CONFIG_ADDR(x) + 4) + +/* Yes, this is not a typo... host2 is actually mapped before host1. */ +#define USB_HOST2_XHCI_BASE 0x10000000 +#define USB_HOST2_DWC3_BASE 0x1000C100 +#define USB_HOST2_PHY_BASE 0x100F8800 +#define USB_HOST1_XHCI_BASE 0x11000000 +#define USB_HOST1_DWC3_BASE 0x1100C100 +#define USB_HOST1_PHY_BASE 0x110F8800 + +#define UART1_DM_BASE ((void *)0x078af000) +#define UART2_DM_BASE ((void *)0x078B1000) + +enum { + BLSP1_UART1, + BLSP1_UART2, +}; + +#define GCC_BLSP1_UART_BCR_BASE (GCC_CLK_CTL_REG + 0x2038) +#define GCC_BLSP1_UART_BCR(x) (GCC_BLSP1_UART_BCR_BASE + (x) * 0xff0) +#define GCC_BLSP1_UART_APPS_CBCR(x) (GCC_BLSP1_UART_BCR(x) + 4) +#define GCC_BLSP1_UART_APPS_CMD_RCGR(x) (GCC_BLSP1_UART_APPS_CBCR(x) + 8) +#define GCC_BLSP1_UART_APPS_CFG_RCGR(x) (GCC_BLSP1_UART_APPS_CMD_RCGR(x) + 4) +#define GCC_BLSP1_UART_APPS_M(x) (GCC_BLSP1_UART_APPS_CFG_RCGR(x) + 4) +#define GCC_BLSP1_UART_APPS_N(x) (GCC_BLSP1_UART_APPS_M(x) + 4) +#define GCC_BLSP1_UART_APPS_D(x) (GCC_BLSP1_UART_APPS_N(x) + 4) +#define GCC_BLSP1_UART_MISC(x) (GCC_BLSP1_UART_APPS_D(x) + 4) + +#define BLSP1_QUP0_BASE ((void *)0x078B5000) +#define BLSP1_QUP1_BASE ((void *)0x078B6000) +#define BLSP1_QUP2_BASE ((void *)0x078B7000) +#define BLSP1_QUP3_BASE ((void *)0x078B8000) + +#define TCSR_BOOT_MISC_DETECT ((void *)0x0193D100) +#define TCSR_RESET_DEBUG_SW_ENTRY ((void *)0x01940000) + +static inline void *blsp_qup_base(blsp_qup_id_t id) +{ + switch (id) { + case BLSP_QUP_ID_0: return BLSP1_QUP0_BASE; + case BLSP_QUP_ID_1: return BLSP1_QUP1_BASE; + case BLSP_QUP_ID_2: return BLSP1_QUP2_BASE; + case BLSP_QUP_ID_3: return BLSP1_QUP3_BASE; + } + return NULL; +} + +#define BLSP_MINI_CORE_SHIFT 8 +#define BLSP_MINI_CORE_I2C (0x2u << BLSP_MINI_CORE_SHIFT) +#define BLSP_MINI_CORE_MASK (0xfu << BLSP_MINI_CORE_SHIFT) + +#define ETIMEDOUT -10 +#define EINVAL -11 +#define EIO -12 + +#endif // __SOC_QUALCOMM_IPQ40XX_IOMAP_H_ diff --git a/src/soc/qualcomm/qcs405/include/soc/ipq_uart.h b/src/soc/qualcomm/qcs405/include/soc/ipq_uart.h new file mode 100644 index 0000000..8cb0f25 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/ipq_uart.h @@ -0,0 +1,273 @@ +/* + * Copyright (c) 2012 The Linux Foundation. All rights reserved.* + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __UART_DM_H__ +#define __UART_DM_H__ + +#define PERIPH_BLK_BLSP 1 + +#define MSM_BOOT_UART_DM_EXTR_BITS(value, start_pos, end_pos) \ + ((value << (32 - end_pos)) >> (32 - (end_pos - start_pos))) + +extern void __udelay(unsigned long usec); + + +enum MSM_BOOT_UART_DM_PARITY_MODE { + MSM_BOOT_UART_DM_NO_PARITY, + MSM_BOOT_UART_DM_ODD_PARITY, + MSM_BOOT_UART_DM_EVEN_PARITY, + MSM_BOOT_UART_DM_SPACE_PARITY +}; + +/* UART Stop Bit Length */ +enum MSM_BOOT_UART_DM_STOP_BIT_LEN { + MSM_BOOT_UART_DM_SBL_9_16, + MSM_BOOT_UART_DM_SBL_1, + MSM_BOOT_UART_DM_SBL_1_9_16, + MSM_BOOT_UART_DM_SBL_2 +}; + +/* UART Bits per Char */ +enum MSM_BOOT_UART_DM_BITS_PER_CHAR { + MSM_BOOT_UART_DM_5_BPS, + MSM_BOOT_UART_DM_6_BPS, + MSM_BOOT_UART_DM_7_BPS, + MSM_BOOT_UART_DM_8_BPS +}; + +/* 8-N-1 Configuration */ +#define MSM_BOOT_UART_DM_8_N_1_MODE (MSM_BOOT_UART_DM_NO_PARITY | \ + (MSM_BOOT_UART_DM_SBL_1 << 2) | \ + (MSM_BOOT_UART_DM_8_BPS << 4)) + +/* UART_DM Registers */ + +/* UART Operational Mode Register */ +#define MSM_BOOT_UART_DM_MR1(base) ((base) + 0x00) +#define MSM_BOOT_UART_DM_MR2(base) ((base) + 0x04) +#define MSM_BOOT_UART_DM_RXBRK_ZERO_CHAR_OFF (1 << 8) +#define MSM_BOOT_UART_DM_LOOPBACK (1 << 7) + +/* UART Clock Selection Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0xA0) +#else +#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0x08) +#endif + +/* UART DM TX FIFO Registers - 4 */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x100+(4*(x))) +#else +#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x70+(4*(x))) +#endif + +/* UART Command Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_CR(base) ((base) + 0xA8) +#else +#define MSM_BOOT_UART_DM_CR(base) ((base) + 0x10) +#endif +#define MSM_BOOT_UART_DM_CR_RX_ENABLE (1 << 0) +#define MSM_BOOT_UART_DM_CR_RX_DISABLE (1 << 1) +#define MSM_BOOT_UART_DM_CR_TX_ENABLE (1 << 2) +#define MSM_BOOT_UART_DM_CR_TX_DISABLE (1 << 3) + +/* UART Channel Command */ +#define MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) ((x & 0x0f) << 4) +#define MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x) ((x >> 4) << 11) +#define MSM_BOOT_UART_DM_CR_CH_CMD(x) \ + (MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) | MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x)) +#define MSM_BOOT_UART_DM_CMD_NULL MSM_BOOT_UART_DM_CR_CH_CMD(0) +#define MSM_BOOT_UART_DM_CMD_RESET_RX MSM_BOOT_UART_DM_CR_CH_CMD(1) +#define MSM_BOOT_UART_DM_CMD_RESET_TX MSM_BOOT_UART_DM_CR_CH_CMD(2) +#define MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT MSM_BOOT_UART_DM_CR_CH_CMD(3) +#define MSM_BOOT_UART_DM_CMD_RES_BRK_CHG_INT MSM_BOOT_UART_DM_CR_CH_CMD(4) +#define MSM_BOOT_UART_DM_CMD_START_BRK MSM_BOOT_UART_DM_CR_CH_CMD(5) +#define MSM_BOOT_UART_DM_CMD_STOP_BRK MSM_BOOT_UART_DM_CR_CH_CMD(6) +#define MSM_BOOT_UART_DM_CMD_RES_CTS_N MSM_BOOT_UART_DM_CR_CH_CMD(7) +#define MSM_BOOT_UART_DM_CMD_RES_STALE_INT MSM_BOOT_UART_DM_CR_CH_CMD(8) +#define MSM_BOOT_UART_DM_CMD_PACKET_MODE MSM_BOOT_UART_DM_CR_CH_CMD(9) +#define MSM_BOOT_UART_DM_CMD_MODE_RESET MSM_BOOT_UART_DM_CR_CH_CMD(C) +#define MSM_BOOT_UART_DM_CMD_SET_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(D) +#define MSM_BOOT_UART_DM_CMD_RES_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(E) +#define MSM_BOOT_UART_DM_CMD_RES_TX_ERR MSM_BOOT_UART_DM_CR_CH_CMD(10) +#define MSM_BOOT_UART_DM_CMD_CLR_TX_DONE MSM_BOOT_UART_DM_CR_CH_CMD(11) +#define MSM_BOOT_UART_DM_CMD_RES_BRKSTRT_INT MSM_BOOT_UART_DM_CR_CH_CMD(12) +#define MSM_BOOT_UART_DM_CMD_RES_BRKEND_INT MSM_BOOT_UART_DM_CR_CH_CMD(13) +#define MSM_BOOT_UART_DM_CMD_RES_PER_FRM_INT MSM_BOOT_UART_DM_CR_CH_CMD(14) + +/*UART General Command */ +#define MSM_BOOT_UART_DM_CR_GENERAL_CMD(x) ((x) << 8) + +#define MSM_BOOT_UART_DM_GCMD_NULL MSM_BOOT_UART_DM_CR_GENERAL_CMD(0) +#define MSM_BOOT_UART_DM_GCMD_CR_PROT_EN MSM_BOOT_UART_DM_CR_GENERAL_CMD(1) +#define MSM_BOOT_UART_DM_GCMD_CR_PROT_DIS MSM_BOOT_UART_DM_CR_GENERAL_CMD(2) +#define MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT MSM_BOOT_UART_DM_CR_GENERAL_CMD(3) +#define MSM_BOOT_UART_DM_GCMD_SW_FORCE_STALE MSM_BOOT_UART_DM_CR_GENERAL_CMD(4) +#define MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(5) +#define MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(6) + +/* UART Interrupt Mask Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0xB0) +#else +#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0x14) +#endif + +#define MSM_BOOT_UART_DM_TXLEV (1 << 0) +#define MSM_BOOT_UART_DM_RXHUNT (1 << 1) +#define MSM_BOOT_UART_DM_RXBRK_CHNG (1 << 2) +#define MSM_BOOT_UART_DM_RXSTALE (1 << 3) +#define MSM_BOOT_UART_DM_RXLEV (1 << 4) +#define MSM_BOOT_UART_DM_DELTA_CTS (1 << 5) +#define MSM_BOOT_UART_DM_CURRENT_CTS (1 << 6) +#define MSM_BOOT_UART_DM_TX_READY (1 << 7) +#define MSM_BOOT_UART_DM_TX_ERROR (1 << 8) +#define MSM_BOOT_UART_DM_TX_DONE (1 << 9) +#define MSM_BOOT_UART_DM_RXBREAK_START (1 << 10) +#define MSM_BOOT_UART_DM_RXBREAK_END (1 << 11) +#define MSM_BOOT_UART_DM_PAR_FRAME_ERR_IRQ (1 << 12) + +#define MSM_BOOT_UART_DM_IMR_ENABLED (MSM_BOOT_UART_DM_TX_READY | \ + MSM_BOOT_UART_DM_TXLEV | \ + MSM_BOOT_UART_DM_RXSTALE) + +/* UART Interrupt Programming Register */ +#define MSM_BOOT_UART_DM_IPR(base) ((base) + 0x18) +#define MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB 0x0f +#define MSM_BOOT_UART_DM_STALE_TIMEOUT_MSB 0 /* Not used currently */ + +/* UART Transmit/Receive FIFO Watermark Register */ +#define MSM_BOOT_UART_DM_TFWR(base) ((base) + 0x1C) +/* Interrupt is generated when FIFO level is less than or equal to this value */ +#define MSM_BOOT_UART_DM_TFW_VALUE 0 + +#define MSM_BOOT_UART_DM_RFWR(base) ((base) + 0x20) +/*Interrupt generated when no of words in RX FIFO is greater than this value */ +#define MSM_BOOT_UART_DM_RFW_VALUE 0 + +/* UART Hunt Character Register */ +#define MSM_BOOT_UART_DM_HCR(base) ((base) + 0x24) + +/* Used for RX transfer initialization */ +#define MSM_BOOT_UART_DM_DMRX(base) ((base) + 0x34) + +/* Default DMRX value - any value bigger than FIFO size would be fine */ +#define MSM_BOOT_UART_DM_DMRX_DEF_VALUE 0x220 + +/* Register to enable IRDA function */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0xB8) +#else +#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0x38) +#endif + +/* UART Data Mover Enable Register */ +#define MSM_BOOT_UART_DM_DMEN(base) ((base) + 0x3C) + +/* Number of characters for Transmission */ +#define MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base) ((base) + 0x040) + +/* UART RX FIFO Base Address */ +#define MSM_BOOT_UART_DM_BADR(base) ((base) + 0x44) + +/* UART Status Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x0A4) +#else +#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x008) +#endif +#define MSM_BOOT_UART_DM_SR_RXRDY (1 << 0) +#define MSM_BOOT_UART_DM_SR_RXFULL (1 << 1) +#define MSM_BOOT_UART_DM_SR_TXRDY (1 << 2) +#define MSM_BOOT_UART_DM_SR_TXEMT (1 << 3) +#define MSM_BOOT_UART_DM_SR_UART_OVERRUN (1 << 4) +#define MSM_BOOT_UART_DM_SR_PAR_FRAME_ERR (1 << 5) +#define MSM_BOOT_UART_DM_RX_BREAK (1 << 6) +#define MSM_BOOT_UART_DM_HUNT_CHAR (1 << 7) +#define MSM_BOOT_UART_DM_RX_BRK_START_LAST (1 << 8) + +/* UART Receive FIFO Registers - 4 in numbers */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x140 + (4*(x))) +#else +#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x70 + (4*(x))) +#endif + +/* UART Masked Interrupt Status Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0xAC) +#else +#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0x10) +#endif + +/* UART Interrupt Status Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0xB4) +#else +#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0x14) +#endif + +/* Number of characters received since the end of last RX transfer */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0xBC) +#else +#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0x38) +#endif + +/* UART TX FIFO Status Register */ +#define MSM_BOOT_UART_DM_TXFS(base) ((base) + 0x4C) +#define MSM_BOOT_UART_DM_TXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x, 0, 6) +#define MSM_BOOT_UART_DM_TXFS_STATE_MSB(x) \ + MSM_BOOT_UART_DM_EXTR_BITS(x, 14, 31) +#define MSM_BOOT_UART_DM_TXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x, 7, 9) +#define MSM_BOOT_UART_DM_TXFS_ASYNC_STATE(x) \ + MSM_BOOT_UART_DM_EXTR_BITS(x, 10, 13) + +/* UART RX FIFO Status Register */ +#define MSM_BOOT_UART_DM_RXFS(base) ((base) + 0x50) +#define MSM_BOOT_UART_DM_RXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x, 0, 6) +#define MSM_BOOT_UART_DM_RXFS_STATE_MSB(x) \ + MSM_BOOT_UART_DM_EXTR_BITS(x, 14, 31) +#define MSM_BOOT_UART_DM_RXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x, 7, 9) +#define MSM_BOOT_UART_DM_RXFS_ASYNC_STATE(x) \ + MSM_BOOT_UART_DM_EXTR_BITS(x, 10, 13) + +/* Macros for Common Errors */ +#define MSM_BOOT_UART_DM_E_SUCCESS 0 +#define MSM_BOOT_UART_DM_E_FAILURE 1 +#define MSM_BOOT_UART_DM_E_TIMEOUT 2 +#define MSM_BOOT_UART_DM_E_INVAL 3 +#define MSM_BOOT_UART_DM_E_MALLOC_FAIL 4 +#define MSM_BOOT_UART_DM_E_RX_NOT_READY 5 + +void ipq40xx_uart_init(void); + +#endif /* __UART_DM_H__ */ diff --git a/src/soc/qualcomm/qcs405/uart.c b/src/soc/qualcomm/qcs405/uart.c new file mode 100644 index 0000000..7cdc29f --- /dev/null +++ b/src/soc/qualcomm/qcs405/uart.c @@ -0,0 +1,309 @@ +/* + * Copyright (c) 2012 The Linux Foundation. All rights reserved. + * Source : APQ8064 LK boot + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <arch/io.h> +#include <boot/coreboot_tables.h> +#include <console/console.h> +#include <console/uart.h> +#include <delay.h> +#include <gpio.h> +#include <soc/clock.h> +#include <soc/blsp.h> +#include <soc/ipq_uart.h> +#include <soc/cdp.h> +#include <stdint.h> +#include <stdlib.h> +#include <soc/iomap.h> + +#define FIFO_DATA_SIZE 4 + +typedef struct { + void *uart_dm_base; + //uart_clk_mnd_t mnd_value; + unsigned blsp_uart; + gpio_func_data_t dbg_uart_gpio[NO_OF_DBG_UART_GPIOS]; +} uart_params_t; + +void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count) +{ + int i; + + for (i = 0; i < count; i++) { + gpio_configure(gpio->gpio, gpio->func, + gpio->pull, gpio->drvstr, gpio->enable); + gpio++; + } +} + +static const uart_params_t uart_board_param = { + .uart_dm_base = UART2_DM_BASE, + //.mnd_value = { 24, 625, 313 }, + .blsp_uart = BLSP1_UART2, + .dbg_uart_gpio = { + { + .gpio = GPIO(17), + .func = 1, + .dir = GPIO_OUTPUT, + .pull = GPIO_PULL_UP, + .enable = GPIO_OUTPUT + }, + { + .gpio = GPIO(18), + .func = 1, + .dir = GPIO_INPUT, + .pull = GPIO_NO_PULL, + .enable = GPIO_INPUT + }, + }, +}; + +/** + * @brief msm_boot_uart_dm_init_rx_transfer - Init Rx transfer + * @param uart_dm_base: UART controller base address + */ +static unsigned int msm_boot_uart_dm_init_rx_transfer(void *uart_dm_base) +{ + /* Reset receiver */ + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_CMD_RESET_RX); + + /* Enable receiver */ + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_CR_RX_ENABLE); + write32(MSM_BOOT_UART_DM_DMRX(uart_dm_base), + MSM_BOOT_UART_DM_DMRX_DEF_VALUE); + + /* Clear stale event */ + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_CMD_RES_STALE_INT); + + /* Enable stale event */ + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT); + + return MSM_BOOT_UART_DM_E_SUCCESS; +} + +#if IS_ENABLED(CONFIG_DRIVERS_UART) +static unsigned int msm_boot_uart_dm_init(void *uart_dm_base); + +/* Received data is valid or not */ +static int valid_data = 0; + +/* Received data */ +static unsigned int word = 0; + + +void uart_tx_byte(int idx, unsigned char data) +{ + int num_of_chars = 1; + void *base = uart_board_param.uart_dm_base; + + /* Wait until transmit FIFO is empty. */ + while (!(read32(MSM_BOOT_UART_DM_SR(base)) & + MSM_BOOT_UART_DM_SR_TXEMT)) + udelay(1); + /* + * TX FIFO is ready to accept new character(s). First write number of + * characters to be transmitted. + */ + write32(MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base), num_of_chars); + + /* And now write the character(s) */ + write32(MSM_BOOT_UART_DM_TF(base, 0), data); +} +#endif /* CONFIG_SERIAL_UART */ + +/** + * @brief msm_boot_uart_dm_reset - resets UART controller + * @param base: UART controller base address + */ +static unsigned int msm_boot_uart_dm_reset(void *base) +{ + write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RESET_RX); + write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RESET_TX); + write32(MSM_BOOT_UART_DM_CR(base), + MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT); + write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RES_TX_ERR); + write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RES_STALE_INT); + + return MSM_BOOT_UART_DM_E_SUCCESS; +} + +/** + * @brief msm_boot_uart_dm_init - initilaizes UART controller + * @param uart_dm_base: UART controller base address + */ +unsigned int msm_boot_uart_dm_init(void *uart_dm_base) +{ + /* Configure UART mode registers MR1 and MR2 */ + /* Hardware flow control isn't supported */ + write32(MSM_BOOT_UART_DM_MR1(uart_dm_base), 0x0); + + /* 8-N-1 configuration: 8 data bits - No parity - 1 stop bit */ + write32(MSM_BOOT_UART_DM_MR2(uart_dm_base), + MSM_BOOT_UART_DM_8_N_1_MODE); + + /* Configure Interrupt Mask register IMR */ + write32(MSM_BOOT_UART_DM_IMR(uart_dm_base), + MSM_BOOT_UART_DM_IMR_ENABLED); + + /* + * Configure Tx and Rx watermarks configuration registers + * TX watermark value is set to 0 - interrupt is generated when + * FIFO level is less than or equal to 0 + */ + write32(MSM_BOOT_UART_DM_TFWR(uart_dm_base), + MSM_BOOT_UART_DM_TFW_VALUE); + + /* RX watermark value */ + write32(MSM_BOOT_UART_DM_RFWR(uart_dm_base), + MSM_BOOT_UART_DM_RFW_VALUE); + + /* Configure Interrupt Programming Register */ + /* Set initial Stale timeout value */ + write32(MSM_BOOT_UART_DM_IPR(uart_dm_base), + MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB); + + /* Configure IRDA if required */ + /* Disabling IRDA mode */ + write32(MSM_BOOT_UART_DM_IRDA(uart_dm_base), 0x0); + + /* Configure hunt character value in HCR register */ + /* Keep it in reset state */ + write32(MSM_BOOT_UART_DM_HCR(uart_dm_base), 0x0); + + /* + * Configure Rx FIFO base address + * Both TX/RX shares same SRAM and default is half-n-half. + * Sticking with default value now. + * As such RAM size is (2^RAM_ADDR_WIDTH, 32-bit entries). + * We have found RAM_ADDR_WIDTH = 0x7f + */ + + /* Issue soft reset command */ + msm_boot_uart_dm_reset(uart_dm_base); + + /* Enable/Disable Rx/Tx DM interfaces */ + /* Data Mover not currently utilized. */ + write32(MSM_BOOT_UART_DM_DMEN(uart_dm_base), 0x0); + + /* Enable transmitter */ + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_CR_TX_ENABLE); + + /* Initialize Receive Path */ + msm_boot_uart_dm_init_rx_transfer(uart_dm_base); + + return 0; +} + +/** + * @brief ipq40xx_uart_init - initializes UART + * + * Initializes clocks, GPIO and UART controller. + */ +void uart_init(int idx) +{ + /* Note int idx isn't used in this driver. */ + void *dm_base; + + dm_base = uart_board_param.uart_dm_base; + + if (read32(MSM_BOOT_UART_DM_CSR(dm_base)) == 0xFF) + return; /* UART must have been already initialized. */ + + ipq_configure_gpio(uart_board_param.dbg_uart_gpio, + NO_OF_DBG_UART_GPIOS); + + /* TODO: Configure the uart clock */ + /*uart_clock_config(uart_board_param.blsp_uart, + uart_board_param.mnd_value.m_value, + uart_board_param.mnd_value.n_value, + uart_board_param.mnd_value.d_value);*/ + + write32(MSM_BOOT_UART_DM_CSR(dm_base), 0xFF); + + /* Initialize UART_DM */ + msm_boot_uart_dm_init(dm_base); +} + +/* for the benefit of non-console uart init */ +void ipq40xx_uart_init(void) +{ + uart_init(0); +} + +/** + * @brief uart_tx_flush - transmits a string of data + * @param idx: string to transmit + */ +void uart_tx_flush(int idx) +{ + void *base = uart_board_param.uart_dm_base; + + while (!(read32(MSM_BOOT_UART_DM_SR(base)) & + MSM_BOOT_UART_DM_SR_TXEMT)) + ; +} + +#if IS_ENABLED(CONFIG_DRIVERS_UART) +/** + * ipq40xx_serial_getc - reads a character + * + * Returns the character read from serial port. + */ +uint8_t uart_rx_byte(int idx) +{ + uint8_t byte; + + byte = (uint8_t)(word & 0xff); + word = word >> 8; + valid_data--; + + return byte; +} +#endif + +#ifndef __PRE_RAM__ +/* TODO: Implement function */ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = (uint64_t)UART2_DM_BASE; + serial.baud = get_uart_baudrate(); + serial.regwidth = 1; + + lb_add_serial(&serial, data); + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/29964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9626c68eadead8b8ec5ffbc08cab7b0ec36478f Gerrit-Change-Number: 29964 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

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Change in ...coreboot[master]: qcs405: clock: Adding the clock support for qcs405
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29962 Change subject: qcs405: clock: Adding the clock support for qcs405 ...................................................................... qcs405: clock: Adding the clock support for qcs405 Add basic clock support and enable UART, SPI clocks. Change-Id: I991bdde5f69e1c0f6ec5d6961275a1c077bc5bae Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Pranav Agrawal <pranava(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/bootblock.c A src/soc/qualcomm/qcs405/clock.c A src/soc/qualcomm/qcs405/include/soc/clock.h 4 files changed, 367 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/29962/1 diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index 6fc87c7..58a62fa 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -7,6 +7,7 @@ bootblock-y += mmu.c bootblock-y += timer.c bootblock-y += gpio.c +bootblock-y += clock.c bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c bootblock-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c @@ -22,6 +23,7 @@ romstage-y += cbmem.c romstage-y += timer.c romstage-y += gpio.c +romstage-y += clock.c romstage-y += mmu.c romstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c romstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c @@ -32,6 +34,7 @@ ramstage-y += cbmem.c ramstage-y += timer.c ramstage-y += gpio.c +ramstage-y += clock.c ramstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c ramstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c diff --git a/src/soc/qualcomm/qcs405/bootblock.c b/src/soc/qualcomm/qcs405/bootblock.c index 5e63f13..15d1c18 100644 --- a/src/soc/qualcomm/qcs405/bootblock.c +++ b/src/soc/qualcomm/qcs405/bootblock.c @@ -15,6 +15,12 @@ #include <bootblock_common.h> #include <soc/mmu.h> +#include <soc/clock.h> + +void bootblock_soc_early_init(void) +{ + clock_init(); +} void bootblock_soc_init(void) { diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c new file mode 100644 index 0000000..6307259 --- /dev/null +++ b/src/soc/qualcomm/qcs405/clock.c @@ -0,0 +1,208 @@ + /* This file is part of the coreboot project. + * + * Copyright 2018 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <types.h> +#include <console/console.h> +#include <delay.h> +#include <timer.h> +#include <timestamp.h> +#include <commonlib/helpers.h> +#include <string.h> + +#include <soc/clock.h> + +#define DIV(div) (div ? (2*div - 1) : 0) +#define HALF_DIVIDER(div2x) (div2x ? (div2x - 1) : 0) + +struct clock_config uart_cfg[] = { + { + .hz = 1843200, + .hw_ctl = 0x0, + .src = SRC_GPLL0_MAIN_800MHZ, + .div = DIV(0), + .m = 36, + .n = 15625, + .d_2 = 15625, + }, + { + .hz = 3686400, + .hw_ctl = 0x0, + .src = SRC_GPLL0_MAIN_800MHZ, + .div = DIV(0), + .m = 72, + .n = 15625, + .d_2 = 15625, + } +}; + +struct clock_config i2c_cfg[] = { + { + .hz = 19200000, + .hw_ctl = 0x0, + .src = SRC_XO_19_2MHZ, + .div = DIV(0), + }, + { + .hz = 50000000, + .hw_ctl = 0x0, + .src = SRC_GPLL0_MAIN_800MHZ, + .div = DIV(32), + } +}; + +struct clock_config spi_cfg[] = { + { + .hz = 19200000, + .hw_ctl = 0x0, + .src = SRC_XO_19_2MHZ, + .div = DIV(0), + }, + { + .hz = 30000000, + .hw_ctl = 0x0, + .src = SRC_XO_19_2MHZ, + .div = DIV(0), + }, + { + .hz = 50000000, + .hw_ctl = 0x0, + .src = SRC_GPLL0_MAIN_800MHZ, + .div = DIV(32), + } +}; + + +static struct qcs405_clock *const blsp1_uart2_clk = + (void *)GCC_BLSP1_UART2_BASE; + +static struct qcs405_clock *const blsp2_qup0_spi_clk = + (void *)GCC_BLSP2_QUP0_SPI_BASE; + +static int clock_configure_mnd(struct qcs405_clock *clk, uint32_t m, uint32_t n, + uint32_t d_2) +{ + uint32_t reg_val; + + /* Configure Root Clock Generator(RCG) for Dual Edge Mode */ + reg_val = read32(&clk->cfg_rcgr); + reg_val |= (2 << CLK_CTL_CFG_MODE_SHFT); + write32(&clk->cfg_rcgr, reg_val); + + /* Set M/N/D config */ + write32(&clk->m, m & CLK_CTL_RCG_MND_BMSK); + write32(&clk->n, ~(n-m) & CLK_CTL_RCG_MND_BMSK); + write32(&clk->d_2, ~(d_2) & CLK_CTL_RCG_MND_BMSK); + + return 0; +} + +static int clock_configure(struct qcs405_clock *clk, + struct clock_config *clk_cfg, + uint32_t hz, uint32_t num_perfs) +{ + uint32_t reg_val; + uint32_t idx; + + for (idx = 0; idx < num_perfs; idx++) + if (hz <= clk_cfg[idx].hz) + break; + + reg_val = (clk_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) | + (clk_cfg[idx].div << CLK_CTL_CFG_SRC_DIV_SHFT); + + /* Set clock config */ + write32(&clk->cfg_rcgr, reg_val); + + if (clk_cfg[idx].m != 0) + clock_configure_mnd(clk, clk_cfg[idx].m, clk_cfg[idx].n, + clk_cfg[idx].d_2); + + /* Commit config to RCG*/ + setbits_le32(&clk->cmd_rcgr, BIT(CLK_CTL_CMD_UPDATE_SHFT)); + + return 0; +} + +static bool clock_is_off(void *cbcr_addr) +{ + return (read32(cbcr_addr) & CLK_CTL_CBC_CLK_OFF_BMSK); +} + +static int clock_enable_vote(void *cbcr_addr, void *vote_addr, + uint32_t vote_bit) +{ + + /* Set clock vote bit */ + setbits_le32(vote_addr, BIT(vote_bit)); + + /* Ensure clock is enabled */ + while (clock_is_off(cbcr_addr)) + ; + + return 0; +} + +static int clock_enable(void *cbcr_addr) +{ + + /* Set clock enable bit */ + setbits_le32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); + + /* Ensure clock is enabled */ + while (clock_is_off(cbcr_addr)) + ; + + return 0; +} + +static int clock_disable(void *cbcr_addr) +{ + + /* Set clock enable bit */ + clrbits_le32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); + return 0; +} + +int clock_reset_bcr(void *bcr_addr, bool reset) +{ + struct qcs405_bcr *bcr = bcr_addr; + + if (reset) + setbits_le32(&bcr->bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); + else + clrbits_le32(&bcr->bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); + + return 0; +} + +void clock_init(void) +{ + + clock_configure(blsp1_uart2_clk, uart_cfg, 1843200, + ARRAY_SIZE(uart_cfg)); + + clock_disable(REG(GCC_BLSP1_UART0_APPS_CBCR)); + clock_enable(REG(GCC_BLSP1_UART0_APPS_CBCR)); + clock_enable(REG(GCC_BLSP1_UART2_APPS_CBCR)); + clock_enable_vote(REG(GCC_BLSP1_AHB_CBCR), + REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE), + BLSP1_AHB_CLK_ENA); + + clock_configure(blsp2_qup0_spi_clk, spi_cfg, 50000000, + ARRAY_SIZE(spi_cfg)); + clock_enable(REG(GCC_BLSP2_QUP0_SPI_APPS_CBCR)); + +} + diff --git a/src/soc/qualcomm/qcs405/include/soc/clock.h b/src/soc/qualcomm/qcs405/include/soc/clock.h new file mode 100644 index 0000000..aa8bbe5 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/clock.h @@ -0,0 +1,150 @@ + /* This file is part of the coreboot project. + * + * Copyright 2018 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_QUALCOMM_QCS405_CLOCK_H__ +#define __SOC_QUALCOMM_QCS405_CLOCK_H__ + +#define GCC_APCS_CLOCK_BRANCH_ENA_VOTE 0x01845004 + +#define GCC_BLSP1_UART0_BASE 0x180600C +#define GCC_BLSP1_UART1_BASE 0x1802044 +#define GCC_BLSP1_UART2_BASE 0x1803034 +#define GCC_BLSP1_UART3_BASE 0x1804014 +#define GCC_BLSP2_UART0_BASE 0x180C044 + +#define GCC_BLSP1_QUP0_SPI_BASE 0x1806034 +#define GCC_BLSP1_QUP1_SPI_BASE 0x1802024 +#define GCC_BLSP1_QUP2_SPI_BASE 0x1803014 +#define GCC_BLSP1_QUP3_SPI_BASE 0x1804024 +#define GCC_BLSP1_QUP4_SPI_BASE 0x1805024 +#define GCC_BLSP2_QUP0_SPI_BASE 0x180C024 + +#define GCC_BLSP1_QUP0_I2C_BASE 0x180602C +#define GCC_BLSP1_QUP1_I2C_BASE 0x180200C +#define GCC_BLSP1_QUP2_I2C_BASE 0x1803000 +#define GCC_BLSP1_QUP3_I2C_BASE 0x1804000 +#define GCC_BLSP1_QUP4_I2C_BASE 0x1805000 +#define GCC_BLSP2_QUP0_I2C_BASE 0x180C00C + +#define GCC_BLSP1_UART0_APPS_CBCR 0x1806004 +#define GCC_BLSP1_UART1_APPS_CBCR 0x180203C +#define GCC_BLSP1_UART2_APPS_CBCR 0x180302C +#define GCC_BLSP1_UART3_APPS_CBCR 0x180400C +#define GCC_BLSP2_UART0_APPS_CBCR 0x180C03C + +#define GCC_BLSP2_QUP0_SPI_APPS_CBCR 0x180C004 + +#define GCC_BLSP1_AHB_CBCR 0x1801008 +#define GCC_BLSP2_AHB_CBCR 0x180B008 + +#define BLSP1_AHB_CLK_ENA 10 +#define BLSP2_AHB_CLK_ENA 20 + + + +#define SRC_XO_19_2MHZ 0 +#define SRC_GPLL0_MAIN_800MHZ 1 + + + +#define GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1 0x0015200C +#define SRC_XO_19_2MHZ 0 +#define REG(addr) ((void *)addr) + +/** + * USB BCR registers + */ +#define GCC_USB_HS_PHY_CFG_AHB_BCR 0x1841038 +#define GCC_USB_HS_BCR 0x1841000 +#define GCC_USB_30_BCR 0x1839000 +#define GCC_USB2A_PHY_BCR 0x1841028 +#define GCC_USB2_HS_PHY_ONLY_BCR 0x1841034 +#define GCC_QUSB2_PHY_BCR 0x184103C + +struct qcs405_clock { + uint32_t cmd_rcgr; + uint32_t cfg_rcgr; + uint32_t m; + uint32_t n; + uint32_t d_2; +}; + +struct qcs405_bcr { + uint32_t bcr; +}; + +struct mdss_clock_config { + const char *clk_name; + struct qcs405_clock *rcgr; + uint32_t *cbcr; +}; + +enum clk_ctl_gpll_user_ctl { + CLK_CTL_GPLL_PLLOUT_EVEN_BMSK = 0x2, + CLK_CTL_GPLL_PLLOUT_EVEN_SHFT = 1 +}; + +enum clk_ctl_cfg_rcgr { + CLK_CTL_CFG_HW_CTL_BMSK = 0x100000, + CLK_CTL_CFG_HW_CTL_SHFT = 20, + CLK_CTL_CFG_MODE_BMSK = 0x3000, + CLK_CTL_CFG_MODE_SHFT = 12, + CLK_CTL_CFG_SRC_SEL_BMSK = 0x700, + CLK_CTL_CFG_SRC_SEL_SHFT = 8, + CLK_CTL_CFG_SRC_DIV_BMSK = 0x1F, + CLK_CTL_CFG_SRC_DIV_SHFT = 0 +}; + +enum clk_ctl_cmd_rcgr { + CLK_CTL_CMD_ROOT_OFF_BMSK = 0x80000000, + CLK_CTL_CMD_ROOT_OFF_SHFT = 31, + CLK_CTL_CMD_ROOT_EN_BMSK = 0x2, + CLK_CTL_CMD_ROOT_EN_SHFT = 1, + CLK_CTL_CMD_UPDATE_BMSK = 0x1, + CLK_CTL_CMD_UPDATE_SHFT = 0 +}; + +enum clk_ctl_cbcr { + CLK_CTL_CBC_CLK_OFF_BMSK = 0x80000000, + CLK_CTL_CBC_CLK_OFF_SHFT = 31, + CLK_CTL_CBC_CLK_EN_BMSK = 0x1, + CLK_CTL_CBC_CLK_EN_SHFT = 0 +}; + +enum clk_ctl_rcg_mnd { + CLK_CTL_RCG_MND_BMSK = 0xFFFF, + CLK_CTL_RCG_MND_SHFT = 0, +}; + +enum clk_ctl_bcr { + CLK_CTL_BCR_BLK_ARES_BMSK = 0x1, + CLK_CTL_BCR_BLK_ARES_SHFT = 0, +}; + +struct clock_config { + uint32_t hz; + uint32_t hw_ctl; + uint32_t src; + uint32_t div; + uint32_t m; + uint32_t n; + uint32_t d_2; +}; + +void clock_init(void); +void clock_reset_aop(void); +int clock_configure_qspi(uint32_t hz); +int clock_reset_bcr(void *bcr_addr, bool reset); + +#endif // __SOC_QUALCOMM_QCS405_CLOCK_H__ -- To view, visit https://review.coreboot.org/c/coreboot/+/29962 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I991bdde5f69e1c0f6ec5d6961275a1c077bc5bae Gerrit-Change-Number: 29962 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: qcs405: Adding the GPIO support for QCS405
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29963 Change subject: qcs405: Adding the GPIO support for QCS405 ...................................................................... qcs405: Adding the GPIO support for QCS405 Add the gpio data for all qcs405 pins Change-Id: Ibdd675527458e597c1f49544425146bd17f28075 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Pranav Agrawal <pranava(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/include/soc/gpio.h 1 file changed, 184 insertions(+), 218 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/29963/1 diff --git a/src/soc/qualcomm/qcs405/include/soc/gpio.h b/src/soc/qualcomm/qcs405/include/soc/gpio.h index f436595..b12ebb1 100644 --- a/src/soc/qualcomm/qcs405/include/soc/gpio.h +++ b/src/soc/qualcomm/qcs405/include/soc/gpio.h @@ -98,247 +98,213 @@ GPIO##index##_FUNC_##func7 = 7 enum { - PIN(0, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(1, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(2, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(3, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(4, NORTH, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(5, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(6, NORTH, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(7, NORTH, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(8, EAST, QUP_L4_0_CS, GP_PDM_MIRB, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(9, EAST, QUP_L5_0_CS, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(10, EAST, MDP_VSYNC_P_MIRA, QUP_L6_0_CS, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(11, EAST, MDP_VSYNC_S_MIRA, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(12, SOUTH, MDP_VSYNC_E, RES_2, TSIF1_SYNC, RES_4, RES_5, - RES_6, RES_7), + PIN(0, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(1, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(2, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(3, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(4, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(5, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(6, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(7, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(8, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(9, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(10, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(11, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(12, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), PIN(13, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), PIN(14, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), PIN(15, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), PIN(16, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(17, NORTH, CCI_I2C_SDA0, QUP_L0, RES_3, RES_4, RES_5, + PIN(17, NORTH, BLSP_UART_TX_A, BLSP_SPI_MOSI, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(18, SOUTH, CCI_I2C_SCL0, QUP_L1, RES_3, RES_4, RES_5, + PIN(18, NORTH, BLSP_UART_RX_A, BLSP_SPI_MISO, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(19, SOUTH, CCI_I2C_SDA1, QUP_L2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(20, SOUTH, CCI_I2C_SCL1, QUP_L3, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(21, SOUTH, CCI_TIMER0, GCC_GP2_CLK_MIRB, RES_3, RES_4, + PIN(19, NORTH, BLSP_UART_CTS_N, AUD_CDC_INT2, RES_3, BLSP_SPI_CS_N, RES_5, RES_6, RES_7), - PIN(22, SOUTH, CCI_TIMER1, GCC_GP3_CLK_MIRB, RES_3, RES_4, + PIN(20, NORTH, BLSP_UART_RFR_N, RES_2, RES_3, BLSP_SPI_CLK, RES_5, + RES_6, RES_7), + PIN(21, SOUTH, M_VOC_EXT_VFR_REF_IRQ_2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(23, SOUTH, CCI_TIMER2, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(24, SOUTH, CCI_TIMER3, CCI_ASYNC_IN1, RES_3, RES_4, + PIN(22, NORTH, BLSP_UART_TX, BLSP_SPI_MOSI_A, ASDIV1, RES_4, RES_5, RES_6, RES_7), - PIN(25, SOUTH, CCI_TIMER4, CCI_ASYNC_IN2, RES_3, RES_4, + PIN(23, NORTH, BLSP_UART_RX, BLSP_SPI_MISO_A, ASDIV2, RES_4, RES_5, RES_6, RES_7), - PIN(26, SOUTH, CCI_ASYNC_IN0, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(27, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(28, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(29, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(30, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(31, NORTH, QUP_L0, QUP_L2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(32, NORTH, QUP_L1, QUP_L3, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(33, NORTH, QUP_L2, QUP_L0, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(34, NORTH, QUP_L3, QUP_L1, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(35, SOUTH, PCI_E0_RST_N, QUP_L4_1_CS, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(36, SOUTH, PCI_E0_CLKREQN, QUP_L5_1_CS, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(37, SOUTH, QUP_L6_1_CS, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(38, NORTH, USB_PHY_PS, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(39, EAST, LPASS_SLIMBUS_DATA2, RES_2, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(40, SOUTH, SD_WRITE_PROTECT, TSIF1_ERROR, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(41, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(42, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(43, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(44, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(45, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(46, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(47, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(48, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(49, NORTH, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(50, NORTH, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(51, NORTH, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(52, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(53, NORTH, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(54, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(55, NORTH, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(56, NORTH, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(57, NORTH, QUA_MI2S_MCLK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(58, NORTH, QUA_MI2S_SCK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(59, NORTH, QUA_MI2S_WS, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(60, NORTH, QUA_MI2S_DATA0, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(61, NORTH, QUA_MI2S_DATA1, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(62, NORTH, QUA_MI2S_DATA2, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(63, NORTH, QUA_MI2S_DATA3, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(64, NORTH, PRI_MI2S_MCLK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(65, NORTH, PRI_MI2S_SCK, QUP_L0, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(66, NORTH, PRI_MI2S_WS, QUP_L1, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(67, NORTH, PRI_MI2S_DATA0, QUP_L2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(68, NORTH, PRI_MI2S_DATA1, QUP_L3, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(69, EAST, SPKR_I2S_MCLK, AUDIO_REF_CLK, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(70, EAST, LPASS_SLIMBUS_CLK, SPKR_I2S_SCK, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(71, EAST, LPASS_SLIMBUS_DATA0, SPKR_I2S_DATA_OUT, RES_3, + PIN(24, NORTH, BLSP_UART_CTS_N, BLSP_I2C_SDA, BLSP_SPI_CS_N_A, RES_4, RES_5, RES_6, RES_7), - PIN(72, EAST, LPASS_SLIMBUS_DATA1, SPKR_I2S_WS, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(73, EAST, BTFM_SLIMBUS_DATA, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(74, EAST, BTFM_SLIMBUS_CLK, TER_MI2S_MCLK, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(75, EAST, TER_MI2S_SCK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(76, EAST, TER_MI2S_WS, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(77, EAST, TER_MI2S_DATA0, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(78, EAST, TER_MI2S_DATA1, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(79, NORTH, SEC_MI2S_MCLK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(80, NORTH, SEC_MI2S_SCK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(81, NORTH, SEC_MI2S_WS, QUP_L0, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(82, NORTH, SEC_MI2S_DATA0, QUP_L1, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(83, NORTH, SEC_MI2S_DATA1, QUP_L2, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(84, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(85, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(86, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(87, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(88, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(89, SOUTH, TSIF1_CLK, QUP_L0, QSPI_CS_N_1, RES_4, RES_5, - RES_6, RES_7), - PIN(90, SOUTH, TSIF1_EN, MDP_VSYNC0_OUT, QUP_L1, QSPI_CS_N_0, - MDP_VSYNC1_OUT, MDP_VSYNC2_OUT, MDP_VSYNC3_OUT), - PIN(91, SOUTH, TSIF1_DATA, SDC4_CMD, QUP_L2, QSPI_DATA, - RES_5, RES_6, RES_7), - PIN(92, SOUTH, TSIF2_ERROR, SDC4_DATA, QUP_L3, QSPI_DATA, - RES_5, RES_6, RES_7), - PIN(93, SOUTH, TSIF2_CLK, SDC4_CLK, QUP_L0, QSPI_DATA, - RES_5, RES_6, RES_7), - PIN(94, SOUTH, TSIF2_EN, SDC4_DATA, QUP_L1, QSPI_DATA, - RES_5, RES_6, RES_7), - PIN(95, SOUTH, TSIF2_DATA, SDC4_DATA, QUP_L2, QSPI_CLK, - RES_5, RES_6, RES_7), - PIN(96, SOUTH, TSIF2_SYNC, SDC4_DATA, QUP_L3, RES_4, - RES_5, RES_6, RES_7), - PIN(97, NORTH, RFFE6_CLK, GRFC37, MDP_VSYNC_P_MIRB, + PIN(25, NORTH, BLSP_UART_RFR_N, BLSP_I2C_SCL, BLSP_SPI_CLK_A, RES_4, RES_5, RES_6, RES_7), - PIN(98, NORTH, RFFE6_DATA, MDP_VSYNC_S_MIRB, RES_3, + PIN(26, EAST, RES_1, BLSP_UART_TX, BLSP_SPI_MOSI, RES_4, RES_5, + RES_6, RES_7), + PIN(27, EAST, RES_1, BLSP_UART_RX, BLSP_SPI_MISO, RES_4, RES_5, + RES_6, RES_7), + PIN(28, EAST, RES_1, BLSP_UART_CTS_N, RES_3, BLSP_SPI_CS_N, RES_5, + RES_6, RES_7), + PIN(29, EAST, RES_1, BLSP_UART_RFR_N, RES_3, BLSP_SPI_CLK, RES_5, + RES_6, RES_7), + PIN(30, NORTH, RES_1, BLSP_UART_TX, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(31, NORTH, RES_1, BLSP_UART_RX, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(32, NORTH, RES_1, BLSP_UART_CTS_N, BLSP_I2C_SDA, RES_4, RES_5, + RES_6, RES_7), + PIN(33, NORTH, RES_1, BLSP_UART_RFR_N, BLSP_I2C_SCL, RES_4, RES_5, + RES_6, RES_7), + PIN(34, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(35, SOUTH, PCIE_CLK_REQ, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(36, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(37, NORTH, NFC_IRQ, BLSP_SPI_MOSI, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(38, NORTH, RES_1, BLSP_SPI_MISO, AUDIO_TS_IN, RES_4, RES_5, + RES_6, RES_7), + PIN(39, EAST, RES_1, RES_2, BLSP_UART_TX_B, RES_4, RES_5, RES_6, + RES_7), + PIN(40, EAST, RES_1, RES_2, BLSP_UART_RX_B, RES_4, RES_5, RES_6, + RES_7), + PIN(41, EAST, RES_1, BLSP_I2C_SDA_B, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(42, EAST, RES_1, BLSP_I2C_SCL_B, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(43, EAST, RES_1, PWM_LED11, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(44, EAST, RES_1, PWM_LED12, BLSP_SPI_CS1_N, RES_4, RES_5, + RES_6, RES_7), + PIN(45, EAST, RES_1, PWM_LED13, BLSP_SPI_CS2_N, RES_4, RES_5, + RES_6, RES_7), + PIN(46, EAST, RES_1, PWM_LED14, BLSP_SPI_CS3_N, RES_4, RES_5, + RES_6, RES_7), + PIN(47, EAST, RES_1, PWM_LED15, BLSP_SPI_MOSI_B, RES_4, RES_5, + RES_6, RES_7), + PIN(48, EAST, RES_1, PWM_LED16, BLSP_SPI_MISO_B, RES_4, RES_5, + RES_6, RES_7), + PIN(49, EAST, RES_1, PWM_LED17, BLSP_SPI_CS_N_B, RES_4, RES_5, + RES_6, RES_7), + PIN(50, EAST, RES_1, PWM_LED18, BLSP_SPI_CLK_B, RES_4, RES_5, + RES_6, RES_7), + PIN(51, EAST, RES_1, PWM_LED19, EXT_MCLK1_B, RES_4, RES_5, RES_6, + RES_7), + PIN(52, EAST, RES_1, PWM_LED20, RES_3, I2S_3_SCK_B, RES_5, RES_6, + RES_7), + PIN(53, EAST, RES_1, PWM_LED21, I2S_3_WS_B, RES_4, RES_5, RES_6, + RES_7), + PIN(54, EAST, RES_1, I2S_3_DATA0_B, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(55, EAST, RES_1, I2S_3_DATA1_B, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(56, EAST, RES_1, RES_2, I2S_3_DATA2_B, RES_4, RES_5, RES_6, + RES_7), + PIN(57, EAST, RES_1, RES_2, I2S_3_DATA3_B, RES_4, RES_5, RES_6, + RES_7), + PIN(58, EAST, RGB_DATA_B, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(59, EAST, RGB_DATA_B, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(60, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(61, NORTH, RGMII_INT, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(62, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(63, NORTH, RGMII_CK_TX, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(64, NORTH, RGMII_TX_3, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(65, NORTH, RGMII_TX_2, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(66, NORTH, RGMII_TX_1, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(67, NORTH, RGMII_TX_0, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(68, NORTH, RGMII_CTL_TX, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(69, NORTH, RGMII_CK_RX, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(70, NORTH, RGMII_RX_3, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(71, NORTH, RGMII_RX_2, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(72, NORTH, RGMII_RX_1, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(73, NORTH, RGMII_RX_0, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(74, NORTH, RGMII_CTL_RX, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(75, NORTH, RGMII_MDIO, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(76, NORTH, RGMII_MDC, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(77, NORTH, IR_IN, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(78, EAST, RGB_DATA_G, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(79, EAST, RGB_DATA_G, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(80, EAST, RGB_DATA_R, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(81, EAST, RGB_DATA_R, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(82, NORTH, BLSP_UART_TX, BLSP_SPI_MOSI, SD_WRITE_PROTECT, RES_4, RES_5, RES_6, RES_7), - PIN(99, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(100, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(101, NORTH, GRFC4, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(102, NORTH, PCI_E1_RST_N, RES_2, RES_3, RES_4, RES_5, + PIN(83, NORTH, BLSP_UART_RX, BLSP_SPI_MISO, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(103, NORTH, PCI_E1_CLKREQN, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(104, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(105, NORTH, UIM2_DATA, QUP_L0, QUP_L4_8_CS, RES_4, RES_5, - RES_6, RES_7), - PIN(106, NORTH, UIM2_CLK, QUP_L1, QUP_L5_8_CS, RES_4, RES_5, - RES_6, RES_7), - PIN(107, NORTH, UIM2_RESET, QUP_L2, QUP_L6_8_CS, RES_4, RES_5, - RES_6, RES_7), - PIN(108, NORTH, UIM2_PRESENT, QUP_L3, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(109, NORTH, UIM1_DATA, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(110, NORTH, UIM1_CLK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(111, NORTH, UIM1_RESET, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(112, NORTH, UIM1_PRESENT, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(113, NORTH, UIM_BATT_ALARM, EDP_HOT_PLUG_DETECT, RES_3, + PIN(84, NORTH, BLSP_UART_CTS_N, BLSP_I2C_SDA, BLSP_SPI_CS_N, RES_4, RES_5, RES_6, RES_7), - PIN(114, NORTH, GRFC8, RES_2, RES_3, GPS_TX_AGGRESSOR_MIRE, + PIN(85, NORTH, BLSP_UART_RFR_N, BLSP_I2C_SCL, BLSP_SPI_CLK, RES_4, RES_5, RES_6, RES_7), - PIN(115, NORTH, GRFC9, RES_2, RES_3, GPS_TX_AGGRESSOR_MIRF, + PIN(86, EAST, RES_1, MCLK_IN1, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(87, EAST, I2S_1_SCK, DSD_CLK_A, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(88, EAST, I2S_1_WS, I2S_1_DATA0_DSD0, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(89, EAST, I2S_1_DATA0, I2S_1_DATA1_DSD1, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(90, EAST, I2S_1_DATA1, I2S_1_DATA2_DSD2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(91, EAST, I2S_1_DATA2, I2S_1_DATA3_DSD3, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(92, EAST, I2S_1_DATA3, I2S_1_DATA4_DSD4, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(93, EAST, I2S_1_DATA4, PWM_LED22, I2S_1_DATA5_DSD5, RES_4, RES_5, RES_6, RES_7), - PIN(116, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(117, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(118, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(119, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(120, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(121, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(122, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(123, EAST, QUP_L4_9_CS, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(124, EAST, QUP_L5_9_CS, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(125, EAST, QUP_L6_9_CS, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(126, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(127, NORTH, GRFC3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(128, NORTH, RES_1, RES_2, GPS_TX_AGGRESSOR_MIRB, RES_4, + PIN(94, EAST, I2S_1_DATA5, PWM_LED23, I2S_1_DATA6_MIR, RES_4, RES_5, RES_6, RES_7), - PIN(129, NORTH, RES_1, RES_2, GPS_TX_AGGRESSOR_MIRC, RES_4, + PIN(95, EAST, RES_1, PWM_LED1, I2S_1_DATA7_MIR, RES_4, RES_5, + RES_6, RES_7), + PIN(96, EAST, RES_1, PWM_LED2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(97, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(98, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(99, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(100, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(101, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(102, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(103, EAST, RES_1, MCLK_IN2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(104, EAST, I2S_3_SCK_A, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(105, EAST, I2S_3_WS_A, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(106, EAST, I2S_3_DATA0_A, RES_2, HDMI_HOT_PLUG_MIR, RES_4, RES_5, RES_6, RES_7), - PIN(130, NORTH, QLINK_REQUEST, RES_2, RES_3, RES_4, RES_5, + PIN(107, EAST, I2S_3_DATA1_A, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(108, EAST, I2S_3_DATA2_A, RES_2, RES_3, PWM_LED3, RES_5, RES_6, RES_7), - PIN(131, NORTH, QLINK_ENABLE, RES_2, RES_3, RES_4, RES_5, + PIN(109, EAST, I2S_3_DATA3_A, RES_2, PWM_LED4, RES_4, RES_5, RES_6, RES_7), - PIN(132, NORTH, GRFC2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(133, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(134, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(135, NORTH, GRFC0, PA_INDICATOR_1_OR_2, RES_3, RES_4, + PIN(110, EAST, RES_1, RES_2, DSD_CLK_B, PWM_LED5, RES_5, RES_6, + RES_7), + PIN(111, EAST, RES_1, I2S_4_DATA0_DSD0, PWM_LED6, RES_4, RES_5, + RES_6, RES_7), + PIN(112, EAST, RES_1, I2S_4_DATA1_DSD1, PWM_LED7, RES_4, RES_5, + RES_6, RES_7), + PIN(113, EAST, RES_1, I2S_4_DATA2_DSD2, PWM_LED8, RES_4, RES_5, + RES_6, RES_7), + PIN(114, EAST, RES_1, I2S_4_DATA3_DSD3, PWM_LED24, RES_4, RES_5, + RES_6, RES_7), + PIN(115, EAST, RES_1, I2S_4_DATA4_DSD4, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(116, EAST, I2S_4_DATA5_DSD5, SPKR_DAC0, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(117, NORTH, BLSP_I2C_SDA, BLSP_SPI_CS_N, PWM_LED9, RES_4, RES_5, RES_6, RES_7), - PIN(136, NORTH, GRFC1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(137, NORTH, RFFE3_DATA, GRFC35, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(138, NORTH, RFFE3_CLK, GRFC32, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(139, NORTH, RFFE4_DATA, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(140, NORTH, RFFE4_CLK, GRFC36, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(141, NORTH, RFFE5_DATA, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(142, NORTH, RFFE5_CLK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(143, NORTH, GRFC5, RES_2, RES_3, GPS_TX_AGGRESSOR_MIRD, + PIN(118, NORTH, BLSP_I2C_SCL, BLSP_SPI_CLK, PWM_LED10, RES_4, RES_5, RES_6, RES_7), - PIN(144, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(145, NORTH, RES_1, GPS_TX_AGGRESSOR_MIRA, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(146, NORTH, RFFE2_DATA, GRFC34, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(147, NORTH, RFFE2_CLK, GRFC33, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(148, NORTH, RFFE1_DATA, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(149, NORTH, RFFE1_CLK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), + PIN(119, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), }; struct tlmm_gpio { -- To view, visit https://review.coreboot.org/c/coreboot/+/29963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdd675527458e597c1f49544425146bd17f28075 Gerrit-Change-Number: 29963 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: qcs405: Enable uart_bit_bang
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29961 Change subject: qcs405: Enable uart_bit_bang ...................................................................... qcs405: Enable uart_bit_bang uart_bit_bang has been enabled for VER, ROM, RAM stages. uart_fill_lb() empty routine has been declared to avoid compilation error. Change-Id: I387779a74913ffb58d74d2f2c5d3e22167bbc310 Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/uart_bitbang.c 2 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/29961/1 diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index 17ba0f1..6fc87c7 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -14,6 +14,7 @@ verstage-y += spi.c verstage-y += timer.c verstage-y += gpio.c +verstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c verstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c ################################################################################ @@ -21,6 +22,8 @@ romstage-y += cbmem.c romstage-y += timer.c romstage-y += gpio.c +romstage-y += mmu.c +romstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c romstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c ################################################################################ @@ -29,6 +32,7 @@ ramstage-y += cbmem.c ramstage-y += timer.c ramstage-y += gpio.c +ramstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c ramstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c ################################################################################ diff --git a/src/soc/qualcomm/qcs405/uart_bitbang.c b/src/soc/qualcomm/qcs405/uart_bitbang.c index 8827bc4..97782bd 100644 --- a/src/soc/qualcomm/qcs405/uart_bitbang.c +++ b/src/soc/qualcomm/qcs405/uart_bitbang.c @@ -19,6 +19,8 @@ #define UART_TX_PIN GPIO(17) +void uart_fill_lb(void *data); + static void set_tx(int line_state) { gpio_set(UART_TX_PIN, line_state); @@ -43,3 +45,11 @@ { return 0; /* not implemented */ } + +//HACK +#ifndef __PRE_RAM__ +/* TODO: Implement function */ +void uart_fill_lb(void *data) +{ +} +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/29961 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I387779a74913ffb58d74d2f2c5d3e22167bbc310 Gerrit-Change-Number: 29961 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: QCS405: Change DRAM size to 1GB
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29960 Change subject: QCS405: Change DRAM size to 1GB ...................................................................... QCS405: Change DRAM size to 1GB Change-Id: I94f01141d6a537166db3900cf21fc2813cfe96dc Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/cbmem.c M src/soc/qualcomm/qcs405/include/soc/mmu.h M src/soc/qualcomm/qcs405/soc.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/29960/1 diff --git a/src/soc/qualcomm/qcs405/cbmem.c b/src/soc/qualcomm/qcs405/cbmem.c index 3b9ad4a..e065409 100644 --- a/src/soc/qualcomm/qcs405/cbmem.c +++ b/src/soc/qualcomm/qcs405/cbmem.c @@ -17,5 +17,5 @@ void *cbmem_top(void) { - return (void *)((uintptr_t)4 * GiB); + return (void *)((uintptr_t)3 * GiB); } diff --git a/src/soc/qualcomm/qcs405/include/soc/mmu.h b/src/soc/qualcomm/qcs405/include/soc/mmu.h index 3951f96..7bf024f 100644 --- a/src/soc/qualcomm/qcs405/include/soc/mmu.h +++ b/src/soc/qualcomm/qcs405/include/soc/mmu.h @@ -16,7 +16,7 @@ #ifndef _SOC_QUALCOMM_QCS405_MMU_H__ #define _SOC_QUALCOMM_QCS405_MMU_H__ -#define DRAMSIZE4GB 0x100000000 +#define DRAMSIZE1GB 0x40000000 void qcs405_mmu_init(void); #ifdef CONFIG_QC_SOC_SIMULATE diff --git a/src/soc/qualcomm/qcs405/soc.c b/src/soc/qualcomm/qcs405/soc.c index c97822a..3de3c02 100644 --- a/src/soc/qualcomm/qcs405/soc.c +++ b/src/soc/qualcomm/qcs405/soc.c @@ -21,7 +21,7 @@ static void soc_read_resources(device_t dev) { - ram_resource(dev, 0, (uintptr_t)_dram / KiB, DRAMSIZE4GB / KiB); + ram_resource(dev, 0, (uintptr_t)_dram / KiB, DRAMSIZE1GB / KiB); reserved_ram_resource(dev, 1, (uintptr_t)_dram_reserved / KiB, _dram_reserved_size / KiB); } -- To view, visit https://review.coreboot.org/c/coreboot/+/29960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94f01141d6a537166db3900cf21fc2813cfe96dc Gerrit-Change-Number: 29960 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: qcs405:Add SPI_RAM_SIMULATION support for QCS405
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29959 Change subject: qcs405:Add SPI_RAM_SIMULATION support for QCS405 ...................................................................... qcs405:Add SPI_RAM_SIMULATION support for QCS405 Change-Id: I895315a995cbbd5e6a7a305e48476f0d0f583cfe Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/mainboard/google/mistral/romstage.c M src/soc/qualcomm/qcs405/Kconfig M src/soc/qualcomm/qcs405/Makefile.inc A src/soc/qualcomm/qcs405/flash_controller.c A src/soc/qualcomm/qcs405/include/soc/flash_controller.h M src/soc/qualcomm/qcs405/include/soc/mmu.h M src/soc/qualcomm/qcs405/mmu.c M src/soc/qualcomm/qcs405/spi.c 8 files changed, 172 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/29959/1 diff --git a/src/mainboard/google/mistral/romstage.c b/src/mainboard/google/mistral/romstage.c index 079e20b..71968fc 100644 --- a/src/mainboard/google/mistral/romstage.c +++ b/src/mainboard/google/mistral/romstage.c @@ -21,6 +21,12 @@ #include <timestamp.h> #include <arch/stages.h> +#ifdef CONFIG_QC_SOC_SIMULATE +extern void qcs405_mmu_dram_config_c(void); +#endif void platform_romstage_main(void) { +#ifdef CONFIG_QC_SOC_SIMULATE + qcs405_mmu_dram_config_c(); +#endif } diff --git a/src/soc/qualcomm/qcs405/Kconfig b/src/soc/qualcomm/qcs405/Kconfig index 492e80e..b24dc9e 100644 --- a/src/soc/qualcomm/qcs405/Kconfig +++ b/src/soc/qualcomm/qcs405/Kconfig @@ -20,4 +20,10 @@ select VBOOT_RETURN_FROM_VERSTAGE select VBOOT_OPROM_MATTERS select VBOOT_STARTS_IN_BOOTBLOCK + +config QC_SOC_SIMULATE + bool + prompt "Build for Early Simulation Environment" + default y + endif diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index 158ce34..17ba0f1 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -8,17 +8,20 @@ bootblock-y += timer.c bootblock-y += gpio.c bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c +bootblock-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c ################################################################################ verstage-y += spi.c verstage-y += timer.c verstage-y += gpio.c +verstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c ################################################################################ romstage-y += spi.c romstage-y += cbmem.c romstage-y += timer.c romstage-y += gpio.c +romstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c ################################################################################ ramstage-y += soc.c @@ -26,6 +29,7 @@ ramstage-y += cbmem.c ramstage-y += timer.c ramstage-y += gpio.c +ramstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c ################################################################################ diff --git a/src/soc/qualcomm/qcs405/flash_controller.c b/src/soc/qualcomm/qcs405/flash_controller.c new file mode 100644 index 0000000..1cb2aeb --- /dev/null +++ b/src/soc/qualcomm/qcs405/flash_controller.c @@ -0,0 +1,98 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* NOR Flash is clocked with 26MHz, from CLK26M -> TOP_SPINFI_IFR */ + +#include <arch/io.h> +#include <assert.h> +#include <console/console.h> +#include <spi_flash.h> +#include <spi-generic.h> +#include <stdint.h> +#include <stdlib.h> +#include <string.h> +#include <symbols.h> +#include <timer.h> + +static struct spi_flash *ram_flash; +static struct spi_ctrlr *ram_ctrlr; + +#define ROM_BASE 0xA0000000 /* Above cbmem_top() */ + +int spi_simulate_ram_flash_probe(const struct spi_slave *spi, + struct spi_flash *flash); + +static int ram_read(const struct spi_flash *flash, u32 addr, size_t len, void *buf) +{ + void *ap = (void *)ROM_BASE; + ap += addr; + memcpy(buf, ap, len); + return 0; +} + +static int ram_write(const struct spi_flash *flash, u32 addr, size_t len, + const void *buf) +{ + void *ap = (void *)ROM_BASE; + ap += addr; + memcpy(ap, buf, len); + return 0; +} + +static int ram_erase(const struct spi_flash *flash, u32 offset, size_t len) +{ + void *ap = (void *)ROM_BASE; + ap += offset; + memset(ap, 0xFF, len); + return 0; +} + +static int ram_status(const struct spi_flash *flash, u8 *reg) +{ + return 0; +} + +static struct spi_flash_ops ram_ops = +{ + .read = ram_read, + .write = ram_write, + .erase = ram_erase, + .status = ram_status, +}; + +int spi_simulate_ram_flash_probe(const struct spi_slave *spi, + struct spi_flash *flash) +{ + static char name[] = "ram_flash"; + + printk(BIOS_INFO, "[%s]..CONFIG_QC_SOC_SIMULATE\n", __FUNCTION__); + + printk(BIOS_INFO, "[%s]..ram_flash\n", __FUNCTION__); + + ram_flash = flash; + ram_ctrlr = (struct spi_ctrlr *)spi->ctrlr; + ram_ctrlr->max_xfer_size = 0x10000; + flash->spi.bus = spi->bus; + flash->spi.cs = spi->cs; + flash->spi.ctrlr = ram_ctrlr; + flash->name = name; + flash->size = 0x800000; + flash->sector_size = 0x200; + flash->erase_cmd = 0x10; + flash->status_cmd = 0x20; + flash->ops = &ram_ops; + + return 0; +} diff --git a/src/soc/qualcomm/qcs405/include/soc/flash_controller.h b/src/soc/qualcomm/qcs405/include/soc/flash_controller.h new file mode 100644 index 0000000..0641928 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/flash_controller.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_QUALCOMM_QCS405_FLASH_CONTROLLER_H__ +#define __SOC_QUALCOMM_QCS405_FLASH_CONTROLLER_H__ + +#include <cbfs.h> +#include <spi-generic.h> +#include <stdint.h> + +struct spi_flash *qcs405_nor_flash_probe(struct spi_slave *spi); +#endif /* __SOC_QUALCOMM_QCS405_FLASH_CONTROLLER_H__ */ diff --git a/src/soc/qualcomm/qcs405/include/soc/mmu.h b/src/soc/qualcomm/qcs405/include/soc/mmu.h index 75cb320..3951f96 100644 --- a/src/soc/qualcomm/qcs405/include/soc/mmu.h +++ b/src/soc/qualcomm/qcs405/include/soc/mmu.h @@ -19,5 +19,8 @@ #define DRAMSIZE4GB 0x100000000 void qcs405_mmu_init(void); +#ifdef CONFIG_QC_SOC_SIMULATE +void qcs405_mmu_dram_config_c(void); +#endif #endif // _SOC_QUALCOMM_QCS405_MMU_H_ diff --git a/src/soc/qualcomm/qcs405/mmu.c b/src/soc/qualcomm/qcs405/mmu.c index b47de42..bebca24 100644 --- a/src/soc/qualcomm/qcs405/mmu.c +++ b/src/soc/qualcomm/qcs405/mmu.c @@ -27,6 +27,16 @@ MA_DEV | MA_S | MA_RW); mmu_config_range((void *)_ssram, _ssram_size, MA_MEM | MA_S | MA_RW); mmu_config_range((void *)_bsram, _bsram_size, MA_MEM | MA_S | MA_RW); +#ifdef CONFIG_QC_SOC_SIMULATE + mmu_config_range((void *)0x80000000, 0x40000000, MA_MEM | MA_S | MA_RW); +#endif mmu_enable(); } + +#ifdef CONFIG_QC_SOC_SIMULATE +void qcs405_mmu_dram_config_c(void) +{ + mmu_config_range((void *)0x80000000, 0x40000000, MA_MEM | MA_NS | MA_RW); +} +#endif diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c index c04b15d..73e538e 100644 --- a/src/soc/qualcomm/qcs405/spi.c +++ b/src/soc/qualcomm/qcs405/spi.c @@ -16,6 +16,25 @@ #include <spi-generic.h> #include <spi_flash.h> +#if IS_ENABLED(CONFIG_QC_SOC_SIMULATE) + +extern int spi_simulate_ram_flash_probe(const struct spi_slave *spi, + struct spi_flash *flash); + +static const struct spi_ctrlr spi_ctrlr = { + .flash_probe = spi_simulate_ram_flash_probe, +}; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_ctrlr, + .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + } +}; + +#else + static int spi_ctrlr_claim_bus(const struct spi_slave *slave) { return 0; @@ -47,4 +66,6 @@ }, }; +#endif + const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); -- To view, visit https://review.coreboot.org/c/coreboot/+/29959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I895315a995cbbd5e6a7a305e48476f0d0f583cfe Gerrit-Change-Number: 29959 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: qcs405: Combine BB with QC-Sec for ROM boot
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29958 Change subject: qcs405: Combine BB with QC-Sec for ROM boot ...................................................................... qcs405: Combine BB with QC-Sec for ROM boot TEST=build & run Change-Id: I2428fd067c0216d9cf6a63e218d1792788317db0 Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Makefile.inc 1 file changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/29958/1 diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index f05c987..158ce34 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -31,8 +31,34 @@ CPPFLAGS_common += -Isrc/soc/qualcomm/qcs405/include +QCS405_BLOB := $(top)/3rdparty/blobs/soc/qualcomm/qcs405 + $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin @printf "Generating: $(subst $(obj)/,,$(@))\n" cp $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin +################################################################################ +QC_SEC_FILE := $(QCS405_BLOB)/qc_sec.mbn +qc_sec_file := $(shell ls $(QC_SEC_FILE)) +ifneq (,$(findstring $(QC_SEC_FILE),$(qc_sec_file))) +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.elf + @util/qualcomm/createxbl.py -f $(objcbfs)/bootblock.elf \ + -x $(QC_SEC_FILE) -o $(objcbfs)/merged_bb_qcsec.mbn \ + -a 64 -d 32 -c 32 +ifeq ($(CONFIG_QC_FLASH_SIMULATE_SDCARD),y) + @printf "\nqgpt.py 512 sector size\n" + @util/qualcomm/qgpt.py -s 512 $(objcbfs)/merged_bb_qcsec.mbn \ + $(objcbfs)/bootblock.bin +else + @printf "\nqgpt.py 4K sector size\n" + @util/qualcomm/qgpt.py $(objcbfs)/merged_bb_qcsec.mbn \ + $(objcbfs)/bootblock.bin +endif + +else +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin + @printf "Generating: $(subst $(obj)/,,$(@))\n" + cp $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin +endif + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/29958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2428fd067c0216d9cf6a63e218d1792788317db0 Gerrit-Change-Number: 29958 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: libpayload: Add UART for qcs405
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29957 Change subject: libpayload: Add UART for qcs405 ...................................................................... libpayload: Add UART for qcs405 TEST=build Change-Id: I43164cf9eacc844af1d048f7b6ebbda96fc9d202 Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M payloads/libpayload/Kconfig M payloads/libpayload/configs/config.mistral M payloads/libpayload/drivers/Makefile.inc 3 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/29957/1 diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index 3cd8ba6..4ab83cb 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -258,6 +258,11 @@ depends on SERIAL_CONSOLE default n +config QCS405_SERIAL_CONSOLE + bool "QCS405 SOC compatible serial port driver" + depends on SERIAL_CONSOLE + default n + config BG4CD_SERIAL_CONSOLE bool "Serial port driver for Marvell's BG4CD" depends on SERIAL_CONSOLE diff --git a/payloads/libpayload/configs/config.mistral b/payloads/libpayload/configs/config.mistral index 5f60392..23bf54e 100644 --- a/payloads/libpayload/configs/config.mistral +++ b/payloads/libpayload/configs/config.mistral @@ -1,3 +1,8 @@ CONFIG_LP_CHROMEOS=y CONFIG_LP_ARCH_ARM64=y CONFIG_LP_TIMER_ARM64_ARCH=y +CONFIG_LP_SERIAL_CONSOLE=y +CONFIG_LP_QCS405_SERIAL_CONSOLE=y +CONFIG_LP_USB=y +CONFIG_LP_USB_EHCI=y +CONFIG_LP_USB_XHCI=y diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index 2d70856..99de283 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -37,6 +37,7 @@ libc-$(CONFIG_LP_S5P_SERIAL_CONSOLE) += serial/s5p.c serial/serial.c libc-$(CONFIG_LP_IPQ806X_SERIAL_CONSOLE) += serial/ipq806x.c serial/serial.c libc-$(CONFIG_LP_IPQ40XX_SERIAL_CONSOLE) += serial/ipq40xx.c serial/serial.c +libc-$(CONFIG_LP_QCS405_SERIAL_CONSOLE) += serial/ipq40xx.c serial/serial.c libc-$(CONFIG_LP_BG4CD_SERIAL_CONSOLE) += serial/bg4cd.c serial/serial.c libc-$(CONFIG_LP_PC_KEYBOARD) += i8042/keyboard.c libc-$(CONFIG_LP_PC_MOUSE) += i8042/mouse.c -- To view, visit https://review.coreboot.org/c/coreboot/+/29957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43164cf9eacc844af1d048f7b6ebbda96fc9d202 Gerrit-Change-Number: 29957 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: qcs405: Implement bitbang UART for bootblock
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29956 Change subject: qcs405: Implement bitbang UART for bootblock ...................................................................... qcs405: Implement bitbang UART for bootblock This patch replaces the UART in the bootblock of QCS405 with a bitbang implementation. Since QCS405 hardware UART needs a firmware blob loaded into it before it becomes usable, it is not really suited for use in the bootblock (since by the time we can read blobs from SPI, the bootblock is essentially over anyway). This solution allows us to still have some console output during early SoC initialization. Change-Id: Ib631929f6194d0da8571a930230f0eb460fefaa6 Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Kconfig M src/soc/qualcomm/qcs405/Makefile.inc A src/soc/qualcomm/qcs405/uart_bitbang.c 3 files changed, 47 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/29956/1 diff --git a/src/soc/qualcomm/qcs405/Kconfig b/src/soc/qualcomm/qcs405/Kconfig index 83c3996..492e80e 100644 --- a/src/soc/qualcomm/qcs405/Kconfig +++ b/src/soc/qualcomm/qcs405/Kconfig @@ -11,6 +11,7 @@ select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER select ARM64_USE_ARCH_TIMER + select HAVE_UART_SPECIAL if SOC_QUALCOMM_QCS405 diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index 131f204..f05c987 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -7,6 +7,7 @@ bootblock-y += mmu.c bootblock-y += timer.c bootblock-y += gpio.c +bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c ################################################################################ verstage-y += spi.c diff --git a/src/soc/qualcomm/qcs405/uart_bitbang.c b/src/soc/qualcomm/qcs405/uart_bitbang.c new file mode 100644 index 0000000..8827bc4 --- /dev/null +++ b/src/soc/qualcomm/qcs405/uart_bitbang.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/uart.h> +#include <gpio.h> +#include <types.h> + +#define UART_TX_PIN GPIO(17) + +static void set_tx(int line_state) +{ + gpio_set(UART_TX_PIN, line_state); +} + +void uart_init(int idx) +{ + gpio_output(UART_TX_PIN, 1); +} + +void uart_tx_byte(int idx, unsigned char data) +{ + uart_bitbang_tx_byte(data, set_tx); +} + +void uart_tx_flush(int idx) +{ + /* unnecessary, PIO Tx means transaction is over when tx_byte returns */ +} + +unsigned char uart_rx_byte(int idx) +{ + return 0; /* not implemented */ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/29956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib631929f6194d0da8571a930230f0eb460fefaa6 Gerrit-Change-Number: 29956 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: qcs405: Add GPIO API
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29955 Change subject: qcs405: Add GPIO API ...................................................................... qcs405: Add GPIO API Introduces new and required GPIO APIs, using common pinmux definitions for GPIO configuration. TEST=build & run Change-Id: I85ce9007c545b44371c4704a0456774d0eff12a8 Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Makefile.inc A src/soc/qualcomm/qcs405/gpio.c A src/soc/qualcomm/qcs405/include/soc/addressmap.h M src/soc/qualcomm/qcs405/include/soc/gpio.h 4 files changed, 436 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/29955/1 diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index b47a61e..131f204 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -6,21 +6,25 @@ bootblock-y += spi.c bootblock-y += mmu.c bootblock-y += timer.c +bootblock-y += gpio.c ################################################################################ verstage-y += spi.c verstage-y += timer.c +verstage-y += gpio.c ################################################################################ romstage-y += spi.c romstage-y += cbmem.c romstage-y += timer.c +romstage-y += gpio.c ################################################################################ ramstage-y += soc.c ramstage-y += spi.c ramstage-y += cbmem.c ramstage-y += timer.c +ramstage-y += gpio.c ################################################################################ diff --git a/src/soc/qualcomm/qcs405/gpio.c b/src/soc/qualcomm/qcs405/gpio.c new file mode 100644 index 0000000..edbb3b9 --- /dev/null +++ b/src/soc/qualcomm/qcs405/gpio.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <types.h> +#include <console/console.h> +#include <delay.h> +#include <timer.h> +#include <timestamp.h> + +#include <gpio.h> + +void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, + uint32_t drive_str, uint32_t enable) +{ + uint32_t reg_val; + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + reg_val = ((enable & GPIO_CFG_OE_BMSK) << GPIO_CFG_OE_SHFT) | + ((drive_str & GPIO_CFG_DRV_BMSK) << GPIO_CFG_DRV_SHFT) | + ((func & GPIO_CFG_FUNC_BMSK) << GPIO_CFG_FUNC_SHFT) | + ((pull & GPIO_CFG_PULL_BMSK) << GPIO_CFG_PULL_SHFT); + + write32(&regs->cfg, reg_val); +} + +void gpio_set(gpio_t gpio, int value) +{ + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + write32(&regs->in_out, (!!value) << GPIO_IO_OUT_SHFT); +} + +int gpio_get(gpio_t gpio) +{ + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + return ((read32(&regs->in_out) >> GPIO_IO_IN_SHFT) & + GPIO_IO_IN_BMSK); +} + +void gpio_input_pulldown(gpio_t gpio) +{ + gpio_configure(gpio, GPIO_FUNC_DISABLE, + GPIO_PULL_DOWN, GPIO_2MA, GPIO_DISABLE); +} + +void gpio_input_pullup(gpio_t gpio) +{ + gpio_configure(gpio, GPIO_FUNC_DISABLE, + GPIO_PULL_UP, GPIO_2MA, GPIO_DISABLE); +} + +void gpio_input(gpio_t gpio) +{ + gpio_configure(gpio, GPIO_FUNC_DISABLE, + GPIO_NO_PULL, GPIO_2MA, GPIO_DISABLE); +} + +void gpio_output(gpio_t gpio, int value) +{ + gpio_set(gpio, value); + gpio_configure(gpio, GPIO_FUNC_DISABLE, + GPIO_NO_PULL, GPIO_2MA, GPIO_ENABLE); +} diff --git a/src/soc/qualcomm/qcs405/include/soc/addressmap.h b/src/soc/qualcomm/qcs405/include/soc/addressmap.h new file mode 100644 index 0000000..435b680 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/addressmap.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2018 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_QUALCOMM_QCS405_ADDRESS_MAP_H__ +#define __SOC_QUALCOMM_QCS405_ADDRESS_MAP_H__ + +#include <stdint.h> + +#define QSPI_BASE 0x88DF000 +#define TLMM_EAST_TILE_BASE 0x7B00000 +#define TLMM_NORTH_TILE_BASE 0x1300000 +#define TLMM_SOUTH_TILE_BASE 0x1000000 + +#endif /* __SOC_QUALCOMM_QCS405_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/qcs405/include/soc/gpio.h b/src/soc/qualcomm/qcs405/include/soc/gpio.h index e1ad453..f436595 100644 --- a/src/soc/qualcomm/qcs405/include/soc/gpio.h +++ b/src/soc/qualcomm/qcs405/include/soc/gpio.h @@ -17,7 +17,336 @@ #define _SOC_QUALCOMM_QCS405_GPIO_H_ #include <types.h> +#include <soc/addressmap.h> -typedef u32 gpio_t; +typedef struct { + u32 addr; +} gpio_t; + +#define TLMM_TILE_SIZE 0x00400000 +#define TLMM_GPIO_OFF_DELTA 0x00001000 +#define TLMM_GPIO_TILE_NUM 3 + +#define TLMM_GPIO_IN_OUT_OFF 0x4 +#define TLMM_GPIO_ID_STATUS_OFF 0x10 + +#define GPIO_FUNC_ENABLE 1 +#define GPIO_FUNC_DISABLE 0 + +/* GPIO TLMM: Direction */ +#define GPIO_INPUT 0 +#define GPIO_OUTPUT 1 + +/* GPIO TLMM: Pullup/Pulldown */ +#define GPIO_NO_PULL 0 +#define GPIO_PULL_DOWN 1 +#define GPIO_KEEPER 2 +#define GPIO_PULL_UP 3 + +/* GPIO TLMM: Drive Strength */ +#define GPIO_2MA 0 +#define GPIO_4MA 1 +#define GPIO_6MA 2 +#define GPIO_8MA 3 +#define GPIO_10MA 4 +#define GPIO_12MA 5 +#define GPIO_14MA 6 +#define GPIO_16MA 7 + +/* GPIO TLMM: Status */ +#define GPIO_DISABLE 0 +#define GPIO_ENABLE 1 + +/* GPIO TLMM: Mask */ +#define GPIO_CFG_PULL_BMSK 0x3 +#define GPIO_CFG_FUNC_BMSK 0xF +#define GPIO_CFG_DRV_BMSK 0x7 +#define GPIO_CFG_OE_BMSK 0x1 + +/* GPIO TLMM: Shift */ +#define GPIO_CFG_PULL_SHFT 0 +#define GPIO_CFG_FUNC_SHFT 2 +#define GPIO_CFG_DRV_SHFT 6 +#define GPIO_CFG_OE_SHFT 9 + +/* GPIO IO: Mask */ +#define GPIO_IO_IN_BMSK 0x1 +#define GPIO_IO_OUT_BMSK 0x1 + +/* GPIO IO: Shift */ +#define GPIO_IO_IN_SHFT 0 +#define GPIO_IO_OUT_SHFT 1 + +/* GPIO ID STATUS: Mask */ +#define GPIO_ID_STATUS_BMSK 0x1 + +/* GPIO MAX Valid # */ +#define GPIO_NUM_MAX 149 + +#define GPIO_FUNC_GPIO 0 + +#define GPIO(num) ((gpio_t){.addr = GPIO##num##_ADDR}) + +#define PIN(index, tlmm, func1, func2, func3, func4, func5, func6, func7) \ +GPIO##index##_ADDR = TLMM_##tlmm##_TILE_BASE + index * TLMM_GPIO_OFF_DELTA, \ +GPIO##index##_FUNC_##func1 = 1, \ +GPIO##index##_FUNC_##func2 = 2, \ +GPIO##index##_FUNC_##func3 = 3, \ +GPIO##index##_FUNC_##func4 = 4, \ +GPIO##index##_FUNC_##func5 = 5, \ +GPIO##index##_FUNC_##func6 = 6, \ +GPIO##index##_FUNC_##func7 = 7 + +enum { + PIN(0, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(1, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(2, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(3, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(4, NORTH, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(5, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(6, NORTH, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(7, NORTH, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(8, EAST, QUP_L4_0_CS, GP_PDM_MIRB, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(9, EAST, QUP_L5_0_CS, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(10, EAST, MDP_VSYNC_P_MIRA, QUP_L6_0_CS, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(11, EAST, MDP_VSYNC_S_MIRA, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(12, SOUTH, MDP_VSYNC_E, RES_2, TSIF1_SYNC, RES_4, RES_5, + RES_6, RES_7), + PIN(13, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(14, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(15, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(16, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(17, NORTH, CCI_I2C_SDA0, QUP_L0, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(18, SOUTH, CCI_I2C_SCL0, QUP_L1, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(19, SOUTH, CCI_I2C_SDA1, QUP_L2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(20, SOUTH, CCI_I2C_SCL1, QUP_L3, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(21, SOUTH, CCI_TIMER0, GCC_GP2_CLK_MIRB, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(22, SOUTH, CCI_TIMER1, GCC_GP3_CLK_MIRB, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(23, SOUTH, CCI_TIMER2, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(24, SOUTH, CCI_TIMER3, CCI_ASYNC_IN1, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(25, SOUTH, CCI_TIMER4, CCI_ASYNC_IN2, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(26, SOUTH, CCI_ASYNC_IN0, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(27, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(28, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(29, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(30, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(31, NORTH, QUP_L0, QUP_L2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(32, NORTH, QUP_L1, QUP_L3, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(33, NORTH, QUP_L2, QUP_L0, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(34, NORTH, QUP_L3, QUP_L1, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(35, SOUTH, PCI_E0_RST_N, QUP_L4_1_CS, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(36, SOUTH, PCI_E0_CLKREQN, QUP_L5_1_CS, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(37, SOUTH, QUP_L6_1_CS, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(38, NORTH, USB_PHY_PS, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(39, EAST, LPASS_SLIMBUS_DATA2, RES_2, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(40, SOUTH, SD_WRITE_PROTECT, TSIF1_ERROR, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(41, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(42, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(43, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(44, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(45, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(46, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(47, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(48, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(49, NORTH, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(50, NORTH, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(51, NORTH, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(52, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(53, NORTH, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(54, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(55, NORTH, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(56, NORTH, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(57, NORTH, QUA_MI2S_MCLK, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(58, NORTH, QUA_MI2S_SCK, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(59, NORTH, QUA_MI2S_WS, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(60, NORTH, QUA_MI2S_DATA0, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(61, NORTH, QUA_MI2S_DATA1, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(62, NORTH, QUA_MI2S_DATA2, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(63, NORTH, QUA_MI2S_DATA3, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(64, NORTH, PRI_MI2S_MCLK, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(65, NORTH, PRI_MI2S_SCK, QUP_L0, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(66, NORTH, PRI_MI2S_WS, QUP_L1, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(67, NORTH, PRI_MI2S_DATA0, QUP_L2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(68, NORTH, PRI_MI2S_DATA1, QUP_L3, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(69, EAST, SPKR_I2S_MCLK, AUDIO_REF_CLK, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(70, EAST, LPASS_SLIMBUS_CLK, SPKR_I2S_SCK, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(71, EAST, LPASS_SLIMBUS_DATA0, SPKR_I2S_DATA_OUT, RES_3, + RES_4, RES_5, RES_6, RES_7), + PIN(72, EAST, LPASS_SLIMBUS_DATA1, SPKR_I2S_WS, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(73, EAST, BTFM_SLIMBUS_DATA, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(74, EAST, BTFM_SLIMBUS_CLK, TER_MI2S_MCLK, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(75, EAST, TER_MI2S_SCK, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(76, EAST, TER_MI2S_WS, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(77, EAST, TER_MI2S_DATA0, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(78, EAST, TER_MI2S_DATA1, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(79, NORTH, SEC_MI2S_MCLK, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(80, NORTH, SEC_MI2S_SCK, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(81, NORTH, SEC_MI2S_WS, QUP_L0, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(82, NORTH, SEC_MI2S_DATA0, QUP_L1, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(83, NORTH, SEC_MI2S_DATA1, QUP_L2, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(84, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(85, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(86, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(87, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(88, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(89, SOUTH, TSIF1_CLK, QUP_L0, QSPI_CS_N_1, RES_4, RES_5, + RES_6, RES_7), + PIN(90, SOUTH, TSIF1_EN, MDP_VSYNC0_OUT, QUP_L1, QSPI_CS_N_0, + MDP_VSYNC1_OUT, MDP_VSYNC2_OUT, MDP_VSYNC3_OUT), + PIN(91, SOUTH, TSIF1_DATA, SDC4_CMD, QUP_L2, QSPI_DATA, + RES_5, RES_6, RES_7), + PIN(92, SOUTH, TSIF2_ERROR, SDC4_DATA, QUP_L3, QSPI_DATA, + RES_5, RES_6, RES_7), + PIN(93, SOUTH, TSIF2_CLK, SDC4_CLK, QUP_L0, QSPI_DATA, + RES_5, RES_6, RES_7), + PIN(94, SOUTH, TSIF2_EN, SDC4_DATA, QUP_L1, QSPI_DATA, + RES_5, RES_6, RES_7), + PIN(95, SOUTH, TSIF2_DATA, SDC4_DATA, QUP_L2, QSPI_CLK, + RES_5, RES_6, RES_7), + PIN(96, SOUTH, TSIF2_SYNC, SDC4_DATA, QUP_L3, RES_4, + RES_5, RES_6, RES_7), + PIN(97, NORTH, RFFE6_CLK, GRFC37, MDP_VSYNC_P_MIRB, + RES_4, RES_5, RES_6, RES_7), + PIN(98, NORTH, RFFE6_DATA, MDP_VSYNC_S_MIRB, RES_3, + RES_4, RES_5, RES_6, RES_7), + PIN(99, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(100, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(101, NORTH, GRFC4, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(102, NORTH, PCI_E1_RST_N, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(103, NORTH, PCI_E1_CLKREQN, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(104, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(105, NORTH, UIM2_DATA, QUP_L0, QUP_L4_8_CS, RES_4, RES_5, + RES_6, RES_7), + PIN(106, NORTH, UIM2_CLK, QUP_L1, QUP_L5_8_CS, RES_4, RES_5, + RES_6, RES_7), + PIN(107, NORTH, UIM2_RESET, QUP_L2, QUP_L6_8_CS, RES_4, RES_5, + RES_6, RES_7), + PIN(108, NORTH, UIM2_PRESENT, QUP_L3, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(109, NORTH, UIM1_DATA, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(110, NORTH, UIM1_CLK, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(111, NORTH, UIM1_RESET, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(112, NORTH, UIM1_PRESENT, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(113, NORTH, UIM_BATT_ALARM, EDP_HOT_PLUG_DETECT, RES_3, + RES_4, RES_5, RES_6, RES_7), + PIN(114, NORTH, GRFC8, RES_2, RES_3, GPS_TX_AGGRESSOR_MIRE, + RES_5, RES_6, RES_7), + PIN(115, NORTH, GRFC9, RES_2, RES_3, GPS_TX_AGGRESSOR_MIRF, + RES_5, RES_6, RES_7), + PIN(116, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(117, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(118, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(119, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(120, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(121, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(122, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(123, EAST, QUP_L4_9_CS, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(124, EAST, QUP_L5_9_CS, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(125, EAST, QUP_L6_9_CS, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(126, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(127, NORTH, GRFC3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(128, NORTH, RES_1, RES_2, GPS_TX_AGGRESSOR_MIRB, RES_4, + RES_5, RES_6, RES_7), + PIN(129, NORTH, RES_1, RES_2, GPS_TX_AGGRESSOR_MIRC, RES_4, + RES_5, RES_6, RES_7), + PIN(130, NORTH, QLINK_REQUEST, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(131, NORTH, QLINK_ENABLE, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(132, NORTH, GRFC2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(133, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(134, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(135, NORTH, GRFC0, PA_INDICATOR_1_OR_2, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(136, NORTH, GRFC1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(137, NORTH, RFFE3_DATA, GRFC35, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(138, NORTH, RFFE3_CLK, GRFC32, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(139, NORTH, RFFE4_DATA, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(140, NORTH, RFFE4_CLK, GRFC36, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(141, NORTH, RFFE5_DATA, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(142, NORTH, RFFE5_CLK, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(143, NORTH, GRFC5, RES_2, RES_3, GPS_TX_AGGRESSOR_MIRD, + RES_5, RES_6, RES_7), + PIN(144, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(145, NORTH, RES_1, GPS_TX_AGGRESSOR_MIRA, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(146, NORTH, RFFE2_DATA, GRFC34, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(147, NORTH, RFFE2_CLK, GRFC33, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(148, NORTH, RFFE1_DATA, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(149, NORTH, RFFE1_CLK, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), +}; + +struct tlmm_gpio { + uint32_t cfg; + uint32_t in_out; +}; + +void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, + uint32_t drive_str, uint32_t enable); #endif // _SOC_QUALCOMM_QCS405_GPIO_H_ -- To view, visit https://review.coreboot.org/c/coreboot/+/29955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85ce9007c545b44371c4704a0456774d0eff12a8 Gerrit-Change-Number: 29955 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: qcs405: Add DRAM resources
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29954 Change subject: qcs405: Add DRAM resources ...................................................................... qcs405: Add DRAM resources TEST=build Change-Id: Iea79a942c297400c88aa205da713bcfcb8c51185 Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/include/soc/memlayout.ld M src/soc/qualcomm/qcs405/include/soc/mmu.h M src/soc/qualcomm/qcs405/include/soc/symbols.h M src/soc/qualcomm/qcs405/soc.c 4 files changed, 17 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/29954/1 diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld index c0f5759..03c6edb 100644 --- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld +++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld @@ -45,7 +45,9 @@ REGION(pmic, 0x8D8F000, 0xA000, 4096)*/ BSRAM_END(0x8D80000) - DRAM_START(0x90000000) - POSTRAM_CBFS_CACHE(0x90000000, 384K) - RAMSTAGE(0x90800000, 128K) + DRAM_START(0x80000000) + /* Various hardware/software subsystems make use of this area */ + REGION(dram_reserved, 0x85000000, 0x1A800000, 4096) + POSTRAM_CBFS_CACHE(0x9F800000, 384K) + RAMSTAGE(0x9F860000, 128K) } diff --git a/src/soc/qualcomm/qcs405/include/soc/mmu.h b/src/soc/qualcomm/qcs405/include/soc/mmu.h index bc42e72..75cb320 100644 --- a/src/soc/qualcomm/qcs405/include/soc/mmu.h +++ b/src/soc/qualcomm/qcs405/include/soc/mmu.h @@ -16,6 +16,8 @@ #ifndef _SOC_QUALCOMM_QCS405_MMU_H__ #define _SOC_QUALCOMM_QCS405_MMU_H__ +#define DRAMSIZE4GB 0x100000000 + void qcs405_mmu_init(void); #endif // _SOC_QUALCOMM_QCS405_MMU_H_ diff --git a/src/soc/qualcomm/qcs405/include/soc/symbols.h b/src/soc/qualcomm/qcs405/include/soc/symbols.h index 7b35c55..f7cdc8d 100644 --- a/src/soc/qualcomm/qcs405/include/soc/symbols.h +++ b/src/soc/qualcomm/qcs405/include/soc/symbols.h @@ -26,4 +26,8 @@ extern u8 _ebsram[]; #define _bsram_size (_ebsram - _bsram) +extern u8 _dram_reserved[]; +extern u8 _edram_reserved[]; +#define _dram_reserved_size (_edram_reserved - _dram_reserved) + #endif // _SOC_QUALCOMM_QCS405_SYMBOLS_H_ diff --git a/src/soc/qualcomm/qcs405/soc.c b/src/soc/qualcomm/qcs405/soc.c index 7870219..c97822a 100644 --- a/src/soc/qualcomm/qcs405/soc.c +++ b/src/soc/qualcomm/qcs405/soc.c @@ -13,12 +13,17 @@ * GNU General Public License for more details. */ +#include <symbols.h> #include <device/device.h> #include <timestamp.h> +#include <soc/mmu.h> +#include <soc/symbols.h> static void soc_read_resources(device_t dev) { - + ram_resource(dev, 0, (uintptr_t)_dram / KiB, DRAMSIZE4GB / KiB); + reserved_ram_resource(dev, 1, (uintptr_t)_dram_reserved / KiB, + _dram_reserved_size / KiB); } static void soc_init(device_t dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/29954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea79a942c297400c88aa205da713bcfcb8c51185 Gerrit-Change-Number: 29954 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: qcs405: Add Timer support
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29952 Change subject: qcs405: Add Timer support ...................................................................... qcs405: Add Timer support Init frequency to 19.2 MHz TEST=build Change-Id: I566c7ff2b7085c9dd89ea74a08f3ba862feab2ab Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Kconfig M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/timer.c 3 files changed, 8 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/29952/1 diff --git a/src/soc/qualcomm/qcs405/Kconfig b/src/soc/qualcomm/qcs405/Kconfig index 560d988..83c3996 100644 --- a/src/soc/qualcomm/qcs405/Kconfig +++ b/src/soc/qualcomm/qcs405/Kconfig @@ -10,6 +10,7 @@ select GENERIC_GPIO_LIB select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER + select ARM64_USE_ARCH_TIMER if SOC_QUALCOMM_QCS405 diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index 2d1f842..b47a61e 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -3,24 +3,24 @@ ################################################################################ bootblock-y += bootblock.c -bootblock-y += timer.c bootblock-y += spi.c bootblock-y += mmu.c +bootblock-y += timer.c ################################################################################ -verstage-y += timer.c verstage-y += spi.c +verstage-y += timer.c ################################################################################ -romstage-y += timer.c romstage-y += spi.c romstage-y += cbmem.c +romstage-y += timer.c ################################################################################ ramstage-y += soc.c -ramstage-y += timer.c ramstage-y += spi.c ramstage-y += cbmem.c +ramstage-y += timer.c ################################################################################ diff --git a/src/soc/qualcomm/qcs405/timer.c b/src/soc/qualcomm/qcs405/timer.c index 8fb84c8..5df2430 100644 --- a/src/soc/qualcomm/qcs405/timer.c +++ b/src/soc/qualcomm/qcs405/timer.c @@ -13,15 +13,11 @@ * GNU General Public License for more details. */ -#include <timer.h> #include <delay.h> - -void timer_monotonic_get(struct mono_time *mt) -{ - -} +#include <arch/lib_helpers.h> +#include <commonlib/helpers.h> void init_timer(void) { - + raw_write_cntfrq_el0(19200*KHz); } -- To view, visit https://review.coreboot.org/c/coreboot/+/29952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I566c7ff2b7085c9dd89ea74a08f3ba862feab2ab Gerrit-Change-Number: 29952 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: libpayload: Add Timer for qcs405
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29953 Change subject: libpayload: Add Timer for qcs405 ...................................................................... libpayload: Add Timer for qcs405 Use ARCH64 Timer TEST=build Change-Id: I15273fdacab0a23e05e821c433cf939be35fab97 Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- A payloads/libpayload/configs/config.mistral 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/29953/1 diff --git a/payloads/libpayload/configs/config.mistral b/payloads/libpayload/configs/config.mistral new file mode 100644 index 0000000..5f60392 --- /dev/null +++ b/payloads/libpayload/configs/config.mistral @@ -0,0 +1,3 @@ +CONFIG_LP_CHROMEOS=y +CONFIG_LP_ARCH_ARM64=y +CONFIG_LP_TIMER_ARM64_ARCH=y -- To view, visit https://review.coreboot.org/c/coreboot/+/29953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15273fdacab0a23e05e821c433cf939be35fab97 Gerrit-Change-Number: 29953 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: util/qualcomm: Add T32 debug scripts
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29951 Change subject: util/qualcomm: Add T32 debug scripts ...................................................................... util/qualcomm: Add T32 debug scripts T32 scripts that allow debug of any coreboot stage on qcs405 Change-Id: I4e792a2806e5ebd3b4075c7bb69c43587920deae Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- A util/qualcomm/scripts/cmm/clear_bss.cmm A util/qualcomm/scripts/cmm/debug_cb_405.cmm M util/qualcomm/scripts/cmm/debug_cb_common.cmm A util/qualcomm/scripts/cmm/pbl32_to_bootblock64_jump.cmm 4 files changed, 212 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/29951/1 diff --git a/util/qualcomm/scripts/cmm/clear_bss.cmm b/util/qualcomm/scripts/cmm/clear_bss.cmm new file mode 100755 index 0000000..16eaac7 --- /dev/null +++ b/util/qualcomm/scripts/cmm/clear_bss.cmm @@ -0,0 +1,16 @@ +d.a 0x80000000 mov x0,#0x8c +d.a 0x80000004 lsl x0, x0, #0x14 +d.a 0x80000008 mov x1,#0x18 +d.a 0x8000000c lsl x1,x1, #0x10 +d.a 0x80000010 mov x2,#0x0 +d.a 0x80000014 mov x3,#0x80 +d.a 0x80000018 lsl x3, x3, #0x18 +d.a 0x8000001c add x3, x3, #0x14 +d.a 0x80000020 str x2,[x0] +d.a 0x80000024 sub x1, x1, #0x8 +d.a 0x80000028 add x0, x0, #0x8 +d.a 0x8000002c cmp x1,0x0 +d.a 0x80000030 b.ne 0x20 +d.a 0x80000034 b 0x34 +r.s pc 0x80000000 +go diff --git a/util/qualcomm/scripts/cmm/debug_cb_405.cmm b/util/qualcomm/scripts/cmm/debug_cb_405.cmm new file mode 100644 index 0000000..166d2aa --- /dev/null +++ b/util/qualcomm/scripts/cmm/debug_cb_405.cmm @@ -0,0 +1,165 @@ +;============================================================================ +;## +;## This file is part of the coreboot project. +;## +;## Copyright (C) 2018, The Linux Foundation. All rights reserved. +;## +;## This program is free software; you can redistribute it and/or modify +;## it under the terms of the GNU General Public License version 2 and +;## only version 2 as published by the Free Software Foundation. +;## +;## This program is distributed in the hope that it will be useful, +;## but WITHOUT ANY WARRANTY; without even the implied warranty of +;## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;## GNU General Public License for more details. +;## +;============================================================================ +; Name: +; debug_cb_405.cmm +; +; Description: +; Debug coreboot 405 front-end +;============================================================================ + +;============================================================================ +; CMM script variables +;============================================================================ + +LOCAL &TargetPkg + +GLOBAL &BBEntryAddr // Bootblock Entry +GLOBAL &BBExitAddr // Bootblock Exit to Xbl-Sec +GLOBAL &VEREntryAddr // Verstage Entry +GLOBAL &ROMEntryAddr // Romstage Entry +GLOBAL &QCLEntryAddr // QCLstage Entry +GLOBAL &RAMEntryAddr // Ramstage Entry +GLOBAL &BL31EntryAddr // BL31 Entry +GLOBAL &DCEntryAddr // Depthcharge Entry +GLOBAL &KernelEntryAddr // Kernel Entry + +GLOBAL &PreRamConsoleAddr +GLOBAL &RamConsoleAddr +GLOBAL &PreRamCbfsCache +GLOBAL &VBoot2Work +GLOBAL &Stack +GLOBAL &Ttb +GLOBAL &Timestamp +GLOBAL &CbmemTop +GLOBAL &PostRamCbfsCache + +GLOBAL &CBTablePtr + +GLOBAL &debug + +;============================================================================ + +;--------------------------------------------------- +; Entry point +;--------------------------------------------------- +ENTRY &ImageName + + // Later these can be parameterized + &TargetPkg="Qcs405Pkg" + + // These settings come from .../src/soc/qualcomm/qcs405/include/soc/memlayout.ld + &BBEntryAddr=0x8c2f000 + &VEREntryAddr=0x8C00000 + &ROMEntryAddr=0x8C00000 + &QCLEntryAddr=0x1485AC00 + &RAMEntryAddr=0x9F860000 + &BL31EntryAddr=0x06820000 + &DCEntryAddr=0xf1104800 + &KernelEntryAddr=0x90080000 + + &PreRamConsoleAddr=0x8C4F400 + &VBoot2Work=0x8C47000 + &Stack=0x8C4B000 + &Ttb=0x8C39000 + &Timestamp=0x8C4F000 + &PreRamCbfsCache=0x8C57400 + &CbmemTop=0x280000000 + &PostRamCbfsCache=0x9F800000 + // End of memlayout.ld settings + + // Common commands irrespective of &Mode + PATH + &CwDir=os.pwd() + PATH + &CwDir + + // position at top of coreboot tree + // find depth count for source loading + cd ..\..\..\.. + &srcpath=os.pwd() + + b.sel PROGRAM onchip + ;sys.u + + b.d /all + + ;go &BBEntryAddr + ;wait !run() + +;--------------------------------------------------- +; Setup area and log +;--------------------------------------------------- + area.clear + area.reset + area.create CB_Logs 1000. 8192. + area.select CB_Logs + + ;winclear + ;b.d /all + + if FILE.EXIST("C:\TEMP\WIN.CMM") + do C:\TEMP\WIN.CMM + + area.view CB_Logs + + PRINT %String "Source Path: &srcpath" + + symbol.sourcepath.setbasedir &srcpath\src + + PRINT "pbl32_to_bootblock64 jump" + do pbl32_to_bootblock64_jump.cmm + do clear_bss.cmm + WAIT 5s + b + + // Make parsing simple, upper-case parameters + &Imagename=STRING.UPR("&Imagename") + IF (STR.CP("&ImageName","DEBUG,*")) + ( + &debug="DEBUG" + ) + ELSE + ( + &debug="" + ) + &Imagename=STR.CUT("&ImageName",6) + IF "&debug"=="" + ( + PRINT "SPI_RAM LOAD" + &ImageName=STRING.UPR("&ImageName") + IF "&ImageName"=="" + ( + &ImageName="RAM,BB" //for RAM load Bootblock only and jump till DC + ) + PRINT "&ImageName" + ) + ELSE + ( + if (STR.CP("&debug","DEBUG")) + ( + PRINT "DEBUG" + &ImageName=STRING.UPR("&ImageName") + IF "&ImageName"=="" + ( + &ImageName="RAM,ALL" //for RAM loading all the images + ) + PRINT "&ImageName" + ) + ) + + DO debug_cb_common.cmm &TargetPkg &srcpath &xblsrcpath &ImageName + + enddo diff --git a/util/qualcomm/scripts/cmm/debug_cb_common.cmm b/util/qualcomm/scripts/cmm/debug_cb_common.cmm index bdb0097..5959ee1 100644 --- a/util/qualcomm/scripts/cmm/debug_cb_common.cmm +++ b/util/qualcomm/scripts/cmm/debug_cb_common.cmm @@ -104,6 +104,10 @@ if &BBStage ( + IF "&debug"=="" + ( + d.load.binary build/coreboot.rom 0xA0000000 + ) &imgpath="build\cbfs\fallback\bootblock.elf" if (&RAMLoad) d.load.elf &imgpath /strippart "coreboot" /sourcepath &srcpath @@ -114,9 +118,17 @@ ;b.s run_romstage /o ;d.set &PreRamConsoleAddr++0x8000 0 d.dump &PreRamConsoleAddr /spotlight - print %String "Now the control is in BootBlock, press enter after debugging to go to next stage" - print %String "Press enter to go to next stage" - enter + IF (STR.CP("&debug","DEBUG")) + ( + print %String "Now the control is in BootBlock, press enter after debugging to go to next stage" + print %String "Press enter to go to next stage" + enter + ) + ELSE + ( + go + enddo + ) ) go &VEREntryAddr diff --git a/util/qualcomm/scripts/cmm/pbl32_to_bootblock64_jump.cmm b/util/qualcomm/scripts/cmm/pbl32_to_bootblock64_jump.cmm new file mode 100644 index 0000000..de01bad --- /dev/null +++ b/util/qualcomm/scripts/cmm/pbl32_to_bootblock64_jump.cmm @@ -0,0 +1,16 @@ +PER.Set.simple SPR:0x36100 %Long 00c5183C +D.S AZSD:0x8600034 %LE %Long 0x8600000 +D.S AZSD:0x8600000 %LE %Long 0x1400000 +d.a 0x8600004 ldr r0,0x8600034 +d.a 0x8600008 mcr p15,0x0,r0,c12,c0,1 +d.a 0x860000c dsb +d.a 0x8600010 isb +d.a 0x8600014 mrc p15,0x0,r1,c12,c0,2 +d.a 0x8600018 orr r1,r1,0x3 +d.a 0x860001c mcr p15,0x0,r1,c12,c0,2 +d.a 0x8600020 isb +d.a 0x8600024 wfi +r.s pc 0x8600004 +go +b + -- To view, visit https://review.coreboot.org/c/coreboot/+/29951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e792a2806e5ebd3b4075c7bb69c43587920deae Gerrit-Change-Number: 29951 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: soc/qualcomm/qcs405: Add MMU support
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29950 Change subject: soc/qualcomm/qcs405: Add MMU support ...................................................................... soc/qualcomm/qcs405: Add MMU support Initialize 1st 4GB as Device Memory, except: * 1st page: NULL address * System_IMEM: Cached SRAM * Boot_IMEM: Cached SRAM Change-Id: I8c6353be2c0379ec94f91223805762a2286de06d Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/bootblock.c A src/soc/qualcomm/qcs405/include/soc/mmu.h A src/soc/qualcomm/qcs405/include/soc/symbols.h A src/soc/qualcomm/qcs405/mmu.c 5 files changed, 85 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/29950/1 diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index 15f5a0c..2d1f842 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -5,6 +5,7 @@ bootblock-y += bootblock.c bootblock-y += timer.c bootblock-y += spi.c +bootblock-y += mmu.c ################################################################################ verstage-y += timer.c diff --git a/src/soc/qualcomm/qcs405/bootblock.c b/src/soc/qualcomm/qcs405/bootblock.c index 3ed37ae..5e63f13 100644 --- a/src/soc/qualcomm/qcs405/bootblock.c +++ b/src/soc/qualcomm/qcs405/bootblock.c @@ -14,8 +14,9 @@ */ #include <bootblock_common.h> +#include <soc/mmu.h> void bootblock_soc_init(void) { - + qcs405_mmu_init(); } diff --git a/src/soc/qualcomm/qcs405/include/soc/mmu.h b/src/soc/qualcomm/qcs405/include/soc/mmu.h new file mode 100644 index 0000000..bc42e72 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/mmu.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_QCS405_MMU_H__ +#define _SOC_QUALCOMM_QCS405_MMU_H__ + +void qcs405_mmu_init(void); + +#endif // _SOC_QUALCOMM_QCS405_MMU_H_ diff --git a/src/soc/qualcomm/qcs405/include/soc/symbols.h b/src/soc/qualcomm/qcs405/include/soc/symbols.h new file mode 100644 index 0000000..7b35c55 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/symbols.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_QCS405_SYMBOLS_H_ +#define _SOC_QUALCOMM_QCS405_SYMBOLS_H_ + +#include <types.h> + +extern u8 _ssram[]; +extern u8 _essram[]; +#define _ssram_size (_essram - _ssram) + +extern u8 _bsram[]; +extern u8 _ebsram[]; +#define _bsram_size (_ebsram - _bsram) + +#endif // _SOC_QUALCOMM_QCS405_SYMBOLS_H_ diff --git a/src/soc/qualcomm/qcs405/mmu.c b/src/soc/qualcomm/qcs405/mmu.c new file mode 100644 index 0000000..b47de42 --- /dev/null +++ b/src/soc/qualcomm/qcs405/mmu.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <symbols.h> +#include <arch/mmu.h> +#include <arch/cache.h> +#include <soc/mmu.h> +#include <soc/symbols.h> + +void qcs405_mmu_init() +{ + mmu_init(); + + mmu_config_range((void *)(4 * KiB), ((4UL * GiB) - (4 * KiB)), + MA_DEV | MA_S | MA_RW); + mmu_config_range((void *)_ssram, _ssram_size, MA_MEM | MA_S | MA_RW); + mmu_config_range((void *)_bsram, _bsram_size, MA_MEM | MA_S | MA_RW); + + mmu_enable(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/29950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c6353be2c0379ec94f91223805762a2286de06d Gerrit-Change-Number: 29950 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: mainboard/google/mistral: Add support for Mistral
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29949 Change subject: mainboard/google/mistral: Add support for Mistral ...................................................................... mainboard/google/mistral: Add support for Mistral Adding a new board variant 'Mistral' based on qcs405 soc. TEST=build Change-Id: I7ecfad68bb50f42acf36f51bc3433add56597c3d Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- A src/mainboard/google/mistral/Kconfig A src/mainboard/google/mistral/Kconfig.name A src/mainboard/google/mistral/Makefile.inc A src/mainboard/google/mistral/board_info.txt A src/mainboard/google/mistral/bootblock.c A src/mainboard/google/mistral/chromeos.c A src/mainboard/google/mistral/chromeos.fmd A src/mainboard/google/mistral/devicetree.cb A src/mainboard/google/mistral/mainboard.c A src/mainboard/google/mistral/memlayout.ld A src/mainboard/google/mistral/romstage.c 11 files changed, 256 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/29949/1 diff --git a/src/mainboard/google/mistral/Kconfig b/src/mainboard/google/mistral/Kconfig new file mode 100644 index 0000000..f8e8ac7 --- /dev/null +++ b/src/mainboard/google/mistral/Kconfig @@ -0,0 +1,43 @@ + +config BOARD_GOOGLE_MISTRAL_COMMON # Umbrella option to be selected by variants + def_bool n + +if BOARD_GOOGLE_MISTRAL_COMMON + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select COMMON_CBFS_SPI_WRAPPER + select SOC_QUALCOMM_QCS405 + select SPI_FLASH + select MAINBOARD_HAS_CHROMEOS + select MISSING_BOARD_RESET + +config VBOOT + select VBOOT_VBNV_FLASH + select VBOOT_MOCK_SECDATA + select VBOOT_NO_BOARD_SUPPORT + select GBB_FLAG_FORCE_DEV_SWITCH_ON + +config MAINBOARD_DIR + string + default google/mistral + +config MAINBOARD_VENDOR + string + default "Google" + +########################################################## +#### Update below when adding a new derivative board. #### +########################################################## + +config MAINBOARD_PART_NUMBER + string + default "Mistral" if BOARD_GOOGLE_MISTRAL + +config GBB_HWID + string + depends on CHROMEOS + default "MISTRAL TEST 1859" if BOARD_GOOGLE_MISTRAL + +endif # BOARD_GOOGLE_MISTRAL_COMMON diff --git a/src/mainboard/google/mistral/Kconfig.name b/src/mainboard/google/mistral/Kconfig.name new file mode 100644 index 0000000..ca51fa2 --- /dev/null +++ b/src/mainboard/google/mistral/Kconfig.name @@ -0,0 +1,4 @@ + +config BOARD_GOOGLE_MISTRAL + bool "Mistral" + select BOARD_GOOGLE_MISTRAL_COMMON diff --git a/src/mainboard/google/mistral/Makefile.inc b/src/mainboard/google/mistral/Makefile.inc new file mode 100644 index 0000000..0e2f6bd --- /dev/null +++ b/src/mainboard/google/mistral/Makefile.inc @@ -0,0 +1,15 @@ + +bootblock-y += memlayout.ld +bootblock-y += chromeos.c +bootblock-y += bootblock.c + +verstage-y += memlayout.ld +verstage-y += chromeos.c + +romstage-y += memlayout.ld +romstage-y += chromeos.c +romstage-y += romstage.c + +ramstage-y += memlayout.ld +ramstage-y += chromeos.c +ramstage-y += mainboard.c diff --git a/src/mainboard/google/mistral/board_info.txt b/src/mainboard/google/mistral/board_info.txt new file mode 100644 index 0000000..5ef77d7 --- /dev/null +++ b/src/mainboard/google/mistral/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Mistral Qualcomm QCS405 reference board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/mistral/bootblock.c b/src/mainboard/google/mistral/bootblock.c new file mode 100644 index 0000000..6718d52 --- /dev/null +++ b/src/mainboard/google/mistral/bootblock.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <timestamp.h> + +void bootblock_mainboard_init(void) +{ + +} diff --git a/src/mainboard/google/mistral/chromeos.c b/src/mainboard/google/mistral/chromeos.c new file mode 100644 index 0000000..538e46f --- /dev/null +++ b/src/mainboard/google/mistral/chromeos.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boot/coreboot_tables.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + +} diff --git a/src/mainboard/google/mistral/chromeos.fmd b/src/mainboard/google/mistral/chromeos.fmd new file mode 100644 index 0000000..e8b9978 --- /dev/null +++ b/src/mainboard/google/mistral/chromeos.fmd @@ -0,0 +1,52 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018, The Linux Foundation. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License version 2 and +## only version 2 as published by the Free Software Foundation. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +FLASH@0x0 0x800000 { + WP_RO@0x0 0x300000 { + RO_SECTION@0x0 0x2FE000 { + BOOTBLOCK@0 248K + COREBOOT(CBFS)@0x3E000 0x1E0000 + FMAP@0x21E000 0x1000 + GBB@0x21F000 0xDEF00 + RO_FRID@0x2FDF00 0x100 + } + RO_VPD@0x2FE000 0x2000 + } + + RW_NVRAM@0x300000 0x8000 + RW_ELOG@0x308000 0x8000 + RW_VPD@0x310000 0x8000 + RW_CDT@0x318000 0x8000 + + RW_SECTION_A@0x320000 0x268000 { + VBLOCK_A@0x0 0x2000 + FW_MAIN_A(CBFS)@0x2000 0x1E1F00 + RW_FWID_A@0x1E3F00 0x100 + RW_DDR_TRAINING_A@0x1E4000 0x4000 + RW_XBL_BUFFER_A@0x1E8000 0x4000 + } + + RW_SHARED@0x588000 0x10000 { + SHARED_DATA@0x0 0x10000 + } + + RW_SECTION_B@0x598000 0x268000 { + VBLOCK_B@0x0 0x2000 + FW_MAIN_B(CBFS)@0x2000 0x1E1F00 + RW_FWID_B@0x1E3F00 0x100 + RW_DDR_TRAINING_B@0x1E4000 0x4000 + RW_XBL_BUFFER_B@0x1E8000 0x4000 + } +} diff --git a/src/mainboard/google/mistral/devicetree.cb b/src/mainboard/google/mistral/devicetree.cb new file mode 100644 index 0000000..977f4c6 --- /dev/null +++ b/src/mainboard/google/mistral/devicetree.cb @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018, The Linux Foundation. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License version 2 and +## only version 2 as published by the Free Software Foundation. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/qualcomm/qcs405 + device cpu_cluster 0 on end +end diff --git a/src/mainboard/google/mistral/mainboard.c b/src/mainboard/google/mistral/mainboard.c new file mode 100644 index 0000000..c249a32 --- /dev/null +++ b/src/mainboard/google/mistral/mainboard.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <bootblock_common.h> +#include <timestamp.h> + +static void mainboard_init(device_t dev) +{ + +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = CONFIG_MAINBOARD_PART_NUMBER, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/mistral/memlayout.ld b/src/mainboard/google/mistral/memlayout.ld new file mode 100644 index 0000000..cbc50e2 --- /dev/null +++ b/src/mainboard/google/mistral/memlayout.ld @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + #include <soc/memlayout.ld> diff --git a/src/mainboard/google/mistral/romstage.c b/src/mainboard/google/mistral/romstage.c new file mode 100644 index 0000000..079e20b --- /dev/null +++ b/src/mainboard/google/mistral/romstage.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/exception.h> +#include <cbmem.h> +#include <halt.h> +#include <program_loading.h> +#include <console/console.h> +#include <timestamp.h> +#include <arch/stages.h> + +void platform_romstage_main(void) +{ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/29949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ecfad68bb50f42acf36f51bc3433add56597c3d Gerrit-Change-Number: 29949 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: soc/qualcomm/qcs405: Support for new SoC
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29948 Change subject: soc/qualcomm/qcs405: Support for new SoC ...................................................................... soc/qualcomm/qcs405: Support for new SoC Adding the basic infrastruture soc support for qcs405 and a new build variant. TEST=build Change-Id: Ia379cf375e4459ed55cc36cb8a0a92cab18b705e Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- A src/soc/qualcomm/qcs405/Kconfig A src/soc/qualcomm/qcs405/Makefile.inc A src/soc/qualcomm/qcs405/bootblock.c A src/soc/qualcomm/qcs405/cbmem.c A src/soc/qualcomm/qcs405/include/soc/gpio.h A src/soc/qualcomm/qcs405/include/soc/memlayout.ld A src/soc/qualcomm/qcs405/soc.c A src/soc/qualcomm/qcs405/spi.c A src/soc/qualcomm/qcs405/timer.c 9 files changed, 288 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/29948/1 diff --git a/src/soc/qualcomm/qcs405/Kconfig b/src/soc/qualcomm/qcs405/Kconfig new file mode 100644 index 0000000..560d988 --- /dev/null +++ b/src/soc/qualcomm/qcs405/Kconfig @@ -0,0 +1,21 @@ + +config SOC_QUALCOMM_QCS405 + bool + default n + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select BOOTBLOCK_CONSOLE + select GENERIC_GPIO_LIB + select GENERIC_UDELAY + select HAVE_MONOTONIC_TIMER + +if SOC_QUALCOMM_QCS405 + +config VBOOT + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_RETURN_FROM_VERSTAGE + select VBOOT_OPROM_MATTERS + select VBOOT_STARTS_IN_BOOTBLOCK +endif diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc new file mode 100644 index 0000000..15f5a0c --- /dev/null +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -0,0 +1,32 @@ + +ifeq ($(CONFIG_SOC_QUALCOMM_QCS405),y) + +################################################################################ +bootblock-y += bootblock.c +bootblock-y += timer.c +bootblock-y += spi.c + +################################################################################ +verstage-y += timer.c +verstage-y += spi.c + +################################################################################ +romstage-y += timer.c +romstage-y += spi.c +romstage-y += cbmem.c + +################################################################################ +ramstage-y += soc.c +ramstage-y += timer.c +ramstage-y += spi.c +ramstage-y += cbmem.c + +################################################################################ + +CPPFLAGS_common += -Isrc/soc/qualcomm/qcs405/include + +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin + @printf "Generating: $(subst $(obj)/,,$(@))\n" + cp $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin + +endif diff --git a/src/soc/qualcomm/qcs405/bootblock.c b/src/soc/qualcomm/qcs405/bootblock.c new file mode 100644 index 0000000..3ed37ae --- /dev/null +++ b/src/soc/qualcomm/qcs405/bootblock.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> + +void bootblock_soc_init(void) +{ + +} diff --git a/src/soc/qualcomm/qcs405/cbmem.c b/src/soc/qualcomm/qcs405/cbmem.c new file mode 100644 index 0000000..3b9ad4a --- /dev/null +++ b/src/soc/qualcomm/qcs405/cbmem.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> + +void *cbmem_top(void) +{ + return (void *)((uintptr_t)4 * GiB); +} diff --git a/src/soc/qualcomm/qcs405/include/soc/gpio.h b/src/soc/qualcomm/qcs405/include/soc/gpio.h new file mode 100644 index 0000000..e1ad453 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/gpio.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_QCS405_GPIO_H_ +#define _SOC_QUALCOMM_QCS405_GPIO_H_ + +#include <types.h> + +typedef u32 gpio_t; + +#endif // _SOC_QUALCOMM_QCS405_GPIO_H_ diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld new file mode 100644 index 0000000..c0f5759 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <memlayout.h> +#include <arch/header.ld> + +/* SYSTEM_IMEM : 0x8600000 - 0x8607FFF */ +#define SSRAM_START(addr) SYMBOL(ssram, addr) +#define SSRAM_END(addr) SYMBOL(essram, addr) + +/* BOOT_IMEM : 0x8C00000 - 0x8D80000 */ +#define BSRAM_START(addr) SYMBOL(bsram, addr) +#define BSRAM_END(addr) SYMBOL(ebsram, addr) + +SECTIONS +{ + SSRAM_START(0x8600000) + SSRAM_END(0x8608000) + + BSRAM_START(0x8C00000) + OVERLAP_VERSTAGE_ROMSTAGE(0x8C00000, 100K) + REGION(fw_reserved2, 0x8C19000, 0x16000, 4096) + BOOTBLOCK(0x8C2F000, 40K) + TTB(0x8C39000, 56K) + VBOOT2_WORK(0x8C47000, 16K) + STACK(0x8C4B000, 16K) + TIMESTAMP(0x8C4F000, 1K) + PRERAM_CBMEM_CONSOLE(0x8C4F400, 32K) + PRERAM_CBFS_CACHE(0x8C57400, 70K) + REGION(bsram_unused, 0x8C68C00, 0xA2400, 0x100) +/* REGION(qclib, 0x8D0B000, 0x80000, 4096) + REGION(dcb, 0x8D8B000, 0x4000, 4096) + REGION(pmic, 0x8D8F000, 0xA000, 4096)*/ + BSRAM_END(0x8D80000) + + DRAM_START(0x90000000) + POSTRAM_CBFS_CACHE(0x90000000, 384K) + RAMSTAGE(0x90800000, 128K) +} diff --git a/src/soc/qualcomm/qcs405/soc.c b/src/soc/qualcomm/qcs405/soc.c new file mode 100644 index 0000000..7870219 --- /dev/null +++ b/src/soc/qualcomm/qcs405/soc.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <timestamp.h> + +static void soc_read_resources(device_t dev) +{ + +} + +static void soc_init(device_t dev) +{ + +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .init = soc_init, +}; + +static void enable_soc_dev(device_t dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_qualcomm_qcs405_ops = { + CHIP_NAME("SOC Qualcomm QCS405") + .enable_dev = enable_soc_dev, +}; diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c new file mode 100644 index 0000000..c04b15d --- /dev/null +++ b/src/soc/qualcomm/qcs405/spi.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <spi-generic.h> +#include <spi_flash.h> + +static int spi_ctrlr_claim_bus(const struct spi_slave *slave) +{ + return 0; +} + +static void spi_ctrlr_release_bus(const struct spi_slave *slave) +{ + +} + +static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, + size_t bytes_out, void *din, size_t bytes_in) +{ + return 0; +} + +static const struct spi_ctrlr spi_ctrlr = { + .claim_bus = spi_ctrlr_claim_bus, + .release_bus = spi_ctrlr_release_bus, + .xfer = spi_ctrlr_xfer, + .max_xfer_size = 65535, +}; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_ctrlr, + .bus_start = 0, + .bus_end = 0, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/qualcomm/qcs405/timer.c b/src/soc/qualcomm/qcs405/timer.c new file mode 100644 index 0000000..8fb84c8 --- /dev/null +++ b/src/soc/qualcomm/qcs405/timer.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <timer.h> +#include <delay.h> + +void timer_monotonic_get(struct mono_time *mt) +{ + +} + +void init_timer(void) +{ + +} -- To view, visit https://review.coreboot.org/c/coreboot/+/29948 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia379cf375e4459ed55cc36cb8a0a92cab18b705e Gerrit-Change-Number: 29948 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: src/soc/intel/braswell: Remove disabled LPE acpi code
by Frans Hendriks (Code Review) 30 Nov '18

30 Nov '18

Hello Patrick Rudolph, build bot (Jenkins), Hannah Williams, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29414 to look at the new patch set (#3). Change subject: src/soc/intel/braswell: Remove disabled LPE acpi code ...................................................................... src/soc/intel/braswell: Remove disabled LPE acpi code The ACPI code for LPE device was included regardless of the availability of the LPE controller. Move the LPE ACPI code to seperate SSDT and hide it when LPE is disabled. BUG=N/A TEST=Intel CherryHill CRB Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/mainboard/google/cyan/Makefile.inc M src/mainboard/google/cyan/acpi/codec_maxim.asl M src/mainboard/google/cyan/acpi/codec_realtek.asl A src/mainboard/google/cyan/ssdtlpe.asl M src/mainboard/intel/strago/Makefile.inc M src/mainboard/intel/strago/acpi/mainboard.asl A src/mainboard/intel/strago/ssdtlpe.asl M src/soc/intel/braswell/acpi/southcluster.asl M src/soc/intel/braswell/include/soc/acpi.h M src/soc/intel/braswell/lpe.c 10 files changed, 157 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/29414/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/29414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73 Gerrit-Change-Number: 29414 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: [Test]: Move {pci, pnp}_devfn_t to <device/pci_ops.h>
by HAOUAS Elyes (Code Review) 30 Nov '18

30 Nov '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29947 Change subject: [Test]: Move {pci,pnp}_devfn_t to <device/pci_ops.h> ...................................................................... [Test]: Move {pci,pnp}_devfn_t to <device/pci_ops.h> Change-Id: I6a3deea676308e2dc703b5e06558b05235191044 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm/armv7/mmu.c M src/arch/arm/include/arch/pci_ops.h M src/arch/arm64/include/arch/pci_ops.h M src/arch/mips/include/arch/pci_ops.h M src/arch/riscv/arch_timer.c M src/arch/x86/cf9_reset.c M src/arch/x86/cpu.c M src/arch/x86/ebda.c M src/arch/x86/include/arch/io.h M src/arch/x86/include/arch/pci_io_cfg.h M src/arch/x86/include/arch/pci_mmio_cfg.h M src/arch/x86/ioapic.c M src/arch/x86/pci_ops_conf1.c M src/commonlib/storage/sdhci.h M src/console/die.c M src/console/post.c M src/cpu/allwinner/a10/clock.c M src/cpu/allwinner/a10/gpio.c M src/cpu/allwinner/a10/pinmux.c M src/cpu/allwinner/a10/raminit.c M src/cpu/allwinner/a10/timer.c M src/cpu/allwinner/a10/twi.c M src/cpu/allwinner/a10/uart.c M src/cpu/amd/family_10h-family_15h/ram_calc.c M src/cpu/amd/geode_lx/cpubug.c M src/cpu/amd/geode_lx/geode_lx_init.c M src/cpu/amd/geode_lx/syspreinit.c M src/cpu/amd/microcode/microcode.c M src/cpu/amd/smm/smm_init.c M src/cpu/intel/fsp_model_406dx/bootblock.c M src/cpu/intel/haswell/bootblock.c M src/cpu/intel/haswell/romstage.c M src/cpu/intel/model_2065x/bootblock.c M src/cpu/intel/model_206ax/bootblock.c M src/cpu/ti/am335x/gpio.c M src/cpu/ti/am335x/pinmux.c M src/cpu/ti/am335x/uart.c M src/cpu/x86/lapic/apic_timer.c M src/cpu/x86/smm/smihandler.c M src/cpu/x86/smm/smm_module_handler.c M src/cpu/x86/tsc/delay_tsc.c M src/device/azalia_device.c M src/device/device.c M src/device/oprom/include/io.h M src/device/oprom/realmode/x86.c M src/device/oprom/realmode/x86_interrupts.c M src/device/oprom/x86emu/sys.c M src/device/oprom/yabel/io.c M src/device/pci_device.c M src/device/pci_early.c M src/device/pci_ops_mmconf.c M src/device/pnp_device.c M src/drivers/aspeed/ast2050/ast2050.c M src/drivers/aspeed/common/aspeed_coreboot.h M src/drivers/elog/gsmi.c M src/drivers/emulation/qemu/bochs.c M src/drivers/emulation/qemu/cirrus.c M src/drivers/emulation/qemu/qemu_debugcon.c M src/drivers/gic/gic.c M src/drivers/i2c/at24rf08c/at24rf08c.c M src/drivers/i2c/at24rf08c/lenovo_serials.c M src/drivers/i2c/designware/dw_i2c.c M src/drivers/intel/fsp1_1/romstage.c M src/drivers/intel/fsp2_0/hand_off_block.c M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/temp_ram_exit.c M src/drivers/intel/fsp2_0/util.c M src/drivers/intel/gma/edid.c M src/drivers/intel/gma/intel_ddi.c M src/drivers/intel/gma/vbt.c M src/drivers/ipmi/ipmi_kcs.c M src/drivers/maxim/max77686/max77686.c M src/drivers/net/ne2k.c M src/drivers/net/r8168.c M src/drivers/pc80/pc/i8254.c M src/drivers/pc80/pc/i8259.c M src/drivers/pc80/pc/isa-dma.c M src/drivers/pc80/pc/keyboard.c M src/drivers/pc80/pc/spkmodem.c M src/drivers/pc80/pc/udelay_io.c M src/drivers/pc80/rtc/mc146818rtc.c M src/drivers/pc80/tpm/tis.c M src/drivers/pc80/vga/vga_io.c M src/drivers/ricoh/rce822/rce822.c M src/drivers/sil/3114/sil_sata.c M src/drivers/uart/oxpcie.c M src/drivers/uart/oxpcie_early.c M src/drivers/uart/pl011.c M src/drivers/uart/sifive.c M src/drivers/uart/uart8250io.c M src/drivers/uart/uart8250mem.c M src/drivers/usb/ehci_debug.c M src/drivers/usb/pci_ehci.c M src/drivers/xgi/common/xgi_coreboot.c M src/drivers/xgi/common/xgi_coreboot.h M src/drivers/xgi/z9s/z9s.c M src/ec/acpi/ec.c M src/ec/compal/ene932/ec.c M src/ec/google/chromeec/crosec_proto.c M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec_i2c.c M src/ec/google/chromeec/ec_lpc.c M src/ec/google/common/mec.c M src/ec/google/wilco/bootblock.c M src/ec/google/wilco/mailbox.c M src/ec/hp/kbc1126/early_init.c M src/ec/hp/kbc1126/ec.c M src/ec/lenovo/h8/h8.c M src/ec/lenovo/pmh7/pmh7.c M src/ec/quanta/ene_kb3940q/ec.c M src/ec/quanta/it8518/ec.c M src/ec/smsc/mec1308/ec.c M src/include/device/azalia_device.h M src/include/device/device.h M src/include/device/pci.h M src/include/device/pci_ehci.h M src/include/device/pnp.h M src/include/pc80/mc146818rtc.h M src/include/reg_script.h M src/lib/edid.c M src/lib/reg_script.c M src/mainboard/adi/rcc-dff/romstage.c M src/mainboard/advansus/a785e-i/mainboard.c M src/mainboard/advansus/a785e-i/mptable.c M src/mainboard/advansus/a785e-i/romstage.c M src/mainboard/amd/bettong/boardid.c M src/mainboard/amd/bettong/mptable.c M src/mainboard/amd/bettong/romstage.c M src/mainboard/amd/bimini_fam10/mainboard.c M src/mainboard/amd/bimini_fam10/mptable.c M src/mainboard/amd/bimini_fam10/romstage.c M src/mainboard/amd/db-ft3b-lc/mainboard.c M src/mainboard/amd/db-ft3b-lc/mptable.c M src/mainboard/amd/db-ft3b-lc/romstage.c M src/mainboard/amd/gardenia/mptable.c M src/mainboard/amd/inagua/mptable.c M src/mainboard/amd/lamar/mainboard.c M src/mainboard/amd/lamar/mptable.c M src/mainboard/amd/lamar/romstage.c M src/mainboard/amd/mahogany_fam10/mainboard.c M src/mainboard/amd/mahogany_fam10/mptable.c M src/mainboard/amd/mahogany_fam10/romstage.c M src/mainboard/amd/olivehill/mptable.c M src/mainboard/amd/olivehill/romstage.c M src/mainboard/amd/olivehillplus/mainboard.c M src/mainboard/amd/olivehillplus/mptable.c M src/mainboard/amd/olivehillplus/romstage.c M src/mainboard/amd/parmer/mptable.c M src/mainboard/amd/parmer/romstage.c M src/mainboard/amd/persimmon/mainboard.c M src/mainboard/amd/persimmon/mptable.c M src/mainboard/amd/serengeti_cheetah_fam10/romstage.c M src/mainboard/amd/south_station/mptable.c M src/mainboard/amd/thatcher/mptable.c M src/mainboard/amd/thatcher/romstage.c M src/mainboard/amd/tilapia_fam10/mainboard.c M src/mainboard/amd/tilapia_fam10/mptable.c M src/mainboard/amd/tilapia_fam10/romstage.c M src/mainboard/amd/torpedo/acpi_tables.c M src/mainboard/amd/torpedo/fadt.c M src/mainboard/amd/torpedo/mptable.c M src/mainboard/amd/union_station/mptable.c M src/mainboard/aopen/dxplplusu/romstage.c M src/mainboard/apple/macbook21/mainboard.c M src/mainboard/apple/macbook21/romstage.c M src/mainboard/apple/macbook21/smihandler.c M src/mainboard/apple/macbookair4_2/early_southbridge.c M src/mainboard/asrock/e350m1/mainboard.c M src/mainboard/asrock/e350m1/mptable.c M src/mainboard/asrock/imb-a180/mptable.c M src/mainboard/asrock/imb-a180/romstage.c M src/mainboard/asus/am1i-a/mptable.c M src/mainboard/asus/am1i-a/romstage.c M src/mainboard/asus/f2a85-m/mptable.c M src/mainboard/asus/f2a85-m/romstage.c M src/mainboard/asus/kcma-d8/bootblock.c M src/mainboard/asus/kcma-d8/mainboard.c M src/mainboard/asus/kcma-d8/mptable.c M src/mainboard/asus/kcma-d8/romstage.c M src/mainboard/asus/kfsn4-dre/acpi_tables.c M src/mainboard/asus/kfsn4-dre/romstage.c M src/mainboard/asus/kgpe-d16/bootblock.c M src/mainboard/asus/kgpe-d16/mainboard.c M src/mainboard/asus/kgpe-d16/mptable.c M src/mainboard/asus/kgpe-d16/romstage.c M src/mainboard/asus/m4a78-em/mainboard.c M src/mainboard/asus/m4a78-em/mptable.c M src/mainboard/asus/m4a78-em/romstage.c M src/mainboard/asus/m4a785-m/mainboard.c M src/mainboard/asus/m4a785-m/mptable.c M src/mainboard/asus/m4a785-m/romstage.c M src/mainboard/asus/m5a88-v/mainboard.c M src/mainboard/asus/m5a88-v/mptable.c M src/mainboard/asus/m5a88-v/romstage.c M src/mainboard/asus/maximus_iv_gene-z/romstage.c M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/asus/p5qc/romstage.c M src/mainboard/asus/p8h61-m_lx/romstage.c M src/mainboard/avalue/eax-785e/mainboard.c M src/mainboard/avalue/eax-785e/mptable.c M src/mainboard/avalue/eax-785e/romstage.c M src/mainboard/bap/ode_e20XX/mptable.c M src/mainboard/bap/ode_e20XX/romstage.c M src/mainboard/bap/ode_e21XX/mainboard.c M src/mainboard/bap/ode_e21XX/mptable.c M src/mainboard/bap/ode_e21XX/romstage.c M src/mainboard/biostar/a68n_5200/mptable.c M src/mainboard/biostar/a68n_5200/romstage.c M src/mainboard/biostar/am1ml/mptable.c M src/mainboard/biostar/am1ml/romstage.c M src/mainboard/compulab/intense_pc/romstage.c M src/mainboard/cubietech/cubieboard/bootblock.c M src/mainboard/elmex/pcm205400/mainboard.c M src/mainboard/elmex/pcm205400/mptable.c M src/mainboard/emulation/qemu-armv7/cbmem.c M src/mainboard/emulation/qemu-armv7/mainboard.c M src/mainboard/emulation/qemu-i440fx/fw_cfg.c M src/mainboard/emulation/qemu-i440fx/memory.c M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/mainboard/emulation/qemu-power8/uart.c M src/mainboard/emulation/qemu-q35/bootblock.c M src/mainboard/emulation/qemu-riscv/uart.c M src/mainboard/emulation/spike-riscv/uart.c M src/mainboard/foxconn/d41s/romstage.c M src/mainboard/getac/p470/ec_oem.c M src/mainboard/getac/p470/mainboard.c M src/mainboard/getac/p470/romstage.c M src/mainboard/getac/p470/smihandler.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c M src/mainboard/gigabyte/ma785gm/mainboard.c M src/mainboard/gigabyte/ma785gm/mptable.c M src/mainboard/gigabyte/ma785gm/romstage.c M src/mainboard/gigabyte/ma785gmt/mainboard.c M src/mainboard/gigabyte/ma785gmt/mptable.c M src/mainboard/gigabyte/ma785gmt/romstage.c M src/mainboard/gigabyte/ma78gm/mainboard.c M src/mainboard/gigabyte/ma78gm/mptable.c M src/mainboard/gigabyte/ma78gm/romstage.c M src/mainboard/gizmosphere/gizmo/mainboard.c M src/mainboard/gizmosphere/gizmo/mptable.c M src/mainboard/gizmosphere/gizmo2/mptable.c M src/mainboard/gizmosphere/gizmo2/romstage.c M src/mainboard/google/auron/smihandler.c M src/mainboard/google/auron/variant.h M src/mainboard/google/auron/variants/buddy/variant.c M src/mainboard/google/beltino/chromeos.c M src/mainboard/google/beltino/lan.c M src/mainboard/google/beltino/mainboard.c M src/mainboard/google/beltino/smihandler.c M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/butterfly/mainboard.c M src/mainboard/google/butterfly/mainboard_smi.c M src/mainboard/google/butterfly/romstage.c M src/mainboard/google/cyan/chromeos.c M src/mainboard/google/cyan/com_init.c M src/mainboard/google/cyan/smihandler.c M src/mainboard/google/eve/smihandler.c M src/mainboard/google/foster/bootblock.c M src/mainboard/google/foster/mainboard.c M src/mainboard/google/foster/reset.c M src/mainboard/google/glados/smihandler.c M src/mainboard/google/gru/bootblock.c M src/mainboard/google/gru/pwm_regulator.c M src/mainboard/google/gru/sdram_configs.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/jecht/lan.c M src/mainboard/google/jecht/mainboard.c M src/mainboard/google/jecht/smihandler.c M src/mainboard/google/kahlee/mainboard.c M src/mainboard/google/kahlee/mptable.c M src/mainboard/google/link/i915.c M src/mainboard/google/link/mainboard.c M src/mainboard/google/link/mainboard_smi.c M src/mainboard/google/link/romstage.c M src/mainboard/google/nyan/bootblock.c M src/mainboard/google/nyan/mainboard.c M src/mainboard/google/nyan/romstage.c M src/mainboard/google/nyan_big/bootblock.c M src/mainboard/google/nyan_big/mainboard.c M src/mainboard/google/nyan_big/romstage.c M src/mainboard/google/nyan_blaze/bootblock.c M src/mainboard/google/nyan_blaze/mainboard.c M src/mainboard/google/nyan_blaze/romstage.c M src/mainboard/google/oak/bootblock.c M src/mainboard/google/oak/mainboard.c M src/mainboard/google/octopus/ec.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/parrot/ec.c M src/mainboard/google/parrot/mainboard.c M src/mainboard/google/parrot/romstage.c M src/mainboard/google/parrot/smihandler.c M src/mainboard/google/rambi/mainboard.c M src/mainboard/google/rambi/mainboard_smi.c M src/mainboard/google/rambi/variants/ninja/lan.c M src/mainboard/google/rambi/variants/sumo/lan.c M src/mainboard/google/slippy/mainboard.c M src/mainboard/google/slippy/smihandler.c M src/mainboard/google/smaug/bootblock.c M src/mainboard/google/smaug/mainboard.c M src/mainboard/google/smaug/reset.c M src/mainboard/google/stout/chromeos.c M src/mainboard/google/stout/ec.c M src/mainboard/google/stout/mainboard.c M src/mainboard/google/stout/mainboard_smi.c M src/mainboard/google/stout/romstage.c M src/mainboard/google/urara/bootblock.c M src/mainboard/google/urara/mainboard.c M src/mainboard/google/veyron/bootblock.c M src/mainboard/google/veyron/mainboard.c M src/mainboard/google/veyron/sdram_configs.c M src/mainboard/google/veyron_mickey/bootblock.c M src/mainboard/google/veyron_mickey/mainboard.c M src/mainboard/google/veyron_mickey/sdram_configs.c M src/mainboard/google/veyron_rialto/bootblock.c M src/mainboard/google/veyron_rialto/mainboard.c M src/mainboard/google/veyron_rialto/romstage.c M src/mainboard/google/veyron_rialto/sdram_configs.c M src/mainboard/hp/2570p/romstage.c M src/mainboard/hp/2760p/romstage.c M src/mainboard/hp/8460p/romstage.c M src/mainboard/hp/8470p/romstage.c M src/mainboard/hp/8770w/romstage.c M src/mainboard/hp/abm/mptable.c M src/mainboard/hp/abm/romstage.c M src/mainboard/hp/compaq_8200_elite_sff/romstage.c M src/mainboard/hp/dl165_g6_fam10/mptable.c M src/mainboard/hp/dl165_g6_fam10/romstage.c M src/mainboard/hp/folio_9470m/romstage.c M src/mainboard/hp/pavilion_m6_1035dx/mainboard.c M src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c M src/mainboard/hp/pavilion_m6_1035dx/mptable.c M src/mainboard/hp/revolve_810_g1/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/ibase/mb899/superio_hwm.c M src/mainboard/iei/kino-780am2-fam10/mainboard.c M src/mainboard/iei/kino-780am2-fam10/mptable.c M src/mainboard/iei/kino-780am2-fam10/romstage.c M src/mainboard/intel/baskingridge/chromeos.c M src/mainboard/intel/baskingridge/mainboard.c M src/mainboard/intel/baskingridge/mainboard_smi.c M src/mainboard/intel/bayleybay_fsp/mainboard.c M src/mainboard/intel/bayleybay_fsp/romstage.c M src/mainboard/intel/camelbackmountain_fsp/mainboard.c M src/mainboard/intel/cannonlake_rvp/smihandler.c M src/mainboard/intel/d510mo/romstage.c M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/intel/dcp847ske/early_southbridge.c M src/mainboard/intel/dcp847ske/superio.h M src/mainboard/intel/dg43gt/romstage.c M src/mainboard/intel/emeraldlake2/chromeos.c M src/mainboard/intel/emeraldlake2/mainboard.c M src/mainboard/intel/emeraldlake2/romstage.c M src/mainboard/intel/emeraldlake2/smihandler.c M src/mainboard/intel/galileo/gpio.c M src/mainboard/intel/galileo/reg_access.c M src/mainboard/intel/glkrvp/ec.c M src/mainboard/intel/kblrvp/chromeos.c M src/mainboard/intel/kblrvp/smihandler.c M src/mainboard/intel/kunimitsu/smihandler.c M src/mainboard/intel/littleplains/romstage.c M src/mainboard/intel/mohonpeak/romstage.c M src/mainboard/intel/strago/com_init.c M src/mainboard/intel/strago/smihandler.c M src/mainboard/intel/wtm2/chromeos.c M src/mainboard/intel/wtm2/mainboard.c M src/mainboard/jetway/nf81-t56n-lf/mainboard.c M src/mainboard/jetway/nf81-t56n-lf/mptable.c M src/mainboard/jetway/pa78vm5/mainboard.c M src/mainboard/jetway/pa78vm5/mptable.c M src/mainboard/jetway/pa78vm5/romstage.c M src/mainboard/kontron/986lcd-m/mainboard.c M src/mainboard/kontron/ktqm77/mainboard.c M src/mainboard/lenovo/g505s/mainboard_smi.c M src/mainboard/lenovo/g505s/mptable.c M src/mainboard/lenovo/l520/romstage.c M src/mainboard/lenovo/l520/smihandler.c M src/mainboard/lenovo/s230u/mainboard.c M src/mainboard/lenovo/s230u/romstage.c M src/mainboard/lenovo/s230u/smihandler.c M src/mainboard/lenovo/t400/acpi_tables.c M src/mainboard/lenovo/t400/dock.c M src/mainboard/lenovo/t400/romstage.c M src/mainboard/lenovo/t420/romstage.c M src/mainboard/lenovo/t420/smihandler.c M src/mainboard/lenovo/t420s/romstage.c M src/mainboard/lenovo/t420s/smihandler.c M src/mainboard/lenovo/t430/romstage.c M src/mainboard/lenovo/t430/smihandler.c M src/mainboard/lenovo/t430s/romstage.c M src/mainboard/lenovo/t430s/smihandler.c M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t520/smihandler.c M src/mainboard/lenovo/t530/romstage.c M src/mainboard/lenovo/t530/smihandler.c M src/mainboard/lenovo/t60/dock.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/t60/smihandler.c M src/mainboard/lenovo/x131e/romstage.c M src/mainboard/lenovo/x1_carbon_gen1/romstage.c M src/mainboard/lenovo/x1_carbon_gen1/smihandler.c M src/mainboard/lenovo/x200/acpi_tables.c M src/mainboard/lenovo/x200/dock.c M src/mainboard/lenovo/x200/romstage.c M src/mainboard/lenovo/x201/dock.c M src/mainboard/lenovo/x201/mainboard.c M src/mainboard/lenovo/x201/romstage.c M src/mainboard/lenovo/x201/smihandler.c M src/mainboard/lenovo/x220/romstage.c M src/mainboard/lenovo/x220/smihandler.c M src/mainboard/lenovo/x230/romstage.c M src/mainboard/lenovo/x230/smihandler.c M src/mainboard/lenovo/x60/dock.c M src/mainboard/lenovo/x60/mainboard.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/lenovo/x60/smihandler.c M src/mainboard/lenovo/z61t/dock.c M src/mainboard/lenovo/z61t/romstage.c M src/mainboard/lenovo/z61t/smihandler.c M src/mainboard/lippert/frontrunner-af/mainboard.c M src/mainboard/lippert/frontrunner-af/mptable.c M src/mainboard/lippert/frontrunner-af/sema.c M src/mainboard/lippert/toucan-af/mainboard.c M src/mainboard/lippert/toucan-af/mptable.c M src/mainboard/msi/ms7721/mptable.c M src/mainboard/msi/ms7721/romstage.c M src/mainboard/msi/ms9652_fam10/romstage.c M src/mainboard/packardbell/ms2290/mainboard.c M src/mainboard/packardbell/ms2290/romstage.c M src/mainboard/pcengines/alix1c/romstage.c M src/mainboard/pcengines/alix2d/irq_tables.c M src/mainboard/pcengines/alix2d/romstage.c M src/mainboard/pcengines/apu1/gpio_ftns.c M src/mainboard/pcengines/apu1/mainboard.c M src/mainboard/pcengines/apu1/mptable.c M src/mainboard/pcengines/apu2/gpio_ftns.c M src/mainboard/pcengines/apu2/mainboard.c M src/mainboard/pcengines/apu2/romstage.c M src/mainboard/roda/rk886ex/m3885.c M src/mainboard/roda/rk886ex/mainboard.c M src/mainboard/roda/rk886ex/romstage.c M src/mainboard/roda/rk9/acpi_tables.c M src/mainboard/roda/rk9/mainboard.c M src/mainboard/roda/rk9/romstage.c M src/mainboard/roda/rk9/smihandler.c M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/samsung/lumpy/smihandler.c M src/mainboard/samsung/stumpy/chromeos.c M src/mainboard/samsung/stumpy/romstage.c M src/mainboard/samsung/stumpy/smihandler.c M src/mainboard/sapphire/pureplatinumh61/romstage.c M src/mainboard/siemens/mc_bdx1/mainboard.c M src/mainboard/siemens/mc_tcu3/mainboard.c M src/mainboard/siemens/mc_tcu3/romstage.c M src/mainboard/sifive/hifive-unleashed/mainboard.c M src/mainboard/supermicro/h8dmr_fam10/romstage.c M src/mainboard/supermicro/h8qme_fam10/romstage.c M src/mainboard/supermicro/h8scm_fam10/mainboard.c M src/mainboard/supermicro/h8scm_fam10/mptable.c M src/mainboard/supermicro/h8scm_fam10/romstage.c M src/mainboard/ti/beaglebone/bootblock.c M src/mainboard/tyan/s2912_fam10/romstage.c M src/mainboard/via/epia-m850/romstage.c M src/northbridge/amd/agesa/family12/northbridge.c M src/northbridge/amd/agesa/family14/northbridge.c M src/northbridge/amd/agesa/family14/state_machine.c M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c M src/northbridge/amd/amdfam10/amdfam10.h M src/northbridge/amd/amdfam10/amdfam10_util.c M src/northbridge/amd/amdfam10/debug.c M src/northbridge/amd/amdfam10/early_ht.c M src/northbridge/amd/amdfam10/ht_config.c M src/northbridge/amd/amdfam10/northbridge.c M src/northbridge/amd/amdfam10/pci.h M src/northbridge/amd/amdfam10/raminit_amdmct.c M src/northbridge/amd/amdk8/reset_test.c M src/northbridge/amd/lx/grphinit.c M src/northbridge/amd/lx/northbridge.c M src/northbridge/amd/lx/northbridgeinit.c M src/northbridge/amd/lx/raminit.c M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/amd/pi/ramtop.c M src/northbridge/intel/e7505/debug.c M src/northbridge/intel/e7505/memmap.c M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/e7505/raminit.c M src/northbridge/intel/fsp_rangeley/acpi.c M src/northbridge/intel/fsp_rangeley/northbridge.c M src/northbridge/intel/fsp_rangeley/port_access.c M src/northbridge/intel/fsp_rangeley/raminit.c M src/northbridge/intel/gm45/bootblock.c M src/northbridge/intel/gm45/early_init.c M src/northbridge/intel/gm45/early_reset.c M src/northbridge/intel/gm45/gma.c M src/northbridge/intel/gm45/igd.c M src/northbridge/intel/gm45/iommu.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/gm45/pcie.c M src/northbridge/intel/gm45/pm.c M src/northbridge/intel/gm45/ram_calc.c M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/gm45/raminit_read_write_training.c M src/northbridge/intel/gm45/raminit_receive_enable_calibration.c M src/northbridge/intel/gm45/thermal.c M src/northbridge/intel/haswell/bootblock.c M src/northbridge/intel/haswell/early_init.c M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/minihd.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/haswell/ram_calc.c M src/northbridge/intel/haswell/raminit.c M src/northbridge/intel/haswell/report_platform.c M src/northbridge/intel/i440bx/debug.c M src/northbridge/intel/i440bx/northbridge.c M src/northbridge/intel/i440bx/ram_calc.c M src/northbridge/intel/i440bx/raminit.c M src/northbridge/intel/i945/bootblock.c M src/northbridge/intel/i945/debug.c M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/i945/ram_calc.c M src/northbridge/intel/i945/rcven.c M src/northbridge/intel/nehalem/bootblock.c M src/northbridge/intel/nehalem/early_init.c M src/northbridge/intel/nehalem/finalize.c M src/northbridge/intel/nehalem/gma.c M src/northbridge/intel/nehalem/northbridge.c M src/northbridge/intel/nehalem/ram_calc.c M src/northbridge/intel/nehalem/raminit.c M src/northbridge/intel/pineview/bootblock.c M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/pineview/gma.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/pineview/ram_calc.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/sandybridge/bootblock.c M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/sandybridge/finalize.c M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c M src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c M src/northbridge/intel/sandybridge/iommu.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/ram_calc.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_ivy.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/romstage.c M src/northbridge/intel/x4x/bootblock.c M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/intel/x4x/early_init.c M src/northbridge/intel/x4x/gma.c M src/northbridge/intel/x4x/northbridge.c M src/northbridge/intel/x4x/ram_calc.c M src/northbridge/intel/x4x/raminit.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/northbridge/intel/x4x/raminit_tables.c M src/northbridge/intel/x4x/rcven.c M src/northbridge/via/vx900/bootblock.c M src/northbridge/via/vx900/chrome9hd.c M src/northbridge/via/vx900/early_smbus.c M src/northbridge/via/vx900/early_vx900.c M src/northbridge/via/vx900/early_vx900.h M src/northbridge/via/vx900/lpc.c M src/northbridge/via/vx900/pcie.c M src/northbridge/via/vx900/raminit_ddr3.c M src/northbridge/via/vx900/vx900.h M src/soc/amd/common/block/pci/amd_pci_util.c M src/soc/amd/common/block/psp/psp.c M src/soc/amd/stoneyridge/acpi.c M src/soc/amd/stoneyridge/enable_usbdebug.c M src/soc/amd/stoneyridge/gpio.c M src/soc/amd/stoneyridge/hda.c M src/soc/amd/stoneyridge/include/soc/northbridge.h M src/soc/amd/stoneyridge/include/soc/pci_devs.h M src/soc/amd/stoneyridge/include/soc/smi.h M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/lpc.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/ramtop.c M src/soc/amd/stoneyridge/reset.c M src/soc/amd/stoneyridge/romstage.c M src/soc/amd/stoneyridge/sata.c M src/soc/amd/stoneyridge/sm.c M src/soc/amd/stoneyridge/southbridge.c M src/soc/amd/stoneyridge/spi.c M src/soc/amd/stoneyridge/tsc_freq.c M src/soc/amd/stoneyridge/usb.c M src/soc/broadcom/cygnus/gpio.c M src/soc/broadcom/cygnus/hw_init.c M src/soc/broadcom/cygnus/i2c.c M src/soc/broadcom/cygnus/iomux.c M src/soc/broadcom/cygnus/ns16550.c M src/soc/broadcom/cygnus/spi.c M src/soc/broadcom/cygnus/timer.c M src/soc/broadcom/cygnus/tz.c M src/soc/broadcom/cygnus/usb.c M src/soc/cavium/cn81xx/bootblock.c M src/soc/cavium/cn81xx/clock.c M src/soc/cavium/cn81xx/cpu.c M src/soc/cavium/cn81xx/ecam0.c M src/soc/cavium/cn81xx/gpio.c M src/soc/cavium/cn81xx/spi.c M src/soc/cavium/cn81xx/timer.c M src/soc/cavium/cn81xx/twsi.c M src/soc/cavium/cn81xx/uart.c M src/soc/cavium/common/bdk-coreboot.c M src/soc/imgtec/pistachio/clocks.c M src/soc/imgtec/pistachio/ddr2_init.c M src/soc/imgtec/pistachio/ddr3_init.c M src/soc/imgtec/pistachio/include/soc/cpu.h M src/soc/imgtec/pistachio/include/soc/spi.h M src/soc/imgtec/pistachio/reset.c M src/soc/imgtec/pistachio/uart.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/cse.c M src/soc/intel/apollolake/include/soc/pci_devs.h M src/soc/intel/apollolake/memmap.c M src/soc/intel/apollolake/pmutil.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/apollolake/smihandler.c M src/soc/intel/apollolake/xdci.c M src/soc/intel/baytrail/acpi.c M src/soc/intel/baytrail/bootblock/bootblock.c M src/soc/intel/baytrail/dptf.c M src/soc/intel/baytrail/elog.c M src/soc/intel/baytrail/emmc.c M src/soc/intel/baytrail/gfx.c M src/soc/intel/baytrail/hda.c M src/soc/intel/baytrail/include/soc/gpio.h M src/soc/intel/baytrail/iosf.c M src/soc/intel/baytrail/lpe.c M src/soc/intel/baytrail/lpss.c M src/soc/intel/baytrail/memmap.c M src/soc/intel/baytrail/perf_power.c M src/soc/intel/baytrail/pmutil.c M src/soc/intel/baytrail/romstage/early_spi.c M src/soc/intel/baytrail/romstage/gfx.c M src/soc/intel/baytrail/romstage/pmc.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/baytrail/romstage/uart.c M src/soc/intel/baytrail/sata.c M src/soc/intel/baytrail/sd.c M src/soc/intel/baytrail/smihandler.c M src/soc/intel/baytrail/smm.c M src/soc/intel/baytrail/southcluster.c M src/soc/intel/baytrail/spi.c M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/bootblock/bootblock.c M src/soc/intel/braswell/elog.c M src/soc/intel/braswell/emmc.c M src/soc/intel/braswell/gfx.c M src/soc/intel/braswell/hda.c M src/soc/intel/braswell/include/soc/gpio.h M src/soc/intel/braswell/iosf.c M src/soc/intel/braswell/lpe.c M src/soc/intel/braswell/lpss.c M src/soc/intel/braswell/memmap.c M src/soc/intel/braswell/pmutil.c M src/soc/intel/braswell/romstage/early_spi.c M src/soc/intel/braswell/romstage/pmc.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/braswell/sata.c M src/soc/intel/braswell/sd.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/braswell/smm.c M src/soc/intel/braswell/southcluster.c M src/soc/intel/braswell/spi.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/adsp.c M src/soc/intel/broadwell/bootblock/cpu.c M src/soc/intel/broadwell/bootblock/pch.c M src/soc/intel/broadwell/bootblock/systemagent.c M src/soc/intel/broadwell/ehci.c M src/soc/intel/broadwell/finalize.c M src/soc/intel/broadwell/gpio.c M src/soc/intel/broadwell/hda.c M src/soc/intel/broadwell/igd.c M src/soc/intel/broadwell/include/soc/pci_devs.h M src/soc/intel/broadwell/iobp.c M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/me.c M src/soc/intel/broadwell/me_status.c M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/minihd.c M src/soc/intel/broadwell/pch.c M src/soc/intel/broadwell/pmutil.c M src/soc/intel/broadwell/romstage/pch.c M src/soc/intel/broadwell/romstage/power_state.c M src/soc/intel/broadwell/romstage/raminit.c M src/soc/intel/broadwell/romstage/report_platform.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/broadwell/romstage/smbus.c M src/soc/intel/broadwell/romstage/spi.c M src/soc/intel/broadwell/romstage/systemagent.c M src/soc/intel/broadwell/romstage/uart.c M src/soc/intel/broadwell/sata.c M src/soc/intel/broadwell/serialio.c M src/soc/intel/broadwell/smbus.c M src/soc/intel/broadwell/smbus_common.c M src/soc/intel/broadwell/smi.c M src/soc/intel/broadwell/smihandler.c M src/soc/intel/broadwell/spi.c M src/soc/intel/broadwell/systemagent.c M src/soc/intel/broadwell/usb_debug.c M src/soc/intel/broadwell/xhci.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/include/soc/pci_devs.h M src/soc/intel/cannonlake/include/soc/pm.h M src/soc/intel/cannonlake/lockdown.c M src/soc/intel/cannonlake/lpc.c M src/soc/intel/cannonlake/memmap.c M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/cannonlake/romstage/power_state.c M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/fast_spi/fast_spi_flash.c M src/soc/intel/common/block/gspi/gspi.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/include/intelblocks/smihandler.h M src/soc/intel/common/block/include/intelblocks/uart.h M src/soc/intel/common/block/lpss/lpss.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcr/pcr.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/common/block/smbus/smbus_early.c M src/soc/intel/common/block/smbus/smbuslib.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/common/block/smm/smitraphandler.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/systemagent/systemagent_early.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/common/hda_verb.c M src/soc/intel/common/pch/lockdown/lockdown.c M src/soc/intel/denverton_ns/bootblock/uart.c M src/soc/intel/denverton_ns/gpio_dnv.c M src/soc/intel/denverton_ns/include/soc/pci_devs.h M src/soc/intel/denverton_ns/include/soc/pm.h M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/denverton_ns/npk.c M src/soc/intel/denverton_ns/pmc.c M src/soc/intel/denverton_ns/pmutil.c M src/soc/intel/denverton_ns/sata.c M src/soc/intel/denverton_ns/smihandler.c M src/soc/intel/denverton_ns/smm.c M src/soc/intel/denverton_ns/soc_util.c M src/soc/intel/denverton_ns/systemagent.c M src/soc/intel/denverton_ns/xhci.c M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/fsp_baytrail/bootblock/bootblock.c M src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c M src/soc/intel/fsp_baytrail/gfx.c M src/soc/intel/fsp_baytrail/include/soc/gpio.h M src/soc/intel/fsp_baytrail/include/soc/i2c.h M src/soc/intel/fsp_baytrail/iosf.c M src/soc/intel/fsp_baytrail/lpe.c M src/soc/intel/fsp_baytrail/lpss.c M src/soc/intel/fsp_baytrail/memmap.c M src/soc/intel/fsp_baytrail/pmutil.c M src/soc/intel/fsp_baytrail/romstage/pmc.c M src/soc/intel/fsp_baytrail/romstage/report_platform.c M src/soc/intel/fsp_baytrail/romstage/romstage.c M src/soc/intel/fsp_baytrail/romstage/uart.c M src/soc/intel/fsp_baytrail/smihandler.c M src/soc/intel/fsp_baytrail/smm.c M src/soc/intel/fsp_baytrail/southcluster.c M src/soc/intel/fsp_baytrail/spi.c M src/soc/intel/fsp_broadwell_de/acpi.c M src/soc/intel/fsp_broadwell_de/gpio.c M src/soc/intel/fsp_broadwell_de/pmutil.c M src/soc/intel/fsp_broadwell_de/romstage/romstage.c M src/soc/intel/fsp_broadwell_de/smbus.c M src/soc/intel/fsp_broadwell_de/smbus_common.c M src/soc/intel/fsp_broadwell_de/smi.c M src/soc/intel/fsp_broadwell_de/smihandler.c M src/soc/intel/fsp_broadwell_de/smmrelocate.c M src/soc/intel/fsp_broadwell_de/southcluster.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/bootblock/report_platform.c M src/soc/intel/icelake/finalize.c M src/soc/intel/icelake/include/soc/pci_devs.h M src/soc/intel/icelake/include/soc/pm.h M src/soc/intel/icelake/lockdown.c M src/soc/intel/icelake/lpc.c M src/soc/intel/icelake/memmap.c M src/soc/intel/icelake/pmutil.c M src/soc/intel/icelake/romstage/power_state.c M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/quark/include/soc/reg_access.h M src/soc/intel/quark/sd.c M src/soc/intel/quark/spi.c M src/soc/intel/quark/spi_debug.c M src/soc/intel/quark/storage_test.c M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/skylake/bootblock/report_platform.c M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/finalize.c M src/soc/intel/skylake/include/soc/pci_devs.h M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/lockdown.c M src/soc/intel/skylake/lpc.c M src/soc/intel/skylake/me.c M src/soc/intel/skylake/memmap.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/soc/intel/skylake/systemagent.c M src/soc/intel/skylake/thermal.c M src/soc/intel/skylake/vr_config.c M src/soc/mediatek/common/gpio.c M src/soc/mediatek/common/include/soc/pmic_wrap_common.h M src/soc/mediatek/common/mtcmos.c M src/soc/mediatek/common/pll.c M src/soc/mediatek/common/pmic_wrap.c M src/soc/mediatek/common/spi.c M src/soc/mediatek/common/timer.c M src/soc/mediatek/common/uart.c M src/soc/mediatek/common/usb.c M src/soc/mediatek/common/wdt.c M src/soc/mediatek/mt8173/ddp.c M src/soc/mediatek/mt8173/dramc_pi_basic_api.c M src/soc/mediatek/mt8173/dramc_pi_calibration_api.c M src/soc/mediatek/mt8173/dsi.c M src/soc/mediatek/mt8173/emi.c M src/soc/mediatek/mt8173/flash_controller.c M src/soc/mediatek/mt8173/gpio.c M src/soc/mediatek/mt8173/gpio_init.c M src/soc/mediatek/mt8173/i2c.c M src/soc/mediatek/mt8173/memory.c M src/soc/mediatek/mt8173/mmu_operations.c M src/soc/mediatek/mt8173/mt6391.c M src/soc/mediatek/mt8173/pll.c M src/soc/mediatek/mt8173/pmic_wrap.c M src/soc/mediatek/mt8173/spi.c M src/soc/mediatek/mt8173/timer.c M src/soc/mediatek/mt8183/auxadc.c M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/gpio.c M src/soc/mediatek/mt8183/mmu_operations.c M src/soc/mediatek/mt8183/mtcmos.c M src/soc/mediatek/mt8183/pll.c M src/soc/mediatek/mt8183/pmic_wrap.c M src/soc/mediatek/mt8183/spi.c M src/soc/nvidia/tegra/apbmisc.c M src/soc/nvidia/tegra/gpio.c M src/soc/nvidia/tegra/i2c.c M src/soc/nvidia/tegra/pingroup.c M src/soc/nvidia/tegra/pinmux.c M src/soc/nvidia/tegra/usb.c M src/soc/nvidia/tegra124/clock.c M src/soc/nvidia/tegra124/display.c M src/soc/nvidia/tegra124/dma.c M src/soc/nvidia/tegra124/dp.c M src/soc/nvidia/tegra124/include/soc/clock.h M src/soc/nvidia/tegra124/monotonic_timer.c M src/soc/nvidia/tegra124/power.c M src/soc/nvidia/tegra124/sdram.c M src/soc/nvidia/tegra124/soc.c M src/soc/nvidia/tegra124/sor.c M src/soc/nvidia/tegra124/spi.c M src/soc/nvidia/tegra124/uart.c M src/soc/nvidia/tegra210/addressmap.c M src/soc/nvidia/tegra210/ccplex.c M src/soc/nvidia/tegra210/clock.c M src/soc/nvidia/tegra210/cpu.c M src/soc/nvidia/tegra210/dc.c M src/soc/nvidia/tegra210/dma.c M src/soc/nvidia/tegra210/dp.c M src/soc/nvidia/tegra210/dsi.c M src/soc/nvidia/tegra210/flow_ctrl.c M src/soc/nvidia/tegra210/funitcfg.c M src/soc/nvidia/tegra210/include/soc/clock.h M src/soc/nvidia/tegra210/include/soc/id.h M src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.c M src/soc/nvidia/tegra210/mipi-phy.c M src/soc/nvidia/tegra210/mipi.c M src/soc/nvidia/tegra210/mipi_dsi.c M src/soc/nvidia/tegra210/monotonic_timer.c M src/soc/nvidia/tegra210/padconfig.c M src/soc/nvidia/tegra210/power.c M src/soc/nvidia/tegra210/ram_code.c M src/soc/nvidia/tegra210/sdram.c M src/soc/nvidia/tegra210/soc.c M src/soc/nvidia/tegra210/sor.c M src/soc/nvidia/tegra210/spi.c M src/soc/nvidia/tegra210/uart.c M src/soc/qualcomm/ipq40xx/blobs_init.c M src/soc/qualcomm/ipq40xx/gpio.c M src/soc/qualcomm/ipq40xx/i2c.c M src/soc/qualcomm/ipq40xx/include/soc/iomap.h M src/soc/qualcomm/ipq40xx/lcc.c M src/soc/qualcomm/ipq40xx/qup.c M src/soc/qualcomm/ipq40xx/spi.c M src/soc/qualcomm/ipq40xx/uart.c M src/soc/qualcomm/ipq40xx/usb.c M src/soc/qualcomm/ipq806x/blobs_init.c M src/soc/qualcomm/ipq806x/gpio.c M src/soc/qualcomm/ipq806x/gsbi.c M src/soc/qualcomm/ipq806x/i2c.c M src/soc/qualcomm/ipq806x/include/soc/iomap.h M src/soc/qualcomm/ipq806x/lcc.c M src/soc/qualcomm/ipq806x/qup.c M src/soc/qualcomm/ipq806x/spi.c M src/soc/qualcomm/ipq806x/uart.c M src/soc/qualcomm/ipq806x/usb.c M src/soc/qualcomm/sdm845/gpio.c M src/soc/rockchip/common/edp.c M src/soc/rockchip/common/gpio.c M src/soc/rockchip/common/i2c.c M src/soc/rockchip/common/include/soc/soc.h M src/soc/rockchip/common/pwm.c M src/soc/rockchip/common/spi.c M src/soc/rockchip/common/vop.c M src/soc/rockchip/rk3288/bootblock.c M src/soc/rockchip/rk3288/clock.c M src/soc/rockchip/rk3288/crypto.c M src/soc/rockchip/rk3288/display.c M src/soc/rockchip/rk3288/gpio.c M src/soc/rockchip/rk3288/hdmi.c M src/soc/rockchip/rk3288/sdram.c M src/soc/rockchip/rk3288/software_i2c.c M src/soc/rockchip/rk3288/timer.c M src/soc/rockchip/rk3288/tsadc.c M src/soc/rockchip/rk3399/bootblock.c M src/soc/rockchip/rk3399/decompressor.c M src/soc/rockchip/rk3399/display.c M src/soc/rockchip/rk3399/gpio.c M src/soc/rockchip/rk3399/mipi.c M src/soc/rockchip/rk3399/saradc.c M src/soc/rockchip/rk3399/sdram.c M src/soc/rockchip/rk3399/timer.c M src/soc/rockchip/rk3399/tsadc.c M src/soc/rockchip/rk3399/usb.c M src/soc/samsung/exynos5250/clock.c M src/soc/samsung/exynos5250/dmc_common.c M src/soc/samsung/exynos5250/dmc_init_ddr3.c M src/soc/samsung/exynos5250/dp-reg.c M src/soc/samsung/exynos5250/fb.c M src/soc/samsung/exynos5250/i2c.c M src/soc/samsung/exynos5250/include/soc/cpu.h M src/soc/samsung/exynos5250/power.c M src/soc/samsung/exynos5250/spi.c M src/soc/samsung/exynos5250/timer.c M src/soc/samsung/exynos5250/tmu.c M src/soc/samsung/exynos5250/trustzone.c M src/soc/samsung/exynos5250/uart.c M src/soc/samsung/exynos5250/usb.c M src/soc/samsung/exynos5420/clock.c M src/soc/samsung/exynos5420/dmc_common.c M src/soc/samsung/exynos5420/dmc_init_ddr3.c M src/soc/samsung/exynos5420/dp.c M src/soc/samsung/exynos5420/dp_lowlevel.c M src/soc/samsung/exynos5420/fimd.c M src/soc/samsung/exynos5420/i2c.c M src/soc/samsung/exynos5420/include/soc/cpu.h M src/soc/samsung/exynos5420/power.c M src/soc/samsung/exynos5420/smp.c M src/soc/samsung/exynos5420/spi.c M src/soc/samsung/exynos5420/timer.c M src/soc/samsung/exynos5420/tmu.c M src/soc/samsung/exynos5420/trustzone.c M src/soc/samsung/exynos5420/uart.c M src/soc/samsung/exynos5420/usb.c M src/soc/sifive/fu540/bootblock.c M src/soc/sifive/fu540/clint.c M src/soc/sifive/fu540/clock.c M src/soc/sifive/fu540/otp.c M src/southbridge/amd/agesa/hudson/bootblock.c M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/agesa/hudson/enable_usbdebug.c M src/southbridge/amd/agesa/hudson/fadt.c M src/southbridge/amd/agesa/hudson/hda.c M src/southbridge/amd/agesa/hudson/hudson.c M src/southbridge/amd/agesa/hudson/imc.c M src/southbridge/amd/agesa/hudson/lpc.c M src/southbridge/amd/agesa/hudson/ramtop.c M src/southbridge/amd/agesa/hudson/reset.c M src/southbridge/amd/agesa/hudson/sata.c M src/southbridge/amd/agesa/hudson/sd.c M src/southbridge/amd/agesa/hudson/sm.c M src/southbridge/amd/agesa/hudson/smi.h M src/southbridge/amd/agesa/hudson/spi.c M src/southbridge/amd/agesa/hudson/usb.c M src/southbridge/amd/amd8111/acpi.c M src/southbridge/amd/amd8111/bootblock.c M src/southbridge/amd/amd8111/nic.c M src/southbridge/amd/amd8111/reset.c M src/southbridge/amd/amd8111/smbus.c M src/southbridge/amd/amd8111/usb.c M src/southbridge/amd/cimx/cimx_util.c M src/southbridge/amd/cimx/sb800/bootblock.c M src/southbridge/amd/cimx/sb800/cfg.c M src/southbridge/amd/cimx/sb800/early.c M src/southbridge/amd/cimx/sb800/fadt.c M src/southbridge/amd/cimx/sb800/lpc.c M src/southbridge/amd/cimx/sb800/ramtop.c M src/southbridge/amd/cimx/sb800/reset.c M src/southbridge/amd/cimx/sb800/smbus.c M src/southbridge/amd/cimx/sb800/spi.c M src/southbridge/amd/cimx/sb900/bootblock.c M src/southbridge/amd/cimx/sb900/early.c M src/southbridge/amd/cimx/sb900/ramtop.c M src/southbridge/amd/cimx/sb900/reset.c M src/southbridge/amd/cimx/sb900/smbus.c M src/southbridge/amd/common/amd_pci_util.c M src/southbridge/amd/cs5536/cs5536.c M src/southbridge/amd/cs5536/early_setup.c M src/southbridge/amd/cs5536/early_smbus.c M src/southbridge/amd/cs5536/smbus.c M src/southbridge/amd/pi/hudson/bootblock.c M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/pi/hudson/enable_usbdebug.c M src/southbridge/amd/pi/hudson/fadt.c M src/southbridge/amd/pi/hudson/gpio.c M src/southbridge/amd/pi/hudson/hda.c M src/southbridge/amd/pi/hudson/hudson.c M src/southbridge/amd/pi/hudson/imc.c M src/southbridge/amd/pi/hudson/lpc.c M src/southbridge/amd/pi/hudson/reset.c M src/southbridge/amd/pi/hudson/sata.c M src/southbridge/amd/pi/hudson/sd.c M src/southbridge/amd/pi/hudson/sm.c M src/southbridge/amd/pi/hudson/smi.h M src/southbridge/amd/pi/hudson/usb.c M src/southbridge/amd/rs780/cmn.c M src/southbridge/amd/rs780/early_setup.c M src/southbridge/amd/rs780/rs780.c M src/southbridge/amd/sb700/bootblock.c M src/southbridge/amd/sb700/early_setup.c M src/southbridge/amd/sb700/enable_usbdebug.c M src/southbridge/amd/sb700/fadt.c M src/southbridge/amd/sb700/hda.c M src/southbridge/amd/sb700/lpc.c M src/southbridge/amd/sb700/pmio.c M src/southbridge/amd/sb700/ramtop.c M src/southbridge/amd/sb700/reset.c M src/southbridge/amd/sb700/sata.c M src/southbridge/amd/sb700/sb700.c M src/southbridge/amd/sb700/sm.c M src/southbridge/amd/sb700/smbus.h M src/southbridge/amd/sb700/spi.c M src/southbridge/amd/sb700/usb.c M src/southbridge/amd/sb800/bootblock.c M src/southbridge/amd/sb800/enable_usbdebug.c M src/southbridge/amd/sb800/fadt.c M src/southbridge/amd/sb800/hda.c M src/southbridge/amd/sb800/lpc.c M src/southbridge/amd/sb800/ramtop.c M src/southbridge/amd/sb800/reset.c M src/southbridge/amd/sb800/sata.c M src/southbridge/amd/sb800/sb800.c M src/southbridge/amd/sb800/sm.c M src/southbridge/amd/sb800/usb.c M src/southbridge/amd/sr5650/cmn.h M src/southbridge/amd/sr5650/early_setup.c M src/southbridge/amd/sr5650/sr5650.c M src/southbridge/broadcom/bcm5785/bootblock.c M src/southbridge/broadcom/bcm5785/lpc.c M src/southbridge/broadcom/bcm5785/reset.c M src/southbridge/broadcom/bcm5785/sata.c M src/southbridge/broadcom/bcm5785/sb_pci_main.c M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/bd82x6x/bootblock.c M src/southbridge/intel/bd82x6x/early_me.c M src/southbridge/intel/bd82x6x/early_me_mrc.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/early_pch_common.c M src/southbridge/intel/bd82x6x/early_smbus.c M src/southbridge/intel/bd82x6x/early_spi.c M src/southbridge/intel/bd82x6x/early_thermal.c M src/southbridge/intel/bd82x6x/early_usb.c M src/southbridge/intel/bd82x6x/early_usb_mrc.c M src/southbridge/intel/bd82x6x/elog.c M src/southbridge/intel/bd82x6x/finalize.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/pch.c M src/southbridge/intel/bd82x6x/sata.c M src/southbridge/intel/bd82x6x/smbus.c M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/bd82x6x/usb_ehci.c M src/southbridge/intel/bd82x6x/usb_xhci.c M src/southbridge/intel/bd82x6x/watchdog.c M src/southbridge/intel/common/acpi_pirq_gen.c M src/southbridge/intel/common/gpio.c M src/southbridge/intel/common/pmbase.c M src/southbridge/intel/common/pmutil.c M src/southbridge/intel/common/smbus.c M src/southbridge/intel/common/smi.c M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/common/spi.c M src/southbridge/intel/common/usb_debug.c M src/southbridge/intel/fsp_rangeley/acpi.c M src/southbridge/intel/fsp_rangeley/early_init.c M src/southbridge/intel/fsp_rangeley/early_smbus.c M src/southbridge/intel/fsp_rangeley/early_spi.c M src/southbridge/intel/fsp_rangeley/early_usb.c M src/southbridge/intel/fsp_rangeley/gpio.c M src/southbridge/intel/fsp_rangeley/lpc.c M src/southbridge/intel/fsp_rangeley/romstage.c M src/southbridge/intel/fsp_rangeley/sata.c M src/southbridge/intel/fsp_rangeley/smbus.c M src/southbridge/intel/fsp_rangeley/spi.c M src/southbridge/intel/fsp_rangeley/watchdog.c M src/southbridge/intel/i82371eb/bootblock.c M src/southbridge/intel/i82371eb/early_pm.c M src/southbridge/intel/i82371eb/early_smbus.c M src/southbridge/intel/i82371eb/i82371eb.h M src/southbridge/intel/i82371eb/reset.c M src/southbridge/intel/i82371eb/smbus.c M src/southbridge/intel/i82371eb/wakeup.c M src/southbridge/intel/i82801dx/ac97.c M src/southbridge/intel/i82801dx/bootblock.c M src/southbridge/intel/i82801dx/early_smbus.c M src/southbridge/intel/i82801dx/lpc.c M src/southbridge/intel/i82801dx/smi.c M src/southbridge/intel/i82801dx/smihandler.c M src/southbridge/intel/i82801gx/ac97.c M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801gx/bootblock.c M src/southbridge/intel/i82801gx/early_lpc.c M src/southbridge/intel/i82801gx/early_smbus.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801gx/smbus.c M src/southbridge/intel/i82801gx/smi.c M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801gx/usb_ehci.c M src/southbridge/intel/i82801gx/watchdog.c M src/southbridge/intel/i82801ix/bootblock.c M src/southbridge/intel/i82801ix/dmi_setup.c M src/southbridge/intel/i82801ix/early_init.c M src/southbridge/intel/i82801ix/early_smbus.c M src/southbridge/intel/i82801ix/hdaudio.c M src/southbridge/intel/i82801ix/i82801ix.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801ix/sata.c M src/southbridge/intel/i82801ix/smbus.c M src/southbridge/intel/i82801ix/smi.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801ix/thermal.c M src/southbridge/intel/i82801jx/bootblock.c M src/southbridge/intel/i82801jx/early_lpc.c M src/southbridge/intel/i82801jx/early_smbus.c M src/southbridge/intel/i82801jx/hdaudio.c M src/southbridge/intel/i82801jx/i82801jx.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/i82801jx/sata.c M src/southbridge/intel/i82801jx/smbus.c M src/southbridge/intel/i82801jx/smi.c M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/i82801jx/thermal.c M src/southbridge/intel/i82870/pci_parity.c M src/southbridge/intel/ibexpeak/azalia.c M src/southbridge/intel/ibexpeak/early_smbus.c M src/southbridge/intel/ibexpeak/early_thermal.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/madt.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/ibexpeak/sata.c M src/southbridge/intel/ibexpeak/smbus.c M src/southbridge/intel/ibexpeak/smi.c M src/southbridge/intel/ibexpeak/smihandler.c M src/southbridge/intel/ibexpeak/thermal.c M src/southbridge/intel/ibexpeak/usb_ehci.c M src/southbridge/intel/lynxpoint/azalia.c M src/southbridge/intel/lynxpoint/bootblock.c M src/southbridge/intel/lynxpoint/early_me.c M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/early_smbus.c M src/southbridge/intel/lynxpoint/early_spi.c M src/southbridge/intel/lynxpoint/early_usb.c M src/southbridge/intel/lynxpoint/elog.c M src/southbridge/intel/lynxpoint/finalize.c M src/southbridge/intel/lynxpoint/hda_verb.c M src/southbridge/intel/lynxpoint/lp_gpio.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/intel/lynxpoint/pmutil.c M src/southbridge/intel/lynxpoint/rcba.c M src/southbridge/intel/lynxpoint/sata.c M src/southbridge/intel/lynxpoint/serialio.c M src/southbridge/intel/lynxpoint/smbus.c M src/southbridge/intel/lynxpoint/smi.c M src/southbridge/intel/lynxpoint/smihandler.c M src/southbridge/intel/lynxpoint/usb_ehci.c M src/southbridge/intel/lynxpoint/usb_xhci.c M src/southbridge/intel/lynxpoint/watchdog.c M src/southbridge/nvidia/ck804/bootblock.c M src/southbridge/nvidia/ck804/ck804.c M src/southbridge/nvidia/ck804/early_smbus.c M src/southbridge/nvidia/ck804/enable_usbdebug.c M src/southbridge/nvidia/ck804/lpc.c M src/southbridge/nvidia/ck804/nic.c M src/southbridge/nvidia/ck804/reset.c M src/southbridge/nvidia/ck804/smbus.c M src/southbridge/nvidia/mcp55/azalia.c M src/southbridge/nvidia/mcp55/bootblock.c M src/southbridge/nvidia/mcp55/early_ctrl.c M src/southbridge/nvidia/mcp55/early_smbus.c M src/southbridge/nvidia/mcp55/enable_usbdebug.c M src/southbridge/nvidia/mcp55/fadt.c M src/southbridge/nvidia/mcp55/lpc.c M src/southbridge/nvidia/mcp55/mcp55.c M src/southbridge/nvidia/mcp55/nic.c M src/southbridge/nvidia/mcp55/reset.c M src/southbridge/nvidia/mcp55/smbus.c M src/southbridge/ricoh/rl5c476/rl5c476.c M src/southbridge/ti/pci1x2x/pci1x2x.c M src/southbridge/ti/pci7420/cardbus.c M src/southbridge/ti/pci7420/firewire.c M src/southbridge/ti/pcixx12/pcixx12.c M src/southbridge/via/common/via_early_smbus.h M src/superio/common/conf_mode.c M src/superio/fintek/common/early_serial.c M src/superio/fintek/common/fintek.h M src/superio/fintek/f71805f/superio.c M src/superio/fintek/f71808a/f71808a_hwm.c M src/superio/fintek/f71808a/f71808a_multifunc.c M src/superio/fintek/f71808a/fintek_internal.h M src/superio/fintek/f71808a/superio.c M src/superio/fintek/f71859/superio.c M src/superio/fintek/f71863fg/superio.c M src/superio/fintek/f71869ad/f71869ad_hwm.c M src/superio/fintek/f71869ad/f71869ad_multifunc.c M src/superio/fintek/f71869ad/fintek_internal.h M src/superio/fintek/f71869ad/superio.c M src/superio/fintek/f71872/superio.c M src/superio/fintek/f81216h/early_serial.c M src/superio/fintek/f81216h/superio.c M src/superio/fintek/f81865f/superio.c M src/superio/fintek/f81866d/f81866d_hwm.c M src/superio/fintek/f81866d/f81866d_uart.c M src/superio/fintek/f81866d/fintek_internal.h M src/superio/fintek/f81866d/superio.c M src/superio/intel/i8900/early_serial.c M src/superio/intel/i8900/superio.c M src/superio/ite/common/early_serial.c M src/superio/ite/common/env_ctrl.c M src/superio/ite/common/ite.h M src/superio/ite/it8623e/superio.c M src/superio/ite/it8671f/early_serial.c M src/superio/ite/it8671f/it8671f.h M src/superio/ite/it8712f/superio.c M src/superio/ite/it8716f/superio.c M src/superio/ite/it8718f/early_serial.c M src/superio/ite/it8718f/it8718f.h M src/superio/ite/it8728f/superio.c M src/superio/ite/it8772f/early_init.c M src/superio/ite/it8772f/it8772f.h M src/superio/ite/it8772f/superio.c M src/superio/ite/it8783ef/it8783ef.h M src/superio/nsc/pc87309/early_serial.c M src/superio/nsc/pc87309/pc87309.h M src/superio/nsc/pc87309/superio.c M src/superio/nsc/pc87360/early_serial.c M src/superio/nsc/pc87360/pc87360.h M src/superio/nsc/pc87360/superio.c M src/superio/nsc/pc87366/early_serial.c M src/superio/nsc/pc87366/pc87366.h M src/superio/nsc/pc87366/superio.c M src/superio/nsc/pc87382/superio.c M src/superio/nsc/pc87384/superio.c M src/superio/nsc/pc87392/early_serial.c M src/superio/nsc/pc87392/superio.c M src/superio/nsc/pc87417/early_init.c M src/superio/nsc/pc87417/early_serial.c M src/superio/nsc/pc87417/pc87417.h M src/superio/nsc/pc87417/superio.c M src/superio/nsc/pc97317/early_serial.c M src/superio/nsc/pc97317/pc97317.h M src/superio/nsc/pc97317/superio.c M src/superio/nuvoton/common/early_serial.c M src/superio/nuvoton/common/nuvoton.h M src/superio/nuvoton/nct5104d/early_init.c M src/superio/nuvoton/nct5104d/superio.c M src/superio/nuvoton/nct5572d/superio.c M src/superio/nuvoton/nct6776/superio.c M src/superio/nuvoton/nct6779d/superio.c M src/superio/nuvoton/nct6791d/superio.c M src/superio/nuvoton/npcd378/superio.c M src/superio/nuvoton/wpcm450/early_init.c M src/superio/nuvoton/wpcm450/superio.c M src/superio/renesas/m3885x/superio.c M src/superio/serverengines/pilot/early_init.c M src/superio/serverengines/pilot/early_serial.c M src/superio/smsc/dme1737/dme1737.h M src/superio/smsc/dme1737/early_serial.c M src/superio/smsc/dme1737/superio.c M src/superio/smsc/kbc1100/early_init.c M src/superio/smsc/kbc1100/kbc1100.h M src/superio/smsc/kbc1100/superio.c M src/superio/smsc/lpc47b272/early_serial.c M src/superio/smsc/lpc47b272/lpc47b272.h M src/superio/smsc/lpc47b272/superio.c M src/superio/smsc/lpc47b397/early_serial.c M src/superio/smsc/lpc47b397/lpc47b397.h M src/superio/smsc/lpc47b397/superio.c M src/superio/smsc/lpc47m10x/early_serial.c M src/superio/smsc/lpc47m10x/lpc47m10x.h M src/superio/smsc/lpc47m10x/superio.c M src/superio/smsc/lpc47m15x/early_serial.c M src/superio/smsc/lpc47m15x/lpc47m15x.h M src/superio/smsc/lpc47m15x/superio.c M src/superio/smsc/lpc47n207/early_serial.c M src/superio/smsc/lpc47n207/lpc47n207.h M src/superio/smsc/lpc47n217/early_serial.c M src/superio/smsc/lpc47n217/lpc47n217.h M src/superio/smsc/lpc47n217/superio.c M src/superio/smsc/lpc47n227/early_serial.c M src/superio/smsc/lpc47n227/superio.c M src/superio/smsc/mec1308/superio.c M src/superio/smsc/sch4037/sch4037_early_init.c M src/superio/smsc/sch4037/superio.c M src/superio/smsc/sio1007/early_serial.c M src/superio/smsc/sio1036/sio1036.h M src/superio/smsc/sio1036/sio1036_early_init.c M src/superio/smsc/sio1036/superio.c M src/superio/smsc/smscsuperio/early_serial.c M src/superio/smsc/smscsuperio/smscsuperio.h M src/superio/smsc/smscsuperio/superio.c M src/superio/via/vt1211/superio.c M src/superio/winbond/common/early_init.c M src/superio/winbond/common/winbond.h M src/superio/winbond/w83627dhg/early_serial.c M src/superio/winbond/w83627dhg/superio.c M src/superio/winbond/w83627dhg/w83627dhg.h M src/superio/winbond/w83627ehg/superio.c M src/superio/winbond/w83627hf/superio.c M src/superio/winbond/w83627thg/superio.c M src/superio/winbond/w83627thg/w83627thg.h M src/superio/winbond/w83627uhg/superio.c M src/superio/winbond/w83667hg-a/superio.c M src/superio/winbond/w83697hf/superio.c M src/superio/winbond/w83977tf/superio.c M src/superio/winbond/wpcd376i/early_serial.c M src/superio/winbond/wpcd376i/superio.c M src/superio/winbond/wpcd376i/wpcd376i.h M util/uio_usbdebug/uio_usbdebug_intel.c 1,357 files changed, 1,359 insertions(+), 53 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/29947/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/29947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a3deea676308e2dc703b5e06558b05235191044 Gerrit-Change-Number: 29947 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: [WIP]opencelluar: Add EC interface
by Patrick Rudolph (Code Review) 30 Nov '18

30 Nov '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29946 Change subject: [WIP]opencelluar: Add EC interface ...................................................................... [WIP]opencelluar: Add EC interface Add the EC driver that uses the OpenCellular Management Protocol. Implement the board_reset() method using introduced methods. Change-Id: I67eb4ee8e0ad297a8d1984d55102146688c291fc Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- A src/ec/opencellular/tiva/Kconfig A src/ec/opencellular/tiva/Makefile.inc A src/ec/opencellular/tiva/ec.c A src/ec/opencellular/tiva/ec.h M src/mainboard/opencellular/elgon/Kconfig M src/mainboard/opencellular/elgon/Makefile.inc A src/mainboard/opencellular/elgon/reset.c 7 files changed, 327 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/29946/1 diff --git a/src/ec/opencellular/tiva/Kconfig b/src/ec/opencellular/tiva/Kconfig new file mode 100644 index 0000000..a56b06a --- /dev/null +++ b/src/ec/opencellular/tiva/Kconfig @@ -0,0 +1,5 @@ +config EC_OPENCELLULAR_TIVA + bool + depends on CONSOLE_SERIAL + help + OpenCellular Tiva EC protocol driver over serial. diff --git a/src/ec/opencellular/tiva/Makefile.inc b/src/ec/opencellular/tiva/Makefile.inc new file mode 100644 index 0000000..fadaf44 --- /dev/null +++ b/src/ec/opencellular/tiva/Makefile.inc @@ -0,0 +1,9 @@ +ifeq ($(CONFIG_EC_OPENCELLULAR_TIVA),y) + +bootblock-y += ec.c +romstage-y += ec.c +verstage-y += ec.c +postcar-y += ec.c +ramstage-y += ec.c + +endif diff --git a/src/ec/opencellular/tiva/ec.c b/src/ec/opencellular/tiva/ec.c new file mode 100644 index 0000000..d46f284 --- /dev/null +++ b/src/ec/opencellular/tiva/ec.c @@ -0,0 +1,203 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <string.h> +#include <console/uart.h> +#include "ec.h" + +/* Packet definition as per OpenCellular Management Protocol */ +enum ec_iface { + EC_UART = 1, + EC_ETHERNET = 2, + EC_SBD = 3, + EC_USB = 4, +}; + +struct ec_header { + uint8_t sof; + uint8_t len; + uint8_t iface; + uint32_t seq; + uint32_t ts; +} __packed; + +struct ec_payload { + uint8_t subsystem; + uint8_t component_id; + uint8_t message_type; + uint8_t action_type; + uint16_t parameter_info; + uint8_t message[48]; +} __packed; + +struct ec_packet { + struct ec_header hdr; + struct ec_payload pld; +} __packed; + +struct ec_msg { + union { + struct ec_packet p; + uint8_t raw[sizeof(struct ec_packet)]; + }; +}; + +/* Create a packet to BMS:TIVA from given arguments */ +static size_t ec_create_tx_msg(struct ec_packet *p, + const enum ec_message_type mt, + const enum ec_action_type at, + const uint8_t parameter_info, + const enum ec_iface iface, + const uint8_t *data_in, + const uint8_t data_in_len) +{ + size_t len = sizeof(*p) - sizeof(p->pld.message) + data_in_len; + + p->pld.subsystem = EC_BMS; + p->pld.component_id = EC_TIVA; + p->pld.message_type = mt; + p->pld.action_type = at; + p->pld.parameter_info = parameter_info; + if (data_in) + memcpy(&p->pld.message, data_in, data_in_len); + + p->hdr.iface = iface; + p->hdr.len = data_in_len; + p->hdr.sof = 0x55; + p->hdr.ts = 0; /* Reserved for future use */ + p->hdr.seq = 0; /* Reserved for future use */ + + return len; +} + +/* Returns true on valid header */ +static bool ec_verify_rx_hdr(struct ec_packet *p, const enum ec_iface iface) +{ + if (p->hdr.sof != 0x55) + return false; + if (p->hdr.len > 48) + return false; + if (p->hdr.iface != iface) + return false; + return true; +} + + +/* Returns true on valid packet */ +static bool ec_verify_rx_msg(struct ec_packet *p, const enum ec_iface iface) +{ + if (!ec_verify_rx_hdr(p, iface)) + return false; + if (p->pld.subsystem != EC_BMS) + return false; + if (p->pld.component_id != EC_TIVA) + return false; + + return true; +} + +/** + * Transmits a packet to EC using one of the UARTs. + * The function is blocking until a data has been transmitted. + * + * All pointers can be NULL if not required. + * + * @param uart_idx The UART connected to EC + * @param mt Message type to transmit + * @param at Action type to transmit + * @param parameter_info Parameter info to transmit + * @param data_in Buffer to data to transmit + * @param data_in_len Length of data to transmit + * + * @return Zero on success, negative on failure + */ +int ec_transmit_msg_uart(const uint8_t uart_idx, + const enum ec_message_type mt, + const enum ec_action_type at, + const uint8_t parameter_info, + const uint8_t *data_in, + const uint8_t data_in_len) +{ + struct ec_msg msg; + + size_t len = ec_create_tx_msg(&msg.p, mt, at, parameter_info, EC_UART, + data_in, data_in_len); + + for (size_t i = 0; i < len; i++) + uart_tx_byte(uart_idx, msg.raw[i]); + + return 0; +} + +/** + * Receives a packet from EC using one of the UARTs. + * The function is blocking and waits for a SOF byte. + * + * The caller must provide a data buffer of size 48. + * If no data buffer is provided the received data (if any) is dropped. + * + * All pointers can be NULL if not required. + * + * @param uart_idx The UART connected to EC + * @param mt Receveived message type + * @param at Receveived action type + * @param parameter_info Receveived parameter info + * @param data_out Buffer to place receveived data + * @param data_out_len Length of received data + * + * @return Zero on success, negative on failure + */ +int ec_receive_msg_uart(const uint8_t uart_idx, + enum ec_message_type *mt, + enum ec_action_type *at, + uint8_t *parameter_info, + uint8_t *data_out, + uint8_t *data_out_len) +{ + struct ec_msg msg; + + do { + msg.raw[0] = uart_rx_byte(uart_idx); + } while (msg.raw[0] != 0x55); + + for (size_t i = 0; i < sizeof(struct ec_header); i++) + msg.raw[i] = uart_rx_byte(uart_idx); + + if (!ec_verify_rx_hdr(&msg.p, EC_UART)) + return -1; + + const size_t len = sizeof(msg.p.pld) - sizeof(msg.p.pld.message) + + msg.p.hdr.len; + + for (size_t i = 0; i < len; i++) + msg.raw[sizeof(struct ec_header) + i] = uart_rx_byte(uart_idx); + + if (!ec_verify_rx_msg(&msg.p, EC_UART)) + return -1; + + if (mt) + *mt = msg.p.pld.message_type; + if (at) + *at = msg.p.pld.action_type; + if (parameter_info) + *parameter_info = msg.p.pld.parameter_info; + if (data_out) + memcpy(data_out, msg.p.pld.message, msg.p.hdr.len); + if (*data_out_len) + *data_out_len = msg.p.hdr.len; + return 0; +} + diff --git a/src/ec/opencellular/tiva/ec.h b/src/ec/opencellular/tiva/ec.h new file mode 100644 index 0000000..7728f7e --- /dev/null +++ b/src/ec/opencellular/tiva/ec.h @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> + +/** + * Command interface as per OpenCellular Management Protocol: + * + * This protocol allows to handle all the configuration, status and alert + * processing through a ‘Request-Response’ mechanism between host and MCU. + */ + +enum ec_subsystem { + EC_SYSTEM = 0, + EC_POWER = 1, + EC_BMS = 2, + EC_HCI = 3, + EC_ETHERNET_SWITCH = 4, + EC_OBC = 5, + EC_GPP = 6, + EC_SDR = 7, + EC_RF = 8, + EC_SYNC = 9, + EC_TEST_MODULE = 10, + EC_WATCHDOG = 11, + EC_ALERT_MANAGER = 12 +}; + +/* We only support subsystem BMS here */ +enum ec_subsystem_bms { + EC_ALL = 0, + EC_TIVA = 1, +}; + +enum ec_message_type { + EC_CONFIG = 1, + EC_STATUS = 2, + EC_ALERT = 3, + EC_COMMAND = 4, +}; + +enum ec_action_type { + EC_GET = 1, + EC_SET = 2, + EC_REPLY = 3, + EC_ACTIVE = 4, + EC_CLEAR = 5, + EC_RESET = 6, + EC_ENABLE = 7, + EC_DISABLE = 8, +}; + +int ec_transmit_msg_uart(const uint8_t uart_idx, + const enum ec_message_type mt, + const enum ec_action_type at, + const uint8_t parameter_info, + const uint8_t *data_in, + const uint8_t data_in_len); + +int ec_receive_msg_uart(const uint8_t uart_idx, + enum ec_message_type *mt, + enum ec_action_type *at, + uint8_t *parameter_info, + uint8_t *data_out, + uint8_t *data_out_len); diff --git a/src/mainboard/opencellular/elgon/Kconfig b/src/mainboard/opencellular/elgon/Kconfig index 3ba2a60..b9f93ab 100644 --- a/src/mainboard/opencellular/elgon/Kconfig +++ b/src/mainboard/opencellular/elgon/Kconfig @@ -25,7 +25,7 @@ select SPI_FLASH_WINBOND select MAINBOARD_HAS_I2C_TPM_GENERIC select MAINBOARD_HAS_TPM1 - select MISSING_BOARD_RESET + select EC_OPENCELLULAR_TIVA config VBOOT select VBOOT_NO_BOARD_SUPPORT diff --git a/src/mainboard/opencellular/elgon/Makefile.inc b/src/mainboard/opencellular/elgon/Makefile.inc index 343a52e..3440833 100644 --- a/src/mainboard/opencellular/elgon/Makefile.inc +++ b/src/mainboard/opencellular/elgon/Makefile.inc @@ -16,16 +16,20 @@ bootblock-y += bootblock.c bootblock-y += memlayout.ld bootblock-y += death.c +bootblock-y += reset.c romstage-y += memlayout.ld romstage-y += romstage.c romstage-y += bdk_devicetree.c romstage-y += death.c +romstage-y += reset.c ramstage-y += mainboard.c ramstage-y += memlayout.ld ramstage-y += bdk_devicetree.c ramstage-y += death.c +ramstage-y += reset.c verstage-y += memlayout.ld verstage-y += death.c +verstage-y += reset.c diff --git a/src/mainboard/opencellular/elgon/reset.c b/src/mainboard/opencellular/elgon/reset.c new file mode 100644 index 0000000..d73d9af --- /dev/null +++ b/src/mainboard/opencellular/elgon/reset.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/opencellular/tiva/ec.h> +#include <reset.h> +#include <soc/gpio.h> +#include "mainboard.h" + +void do_board_reset(void) +{ + /* Route UART0 to EC */ + gpio_output(ELGON_GPIO_UART_SEL, 1); + + ec_transmit_msg_uart(0, EC_COMMAND, EC_RESET, 0, NULL, 0); + /* FIXME: Is there a response ? */ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/29946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67eb4ee8e0ad297a8d1984d55102146688c291fc Gerrit-Change-Number: 29946 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: riscv: add support to select the privilege level of the payload running
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29494 ) Change subject: riscv: add support to select the privilege level of the payload running ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/#/c/29494/10/src/arch/riscv/boot.c File src/arch/riscv/boot.c: https://review.coreboot.org/#/c/29494/10/src/arch/riscv/boot.c@49 PS10, Line 49: void (*doit)(void *) = prog_entry(prog); function definition argument 'void *' should also have an identifier name -- To view, visit https://review.coreboot.org/c/coreboot/+/29494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96961246cd257b63cf167238aa0cf6e65272b951 Gerrit-Change-Number: 29494 Gerrit-PatchSet: 10 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 30 Nov 2018 07:09:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: riscv: add support to select the privilege level of the payload running
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29494 ) Change subject: riscv: add support to select the privilege level of the payload running ...................................................................... Patch Set 9: (4 comments) https://review.coreboot.org/#/c/29494/9/src/arch/riscv/boot.c File src/arch/riscv/boot.c: https://review.coreboot.org/#/c/29494/9/src/arch/riscv/boot.c@43 PS9, Line 43: void (*fn)(uintptr_t, uintptr_t) = prog_entry(prog); function definition argument 'uintptr_t' should also have an identifier name https://review.coreboot.org/#/c/29494/9/src/arch/riscv/boot.c@43 PS9, Line 43: void (*fn)(uintptr_t, uintptr_t) = prog_entry(prog); function definition argument 'uintptr_t' should also have an identifier name https://review.coreboot.org/#/c/29494/9/src/arch/riscv/boot.c@49 PS9, Line 49: void (*doit)(void *) = prog_entry(prog); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/29494/9/src/arch/riscv/payload.c File src/arch/riscv/payload.c: https://review.coreboot.org/#/c/29494/9/src/arch/riscv/payload.c@28 PS9, Line 28: uintptr_t status = read_csr(mstatus) trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/29494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96961246cd257b63cf167238aa0cf6e65272b951 Gerrit-Change-Number: 29494 Gerrit-PatchSet: 9 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 30 Nov 2018 07:05:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: riscv: add support to select the privilege level of the payload running
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29494 ) Change subject: riscv: add support to select the privilege level of the payload running ...................................................................... Patch Set 8: (2 comments) https://review.coreboot.org/#/c/29494/8/src/arch/riscv/boot.c File src/arch/riscv/boot.c: https://review.coreboot.org/#/c/29494/8/src/arch/riscv/boot.c@50 PS8, Line 50: void (*doit)(void *) = prog_entry(prog); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/29494/8/src/arch/riscv/payload.c File src/arch/riscv/payload.c: https://review.coreboot.org/#/c/29494/8/src/arch/riscv/payload.c@28 PS8, Line 28: uintptr_t status = read_csr(mstatus) trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/29494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96961246cd257b63cf167238aa0cf6e65272b951 Gerrit-Change-Number: 29494 Gerrit-PatchSet: 8 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 30 Nov 2018 07:00:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/fizz/variants/karma: Update USB port info
by Furquan Shaikh (Code Review) 30 Nov '18

30 Nov '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29912 ) Change subject: mb/google/fizz/variants/karma: Update USB port info ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7383b3d676fd7c775a6d749c70af65b28cf941eb Gerrit-Change-Number: 29912 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 04:19:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/fizz/variants/karma: Disable native SD card controller
by Furquan Shaikh (Code Review) 30 Nov '18

30 Nov '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29918 ) Change subject: mb/google/fizz/variants/karma: Disable native SD card controller ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68dc9be511a370d882e4656c165efbe5dc6ee52e Gerrit-Change-Number: 29918 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 04:17:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: Shyvana: ELAN touchpad I2C special timing requirement
by Furquan Shaikh (Code Review) 30 Nov '18

30 Nov '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29922 ) Change subject: Shyvana: ELAN touchpad I2C special timing requirement ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifeb08c2530e6a7674f23f7d48cefa16cfc59cb13 Gerrit-Change-Number: 29922 Gerrit-PatchSet: 4 Gerrit-Owner: YanRu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: YanRu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-CC: Jerry Chou <jerry_chou(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Statham Chu <statham_chu(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Fri, 30 Nov 2018 04:15:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: smmstore: update smm store filename to use an underscore
by Duncan Laurie (Code Review) 30 Nov '18

30 Nov '18

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29854 ) Change subject: smmstore: update smm store filename to use an underscore ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If70772e17cc1668a28b376eeccfde0424e637b1a Gerrit-Change-Number: 29854 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 02:23:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/sarien/variants/sarien: Enable melf touchscreen
by Duncan Laurie (Code Review) 30 Nov '18

30 Nov '18

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29830 ) Change subject: mb/google/sarien/variants/sarien: Enable melf touchscreen ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29830/2/src/mainboard/google/sarien/variant… File src/mainboard/google/sarien/variants/sarien/devicetree.cb: https://review.coreboot.org/#/c/29830/2/src/mainboard/google/sarien/variant… PS2, Line 124: GPP_B13 There does not seem to be a dedicated touchscreen reset pin, this is PLTRST and doesn't seem like what we should be using. -- To view, visit https://review.coreboot.org/c/coreboot/+/29830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I926c988c141628ae2d98206f9eb615d06357a366 Gerrit-Change-Number: 29830 Gerrit-PatchSet: 2 Gerrit-Owner: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Crystal Lin <crystal_lin(a)compal.corp-partner.google.com> Gerrit-CC: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Fri, 30 Nov 2018 02:17:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: google/sarien: Increase BIOS region to 28MB
by Duncan Laurie (Code Review) 30 Nov '18

30 Nov '18

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29945 ) Change subject: google/sarien: Increase BIOS region to 28MB ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9bc0fa0f662e5ec64e77f2005dbb2e7edb8b2524 Gerrit-Change-Number: 29945 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 02:08:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: google/sarien: Increase BIOS region to 28MB
by Lijian Zhao (Code Review) 30 Nov '18

30 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29945 to look at the new patch set (#2). Change subject: google/sarien: Increase BIOS region to 28MB ...................................................................... google/sarien: Increase BIOS region to 28MB Platform have a 32MB SPI chip, so we can increase the bios region from 16MB to 28MB. BUG=b:119267832 TEST=Build and boot fine on sarien platform. Change-Id: I9bc0fa0f662e5ec64e77f2005dbb2e7edb8b2524 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/google/sarien/chromeos.fmd 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/29945/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9bc0fa0f662e5ec64e77f2005dbb2e7edb8b2524 Gerrit-Change-Number: 29945 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/baytrail: Improve CAR setup
by Matt DeVillier (Code Review) 30 Nov '18

30 Nov '18

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29928 ) Change subject: soc/intel/baytrail: Improve CAR setup ...................................................................... Patch Set 2: Code-Review+1 tested on google/squawks in conjunction with 29929/30 -- To view, visit https://review.coreboot.org/c/coreboot/+/29928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ba67bb8b049c3f25b856f6ebb1399d275764f54 Gerrit-Change-Number: 29928 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 01:29:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: soc/intel/baytrail: Use postcar_frame functions to set up frame
by Matt DeVillier (Code Review) 30 Nov '18

30 Nov '18

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29929 ) Change subject: soc/intel/baytrail: Use postcar_frame functions to set up frame ...................................................................... Patch Set 2: Code-Review+1 tested on google/squawks in conjunction with 29928/30 -- To view, visit https://review.coreboot.org/c/coreboot/+/29929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77e375a2ff2fbf1be4ded922195b80b49ffa4cc5 Gerrit-Change-Number: 29929 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 01:29:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: soc/intel/baytrail: Implement POSTCAR stage
by Matt DeVillier (Code Review) 30 Nov '18

30 Nov '18

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29930 ) Change subject: soc/intel/baytrail: Implement POSTCAR stage ...................................................................... Patch Set 2: Code-Review+1 tested on google/squawks in conjunction with 29928/29 -- To view, visit https://review.coreboot.org/c/coreboot/+/29930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62a70ae35fe92808f180f2b5f21c5899a96c2c16 Gerrit-Change-Number: 29930 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 01:29:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: google/sarien: Increase BIOS region to 28MB
by Lijian Zhao (Code Review) 30 Nov '18

30 Nov '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29945 Change subject: google/sarien: Increase BIOS region to 28MB ...................................................................... google/sarien: Increase BIOS region to 28MB Platform have a 32MB SPI chip, so we can increase the bios region from 16MB to 28MB. BUG=b:119267832 TEST=Build and boot fine on sarien platform. Change-Id: I9bc0fa0f662e5ec64e77f2005dbb2e7edb8b2524 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/google/sarien/chromeos.fmd 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/29945/1 diff --git a/src/mainboard/google/sarien/chromeos.fmd b/src/mainboard/google/sarien/chromeos.fmd index 6631769..ec08b83 100644 --- a/src/mainboard/google/sarien/chromeos.fmd +++ b/src/mainboard/google/sarien/chromeos.fmd @@ -1,11 +1,11 @@ FLASH@0xfe000000 0x2000000 { - SI_ALL@0x0 0x1000000 { + SI_ALL@0x0 0x400000 { SI_DESC@0x0 0x1000 SI_EC@0x1000 0x100000 SI_GBE@0x101000 0x2000 - SI_ME@0x103000 0xefd000 + SI_ME@0x103000 0x2fd000 } - SI_BIOS@0x1000000 0x1000000 { + SI_BIOS@0x400000 0x1c00000 { RW_SECTION_A@0x0 0x280000 { VBLOCK_A@0x0 0x10000 FW_MAIN_A(CBFS)@0x10000 0x26ffc0 @@ -30,7 +30,7 @@ RW_NVRAM@0x2a000 0x6000 } CONSOLE@0x530000 0x20000 - RW_LEGACY(CBFS)@0x550000 0x6b0000 + RW_LEGACY(CBFS)@0x550000 0x12b0000 WP_RO@0xc00000 0x400000 { RO_VPD@0x0 0x4000 RO_UNUSED@0x4000 0xc000 -- To view, visit https://review.coreboot.org/c/coreboot/+/29945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9bc0fa0f662e5ec64e77f2005dbb2e7edb8b2524 Gerrit-Change-Number: 29945 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: soc/intel/common: Limit BIOS region cache to 16MB
by Lijian Zhao (Code Review) 30 Nov '18

30 Nov '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29944 Change subject: soc/intel/common: Limit BIOS region cache to 16MB ...................................................................... soc/intel/common: Limit BIOS region cache to 16MB Cache BIOS region can boost boot performance, however it can't be over 16MB, according to processor EDS vol1, FLASH+APIC LT will be less than 20MB under 4G. Set the maxiam to 16GB to save numbers of mtrr entries. BUG=b:119267832 TEST=Build and boot up fine on whiskeylake rvp platform. Change-Id: I46a47c8bf66b14fb2fcb7b6b1d30d02886c450a4 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/common/block/fast_spi/fast_spi.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/29944/1 diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 5ff0872..8649f0c 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -240,6 +240,10 @@ if (!bios_size) return; + /* Cache up to 16MB to boost boot performace */ + if (bios_size > 16 * MiB) + bios_size = 16 * MiB; + /* Round to power of two */ alignment = 1UL << (log2_ceil(bios_size)); bios_size = ALIGN_UP(bios_size, alignment); -- To view, visit https://review.coreboot.org/c/coreboot/+/29944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46a47c8bf66b14fb2fcb7b6b1d30d02886c450a4 Gerrit-Change-Number: 29944 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: arch/power8: Rename to ppc64
by Jonathan Neuschäfer (Code Review) 30 Nov '18

30 Nov '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29943 Change subject: arch/power8: Rename to ppc64 ...................................................................... arch/power8: Rename to ppc64 POWER8 is a specific implementation of ppc64, which is by now outdated (POWER9 has been on the market for a while). Rename arch/power8/ to potentially cover a wider range of hardware. TEST=Toolchains built before/after this commit can build coreboot for emulation/qemu-power8 from before/after this commit. Change-Id: I2d6f08b12a9ffc8a652ddcd6f24ad85ecb33ca52 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M Documentation/releases/coreboot-4.9-relnotes.md M MAINTAINERS D src/arch/power8/Kconfig A src/arch/ppc64/Kconfig R src/arch/ppc64/Makefile.inc R src/arch/ppc64/boot.c R src/arch/ppc64/bootblock.S R src/arch/ppc64/id.ld R src/arch/ppc64/include/arch/byteorder.h R src/arch/ppc64/include/arch/cache.h R src/arch/ppc64/include/arch/cbconfig.h R src/arch/ppc64/include/arch/cpu.h R src/arch/ppc64/include/arch/early_variables.h R src/arch/ppc64/include/arch/exception.h R src/arch/ppc64/include/arch/header.ld R src/arch/ppc64/include/arch/hlt.h R src/arch/ppc64/include/arch/io.h R src/arch/ppc64/include/arch/memlayout.h R src/arch/ppc64/include/arch/stages.h R src/arch/ppc64/include/stdint.h R src/arch/ppc64/misc.c R src/arch/ppc64/prologue.inc R src/arch/ppc64/rom_media.c R src/arch/ppc64/stages.c R src/arch/ppc64/tables.c M src/cpu/qemu-power8/Kconfig M src/device/Kconfig M src/mainboard/emulation/qemu-power8/Kconfig M toolchain.inc M util/crossgcc/Makefile M util/crossgcc/Makefile.inc M util/lint/check_lint_tests M util/xcompile/xcompile 33 files changed, 66 insertions(+), 64 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/29943/1 diff --git a/Documentation/releases/coreboot-4.9-relnotes.md b/Documentation/releases/coreboot-4.9-relnotes.md index c59744e..a24266a 100644 --- a/Documentation/releases/coreboot-4.9-relnotes.md +++ b/Documentation/releases/coreboot-4.9-relnotes.md @@ -23,6 +23,8 @@ * Add bootblock compression capability: on systems that copy the bootblock from very slow flash to ERAM, allow adding a stub that decompresses the bootblock into ERAM to minimize the amount of flash reads +* Rename the POWER8 architecture port to PPC64 to reflect that it isn't limited + to POWER8 Toolchain --------- diff --git a/MAINTAINERS b/MAINTAINERS index 3df572c..b3cc559 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -144,11 +144,11 @@ F: src/mainboard/sifive/ F: util/riscv/ -POWER8 ARCHITECTURE +PPC64 ARCHITECTURE M: Ronald Minnich <rminnich(a)gmail.com> M: Timothy Pearson <tpearson(a)raptorengineeringinc.com> S: Maintained -F: src/arch/power8/ +F: src/arch/ppc64/ F: src/cpu/qemu-power8/ F: src/mainboard/emulation/qemu-power8/ diff --git a/src/arch/power8/Kconfig b/src/arch/power8/Kconfig deleted file mode 100644 index 476de2b..0000000 --- a/src/arch/power8/Kconfig +++ /dev/null @@ -1,25 +0,0 @@ -config ARCH_POWER8 - bool - default n - -config ARCH_BOOTBLOCK_POWER8 - bool - default n - select ARCH_POWER8 - select BOOTBLOCK_CUSTOM - select C_ENVIRONMENT_BOOTBLOCK - select ARCH_VERSTAGE_POWER8 - select ARCH_ROMSTAGE_POWER8 - select ARCH_RAMSTAGE_POWER8 - -config ARCH_VERSTAGE_POWER8 - bool - default n - -config ARCH_ROMSTAGE_POWER8 - bool - default n - -config ARCH_RAMSTAGE_POWER8 - bool - default n diff --git a/src/arch/ppc64/Kconfig b/src/arch/ppc64/Kconfig new file mode 100644 index 0000000..9e37bfc --- /dev/null +++ b/src/arch/ppc64/Kconfig @@ -0,0 +1,25 @@ +config ARCH_PPC64 + bool + default n + +config ARCH_BOOTBLOCK_PPC64 + bool + default n + select ARCH_PPC64 + select BOOTBLOCK_CUSTOM + select C_ENVIRONMENT_BOOTBLOCK + select ARCH_VERSTAGE_PPC64 + select ARCH_ROMSTAGE_PPC64 + select ARCH_RAMSTAGE_PPC64 + +config ARCH_VERSTAGE_PPC64 + bool + default n + +config ARCH_ROMSTAGE_PPC64 + bool + default n + +config ARCH_RAMSTAGE_PPC64 + bool + default n diff --git a/src/arch/power8/Makefile.inc b/src/arch/ppc64/Makefile.inc similarity index 88% rename from src/arch/power8/Makefile.inc rename to src/arch/ppc64/Makefile.inc index 98f9db1..99d8634 100644 --- a/src/arch/power8/Makefile.inc +++ b/src/arch/ppc64/Makefile.inc @@ -16,14 +16,14 @@ ## ################################################################################ -power8_flags = -I$(src)/arch/power8/ -mbig-endian -mcpu=power8 -mtune=power8 +ppc64_flags = -I$(src)/arch/ppc64/ -mbig-endian -mcpu=power8 -mtune=power8 -power8_asm_flags = +ppc64_asm_flags = ################################################################################ ## bootblock ################################################################################ -ifeq ($(CONFIG_ARCH_BOOTBLOCK_POWER8),y) +ifeq ($(CONFIG_ARCH_BOOTBLOCK_PPC64),y) bootblock-y = bootblock.S stages.c bootblock-y += boot.c @@ -35,7 +35,7 @@ $(top)/src/lib/memmove.c \ $(top)/src/lib/memset.c -bootblock-generic-ccopts += $(power8_flags) +bootblock-generic-ccopts += $(ppc64_flags) $(objcbfs)/bootblock.debug: $$(bootblock-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" @@ -48,7 +48,7 @@ ################################################################################ ## romstage ################################################################################ -ifeq ($(CONFIG_ARCH_ROMSTAGE_POWER8),y) +ifeq ($(CONFIG_ARCH_ROMSTAGE_PPC64),y) romstage-y += boot.c romstage-y += stages.c @@ -68,15 +68,15 @@ @printf " LINK $(subst $(obj)/,,$(@))\n" $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(call src-to-obj,romstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage) -romstage-c-ccopts += $(power8_flags) -romstage-S-ccopts += $(power8_asm_flags) +romstage-c-ccopts += $(ppc64_flags) +romstage-S-ccopts += $(ppc64_asm_flags) endif ################################################################################ ## ramstage ################################################################################ -ifeq ($(CONFIG_ARCH_RAMSTAGE_POWER8),y) +ifeq ($(CONFIG_ARCH_RAMSTAGE_PPC64),y) ramstage-y += rom_media.c ramstage-y += stages.c @@ -102,7 +102,7 @@ @printf " CC $(subst $(obj)/,,$(@))\n" $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(call src-to-obj,ramstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage) -ramstage-c-ccopts += $(power8_flags) -ramstage-S-ccopts += $(power8_asm_flags) +ramstage-c-ccopts += $(ppc64_flags) +ramstage-S-ccopts += $(ppc64_asm_flags) endif diff --git a/src/arch/power8/boot.c b/src/arch/ppc64/boot.c similarity index 100% rename from src/arch/power8/boot.c rename to src/arch/ppc64/boot.c diff --git a/src/arch/power8/bootblock.S b/src/arch/ppc64/bootblock.S similarity index 100% rename from src/arch/power8/bootblock.S rename to src/arch/ppc64/bootblock.S diff --git a/src/arch/power8/id.ld b/src/arch/ppc64/id.ld similarity index 100% rename from src/arch/power8/id.ld rename to src/arch/ppc64/id.ld diff --git a/src/arch/power8/include/arch/byteorder.h b/src/arch/ppc64/include/arch/byteorder.h similarity index 100% rename from src/arch/power8/include/arch/byteorder.h rename to src/arch/ppc64/include/arch/byteorder.h diff --git a/src/arch/power8/include/arch/cache.h b/src/arch/ppc64/include/arch/cache.h similarity index 100% rename from src/arch/power8/include/arch/cache.h rename to src/arch/ppc64/include/arch/cache.h diff --git a/src/arch/power8/include/arch/cbconfig.h b/src/arch/ppc64/include/arch/cbconfig.h similarity index 100% rename from src/arch/power8/include/arch/cbconfig.h rename to src/arch/ppc64/include/arch/cbconfig.h diff --git a/src/arch/power8/include/arch/cpu.h b/src/arch/ppc64/include/arch/cpu.h similarity index 86% rename from src/arch/power8/include/arch/cpu.h rename to src/arch/ppc64/include/arch/cpu.h index a4421e5..3238bfb 100644 --- a/src/arch/power8/include/arch/cpu.h +++ b/src/arch/ppc64/include/arch/cpu.h @@ -36,10 +36,10 @@ #endif }; -struct cpuinfo_power8 { - uint8_t power8; /* CPU family */ - uint8_t power8_vendor; /* CPU vendor */ - uint8_t power8_model; +struct cpuinfo_ppc64 { + uint8_t ppc64; /* CPU family */ + uint8_t ppc64_vendor; /* CPU vendor */ + uint8_t ppc64_model; }; #endif diff --git a/src/arch/power8/include/arch/early_variables.h b/src/arch/ppc64/include/arch/early_variables.h similarity index 100% rename from src/arch/power8/include/arch/early_variables.h rename to src/arch/ppc64/include/arch/early_variables.h diff --git a/src/arch/power8/include/arch/exception.h b/src/arch/ppc64/include/arch/exception.h similarity index 100% rename from src/arch/power8/include/arch/exception.h rename to src/arch/ppc64/include/arch/exception.h diff --git a/src/arch/power8/include/arch/header.ld b/src/arch/ppc64/include/arch/header.ld similarity index 100% rename from src/arch/power8/include/arch/header.ld rename to src/arch/ppc64/include/arch/header.ld diff --git a/src/arch/power8/include/arch/hlt.h b/src/arch/ppc64/include/arch/hlt.h similarity index 100% rename from src/arch/power8/include/arch/hlt.h rename to src/arch/ppc64/include/arch/hlt.h diff --git a/src/arch/power8/include/arch/io.h b/src/arch/ppc64/include/arch/io.h similarity index 100% rename from src/arch/power8/include/arch/io.h rename to src/arch/ppc64/include/arch/io.h diff --git a/src/arch/power8/include/arch/memlayout.h b/src/arch/ppc64/include/arch/memlayout.h similarity index 100% rename from src/arch/power8/include/arch/memlayout.h rename to src/arch/ppc64/include/arch/memlayout.h diff --git a/src/arch/power8/include/arch/stages.h b/src/arch/ppc64/include/arch/stages.h similarity index 100% rename from src/arch/power8/include/arch/stages.h rename to src/arch/ppc64/include/arch/stages.h diff --git a/src/arch/power8/include/stdint.h b/src/arch/ppc64/include/stdint.h similarity index 95% rename from src/arch/power8/include/stdint.h rename to src/arch/ppc64/include/stdint.h index 8cb34ee..6425824 100644 --- a/src/arch/power8/include/stdint.h +++ b/src/arch/ppc64/include/stdint.h @@ -11,8 +11,8 @@ * GNU General Public License for more details. */ -#ifndef POWER8_STDINT_H -#define POWER8_STDINT_H +#ifndef PPC64_STDINT_H +#define PPC64_STDINT_H /* Exact integral types */ typedef unsigned char uint8_t; @@ -73,4 +73,4 @@ typedef s64 intptr_t; typedef u64 uintptr_t; -#endif /* POWER8_STDINT_H */ +#endif /* PPC64_STDINT_H */ diff --git a/src/arch/power8/misc.c b/src/arch/ppc64/misc.c similarity index 100% rename from src/arch/power8/misc.c rename to src/arch/ppc64/misc.c diff --git a/src/arch/power8/prologue.inc b/src/arch/ppc64/prologue.inc similarity index 100% rename from src/arch/power8/prologue.inc rename to src/arch/ppc64/prologue.inc diff --git a/src/arch/power8/rom_media.c b/src/arch/ppc64/rom_media.c similarity index 100% rename from src/arch/power8/rom_media.c rename to src/arch/ppc64/rom_media.c diff --git a/src/arch/power8/stages.c b/src/arch/ppc64/stages.c similarity index 100% rename from src/arch/power8/stages.c rename to src/arch/ppc64/stages.c diff --git a/src/arch/power8/tables.c b/src/arch/ppc64/tables.c similarity index 100% rename from src/arch/power8/tables.c rename to src/arch/ppc64/tables.c diff --git a/src/cpu/qemu-power8/Kconfig b/src/cpu/qemu-power8/Kconfig index d273cc3..c1f8309 100644 --- a/src/cpu/qemu-power8/Kconfig +++ b/src/cpu/qemu-power8/Kconfig @@ -15,7 +15,7 @@ config CPU_QEMU_POWER8 bool - select ARCH_BOOTBLOCK_POWER8 - select ARCH_VERSTAGE_POWER8 - select ARCH_ROMSTAGE_POWER8 - select ARCH_RAMSTAGE_POWER8 + select ARCH_BOOTBLOCK_PPC64 + select ARCH_VERSTAGE_PPC64 + select ARCH_ROMSTAGE_PPC64 + select ARCH_RAMSTAGE_PPC64 diff --git a/src/device/Kconfig b/src/device/Kconfig index 016e104..66f57d9 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -85,7 +85,7 @@ # TODO: Explain differences (if any) for onboard cards. config VGA_ROM_RUN bool "Run VGA Option ROMs" - depends on PCI && (ARCH_X86 || ARCH_POWER8) && !MAINBOARD_FORCE_NATIVE_VGA_INIT + depends on PCI && (ARCH_X86 || ARCH_PPC64) && !MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_VGA_TEXT_FRAMEBUFFER help Execute VGA Option ROMs in coreboot if found. This can be used diff --git a/src/mainboard/emulation/qemu-power8/Kconfig b/src/mainboard/emulation/qemu-power8/Kconfig index 9e14cab..c756710 100644 --- a/src/mainboard/emulation/qemu-power8/Kconfig +++ b/src/mainboard/emulation/qemu-power8/Kconfig @@ -20,9 +20,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select BOARD_ROMSIZE_KB_4096 - select ARCH_BOOTBLOCK_POWER8 + select ARCH_BOOTBLOCK_PPC64 select HAVE_UART_SPECIAL - select ARCH_POWER8 + select ARCH_PPC64 select BOOT_DEVICE_NOT_SPI_FLASH select MISSING_BOARD_RESET diff --git a/toolchain.inc b/toolchain.inc index ec57b5d..0486287 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -57,7 +57,7 @@ ARCHDIR-arm64 := arm64 ARCHDIR-riscv := riscv ARCHDIR-mips := mips -ARCHDIR-power8 := power8 +ARCHDIR-ppc64 := ppc64 CFLAGS_arm += CFLAGS_arm64 += -mgeneral-regs-only @@ -65,7 +65,7 @@ CFLAGS_riscv += CFLAGS_x86_32 += CFLAGS_x86_64 += -mcmodel=large -mno-red-zone -CFLAGS_power8 += +CFLAGS_ppc64 += # Some boards only provide 2K stacks, so storing lots of data there leads to # problems. Since C rules don't allow us to statically determine the maximum @@ -85,7 +85,7 @@ CFLAGS_arm64 += -Wstack-usage=1536 CFLAGS_mips += -Wstack-usage=1536 CFLAGS_riscv += -Wstack-usage=1536 -CFLAGS_power8 += -Wstack-usage=1536 +CFLAGS_ppc64 += -Wstack-usage=1536 endif toolchain_to_dir = \ diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index 0c092d7..a8ea815 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -9,12 +9,12 @@ all all_with_gdb: $(MAKE) build-i386 build-x64 build-arm build-mips \ - build-riscv build-aarch64 build-power8 build-nds32le \ + build-riscv build-aarch64 build-ppc64 build-nds32le \ build_clang build_iasl build_make all_without_gdb: $(MAKE) SKIP_GDB=1 build-i386 build-x64 build-arm build-mips \ - build-riscv build-aarch64 build-power8 build-nds32le \ + build-riscv build-aarch64 build-ppc64 build-nds32le \ build_clang build_iasl build_make build_tools: build_gcc build_gdb @@ -63,7 +63,7 @@ # GDB is currently not supported on RISC-V @$(MAKE) build_gcc BUILD_PLATFORM=riscv-elf -build-power8: +build-ppc64: @$(MAKE) build_tools BUILD_PLATFORM=powerpc64-linux-gnu build-nds32le: @@ -85,6 +85,6 @@ .PHONY: build_gcc build_iasl build_gdb build_clang all all_with_gdb \ all_without_gdb build_tools build-i386 build-x64 build-arm \ - build-aarch64 build-mips build-riscv build-power8 build-nds32le \ + build-aarch64 build-mips build-riscv build-ppc64 build-nds32le \ clean distclean clean_tempfiles .NOTPARALLEL: diff --git a/util/crossgcc/Makefile.inc b/util/crossgcc/Makefile.inc index f7da7de..7fdc443 100644 --- a/util/crossgcc/Makefile.inc +++ b/util/crossgcc/Makefile.inc @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -TOOLCHAIN_ARCHES := i386 x64 arm aarch64 mips riscv power8 nds32le +TOOLCHAIN_ARCHES := i386 x64 arm aarch64 mips riscv ppc64 nds32le help_toolchain help:: @echo '*** Toolchain targets ***' diff --git a/util/lint/check_lint_tests b/util/lint/check_lint_tests index 5ba33c8..6b1860f 100755 --- a/util/lint/check_lint_tests +++ b/util/lint/check_lint_tests @@ -6,7 +6,7 @@ #lint-stable-000-license-headers TESTFILE000a=src/arch/x86/thread.c -TESTFILE000b=src/arch/power8/misc.c +TESTFILE000b=src/arch/ppc64/misc.c sed -i.bak 's/^[[:space:]]\*[[:space:]].*//' ${TESTFILE000a} sed -i.bak 's/^[[:space:]]\*[[:space:]]but WITHOUT ANY WARRANTY;//' ${TESTFILE000b} diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 6d82a4d..7713543 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -303,7 +303,7 @@ } # Architecture definitions -SUPPORTED_ARCHITECTURES="arm arm64 mipsel riscv x64 x86 power8" +SUPPORTED_ARCHITECTURES="arm arm64 mipsel riscv x64 x86 ppc64" # TARCH: local name for the architecture # (used as CC_${TARCH} in the build system) @@ -366,12 +366,12 @@ TENDIAN="EL" } -arch_config_power8() { - TARCH="power8" +arch_config_ppc64() { + TARCH="ppc64" TBFDARCHS="powerpc" TCLIST="powerpc64" TWIDTH="64" - TSUPP="power8" + TSUPP="ppc64 power8" TABI="linux-gnu" # there is no generic ABI on ppc64 CC_RT_EXTRA_GCC="-mcpu=power8 -mbig-endian" } -- To view, visit https://review.coreboot.org/c/coreboot/+/29943 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d6f08b12a9ffc8a652ddcd6f24ad85ecb33ca52 Gerrit-Change-Number: 29943 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: cpu/amd/quadcore/quadcore.c: Fix message error "timeout not used"
by HAOUAS Elyes (Code Review) 29 Nov '18

29 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29941 to look at the new patch set (#4). Change subject: cpu/amd/quadcore/quadcore.c: Fix message error "timeout not used" ...................................................................... cpu/amd/quadcore/quadcore.c: Fix message error "timeout not used" Change-Id: I826ba637c77dcdac04d0494c00b1b90e5303c63e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/quadcore/quadcore.c 1 file changed, 9 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/29941/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/29941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I826ba637c77dcdac04d0494c00b1b90e5303c63e Gerrit-Change-Number: 29941 Gerrit-PatchSet: 4 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: cpu/amd/quadcore/quadcore.c: Fix message error "timeout not used"
by HAOUAS Elyes (Code Review) 29 Nov '18

29 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29941 to look at the new patch set (#3). Change subject: cpu/amd/quadcore/quadcore.c: Fix message error "timeout not used" ...................................................................... cpu/amd/quadcore/quadcore.c: Fix message error "timeout not used" Change-Id: I826ba637c77dcdac04d0494c00b1b90e5303c63e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/quadcore/quadcore.c 1 file changed, 9 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/29941/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/29941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I826ba637c77dcdac04d0494c00b1b90e5303c63e Gerrit-Change-Number: 29941 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: cpu/amd/quadcore/quadcore.c: Fix message error "timeout not used"
by build bot (Jenkins) (Code Review) 29 Nov '18

29 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29941 ) Change subject: cpu/amd/quadcore/quadcore.c: Fix message error "timeout not used" ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/#/c/29941/2/src/cpu/amd/quadcore/quadcore.c File src/cpu/amd/quadcore/quadcore.c: https://review.coreboot.org/#/c/29941/2/src/cpu/amd/quadcore/quadcore.c@106 PS2, Line 106: } else { code indent should use tabs where possible https://review.coreboot.org/#/c/29941/2/src/cpu/amd/quadcore/quadcore.c@106 PS2, Line 106: } else { please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/29941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I826ba637c77dcdac04d0494c00b1b90e5303c63e Gerrit-Change-Number: 29941 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Thu, 29 Nov 2018 21:25:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: cpu/amd/quadcore/quadcore.c: Fix message error "timeout not used"
by HAOUAS Elyes (Code Review) 29 Nov '18

29 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29941 to look at the new patch set (#2). Change subject: cpu/amd/quadcore/quadcore.c: Fix message error "timeout not used" ...................................................................... cpu/amd/quadcore/quadcore.c: Fix message error "timeout not used" Change-Id: I826ba637c77dcdac04d0494c00b1b90e5303c63e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/quadcore/quadcore.c 1 file changed, 9 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/29941/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I826ba637c77dcdac04d0494c00b1b90e5303c63e Gerrit-Change-Number: 29941 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: sb/intel/lynxpoint/usb_{e, x}hci.c: Don't use device_t
by HAOUAS Elyes (Code Review) 29 Nov '18

29 Nov '18

Hello Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29932 to look at the new patch set (#2). Change subject: sb/intel/lynxpoint/usb_{e,x}hci.c: Don't use device_t ...................................................................... sb/intel/lynxpoint/usb_{e,x}hci.c: Don't use device_t Use of device_t is deprecated. Change-Id: Ie75450c844e2317ded157465eb0fc6a9ec1b3ab0 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/lynxpoint/usb_ehci.c M src/southbridge/intel/lynxpoint/usb_xhci.c 2 files changed, 9 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/29932/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie75450c844e2317ded157465eb0fc6a9ec1b3ab0 Gerrit-Change-Number: 29932 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: sb/intel/lynxpoint/usb_ehci.c: Don't use device_t
by HAOUAS Elyes (Code Review) 29 Nov '18

29 Nov '18

HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29933 ) Change subject: sb/intel/lynxpoint/usb_ehci.c: Don't use device_t ...................................................................... Abandoned see 29932 -- To view, visit https://review.coreboot.org/c/coreboot/+/29933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2c24bbe6181ea6cf484c33a9fbf119f853efcf4 Gerrit-Change-Number: 29933 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: Crash Test
by HAOUAS Elyes (Code Review) 29 Nov '18

29 Nov '18

HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29926 ) Change subject: Crash Test ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/29926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3dde296ab4b84add8a8ab6a3bb5ecb65da2c158 Gerrit-Change-Number: 29926 Gerrit-PatchSet: 5 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: src/device/dram/ddr3.c: Remove not used variable
by HAOUAS Elyes (Code Review) 29 Nov '18

29 Nov '18

HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29937 ) Change subject: src/device/dram/ddr3.c: Remove not used variable ...................................................................... Abandoned see 29917 -- To view, visit https://review.coreboot.org/c/coreboot/+/29937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4947f1798da558c69d7ff7060cf7de1c171b031 Gerrit-Change-Number: 29937 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: sb/intel/i82371eb/fadt.c: Remove not used variable
by HAOUAS Elyes (Code Review) 29 Nov '18

29 Nov '18

HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29939 ) Change subject: sb/intel/i82371eb/fadt.c: Remove not used variable ...................................................................... Abandoned see 29917 -- To view, visit https://review.coreboot.org/c/coreboot/+/29939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06c693a6b95532df7bbe6b007c048e9526485a74 Gerrit-Change-Number: 29939 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: arch/arm64/boot.c: Remove not used variable
by HAOUAS Elyes (Code Review) 29 Nov '18

29 Nov '18

HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29940 ) Change subject: arch/arm64/boot.c: Remove not used variable ...................................................................... Abandoned see 29917 -- To view, visit https://review.coreboot.org/c/coreboot/+/29940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic275f3d3377b4bd40ca9fb591332dc9b2fd9effe Gerrit-Change-Number: 29940 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: sb/amd/common/amd_pci_util.c: Remove not used variable
by HAOUAS Elyes (Code Review) 29 Nov '18

29 Nov '18

HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29942 ) Change subject: sb/amd/common/amd_pci_util.c: Remove not used variable ...................................................................... Abandoned see 29917 -- To view, visit https://review.coreboot.org/c/coreboot/+/29942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie239d067529f6cdea2bea5ae7327562ccb080196 Gerrit-Change-Number: 29942 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: {sb, lib, drivers, device, arch}: Remove not used variable
by HAOUAS Elyes (Code Review) 29 Nov '18

29 Nov '18

Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29917 to look at the new patch set (#4). Change subject: {sb,lib,drivers,device,arch}: Remove not used variable ...................................................................... {sb,lib,drivers,device,arch}: Remove not used variable Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm64/boot.c M src/device/dram/ddr3.c M src/drivers/spi/sst.c M src/lib/selfboot.c M src/southbridge/amd/common/amd_pci_util.c M src/southbridge/intel/i82371eb/fadt.c 6 files changed, 5 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/29917/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 4 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: cpu/amd/quadcore/quadcore.c: Remove not used variable
by HAOUAS Elyes (Code Review) 29 Nov '18

29 Nov '18

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29941 ) Change subject: cpu/amd/quadcore/quadcore.c: Remove not used variable ...................................................................... Patch Set 1: > Would it be possible to group these into reasonable sized patches - > maybe 15 or 20 changes in a patch? Say do all of the ones in the > src/cpu/amd or src/cpu subdirectory instead of doing them > one-by-one? If that's not needed, and there are really only a few > issues, I'm fine with them being done one-off, but I'm doubtful > that that's the case. Sure ! :) -- To view, visit https://review.coreboot.org/c/coreboot/+/29941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I826ba637c77dcdac04d0494c00b1b90e5303c63e Gerrit-Change-Number: 29941 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Thu, 29 Nov 2018 20:12:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/amd/common/amd_pci_util.c: Remove not used variable
by HAOUAS Elyes (Code Review) 29 Nov '18

29 Nov '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29942 Change subject: sb/amd/common/amd_pci_util.c: Remove not used variable ...................................................................... sb/amd/common/amd_pci_util.c: Remove not used variable Change-Id: Ie239d067529f6cdea2bea5ae7327562ccb080196 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/amd/common/amd_pci_util.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/29942/1 diff --git a/src/southbridge/amd/common/amd_pci_util.c b/src/southbridge/amd/common/amd_pci_util.c index ca76809..acec116 100644 --- a/src/southbridge/amd/common/amd_pci_util.c +++ b/src/southbridge/amd/common/amd_pci_util.c @@ -100,7 +100,6 @@ u16 target_pin = 0; /* Pin we will search our tables for */ u16 int_line = 0; /* IRQ number read from PCI_INTR table and programmed to INT_LINE reg 0x3C */ u16 pci_intr_idx = 0; /* Index into PCI_INTR table, 0xC00/0xC01 */ - u8 bus = 0; /* A PCI Device Bus number */ u16 devfn = 0; /* A PCI Device and Function number */ u8 bridged_device = 0; /* This device is on a PCI bridge */ u32 i = 0; @@ -132,7 +131,6 @@ if (int_pin < 1 || int_pin > 4) continue; /* Device has invalid INT_PIN so skip it */ - bus = target_dev->bus->secondary; devfn = target_dev->path.pci.devfn; /* -- To view, visit https://review.coreboot.org/c/coreboot/+/29942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie239d067529f6cdea2bea5ae7327562ccb080196 Gerrit-Change-Number: 29942 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Crash Test
by Martin Roth (Code Review) 29 Nov '18

29 Nov '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29926 ) Change subject: Crash Test ...................................................................... Patch Set 4: You might want to turn off warnings-as-errors to see the entire list of issues instead of having the build stop on the first one. Also, why are you disabling the other warnings in this patch? -- To view, visit https://review.coreboot.org/c/coreboot/+/29926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3dde296ab4b84add8a8ab6a3bb5ecb65da2c158 Gerrit-Change-Number: 29926 Gerrit-PatchSet: 4 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Nov 2018 19:55:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: cpu/amd/quadcore/quadcore.c: Remove not used variable
by Martin Roth (Code Review) 29 Nov '18

29 Nov '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29941 ) Change subject: cpu/amd/quadcore/quadcore.c: Remove not used variable ...................................................................... Patch Set 1: Would it be possible to group these into reasonable sized patches - maybe 15 or 20 changes in a patch? Say do all of the ones in the src/cpu/amd or src/cpu subdirectory instead of doing them one-by-one? If that's not needed, and there are really only a few issues, I'm fine with them being done one-off, but I'm doubtful that that's the case. -- To view, visit https://review.coreboot.org/c/coreboot/+/29941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I826ba637c77dcdac04d0494c00b1b90e5303c63e Gerrit-Change-Number: 29941 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Thu, 29 Nov 2018 19:54:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/arm64/boot.c: Remove not used variable
by HAOUAS Elyes (Code Review) 29 Nov '18

29 Nov '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29940 Change subject: arch/arm64/boot.c: Remove not used variable ...................................................................... arch/arm64/boot.c: Remove not used variable Change-Id: Ic275f3d3377b4bd40ca9fb591332dc9b2fd9effe Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm64/boot.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/29940/1 diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c index 54a33e0..261a562 100644 --- a/src/arch/arm64/boot.c +++ b/src/arch/arm64/boot.c @@ -40,7 +40,6 @@ void arch_prog_run(struct prog *prog) { void (*doit)(void *); - void *arg; if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { run_payload(prog); @@ -48,7 +47,6 @@ } doit = prog_entry(prog); - arg = prog_entry_arg(prog); doit(prog_entry_arg(prog)); } -- To view, visit https://review.coreboot.org/c/coreboot/+/29940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic275f3d3377b4bd40ca9fb591332dc9b2fd9effe Gerrit-Change-Number: 29940 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/amd/quadcore/quadcore.c: Remove not used variable
by HAOUAS Elyes (Code Review) 29 Nov '18

29 Nov '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29941 Change subject: cpu/amd/quadcore/quadcore.c: Remove not used variable ...................................................................... cpu/amd/quadcore/quadcore.c: Remove not used variable Change-Id: I826ba637c77dcdac04d0494c00b1b90e5303c63e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/quadcore/quadcore.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/29941/1 diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c index c2d277a..e47c4a3 100644 --- a/src/cpu/amd/quadcore/quadcore.c +++ b/src/cpu/amd/quadcore/quadcore.c @@ -94,13 +94,10 @@ */ /* Wait for the first core of each compute unit to start... */ - uint32_t timeout; for (i = 1; i < cores + 1; i++) { if (!(i & 0x1)) { uint32_t ap_apicid = get_boot_apic_id(nodeid, i); - timeout = wait_cpu_state(ap_apicid, - F10_APSTATE_ASLEEP, F10_APSTATE_ASLEEP); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/29941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I826ba637c77dcdac04d0494c00b1b90e5303c63e Gerrit-Change-Number: 29941 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/i82371eb/fadt.c: Remove not used variable
by HAOUAS Elyes (Code Review) 29 Nov '18

29 Nov '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29939 Change subject: sb/intel/i82371eb/fadt.c: Remove not used variable ...................................................................... sb/intel/i82371eb/fadt.c: Remove not used variable Change-Id: I06c693a6b95532df7bbe6b007c048e9526485a74 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82371eb/fadt.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/29939/1 diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index 41ad31c..35ee083 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -31,11 +31,8 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) { acpi_header_t *header = &(fadt->header); - struct device *dev; /* Power management controller */ - dev = dev_find_device(PCI_VENDOR_ID_INTEL, - PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI, 0); memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); -- To view, visit https://review.coreboot.org/c/coreboot/+/29939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06c693a6b95532df7bbe6b007c048e9526485a74 Gerrit-Change-Number: 29939 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: lib/selfboot.c: Remove not used variable
by HAOUAS Elyes (Code Review) 29 Nov '18

29 Nov '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29938 Change subject: lib/selfboot.c: Remove not used variable ...................................................................... lib/selfboot.c: Remove not used variable Change-Id: Iaba1ac1967fddae843cee61ef671d4f66648b078 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/lib/selfboot.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/29938/1 diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 9c52cd6..f1c2ba4 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -144,9 +144,9 @@ { uint8_t *dest; size_t memsz; - struct cbfs_payload_segment *first_segment, *seg, segment; + struct cbfs_payload_segment *seg, segment; - for (first_segment = seg = cbfssegs;; ++seg) { + for (seg = cbfssegs;; ++seg) { printk(BIOS_DEBUG, "Checking segment from ROM address 0x%p\n", seg); cbfs_decode_payload_segment(&segment, seg); dest = (uint8_t *)(uintptr_t)segment.load_addr; -- To view, visit https://review.coreboot.org/c/coreboot/+/29938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba1ac1967fddae843cee61ef671d4f66648b078 Gerrit-Change-Number: 29938 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/device/dram/ddr3.c: Remove not used variable
by HAOUAS Elyes (Code Review) 29 Nov '18

29 Nov '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29937 Change subject: src/device/dram/ddr3.c: Remove not used variable ...................................................................... src/device/dram/ddr3.c: Remove not used variable Change-Id: Ib4947f1798da558c69d7ff7060cf7de1c171b031 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/dram/ddr3.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/29937/1 diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index f27fdcb..e545b4d 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -136,7 +136,7 @@ u8 reg8; u32 mtb; /* medium time base */ u32 ftb; /* fine time base */ - unsigned int val, param; + unsigned int val; ret = SPD_STATUS_OK; @@ -173,8 +173,7 @@ printram(" Invalid number of memory banks\n"); ret = SPD_STATUS_INVALID_FIELD; } - param = 1 << (val + 3); - printram(" Banks : %u\n", param); + printram(" Banks : %u\n", 1 << (val + 3)); /* SDRAM capacity */ capacity_shift = reg8 & 0x0f; if (capacity_shift > 0x06) { -- To view, visit https://review.coreboot.org/c/coreboot/+/29937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4947f1798da558c69d7ff7060cf7de1c171b031 Gerrit-Change-Number: 29937 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Crash Test
by Martin Roth (Code Review) 29 Nov '18

29 Nov '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29926 ) Change subject: Crash Test ...................................................................... Patch Set 2: Good check. We should get those fixed - no need for these to be ignored. -- To view, visit https://review.coreboot.org/c/coreboot/+/29926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3dde296ab4b84add8a8ab6a3bb5ecb65da2c158 Gerrit-Change-Number: 29926 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Nov 2018 18:17:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: Documentation: Add disassembly guide for x220
by Patrick Rudolph (Code Review) 29 Nov '18

29 Nov '18

Hello Arthur Heymans, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29936 to look at the new patch set (#2). Change subject: Documentation: Add disassembly guide for x220 ...................................................................... Documentation: Add disassembly guide for x220 Add pictures and basic information. Copyright CC BY-SA 2016 Karl Cordes Change-Id: I06618092817b91062b35f3b054a82cf573f641b8 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- A Documentation/mainboard/lenovo/diss_x220_1.jpg A Documentation/mainboard/lenovo/diss_x220_2.jpg M Documentation/mainboard/lenovo/xx20_series.md 3 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/29936/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06618092817b91062b35f3b054a82cf573f641b8 Gerrit-Change-Number: 29936 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: google/grunt: Update hynix-H5ANAG6NAMR-UH.spd.hex SPD file Module Par...
by Martin Roth (Code Review) 29 Nov '18

29 Nov '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29873 ) Change subject: google/grunt: Update hynix-H5ANAG6NAMR-UH.spd.hex SPD file Module Part Number ...................................................................... google/grunt: Update hynix-H5ANAG6NAMR-UH.spd.hex SPD file Module Part Number Correct Ram_ID=0b0001 SPD Module Part Number to "H5ANAG6NAMR-UH" from "HMAA51S6AMR6N-UH". BUG=b:120000816 BRANCH=master TEST=mosys memory spd print all Change-Id: I59d920498ff6b73e9e7b2887771ad6bc6c6c0b66 Signed-off-by: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/29873 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5ANAG6NAMR-UH.spd.hex 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5ANAG6NAMR-UH.spd.hex b/src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5ANAG6NAMR-UH.spd.hex index bd184ad..0071c88 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5ANAG6NAMR-UH.spd.hex +++ b/src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5ANAG6NAMR-UH.spd.hex @@ -19,8 +19,8 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80 AD 01 00 00 00 00 00 00 48 4D 41 41 35 31 53 -36 41 4D 52 36 4E 2D 55 48 20 20 20 20 00 80 AD +80 AD 01 00 00 00 00 00 00 48 35 41 4E 41 47 36 +4E 41 4D 52 2D 55 48 20 20 20 20 20 20 00 80 AD FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/29873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59d920498ff6b73e9e7b2887771ad6bc6c6c0b66 Gerrit-Change-Number: 29873 Gerrit-PatchSet: 2 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: google/grunt: Update hynix-H5ANAG6NAMR-UH.spd.hex SPD file Module Par...
by Martin Roth (Code Review) 29 Nov '18

29 Nov '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29873 ) Change subject: google/grunt: Update hynix-H5ANAG6NAMR-UH.spd.hex SPD file Module Part Number ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59d920498ff6b73e9e7b2887771ad6bc6c6c0b66 Gerrit-Change-Number: 29873 Gerrit-PatchSet: 1 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Nov 2018 18:07:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: Documentation: Add disassembly guide for x220
by Arthur Heymans (Code Review) 29 Nov '18

29 Nov '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29936 ) Change subject: Documentation: Add disassembly guide for x220 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06618092817b91062b35f3b054a82cf573f641b8 Gerrit-Change-Number: 29936 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Nov 2018 17:59:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: Documentation: Add disassembly guide for x220
by Patrick Rudolph (Code Review) 29 Nov '18

29 Nov '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29936 Change subject: Documentation: Add disassembly guide for x220 ...................................................................... Documentation: Add disassembly guide for x220 Add pictures and basic information. Copyright CC BY-SA 2016 Karl Cordes Change-Id: I06618092817b91062b35f3b054a82cf573f641b8 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- A Documentation/mainboard/lenovo/diss_x220_1.jpg A Documentation/mainboard/lenovo/diss_x220_2.jpg M Documentation/mainboard/lenovo/xx20_series.md 3 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/29936/1 diff --git a/Documentation/mainboard/lenovo/diss_x220_1.jpg b/Documentation/mainboard/lenovo/diss_x220_1.jpg new file mode 100644 index 0000000..7e81373 --- /dev/null +++ b/Documentation/mainboard/lenovo/diss_x220_1.jpg Binary files differ diff --git a/Documentation/mainboard/lenovo/diss_x220_2.jpg b/Documentation/mainboard/lenovo/diss_x220_2.jpg new file mode 100644 index 0000000..8e3b252 --- /dev/null +++ b/Documentation/mainboard/lenovo/diss_x220_2.jpg Binary files differ diff --git a/Documentation/mainboard/lenovo/xx20_series.md b/Documentation/mainboard/lenovo/xx20_series.md index 8603853..cc835d1 100644 --- a/Documentation/mainboard/lenovo/xx20_series.md +++ b/Documentation/mainboard/lenovo/xx20_series.md @@ -37,6 +37,28 @@ Please also have a look at :doc:`../../flash_tutorial/index`. ``` +## Dissasemble instructions + +1. Remove the keyboard. +2. Remove the palm rest. + +The disassembled device looks like: +![][dis1] + +[dis1]: diss_x220_1.jpg + +3. Remove the foil right next to the SD-Card reader. +4. On x220: you'll find one flash IC + On x230: you'll find two flash ICs +5. You can easily flash it using a pomona test clip + +Closeup view of the flash IC: +![][dis2] + +[dis2]: diss_x220_2.jpg + +Pictures by `Copyright 2016 Karl Cordes` + ## Flash layout There's one 8MiB flash which contains IFD, GBE, ME and BIOS regions. On Lenovo's UEFI the EC firmware update is placed at the start of the BIOS -- To view, visit https://review.coreboot.org/c/coreboot/+/29936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06618092817b91062b35f3b054a82cf573f641b8 Gerrit-Change-Number: 29936 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/xcompile/xcompile: Enable x86_64 support
by Patrick Rudolph (Code Review) 29 Nov '18

29 Nov '18

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29877 to look at the new patch set (#3). Change subject: util/xcompile/xcompile: Enable x86_64 support ...................................................................... util/xcompile/xcompile: Enable x86_64 support Similar to i686 on x86_32, compile for nocona on x86_64. Nocona is the first Pentium 4 CPU that has long mode support. Required for 64bit support. Change-Id: Ied28f98f89610a748be8d66cf35814e9112a4407 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M util/xcompile/xcompile 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/29877/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/29877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied28f98f89610a748be8d66cf35814e9112a4407 Gerrit-Change-Number: 29877 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: LinuxBoot: fix initramfs xz compression
by Marcello Sylvester Bauer (Code Review) 29 Nov '18

29 Nov '18

Marcello Sylvester Bauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29935 Change subject: LinuxBoot: fix initramfs xz compression ...................................................................... LinuxBoot: fix initramfs xz compression Add the flag '--check=crc32' to the xz compression to use CRC32 for the integrity check. The linux kernel does not support CRC64 for integrity checks, which is the default flag on most xz applications. Change-Id: I738bd99ef22aa053dc198df5595e1878069de13e Signed-off-by: Marcello Sylvester Bauer <info(a)marcellobauer.com> --- M payloads/external/LinuxBoot/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/29935/1 diff --git a/payloads/external/LinuxBoot/Makefile b/payloads/external/LinuxBoot/Makefile index 8016095..a67b16a 100644 --- a/payloads/external/LinuxBoot/Makefile +++ b/payloads/external/LinuxBoot/Makefile @@ -39,7 +39,7 @@ initramfs_compressed: initramfs ifeq ($(CONFIG_LINUXBOOT_INITRAMFS_COMPRESSION_XZ),y) - xz --keep --force --lzma2=dict=1MiB $(top)/$(CONFIG_LINUXBOOT_INITRAMFS) + xz --keep --force --check=crc32 --lzma2=dict=1MiB $(top)/$(CONFIG_LINUXBOOT_INITRAMFS) endif ifeq ($(CONFIG_LINUXBOOT_COMPILE_KERNEL),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/29935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I738bd99ef22aa053dc198df5595e1878069de13e Gerrit-Change-Number: 29935 Gerrit-PatchSet: 1 Gerrit-Owner: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/broadwell: Implement postcar stage
by Matt DeVillier (Code Review) 29 Nov '18

29 Nov '18

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29927 ) Change subject: soc/intel/broadwell: Implement postcar stage ...................................................................... Patch Set 1: Code-Review+1 google/guado builds/boots normally -- To view, visit https://review.coreboot.org/c/coreboot/+/29927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I428832a2d7e46ce61a7f9bd498b609feb4518eb0 Gerrit-Change-Number: 29927 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Nov 2018 16:23:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: Untangle CBFS microcode updates
by Nico Huber (Code Review) 29 Nov '18

29 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29934 ) Change subject: Untangle CBFS microcode updates ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29934/1/src/cpu/Kconfig File src/cpu/Kconfig: https://review.coreboot.org/#/c/29934/1/src/cpu/Kconfig@107 PS1, Line 107: select USE_CPU_MICROCODE_CBFS_BINS depends on !POOR_MICROCODE_MAINTENANCE -- To view, visit https://review.coreboot.org/c/coreboot/+/29934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib403402e240d3531640a62ce93b7a93b4ef6ca5e Gerrit-Change-Number: 29934 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Comment-Date: Thu, 29 Nov 2018 16:10:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: Untangle CBFS microcode updates
by Nico Huber (Code Review) 29 Nov '18

29 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29934 Change subject: Untangle CBFS microcode updates ...................................................................... Untangle CBFS microcode updates Change-Id: Ib403402e240d3531640a62ce93b7a93b4ef6ca5e Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M Makefile.inc M src/cpu/Kconfig M src/cpu/Makefile.inc M src/cpu/amd/family_10h-family_15h/Kconfig M src/cpu/amd/family_10h-family_15h/Makefile.inc M src/cpu/intel/fsp_model_406dx/Kconfig M src/cpu/intel/microcode/Makefile.inc M src/soc/intel/apollolake/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/fsp_baytrail/Kconfig M src/soc/intel/fsp_broadwell_de/Kconfig M src/soc/intel/icelake/Kconfig 12 files changed, 61 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/29934/1 diff --git a/Makefile.inc b/Makefile.inc index aaae7bc..e24c859 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1048,7 +1048,7 @@ $(FIT_OPTIONS) endif -ifeq ($(CONFIG_CPU_MICROCODE_CBFS_GENERATE),y) +ifeq ($(CONFIG_USE_CPU_MICROCODE_CBFS_BINS),y) @printf " UPDATE-FIT\n" $(CBFSTOOL) $@.tmp update-fit -n cpu_microcode_blob.bin -x $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \ $(FIT_OPTIONS) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index a7cb99e..807a4ce 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -84,14 +84,27 @@ This is selected by a board or chipset to set the default for the microcode source choice to a list of external microcode headers +config POOR_MICROCODE_MAINTENANCE + bool + help + Selected by platforms that don't maintain microcode updates in the + blobs repo. + +config USE_CPU_MICROCODE_CBFS_BINS + bool + help + Selected to add binary microcode files (`cpu_microcode_bins` in the + makefiles) to CBFS. + choice prompt "Include CPU microcode in CBFS" if ARCH_X86 default CPU_MICROCODE_CBFS_EXTERNAL_HEADER if USES_MICROCODE_HEADER_FILES - default CPU_MICROCODE_CBFS_GENERATE if SUPPORT_CPU_UCODE_IN_CBFS && USE_BLOBS - default CPU_MICROCODE_CBFS_NONE if !SUPPORT_CPU_UCODE_IN_CBFS + default CPU_MICROCODE_CBFS_NONE if POOR_MICROCODE_MAINTENANCE + depends on SUPPORT_CPU_UCODE_IN_CBFS -config CPU_MICROCODE_CBFS_GENERATE +config CPU_MICROCODE_CBFS_DEFAULT_BINS bool "Generate from tree" + select USE_CPU_MICROCODE_CBFS_BINS help Select this option if you want microcode updates to be assembled when building coreboot and included in the final image as a separate CBFS @@ -102,8 +115,27 @@ If unsure, select this option. +config CPU_MICROCODE_CBFS_EXTERNAL_BINS + bool "Include external microcode binary" + select USE_CPU_MICROCODE_CBFS_BINS + depends on !CPU_MICROCODE_MULTIPLE_FILES + help + Select this option if you want to include external binary files + in the CPUs native format. They will be included as a separate + file in CBFS. + + A word of caution: only select this option if you are sure the + microcode that you have is newer than the microcode shipping with + coreboot. + + The microcode file may be removed from the ROM image at a later + time with cbfstool, if desired. + + If unsure, and applicable, select "Generate from tree" + config CPU_MICROCODE_CBFS_EXTERNAL_HEADER bool "Include external microcode header files" + depends on !CPU_MICROCODE_MULTIPLE_FILES help Select this option if you want to include external c header files containing the CPU microcode. This will be included as a separate @@ -116,25 +148,17 @@ The microcode file may be removed from the ROM image at a later time with cbfstool, if desired. - If unsure, select "Generate from tree" + If unsure, and applicable, select "Generate from tree" config CPU_MICROCODE_CBFS_NONE bool "Do not include microcode updates" help Select this option if you do not want CPU microcode included in CBFS. - Note that for some CPUs, the microcode is hard-coded into the source - tree and is not loaded from CBFS. In this case, microcode will still - be updated. There is a push to move all microcode to CBFS, but this - change is not implemented for all CPUs. - - This option currently applies to: - - Intel SandyBridge/IvyBridge - - VIA Nano Microcode may be added to the ROM image at a later time with cbfstool, if desired. - If unsure, select "Generate from tree" + If unsure, and applicable, select "Generate from tree" The GOOD: Microcode updates intend to solve issues that have been discovered @@ -164,8 +188,6 @@ config CPU_MICROCODE_MULTIPLE_FILES bool - default n - depends on CPU_MICROCODE_CBFS_GENERATE help Select this option to install separate microcode container files into CBFS instead of using the traditional monolithic microcode file format. @@ -179,7 +201,7 @@ config CPU_UCODE_BINARIES string "Microcode binary path and filename" - depends on CPU_MICROCODE_CBFS_GENERATE + depends on CPU_MICROCODE_CBFS_EXTERNAL_BINS default "" help Some platforms have microcode in the blobs directory, and these can diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 72fc29c..57241f6 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -17,7 +17,7 @@ ################################################################################ ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y) -cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += cpu_microcode_blob.bin +cbfs-files-$(CONFIG_USE_CPU_MICROCODE_CBFS_BINS) += cpu_microcode_blob.bin endif ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) @@ -29,6 +29,11 @@ util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES) endif +ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS),y) +cpu_microcode_bins := $(call strip_quotes,$(CONFIG_CPU_UCODE_BINARIES)) +endif +# otherwise `cpu_microcode_bins` should be filled by platform makefiles + # We just mash all microcode binaries together into one binary to rule them all. # This approach assumes that the microcode binaries are properly padded, and # their headers specify the correct size. This works fairly well on isolatied @@ -37,21 +42,26 @@ # there is only one microcode binary (i.e. one container), then we don't have # this issue, and this rule will continue to work. $(obj)/cpu_microcode_blob.bin: $$(wildcard $$(cpu_microcode_bins)) + NO_MICROCODE_BINS=1; \ for bin in $(cpu_microcode_bins); do \ + NO_MICROCODE_BINS=0; \ if [ ! -f "$$bin" ]; then \ echo "Microcode error: $$bin does not exist"; \ NO_MICROCODE_FILE=1; \ fi; \ done; \ if [ -n "$$NO_MICROCODE_FILE" ]; then \ - if [ -z "$(CONFIG_USE_BLOBS)" ] && [ -n "$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)" ]; then \ + if [ -z "$(CONFIG_USE_BLOBS)" ] && [ -n "$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS)" ]; then \ echo "Try enabling binary-only repository in Kconfig 'General setup' menu."; \ fi; \ false; \ fi + if [ "$$NO_MICROCODE_BINS" -eq 1 ]; then \ + false; \ + fi @printf " MICROCODE $(subst $(obj)/,,$(@))\n" @echo $(cpu_microcode_bins) - cat /dev/null $+ > $@ + cat $+ > $@ cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin cpu_microcode_blob.bin-type := microcode diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig index 8e90247..5193d1d 100644 --- a/src/cpu/amd/family_10h-family_15h/Kconfig +++ b/src/cpu/amd/family_10h-family_15h/Kconfig @@ -10,7 +10,7 @@ select UDELAY_LAPIC select HAVE_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS - select CPU_MICROCODE_MULTIPLE_FILES if !CPU_MICROCODE_CBFS_NONE + select CPU_MICROCODE_MULTIPLE_FILES select ACPI_HUGE_LOWMEM_BACKUP if CPU_AMD_MODEL_10XXX diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc index 2ed76e1..7035323 100644 --- a/src/cpu/amd/family_10h-family_15h/Makefile.inc +++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc @@ -15,11 +15,11 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c # Microcode for Family 10h, 11h, 12h, and 14h -cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin +cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS) += microcode_amd.bin microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin microcode_amd.bin-type := microcode # Microcode for Family 15h -cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd_fam15h.bin +cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS) += microcode_amd_fam15h.bin microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin microcode_amd_fam15h.bin-type := microcode diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index 4c79b23..1f73749 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -29,6 +29,7 @@ select SSE2 select UDELAY_LAPIC select SUPPORT_CPU_UCODE_IN_CBFS + select POOR_MICROCODE_MAINTENANCE select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc index b56e6a7..f589430 100644 --- a/src/cpu/intel/microcode/Makefile.inc +++ b/src/cpu/intel/microcode/Makefile.inc @@ -4,5 +4,3 @@ ################################################################################ ramstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c romstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c - -cpu_microcode_bins += $(call strip_quotes,$(CONFIG_CPU_UCODE_BINARIES)) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 4a841be..66db8db 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -31,6 +31,7 @@ select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select IOAPIC select PCR_COMMON_IOSF_1_0 + select POOR_MICROCODE_MAINTENANCE select SMP select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 9452b6d..a9a511e 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -46,6 +46,7 @@ select PARALLEL_MP select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 + select POOR_MICROCODE_MAINTENANCE select POSTCAR_CONSOLE select POSTCAR_STAGE select REG_SCRIPT diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 7d82f3f..a8d9fd4 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -41,6 +41,7 @@ select TSC_SYNC_MFENCE select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS + select POOR_MICROCODE_MAINTENANCE select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SPI_CONSOLE_SUPPORT diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index fe0fa8d..88ba382 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -21,6 +21,7 @@ select IOAPIC select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS + select POOR_MICROCODE_MAINTENANCE # Microcode header files are delivered in FSP package select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN select INTEL_DESCRIPTOR_MODE_CAPABLE diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 727fccee..bd53c8b 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -33,6 +33,7 @@ select PARALLEL_MP select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 + select POOR_MICROCODE_MAINTENANCE select POSTCAR_CONSOLE select POSTCAR_STAGE select REG_SCRIPT -- To view, visit https://review.coreboot.org/c/coreboot/+/29934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib403402e240d3531640a62ce93b7a93b4ef6ca5e Gerrit-Change-Number: 29934 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/lynxpoint/usb_ehci.c: Don't use device_t
by HAOUAS Elyes (Code Review) 29 Nov '18

29 Nov '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29933 Change subject: sb/intel/lynxpoint/usb_ehci.c: Don't use device_t ...................................................................... sb/intel/lynxpoint/usb_ehci.c: Don't use device_t Use of device_t is deprecated. Change-Id: If2c24bbe6181ea6cf484c33a9fbf119f853efcf4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/lynxpoint/usb_ehci.c 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/29933/1 diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c index e2486cf..7f300d6 100644 --- a/src/southbridge/intel/lynxpoint/usb_ehci.c +++ b/src/southbridge/intel/lynxpoint/usb_ehci.c @@ -25,7 +25,7 @@ #ifdef __SMM__ -void usb_ehci_disable(device_t dev) +void usb_ehci_disable(pci_devfn_t dev) { u16 reg16; u32 reg32; @@ -57,7 +57,7 @@ } /* Handler for EHCI controller on entry to S3/S4/S5 */ -void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ) +void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ) { u32 reg32; u8 *bar0_base; @@ -164,7 +164,8 @@ printk(BIOS_DEBUG, "done.\n"); } -static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { u8 access_cntl; -- To view, visit https://review.coreboot.org/c/coreboot/+/29933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2c24bbe6181ea6cf484c33a9fbf119f853efcf4 Gerrit-Change-Number: 29933 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/soc/intel/braswell: Remove disabled LPE acpi code
by HAOUAS Elyes (Code Review) 29 Nov '18

29 Nov '18

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29414 ) Change subject: src/soc/intel/braswell: Remove disabled LPE acpi code ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29414/2/src/mainboard/intel/strago/ssdtlpe.… File src/mainboard/intel/strago/ssdtlpe.asl: https://review.coreboot.org/#/c/29414/2/src/mainboard/intel/strago/ssdtlpe.… PS2, Line 19: 1 2 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/29414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73 Gerrit-Change-Number: 29414 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 29 Nov 2018 15:20:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/intel/lynxpoint/usb_xhci.c: Don't use device_t
by HAOUAS Elyes (Code Review) 29 Nov '18

29 Nov '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29932 Change subject: sb/intel/lynxpoint/usb_xhci.c: Don't use device_t ...................................................................... sb/intel/lynxpoint/usb_xhci.c: Don't use device_t Use of device_t is deprecated. Change-Id: Ie75450c844e2317ded157465eb0fc6a9ec1b3ab0 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/lynxpoint/usb_xhci.c 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/29932/1 diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index af0e56f..186e3f9 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -154,7 +154,7 @@ #ifdef __SMM__ /* Handler for XHCI controller on entry to S3/S4/S5 */ -void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ) +void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ) { u16 reg16; u32 reg32; @@ -238,7 +238,7 @@ #else /* !__SMM__ */ -static void usb_xhci_clock_gating(device_t dev) +static void usb_xhci_clock_gating(struct device *dev) { u32 reg32; u16 reg16; @@ -285,7 +285,7 @@ pci_write_config32(dev, 0xa4, reg32); } -static void usb_xhci_init(device_t dev) +static void usb_xhci_init(struct device *dev) { u32 reg32; u16 reg16; @@ -359,8 +359,8 @@ } } -static void usb_xhci_set_subsystem(device_t dev, unsigned vendor, - unsigned device) +static void usb_xhci_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, -- To view, visit https://review.coreboot.org/c/coreboot/+/29932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie75450c844e2317ded157465eb0fc6a9ec1b3ab0 Gerrit-Change-Number: 29932 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/soc/intel/braswell: Remove disabled LPE acpi code
by Frans Hendriks (Code Review) 29 Nov '18

29 Nov '18

Hello Hannah Williams, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29414 to look at the new patch set (#2). Change subject: src/soc/intel/braswell: Remove disabled LPE acpi code ...................................................................... src/soc/intel/braswell: Remove disabled LPE acpi code The ACPI code for LPE device was included regardless of the availability of the LPE controller. Move the LPE ACPI code to seperate SSDT and hide it when LPE is disabled. BUG=N/A TEST=Intel CherryHill CRB Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/mainboard/google/cyan/Makefile.inc M src/mainboard/google/cyan/acpi/codec_maxim.asl M src/mainboard/google/cyan/acpi/codec_realtek.asl A src/mainboard/google/cyan/ssdtlpe.asl M src/mainboard/intel/strago/Makefile.inc M src/mainboard/intel/strago/acpi/mainboard.asl A src/mainboard/intel/strago/ssdtlpe.asl M src/soc/intel/braswell/acpi/southcluster.asl M src/soc/intel/braswell/include/soc/acpi.h M src/soc/intel/braswell/lpe.c 10 files changed, 143 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/29414/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73 Gerrit-Change-Number: 29414 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: cpu/intel/fsp_model_406dx: Drop dead microcode reference
by Nico Huber (Code Review) 29 Nov '18

29 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29931 Change subject: cpu/intel/fsp_model_406dx: Drop dead microcode reference ...................................................................... cpu/intel/fsp_model_406dx: Drop dead microcode reference The referenced Kconfig symbols don't exist (anymore?). Change-Id: Ia724262a526fe960c17ae4b248acfa42fc342331 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/cpu/intel/fsp_model_406dx/Makefile.inc 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/29931/1 diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc index d82ddd6..26f4633 100644 --- a/src/cpu/intel/fsp_model_406dx/Makefile.inc +++ b/src/cpu/intel/fsp_model_406dx/Makefile.inc @@ -19,8 +19,4 @@ ramstage-y += acpi.c -ifeq ($(CONFIG_HAVE_CPU_MICROCODE_FILE), y) -cpu_microcode_bins += $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE)) -endif - CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx -- To view, visit https://review.coreboot.org/c/coreboot/+/29931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia724262a526fe960c17ae4b248acfa42fc342331 Gerrit-Change-Number: 29931 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/gm45: Make fetching the blc_pwm freq global
by Nico Huber (Code Review) 29 Nov '18

29 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29925 ) Change subject: nb/intel/gm45: Make fetching the blc_pwm freq global ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3f6ba3ae31a5ab47f44d207678c1c4a6a43b7ec Gerrit-Change-Number: 29925 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Nov 2018 14:42:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/gm45: Make fetching the blc_pwm freq its own function
by Nico Huber (Code Review) 29 Nov '18

29 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29924 ) Change subject: nb/intel/gm45: Make fetching the blc_pwm freq its own function ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ad364f84f3658be98ce7ad3a6f0f0fe3247fc41 Gerrit-Change-Number: 29924 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Nov 2018 14:41:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: Crash Test
by HAOUAS Elyes (Code Review) 29 Nov '18

29 Nov '18

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29926 ) Change subject: Crash Test ...................................................................... Patch Set 2: > Definitely a "Crash Test" Yep. Please rebase this one on your changes ;) -- To view, visit https://review.coreboot.org/c/coreboot/+/29926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3dde296ab4b84add8a8ab6a3bb5ecb65da2c158 Gerrit-Change-Number: 29926 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Nov 2018 14:41:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: [WIP]mb/intel/x200: Add data.vbt
by build bot (Jenkins) (Code Review) 29 Nov '18

29 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29904 ) Change subject: [WIP]mb/intel/x200: Add data.vbt ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/29904/5/src/mainboard/lenovo/x200/blc.c File src/mainboard/lenovo/x200/blc.c: https://review.coreboot.org/#/c/29904/5/src/mainboard/lenovo/x200/blc.c@62 PS5, Line 62: } else { else is not generally useful after a break or return -- To view, visit https://review.coreboot.org/c/coreboot/+/29904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c4a7011ce03cdd511fa2e2160c2f006ba2707ba Gerrit-Change-Number: 29904 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 29 Nov 2018 13:39:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/gm45: Make fetching the blc_pwm freq global
by Arthur Heymans (Code Review) 29 Nov '18

29 Nov '18

Hello Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29925 to look at the new patch set (#2). Change subject: nb/intel/gm45: Make fetching the blc_pwm freq global ...................................................................... nb/intel/gm45: Make fetching the blc_pwm freq global This can be used to select the proper VBT. Change-Id: Id3f6ba3ae31a5ab47f44d207678c1c4a6a43b7ec Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/gm45/gma.c 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/29925/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3f6ba3ae31a5ab47f44d207678c1c4a6a43b7ec Gerrit-Change-Number: 29925 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: nb/intel/gm45: Make fetching the blc_pwm freq its own function
by Arthur Heymans (Code Review) 29 Nov '18

29 Nov '18

Hello Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29924 to look at the new patch set (#2). Change subject: nb/intel/gm45: Make fetching the blc_pwm freq its own function ...................................................................... nb/intel/gm45: Make fetching the blc_pwm freq its own function Also check the EDID string using strcmp instead of strncmp. Change-Id: I9ad364f84f3658be98ce7ad3a6f0f0fe3247fc41 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/gm45/gma.c 1 file changed, 36 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/29924/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ad364f84f3658be98ce7ad3a6f0f0fe3247fc41 Gerrit-Change-Number: 29924 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/baytrail: Improve CAR setup
by Arthur Heymans (Code Review) 29 Nov '18

29 Nov '18

Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29928 to look at the new patch set (#2). Change subject: soc/intel/baytrail: Improve CAR setup ...................................................................... soc/intel/baytrail: Improve CAR setup This patch does the following: - improve the style by removing tabs in front of jmp addresses - Make the code for zeroing variable MTRR more readable (copied from cpu/intel/car) - Fetch PHYSMASK high from cpuid instead of Kconfig Change-Id: I6ba67bb8b049c3f25b856f6ebb1399d275764f54 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/baytrail/romstage/cache_as_ram.inc 1 file changed, 50 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/29928/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ba67bb8b049c3f25b856f6ebb1399d275764f54 Gerrit-Change-Number: 29928 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: Crash Test
by Angel Pons (Code Review) 29 Nov '18

29 Nov '18

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29926 ) Change subject: Crash Test ...................................................................... Patch Set 2: Definitely a "Crash Test" -- To view, visit https://review.coreboot.org/c/coreboot/+/29926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3dde296ab4b84add8a8ab6a3bb5ecb65da2c158 Gerrit-Change-Number: 29926 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Nov 2018 13:23:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/gm45: Make fetching the blc_pwm freq global
by Arthur Heymans (Code Review) 29 Nov '18

29 Nov '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29925 ) Change subject: nb/intel/gm45: Make fetching the blc_pwm freq global ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29925/1/src/northbridge/intel/gm45/gma.c File src/northbridge/intel/gm45/gma.c: https://review.coreboot.org/#/c/29925/1/src/northbridge/intel/gm45/gma.c@673 PS1, Line 673: int get_blc_pwm_freq_value(void) > Alternative to caching the string: Call it with NULL for the VBT […] That would be better. Thx -- To view, visit https://review.coreboot.org/c/coreboot/+/29925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3f6ba3ae31a5ab47f44d207678c1c4a6a43b7ec Gerrit-Change-Number: 29925 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 29 Nov 2018 13:19:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/baytrail: Implement POSTCAR stage
by Arthur Heymans (Code Review) 29 Nov '18

29 Nov '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29930 Change subject: soc/intel/baytrail: Implement POSTCAR stage ...................................................................... soc/intel/baytrail: Implement POSTCAR stage Use common code to tear down CAR. Change-Id: I62a70ae35fe92808f180f2b5f21c5899a96c2c16 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/baytrail/romstage/cache_as_ram.inc M src/soc/intel/baytrail/romstage/romstage.c 4 files changed, 15 insertions(+), 90 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/29930/1 diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 66fcded..ece4d61 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -38,6 +38,8 @@ select HAVE_SPI_CONSOLE_SUPPORT select INTEL_GMA_ACPI select INTEL_GMA_SWSMISCI + select POSTCAR_STAGE + select POSTCAR_CONSOLE config VBOOT select VBOOT_STARTS_IN_ROMSTAGE diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 324dcdd..3658f5a 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -10,6 +10,7 @@ ramstage-y += memmap.c romstage-y += memmap.c +postcar-y += memmap.c ramstage-y += tsc_freq.c romstage-y += tsc_freq.c smm-y += tsc_freq.c @@ -20,6 +21,7 @@ ramstage-y += iosf.c romstage-y += iosf.c smm-y += iosf.c +postcar-y += iosf.c ramstage-y += northcluster.c ramstage-y += ramstage.c ramstage-y += gpio.c @@ -51,6 +53,8 @@ # Remove as ramstage gets fleshed out ramstage-y += placeholders.c +postcar-y += ../../../cpu/intel/car/non-evict/exit_car.S + cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin CPPFLAGS_common += -Isrc/soc/intel/baytrail/include diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc index a2168ad..3bed040 100644 --- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc +++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc @@ -197,95 +197,11 @@ post_code(0x2a) /* Call romstage.c main function. */ call romstage_main - /* Save return value from romstage_main. It contains the stack to use - * after cache-as-ram is torn down. It also contains the information - * for setting up MTRRs. */ - movl %eax, %ebx - post_code(0x2b) - - /* Disable cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - post_code(0x2c) - - /* Disable MTRR. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - andl $(~MTRR_DEF_TYPE_EN), %eax - wrmsr - - invd - - post_code(0x2d) - - /* Disable the no eviction run state */ - movl $NoEvictMod_MSR, %ecx - rdmsr - andl $~2, %eax - wrmsr - - /* Disable the no eviction mode */ - rdmsr - andl $~1, %eax - wrmsr - - post_code(0x2e) - - /* Setup stack as indicated by return value from romstage_main(). */ - movl %ebx, %esp - - /* Get number of MTRRs. */ - popl %ebx - movl $MTRR_PHYS_BASE(0), %ecx -1: - testl %ebx, %ebx - jz 1f - - /* Low 32 bits of MTRR base. */ - popl %eax - /* Upper 32 bits of MTRR base. */ - popl %edx - /* Write MTRR base. */ - wrmsr - inc %ecx - /* Low 32 bits of MTRR mask. */ - popl %eax - /* Upper 32 bits of MTRR mask. */ - popl %edx - /* Write MTRR mask. */ - wrmsr - inc %ecx - - dec %ebx - jmp 1b -1: - post_code(0x2f) - - /* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax - movl %eax, %cr0 - - post_code(0x30) - - /* Enable MTRR. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - orl $MTRR_DEF_TYPE_EN, %eax - wrmsr - - post_code(0x31) - -__main: - post_code(POST_PREPARE_RAMSTAGE) - cld /* Clear direction flag. */ - call romstage_after_car + /* Should never see this postcode */ + post_code(POST_DEAD_CODE) .Lhlt: - post_code(POST_DEAD_CODE) hlt jmp .Lhlt diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index dd1fd29..0e1d57e 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -47,7 +47,7 @@ * Because we can't use global variables the stack is used for allocations -- * thus the need to call back and forth. */ -static void *setup_stack_and_mtrrs(void); +static void platform_enter_postcar(void); static void program_base_addresses(void) { @@ -128,7 +128,10 @@ /* Call into mainboard. */ mainboard_romstage_entry(&rp); - return setup_stack_and_mtrrs(); + platform_enter_postcar(); + + /* We don't return here */ + return NULL; } static struct chipset_power_state power_state CAR_GLOBAL; @@ -245,7 +248,7 @@ /* setup_stack_and_mtrrs() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ -static void *setup_stack_and_mtrrs(void) +static void platform_enter_postcar(void) { struct postcar_frame pcf; uintptr_t top_of_ram; @@ -267,5 +270,5 @@ postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); - return postcar_commit_mtrrs(&pcf); + run_postcar_phase(&pcf); } -- To view, visit https://review.coreboot.org/c/coreboot/+/29930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62a70ae35fe92808f180f2b5f21c5899a96c2c16 Gerrit-Change-Number: 29930 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/baytrail: Use postcar_frame functions to set up frame
by Arthur Heymans (Code Review) 29 Nov '18

29 Nov '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29929 Change subject: soc/intel/baytrail: Use postcar_frame functions to set up frame ...................................................................... soc/intel/baytrail: Use postcar_frame functions to set up frame Change-Id: I77e375a2ff2fbf1be4ded922195b80b49ffa4cc5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/baytrail/romstage/romstage.c 1 file changed, 17 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/29929/1 diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 18c9353..dd1fd29 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -241,76 +241,31 @@ return stack; } +#define ROMSTAGE_RAM_STACK_SIZE 0x5000 + /* setup_stack_and_mtrrs() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ static void *setup_stack_and_mtrrs(void) { - int num_mtrrs; - uint32_t *slot; - uint32_t mtrr_mask_upper; - uint32_t top_of_ram; + struct postcar_frame pcf; + uintptr_t top_of_ram; - /* Top of stack needs to be aligned to a 4-byte boundary. */ - slot = (void *)romstage_ram_stack_top(); - num_mtrrs = 0; - - /* The upper bits of the MTRR mask need to set according to the number - * of physical address bits. */ - mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1; - - /* The order for each MTRR is value then base with upper 32-bits of - * each value coming before the lower 32-bits. The reasoning for - * this ordering is to create a stack layout like the following: - * +0: Number of MTRRs - * +4: MTRR base 0 31:0 - * +8: MTRR base 0 63:32 - * +12: MTRR mask 0 31:0 - * +16: MTRR mask 0 63:32 - * +20: MTRR base 1 31:0 - * +24: MTRR base 1 63:32 - * +28: MTRR mask 1 31:0 - * +32: MTRR mask 1 63:32 - */ - + if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ - slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID); - slot = stack_push(slot, 0); /* upper base */ - slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); - num_mtrrs++; + postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, + MTRR_TYPE_WRPROT); /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID); - slot = stack_push(slot, 0); /* upper base */ - slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK); - num_mtrrs++; + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - top_of_ram = (uint32_t)cbmem_top(); - /* Cache 8MiB below the top of ram. The top of RAM under 4GiB is the - * start of the TSEG region. It is required to be 8MiB aligned. Set - * this area as cacheable so it can be used later for ramstage before - * setting up the entire RAM as cacheable. */ - slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID); - slot = stack_push(slot, 0); /* upper base */ - slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK); - num_mtrrs++; + /* Cache at least 8 MiB below the top of ram, and at most 8 MiB + * above top of the ram. This satisfies MTRR alignment requirement + * with different TSEG size configurations. + */ + top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB, + MTRR_TYPE_WRBACK); - /* Cache 8MiB at the top of ram. Top of RAM is where the TSEG - * region resides. However, it is not restricted to SMM mode until - * SMM has been relocated. By setting the region to cacheable it - * provides faster access when relocating the SMM handler as well - * as using the TSEG region for other purposes. */ - slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID); - slot = stack_push(slot, 0); /* upper base */ - slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK); - num_mtrrs++; - - /* Save the number of MTRRs to setup. Return the stack location - * pointing to the number of MTRRs. */ - slot = stack_push(slot, num_mtrrs); - - return slot; + return postcar_commit_mtrrs(&pcf); } -- To view, visit https://review.coreboot.org/c/coreboot/+/29929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77e375a2ff2fbf1be4ded922195b80b49ffa4cc5 Gerrit-Change-Number: 29929 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/baytrail: Improve CAR setup
by Arthur Heymans (Code Review) 29 Nov '18

29 Nov '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29928 Change subject: soc/intel/baytrail: Improve CAR setup ...................................................................... soc/intel/baytrail: Improve CAR setup This patch does the following: - improve the style by removing tabs in front of jmp addresses - Make the code for zeroing variable MTRR more readable (copied from cpu/intel/car) - Fetch PHYHSMASK high from cpuid instead of Kconfig Change-Id: I6ba67bb8b049c3f25b856f6ebb1399d275764f54 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/baytrail/romstage/cache_as_ram.inc 1 file changed, 49 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/29928/1 diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc index 9969d5d..a2168ad 100644 --- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc +++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc @@ -32,7 +32,6 @@ #define CODE_CACHE_SIZE _ALIGN_UP_POW2(___FMAP__COREBOOT_SIZE) #define CODE_CACHE_BASE (-CODE_CACHE_SIZE) #define CODE_CACHE_MASK (~(CODE_CACHE_SIZE - 1)) -#define CPU_PHYSMASK_HI ((1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1) #define NoEvictMod_MSR 0x2e0 #define BBL_CR_CTL3_MSR 0x11e @@ -71,24 +70,42 @@ movl $0x200, %ecx xorl %eax, %eax xorl %edx, %edx - 1: +1: wrmsr inc %ecx dec %ebx jnz 1b - /* Zero out all fixed range and variable range MTRRs. */ - movl $fixed_mtrr_table, %esi - movl $((fixed_mtrr_table_end - fixed_mtrr_table) >> 1), %edi - xorl %eax, %eax - xorl %edx, %edx - 1: - movw (%esi), %bx - movzx %bx, %ecx + /* Clear/disable fixed MTRRs */ + mov $fixed_mtrr_list_size, %ebx + xor %eax, %eax + xor %edx, %edx + +clear_fixed_mtrr: + add $-2, %ebx + movzwl fixed_mtrr_list(%ebx), %ecx wrmsr - add $2, %esi - dec %edi - jnz 1b + jnz clear_fixed_mtrr + + /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ + movl $0x80000008, %eax + cpuid + movb %al, %cl + sub $32, %cl + movl $1, %edx + shl %cl, %edx + subl $1, %edx + + /* Preload high word of address mask (in %edx) for Variable + * MTRRs 0 and 1. + */ +addrsize_set_high: + xorl %eax, %eax + movl $MTRR_PHYS_MASK(0), %ecx + wrmsr + movl $MTRR_PHYS_MASK(1), %ecx + wrmsr + post_code(0x23) /* Set Cache-as-RAM base address. */ @@ -100,8 +117,8 @@ post_code(0x24) /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx + rdmsr movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax - movl $CPU_PHYSMASK_HI, %edx wrmsr post_code(0x25) @@ -111,9 +128,9 @@ xorl %edx, %edx wrmsr - movl $(MTRR_PHYS_MASK(1)), %ecx - movl $(CODE_CACHE_MASK | MTRR_PHYS_MASK_VALID), %eax - movl $CPU_PHYSMASK_HI, %edx + movl $MTRR_PHYS_MASK(1), %ecx + rdmsr + movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr /* Enable MTRR. */ @@ -133,7 +150,7 @@ post_code(0x27) /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax + movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 @@ -212,7 +229,7 @@ /* Disable the no eviction mode */ rdmsr - andl $~1, %eax + andl $~1, %eax wrmsr post_code(0x2e) @@ -272,10 +289,16 @@ hlt jmp .Lhlt -/* Fixed MTRRs */ -fixed_mtrr_table: - .word 0x250, 0x258, 0x259 - .word 0x268, 0x269, 0x26A - .word 0x26B, 0x26C, 0x26D - .word 0x26E, 0x26F -fixed_mtrr_table_end: +fixed_mtrr_list: + .word MTRR_FIX_64K_00000 + .word MTRR_FIX_16K_80000 + .word MTRR_FIX_16K_A0000 + .word MTRR_FIX_4K_C0000 + .word MTRR_FIX_4K_C8000 + .word MTRR_FIX_4K_D0000 + .word MTRR_FIX_4K_D8000 + .word MTRR_FIX_4K_E0000 + .word MTRR_FIX_4K_E8000 + .word MTRR_FIX_4K_F0000 + .word MTRR_FIX_4K_F8000 +fixed_mtrr_list_size = . - fixed_mtrr_list -- To view, visit https://review.coreboot.org/c/coreboot/+/29928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ba67bb8b049c3f25b856f6ebb1399d275764f54 Gerrit-Change-Number: 29928 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/gm45: Make fetching the blc_pwm freq global
by Nico Huber (Code Review) 29 Nov '18

29 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29925 ) Change subject: nb/intel/gm45: Make fetching the blc_pwm freq global ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/29925/1/src/northbridge/intel/gm45/gma.c File src/northbridge/intel/gm45/gma.c: https://review.coreboot.org/#/c/29925/1/src/northbridge/intel/gm45/gma.c@44 PS1, Line 44: char edid_ascii_string[EDID_ASCII_STRING_LENGTH + 1]; static? https://review.coreboot.org/#/c/29925/1/src/northbridge/intel/gm45/gma.c@673 PS1, Line 673: int get_blc_pwm_freq_value(void) Alternative to caching the string: Call it with NULL for the VBT stuff and make the check below: if (blc_pwm_freq > 0 || !edid_ascii_string) Reasoning: If the lookup would succeed `blc_pwm_freq` would already be set, if not, there's no need to try again. -- To view, visit https://review.coreboot.org/c/coreboot/+/29925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3f6ba3ae31a5ab47f44d207678c1c4a6a43b7ec Gerrit-Change-Number: 29925 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 29 Nov 2018 13:09:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/gm45: Make fetching the blc_pwm freq its own function
by Nico Huber (Code Review) 29 Nov '18

29 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29924 ) Change subject: nb/intel/gm45: Make fetching the blc_pwm freq its own function ...................................................................... Patch Set 1: (3 comments) https://review.coreboot.org/#/c/29924/1/src/northbridge/intel/gm45/gma.c File src/northbridge/intel/gm45/gma.c: https://review.coreboot.org/#/c/29924/1/src/northbridge/intel/gm45/gma.c@673 PS1, Line 673: = -1 Initialization is unnecessary as you check `> 0`. https://review.coreboot.org/#/c/29924/1/src/northbridge/intel/gm45/gma.c@684 PS1, Line 684: if (!strcmp(blc_pwm[i].ascii_string, edid_ascii_string)) { Please mention this tiny functional change in the commit message. https://review.coreboot.org/#/c/29924/1/src/northbridge/intel/gm45/gma.c@746 PS1, Line 746: if (pwm_freq < 0) eeeek, it's unsigned -- To view, visit https://review.coreboot.org/c/coreboot/+/29924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ad364f84f3658be98ce7ad3a6f0f0fe3247fc41 Gerrit-Change-Number: 29924 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 29 Nov 2018 13:04:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: payloads/external/Linuxboot/targets: use go get to install u-root
by Marcello Sylvester Bauer (Code Review) 29 Nov '18

29 Nov '18

Marcello Sylvester Bauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29515 ) Change subject: payloads/external/Linuxboot/targets: use go get to install u-root ...................................................................... Patch Set 3: changes has already been submitted on my resent submit :) https://review.coreboot.org/c/coreboot/+/29778 -- To view, visit https://review.coreboot.org/c/coreboot/+/29515 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72866944165823300566e2e9bdaba59599a88178 Gerrit-Change-Number: 29515 Gerrit-PatchSet: 3 Gerrit-Owner: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Nov 2018 12:47:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: payloads/external/Linuxboot: support u-root versions
by Marcello Sylvester Bauer (Code Review) 29 Nov '18

29 Nov '18

Marcello Sylvester Bauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29516 ) Change subject: payloads/external/Linuxboot: support u-root versions ...................................................................... Patch Set 4: changes has already been submitted on my resent submit :) https://review.coreboot.org/c/coreboot/+/29778 -- To view, visit https://review.coreboot.org/c/coreboot/+/29516 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65e1ccf0319809f7fab23142b31882e9928a5ec2 Gerrit-Change-Number: 29516 Gerrit-PatchSet: 4 Gerrit-Owner: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Nov 2018 12:47:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/broadwell: Implement postcar stage
by Arthur Heymans (Code Review) 29 Nov '18

29 Nov '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29927 ) Change subject: soc/intel/broadwell: Implement postcar stage ...................................................................... Patch Set 1: I don't own such a device so it would be nice if someone had some time to test. -- To view, visit https://review.coreboot.org/c/coreboot/+/29927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I428832a2d7e46ce61a7f9bd498b609feb4518eb0 Gerrit-Change-Number: 29927 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 29 Nov 2018 12:40:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/broadwell: Implement postcar stage
by Arthur Heymans (Code Review) 29 Nov '18

29 Nov '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29927 Change subject: soc/intel/broadwell: Implement postcar stage ...................................................................... soc/intel/broadwell: Implement postcar stage This does the following: - Reuse the cpu/intel/car/non-evict CAR setup and exit. - Use postcar_frame functions to set up the postcar frame Change-Id: I428832a2d7e46ce61a7f9bd498b609feb4518eb0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/Makefile.inc M src/soc/intel/broadwell/include/soc/pci_devs.h M src/soc/intel/broadwell/romstage/Makefile.inc D src/soc/intel/broadwell/romstage/cache_as_ram.inc M src/soc/intel/broadwell/romstage/romstage.c D src/soc/intel/broadwell/romstage/stack.c 7 files changed, 42 insertions(+), 426 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/29927/1 diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 18ec51f..e6cbd95 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -40,6 +40,8 @@ select HAVE_SPI_CONSOLE_SUPPORT select CPU_INTEL_COMMON select INTEL_GMA_ACPI + select POSTCAR_STAGE + select POSTCAR_CONSOLE config PCIEXP_ASPM bool diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 4e4d3eb..caf963c 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -30,6 +30,7 @@ romstage-y += me_status.c ramstage-y += memmap.c romstage-y += memmap.c +postcar-y += memmap.c ramstage-y += minihd.c ramstage-y += monotonic_timer.c smm-y += monotonic_timer.c @@ -55,6 +56,7 @@ smm-$(CONFIG_SPI_FLASH_SMM) += spi.c ramstage-y += stage_cache.c romstage-y += stage_cache.c +postcar-y += stage_cache.c ramstage-y += systemagent.c ramstage-y += tsc_freq.c romstage-y += tsc_freq.c @@ -65,6 +67,8 @@ ramstage-y += xhci.c smm-y += xhci.c +postcar-y += ../../../cpu/intel/car/non-evict/exit_car.S + ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin diff --git a/src/soc/intel/broadwell/include/soc/pci_devs.h b/src/soc/intel/broadwell/include/soc/pci_devs.h index 0880353..a46f9fc 100644 --- a/src/soc/intel/broadwell/include/soc/pci_devs.h +++ b/src/soc/intel/broadwell/include/soc/pci_devs.h @@ -19,7 +19,7 @@ #define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) -#if defined(__PRE_RAM__) || defined(__SMM__) || defined(__ROMCC__) +#if defined(__SIMPLE_DEVICE__) #include <arch/io.h> #define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc index 1617812..2d562d9 100644 --- a/src/soc/intel/broadwell/romstage/Makefile.inc +++ b/src/soc/intel/broadwell/romstage/Makefile.inc @@ -1,4 +1,4 @@ -cpu_incs-y += $(src)/soc/intel/broadwell/romstage/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S romstage-y += cpu.c romstage-y += pch.c @@ -8,6 +8,5 @@ romstage-y += romstage.c romstage-y += smbus.c romstage-y += spi.c -romstage-y += stack.c romstage-y += systemagent.c romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc deleted file mode 100644 index 6d3d6dd..0000000 --- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc +++ /dev/null @@ -1,318 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cpu/x86/mtrr.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/post_code.h> - -/* The full cache-as-ram size includes the cache-as-ram portion from coreboot - * and the space used by the reference code. These 2 values combined should - * be a power of 2 because the MTRR setup assumes that. */ -#define CACHE_AS_RAM_SIZE \ - (CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_RAM_MRC_VAR_SIZE) -#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE -#define CACHE_AS_RAM_LIMIT (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) - -/* Cache 4GB - MRC_SIZE_KB for MRC */ -#define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1) -#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES) -#define CACHE_MRC_MASK (~CACHE_MRC_BYTES) - -#define CPU_MAXPHYSADDR CONFIG_CPU_ADDR_BITS -#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYSADDR - 32) - 1) - -#define NoEvictMod_MSR 0x2e0 - - /* Save the BIST result. */ - movl %eax, %ebp - -cache_as_ram: - post_code(0x20) - - /* Send INIT IPI to all excluding ourself. */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) - - /* All CPUs need to be in Wait for SIPI state */ -wait_for_sipi: - movl (%esi), %eax - bt $12, %eax - jc wait_for_sipi - - post_code(0x21) - /* Zero out all fixed range and variable range MTRRs. */ - movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) >> 1), %edi - xorl %eax, %eax - xorl %edx, %edx -clear_mtrrs: - movw (%esi), %bx - movzx %bx, %ecx - wrmsr - add $2, %esi - dec %edi - jnz clear_mtrrs - - post_code(0x22) - /* Configure the default memory type to uncacheable. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - andl $(~0x00000cff), %eax - wrmsr - - post_code(0x23) - /* Set Cache-as-RAM base address. */ - movl $(MTRR_PHYS_BASE(0)), %ecx - movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax - xorl %edx, %edx - wrmsr - - post_code(0x24) - /* Set Cache-as-RAM mask. */ - movl $(MTRR_PHYS_MASK(0)), %ecx - movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax - movl $CPU_PHYSMASK_HI, %edx - wrmsr - - post_code(0x25) - - /* Enable MTRR. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - orl $MTRR_DEF_TYPE_EN, %eax - wrmsr - - /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax - andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax - invd - movl %eax, %cr0 - - /* enable the 'no eviction' mode */ - movl $NoEvictMod_MSR, %ecx - rdmsr - orl $1, %eax - andl $~2, %eax - wrmsr - - /* Clear the cache memory region. This will also fill up the cache */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE >> 2), %ecx - xorl %eax, %eax - rep stosl - - /* enable the 'no eviction run' state */ - movl $NoEvictMod_MSR, %ecx - rdmsr - orl $3, %eax - wrmsr - - post_code(0x26) - /* Enable Cache-as-RAM mode by disabling cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - /* Enable cache for our code in Flash because we do XIP here */ - movl $MTRR_PHYS_BASE(1), %ecx - xorl %edx, %edx - /* - * IMPORTANT: The following calculation _must_ be done at runtime. See - * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html - */ - movl $_program, %eax - andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax - orl $MTRR_TYPE_WRPROT, %eax - wrmsr - - movl $MTRR_PHYS_MASK(1), %ecx - movl $CPU_PHYSMASK_HI, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax - wrmsr - - post_code(0x27) - /* Enable caching for RAM init code to run faster */ - movl $MTRR_PHYS_BASE(2), %ecx - movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax - xorl %edx, %edx - wrmsr - movl $MTRR_PHYS_MASK(2), %ecx - movl $(CACHE_MRC_MASK | MTRR_PHYS_MASK_VALID), %eax - movl $CPU_PHYSMASK_HI, %edx - wrmsr - - post_code(0x28) - /* Enable cache. */ - movl %cr0, %eax - andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax - movl %eax, %cr0 - - /* Setup the stack. */ - movl $(CACHE_AS_RAM_LIMIT), %eax - movl %eax, %esp - - /* Restore the BIST result. */ - movl %ebp, %eax - - /* Build the call frame. */ - movl %esp, %ebp - movd %mm1, %ebx - pushl %ebx - movd %mm0, %ebx - pushl %ebx - pushl %eax - -before_romstage: - post_code(0x29) - /* Call romstage.c main function. */ - call romstage_main - /* Save return value from romstage_main. It contains the stack to use - * after cache-as-ram is torn down. It also contains the information - * for setting up MTRRs. */ - movl %eax, %ebx - - post_code(0x2f) - - post_code(0x30) - - /* Disable cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - post_code(0x31) - - /* Disable MTRR. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - andl $(~MTRR_DEF_TYPE_EN), %eax - wrmsr - - post_code(0x31) - - /* Disable the no eviction run state */ - movl $NoEvictMod_MSR, %ecx - rdmsr - andl $~2, %eax - wrmsr - - invd - - /* Disable the no eviction mode */ - rdmsr - andl $~1, %eax - wrmsr - - /* Clear MTRR that was used to cache MRC */ - xorl %eax, %eax - xorl %edx, %edx - movl $MTRR_PHYS_BASE(2), %ecx - wrmsr - movl $MTRR_PHYS_MASK(2), %ecx - wrmsr - - post_code(0x33) - - /* Enable cache. */ - movl %cr0, %eax - andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax - movl %eax, %cr0 - - post_code(0x36) - - /* Disable cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - post_code(0x38) - - /* Setup stack as indicated by return value from romstage_main(). */ - movl %ebx, %esp - - /* Get number of MTRRs. */ - popl %ebx - movl $MTRR_PHYS_BASE(0), %ecx -1: - testl %ebx, %ebx - jz 1f - - /* Low 32 bits of MTRR base. */ - popl %eax - /* Upper 32 bits of MTRR base. */ - popl %edx - /* Write MTRR base. */ - wrmsr - inc %ecx - /* Low 32 bits of MTRR mask. */ - popl %eax - /* Upper 32 bits of MTRR mask. */ - popl %edx - /* Write MTRR mask. */ - wrmsr - inc %ecx - - dec %ebx - jmp 1b -1: - post_code(0x39) - - /* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax - movl %eax, %cr0 - - post_code(0x3a) - - /* Enable MTRR. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - orl $MTRR_DEF_TYPE_EN, %eax - wrmsr - - post_code(0x3b) - - /* Invalidate the cache again. */ - invd - - post_code(0x3c) - -__main: - post_code(POST_PREPARE_RAMSTAGE) - cld /* Clear direction flag. */ - call romstage_after_car - -.Lhlt: - post_code(POST_DEAD_CODE) - hlt - jmp .Lhlt - -mtrr_table: - /* Fixed MTRRs */ - .word 0x250, 0x258, 0x259 - .word 0x268, 0x269, 0x26A - .word 0x26B, 0x26C, 0x26D - .word 0x26E, 0x26F - /* Variable MTRRs */ - .word 0x200, 0x201, 0x202, 0x203 - .word 0x204, 0x205, 0x206, 0x207 - .word 0x208, 0x209, 0x20A, 0x20B - .word 0x20C, 0x20D, 0x20E, 0x20F - .word 0x210, 0x211, 0x212, 0x213 -mtrr_table_end: diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 7a796f4..1e92521 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -19,6 +19,7 @@ #include <arch/cbfs.h> #include <arch/early_variables.h> #include <bootmode.h> +#include <cbmem.h> #include <console/console.h> #include <cpu/x86/mtrr.h> #include <elog.h> @@ -32,6 +33,36 @@ #include <soc/romstage.h> #include <soc/spi.h> +#define ROMSTAGE_RAM_STACK_SIZE 0x5000 + +/* platform_enter_postcar() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use, + * and continues execution in postcar stage. */ +static void platform_enter_postcar(void) +{ + struct postcar_frame pcf; + uintptr_t top_of_ram; + + if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + die("Unable to initialize postcar frame.\n"); + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, + MTRR_TYPE_WRPROT); + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + + /* Cache at least 8 MiB below the top of ram, and at most 8 MiB + * above top of the ram. This satisfies MTRR alignment requirement + * with different TSEG size configurations. + */ + top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB, + MTRR_TYPE_WRBACK); + + run_postcar_phase(&pcf); +} + /* Entry from cache-as-ram.inc. */ asmlinkage void *romstage_main(unsigned long bist, uint32_t tsc_low, uint32_t tsc_hi) @@ -74,7 +105,9 @@ /* Call into mainboard. */ mainboard_romstage_entry(&rp); - return setup_stack_and_mtrrs(); + platform_enter_postcar(); + + return NULL; } /* Entry from the mainboard. */ diff --git a/src/soc/intel/broadwell/romstage/stack.c b/src/soc/intel/broadwell/romstage/stack.c deleted file mode 100644 index 3595676..0000000 --- a/src/soc/intel/broadwell/romstage/stack.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stddef.h> -#include <stdint.h> -#include <arch/cpu.h> -#include <arch/early_variables.h> -#include <cbmem.h> -#include <cpu/x86/mtrr.h> -#include <soc/romstage.h> -#include <program_loading.h> - -static inline uint32_t *stack_push(u32 *stack, u32 value) -{ - stack = &stack[-1]; - *stack = value; - return stack; -} - -/* setup_stack_and_mtrrs() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use. */ -void *setup_stack_and_mtrrs(void) -{ - int num_mtrrs; - uint32_t *slot; - uint32_t mtrr_mask_upper; - uint32_t top_of_ram; - - /* Top of stack needs to be aligned to a 4-byte boundary. */ - slot = (void *)romstage_ram_stack_top(); - num_mtrrs = 0; - - /* The upper bits of the MTRR mask need to set according to the number - * of physical address bits. */ - mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1; - - /* The order for each MTRR is value then base with upper 32-bits of - * each value coming before the lower 32-bits. The reasoning for - * this ordering is to create a stack layout like the following: - * +0: Number of MTRRs - * +4: MTRR base 0 31:0 - * +8: MTRR base 0 63:32 - * +12: MTRR mask 0 31:0 - * +16: MTRR mask 0 63:32 - * +20: MTRR base 1 31:0 - * +24: MTRR base 1 63:32 - * +28: MTRR mask 1 31:0 - * +32: MTRR mask 1 63:32 - */ - - /* Cache the ROM as WP just below 4GiB. */ - slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID); - slot = stack_push(slot, 0); /* upper base */ - slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); - num_mtrrs++; - - /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID); - slot = stack_push(slot, 0); /* upper base */ - slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK); - num_mtrrs++; - - top_of_ram = (uint32_t)cbmem_top(); - /* Cache 8MiB below the top of ram. The top of RAM under 4GiB is the - * start of the TSEG region. It is required to be 8MiB aligned. Set - * this area as cacheable so it can be used later for ramstage before - * setting up the entire RAM as cacheable. */ - slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID); - slot = stack_push(slot, 0); /* upper base */ - slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK); - num_mtrrs++; - - /* Cache 8MiB at the top of ram. Top of RAM is where the TSEG - * region resides. However, it is not restricted to SMM mode until - * SMM has been relocated. By setting the region to cacheable it - * provides faster access when relocating the SMM handler as well - * as using the TSEG region for other purposes. */ - slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID); - slot = stack_push(slot, 0); /* upper base */ - slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK); - num_mtrrs++; - - /* Save the number of MTRRs to setup. Return the stack location - * pointing to the number of MTRRs. */ - slot = stack_push(slot, num_mtrrs); - - return slot; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/29927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I428832a2d7e46ce61a7f9bd498b609feb4518eb0 Gerrit-Change-Number: 29927 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Crash Test
by HAOUAS Elyes (Code Review) 29 Nov '18

29 Nov '18

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29926 to look at the new patch set (#2). Change subject: Crash Test ...................................................................... Crash Test Test CFLAGS_common += -Wno-unused-function \ -Wno-tautological-compare -Wno-shift-overflow Change-Id: Ic3dde296ab4b84add8a8ab6a3bb5ecb65da2c158 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/29926/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3dde296ab4b84add8a8ab6a3bb5ecb65da2c158 Gerrit-Change-Number: 29926 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: Test CFLAGS_common
by HAOUAS Elyes (Code Review) 29 Nov '18

29 Nov '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29926 Change subject: Test CFLAGS_common ...................................................................... Test CFLAGS_common Test CFLAGS_common += -Wno-unused-function \ -Wno-tautological-compare -Wno-shift-overflow Change-Id: Ic3dde296ab4b84add8a8ab6a3bb5ecb65da2c158 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/29926/1 diff --git a/Makefile.inc b/Makefile.inc index aaae7bc..489952d 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -395,7 +395,7 @@ CFLAGS_common += -Wno-packed-not-aligned CFLAGS_common += -fconserve-stack # cf. commit f69a99db (coreboot: x86: enable gc-sections) -CFLAGS_common += -Wno-unused-but-set-variable +CFLAGS_common += -Wno-unused-function -Wno-tautological-compare -Wno-shift-overflow endif endif -- To view, visit https://review.coreboot.org/c/coreboot/+/29926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3dde296ab4b84add8a8ab6a3bb5ecb65da2c158 Gerrit-Change-Number: 29926 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/gm45: Make fetching the blc_pwm freq global
by build bot (Jenkins) (Code Review) 29 Nov '18

29 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29925 ) Change subject: nb/intel/gm45: Make fetching the blc_pwm freq global ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29925/1/src/northbridge/intel/gm45/gma.c File src/northbridge/intel/gm45/gma.c: https://review.coreboot.org/#/c/29925/1/src/northbridge/intel/gm45/gma.c@784 PS1, Line 784: memcpy(edid_ascii_string, edid_lvds.ascii_string, sizeof(edid_ascii_string)); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3f6ba3ae31a5ab47f44d207678c1c4a6a43b7ec Gerrit-Change-Number: 29925 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Nov 2018 11:29:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: [WIP]mb/intel/x200: Add data.vbt
by build bot (Jenkins) (Code Review) 29 Nov '18

29 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29904 ) Change subject: [WIP]mb/intel/x200: Add data.vbt ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/29904/4/src/mainboard/lenovo/x200/blc.c File src/mainboard/lenovo/x200/blc.c: https://review.coreboot.org/#/c/29904/4/src/mainboard/lenovo/x200/blc.c@62 PS4, Line 62: } else { else is not generally useful after a break or return -- To view, visit https://review.coreboot.org/c/coreboot/+/29904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c4a7011ce03cdd511fa2e2160c2f006ba2707ba Gerrit-Change-Number: 29904 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 29 Nov 2018 11:29:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/gm45: Make fetching the blc_pwm freq global
by Arthur Heymans (Code Review) 29 Nov '18

29 Nov '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29925 Change subject: nb/intel/gm45: Make fetching the blc_pwm freq global ...................................................................... nb/intel/gm45: Make fetching the blc_pwm freq global This can be used to select the proper VBT. Change-Id: Id3f6ba3ae31a5ab47f44d207678c1c4a6a43b7ec Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/gm45/gma.c 2 files changed, 8 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/29925/1 diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 95863d9..37e1ddc 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -443,6 +443,7 @@ int pwm_freq; /* In Hz */ }; int get_blc_values(const struct blc_pwm_t **entries); +int get_blc_pwm_freq_value(void); #if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 34cf367..511225f 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -41,6 +41,8 @@ static struct resource *gtt_res = NULL; +char edid_ascii_string[EDID_ASCII_STRING_LENGTH + 1]; + u32 gtt_read(u32 reg) { return read32(res2mmio(gtt_res, reg, 0)); @@ -668,7 +670,7 @@ return (blc_mod << 16) | blc_mod; } -static int get_blc_pwm_freq_value(const char *edid_ascii_string) +int get_blc_pwm_freq_value(void) { static int blc_pwm_freq = -1; const struct blc_pwm_t *blc_pwm; @@ -701,8 +703,7 @@ return blc_pwm_freq; } -static void gma_pm_init_post_vbios(struct device *const dev, - const char *edid_ascii_string) +static void gma_pm_init_post_vbios(struct device *const dev) { const struct northbridge_intel_gm45_config *const conf = dev->chip_info; @@ -739,7 +740,7 @@ reg8 = 100; if (conf->duty_cycle != 0) reg8 = conf->duty_cycle; - pwm_freq = get_blc_pwm_freq_value(edid_ascii_string); + pwm_freq = get_blc_pwm_freq_value(); if (pwm_freq < 0 && conf->default_pwm_freq != 0) pwm_freq = conf->default_pwm_freq; @@ -780,7 +781,8 @@ decode_edid(edid_data_lvds, sizeof(edid_data_lvds), &edid_lvds); /* Post VBIOS init */ - gma_pm_init_post_vbios(dev, edid_lvds.ascii_string); + memcpy(edid_ascii_string, edid_lvds.ascii_string, sizeof(edid_ascii_string)); + gma_pm_init_post_vbios(dev); int vga_disable = (pci_read_config16(dev, D0F0_GGC) & 2) >> 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/29925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3f6ba3ae31a5ab47f44d207678c1c4a6a43b7ec Gerrit-Change-Number: 29925 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/gm45: Make fetching the blc_pwm freq its own function
by Arthur Heymans (Code Review) 29 Nov '18

29 Nov '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29924 Change subject: nb/intel/gm45: Make fetching the blc_pwm freq its own function ...................................................................... nb/intel/gm45: Make fetching the blc_pwm freq its own function Change-Id: I9ad364f84f3658be98ce7ad3a6f0f0fe3247fc41 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/gm45/gma.c 1 file changed, 37 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/29924/1 diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index b86e2b3..34cf367 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -668,6 +668,39 @@ return (blc_mod << 16) | blc_mod; } +static int get_blc_pwm_freq_value(const char *edid_ascii_string) +{ + static int blc_pwm_freq = -1; + const struct blc_pwm_t *blc_pwm; + int i; + int blc_array_len; + + if (blc_pwm_freq > 0) + return blc_pwm_freq; + + blc_array_len = get_blc_values(&blc_pwm); + /* Find EDID string and pwm freq in lookup table */ + for (i = 0; i < blc_array_len; i++) { + if (!strcmp(blc_pwm[i].ascii_string, edid_ascii_string)) { + blc_pwm_freq = blc_pwm[i].pwm_freq; + printk(BIOS_DEBUG, "Found EDID string: %s in lookup table, pwm: %dHz\n", + blc_pwm[i].ascii_string, blc_pwm_freq); + break; + } + } + + if (i == blc_array_len) + printk(BIOS_NOTICE, "Your panels EDID `%s` wasn't found in the" + "lookup table.\n You may have issues with your panels" + "backlight.\n If you want to help improving coreboot" + "please report: this EDID string\n and the result" + "of `intel_read read BLC_PWM_CTL`" + "(from intel-gpu-tools)\n while running vendor BIOS\n", + edid_ascii_string); + + return blc_pwm_freq; +} + static void gma_pm_init_post_vbios(struct device *const dev, const char *edid_ascii_string) { @@ -675,9 +708,7 @@ u32 reg32; u8 reg8; - const struct blc_pwm_t *blc_pwm; - int blc_array_len, i; - u16 pwm_freq = 0; + u16 pwm_freq; /* Setup Panel Power On Delays */ reg32 = gtt_read(PP_ON_DELAYS); @@ -708,31 +739,11 @@ reg8 = 100; if (conf->duty_cycle != 0) reg8 = conf->duty_cycle; - blc_array_len = get_blc_values(&blc_pwm); - if (conf->default_pwm_freq != 0) + pwm_freq = get_blc_pwm_freq_value(edid_ascii_string); + if (pwm_freq < 0 && conf->default_pwm_freq != 0) pwm_freq = conf->default_pwm_freq; - /* Find EDID string and pwm freq in lookup table */ - for (i = 0; i < blc_array_len; i++) { - if (!strncmp(blc_pwm[i].ascii_string, edid_ascii_string, - strlen(blc_pwm[i].ascii_string))) { - pwm_freq = blc_pwm[i].pwm_freq; - printk(BIOS_DEBUG, "Found EDID string: %s in lookup table, pwm: %dHz\n", - blc_pwm[i].ascii_string, pwm_freq); - break; - } - } - - if (i == blc_array_len) - printk(BIOS_NOTICE, "Your panels EDID `%s` wasn't found in the" - "lookup table.\n You may have issues with your panels" - "backlight.\n If you want to help improving coreboot" - "please report: this EDID string\n and the result" - "of `intel_read read BLC_PWM_CTL`" - "(from intel-gpu-tools)\n while running vendor BIOS\n", - edid_ascii_string); - - if (pwm_freq == 0) + if (pwm_freq < 0) gtt_write(BLC_PWM_CTL, 0x06100610); else gtt_write(BLC_PWM_CTL, freq_to_blc_pwm_ctl(dev, pwm_freq, -- To view, visit https://review.coreboot.org/c/coreboot/+/29924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ad364f84f3658be98ce7ad3a6f0f0fe3247fc41 Gerrit-Change-Number: 29924 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: TEST COMMIT
by Name of user not set (Code Review) 29 Nov '18

29 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29923 Change subject: TEST COMMIT ...................................................................... TEST COMMIT Change-Id: Ic95fb9cbeb98c6f6f502619b7f4921bc5febb7cd Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M Makefile 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/29923/1 diff --git a/Makefile b/Makefile index 1d4a488..53c8251 100644 --- a/Makefile +++ b/Makefile @@ -1,3 +1,4 @@ + ## ## This file is part of the coreboot project. ## -- To view, visit https://review.coreboot.org/c/coreboot/+/29923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic95fb9cbeb98c6f6f502619b7f4921bc5febb7cd Gerrit-Change-Number: 29923 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

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Change in ...coreboot[master]: riscv: add support to select the privilege level of the payload running
by build bot (Jenkins) (Code Review) 29 Nov '18

29 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29494 ) Change subject: riscv: add support to select the privilege level of the payload running ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/#/c/29494/7/src/arch/riscv/boot.c File src/arch/riscv/boot.c: https://review.coreboot.org/#/c/29494/7/src/arch/riscv/boot.c@50 PS7, Line 50: void (*doit)(void *) = prog_entry(prog); function definition argument 'void *' should also have an identifier name -- To view, visit https://review.coreboot.org/c/coreboot/+/29494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96961246cd257b63cf167238aa0cf6e65272b951 Gerrit-Change-Number: 29494 Gerrit-PatchSet: 7 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Thu, 29 Nov 2018 10:34:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/dragonegg: Don't use device_t
by Patrick Georgi (Code Review) 29 Nov '18

29 Nov '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29915 ) Change subject: mb/google/dragonegg: Don't use device_t ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief858f6612d1c7b4b0c286cf5938f8c29055f1b5 Gerrit-Change-Number: 29915 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Nov 2018 09:30:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: include/device/smbus.h: Don't use device_t
by Patrick Georgi (Code Review) 29 Nov '18

29 Nov '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29914 ) Change subject: include/device/smbus.h: Don't use device_t ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c88642133d3cbf33015e3e1e855fb2c786878d6 Gerrit-Change-Number: 29914 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Nov 2018 09:30:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/x86/Makefile.inc: Fix typo
by Patrick Georgi (Code Review) 29 Nov '18

29 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29878 ) Change subject: arch/x86/Makefile.inc: Fix typo ...................................................................... arch/x86/Makefile.inc: Fix typo Link 32bit ramstage if CONFIG_ARCH_RAMSTAGE_X86_32 is set. Required for 64bit ramstage support. Change-Id: Ib0c06f494dcc035d182ab9034e910ceceb236198 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/c/29878 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/x86/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index fcc57c5..c5cf625 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -398,7 +398,7 @@ $(objgenerated)/ramstage.o: $$(ramstage-objs) $(COMPILER_RT_ramstage) $$(ramstage-libs) @printf " CC $(subst $(obj)/,,$(@))\n" -ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) +ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) $(LD_ramstage) -m elf_i386 -r -o $@ $(COMPILER_RT_FLAGS_ramstage) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) $(ramstage-libs) --no-whole-archive $(COMPILER_RT_ramstage) --end-group else $(LD_ramstage) -m elf_x86_64 -r -o $@ $(COMPILER_RT_FLAGS_ramstage) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) $(ramstage-libs) --no-whole-archive $(COMPILER_RT_ramstage) --end-group -- To view, visit https://review.coreboot.org/c/coreboot/+/29878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0c06f494dcc035d182ab9034e910ceceb236198 Gerrit-Change-Number: 29878 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: MAINTAINERS: Add myself as a maintainer
by Angel Pons (Code Review) 29 Nov '18

29 Nov '18

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29913 ) Change subject: MAINTAINERS: Add myself as a maintainer ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70df3b9e4e36c2e5d73f8888fe0ec220aa8a91b7 Gerrit-Change-Number: 29913 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Nov 2018 09:25:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mediatek/mt8183: Add external interrupts (EINT) support
by Tristan Hsieh (Code Review) 29 Nov '18

29 Nov '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29921 Change subject: mediatek/mt8183: Add external interrupts (EINT) support ...................................................................... mediatek/mt8183: Add external interrupts (EINT) support To communicate with TPM, We need EINT dirver for TPM intterupt. BUG=b:80501386 BRANCH=none TEST=emerge-kukui coreboot Change-Id: I730ee52226d17bf4ab51aa0ec09ea331766548ab Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/addressmap.h 2 files changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/29921/1 diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index b981e45..244b2c4 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -2,7 +2,7 @@ bootblock-y += auxadc.c bootblock-y += bootblock.c -bootblock-y += ../common/gpio.c gpio.c +bootblock-y += ../common/eint.c ../common/gpio.c gpio.c bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c bootblock-y += ../common/timer.c @@ -14,7 +14,7 @@ decompressor-y += ../common/timer.c verstage-y += auxadc.c -verstage-y += ../common/gpio.c gpio.c +verstage-y += ../common/eint.c ../common/gpio.c gpio.c verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c verstage-y += ../common/timer.c verstage-y += ../common/uart.c @@ -26,7 +26,7 @@ romstage-y += dramc_pi_basic_api.c romstage-y += dramc_pi_calibration_api.c romstage-y += memory.c -romstage-y += ../common/gpio.c gpio.c +romstage-y += ../common/eint.c ../common/gpio.c gpio.c romstage-y += ../common/mmu_operations.c mmu_operations.c romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6358.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c @@ -36,7 +36,7 @@ ramstage-y += auxadc.c ramstage-y += ../common/cbmem.c emi.c -ramstage-y += ../common/gpio.c gpio.c +ramstage-y += ../common/eint.c ../common/gpio.c gpio.c ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += soc.c diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h index 7578c28..2b2c8e8 100644 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -28,6 +28,7 @@ SPM_BASE = IO_PHYS + 0x00006000, RGU_BASE = IO_PHYS + 0x00007000, GPT_BASE = IO_PHYS + 0x00008000, + EINT_BASE = IO_PHYS + 0x0000B000, APMIXED_BASE = IO_PHYS + 0x0000C000, PWRAP_BASE = IO_PHYS + 0x0000D000, EMI_BASE = IO_PHYS + 0x00219000, -- To view, visit https://review.coreboot.org/c/coreboot/+/29921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I730ee52226d17bf4ab51aa0ec09ea331766548ab Gerrit-Change-Number: 29921 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: broadcom: Remove SoC and board support
by Angel Pons (Code Review) 29 Nov '18

29 Nov '18

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29905 ) Change subject: broadcom: Remove SoC and board support ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/29905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I148dd7eb0192d396cb69bc26c4062f88a764771a Gerrit-Change-Number: 29905 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Nov 2018 09:20:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: [WIP, DONOTMERGE] Remove -Wno-unused-but-set-variable
by Angel Pons (Code Review) 29 Nov '18

29 Nov '18

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29920 Change subject: [WIP, DONOTMERGE] Remove -Wno-unused-but-set-variable ...................................................................... [WIP, DONOTMERGE] Remove -Wno-unused-but-set-variable It should work properly now. Right now, this would break pretty much everything. Change-Id: I893e00079b85c82dc9f43fefb00fc00b4d078928 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/29920/1 diff --git a/Makefile.inc b/Makefile.inc index aaae7bc..2ef0851 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -395,7 +395,7 @@ CFLAGS_common += -Wno-packed-not-aligned CFLAGS_common += -fconserve-stack # cf. commit f69a99db (coreboot: x86: enable gc-sections) -CFLAGS_common += -Wno-unused-but-set-variable +# CFLAGS_common += -Wno-unused-but-set-variable endif endif -- To view, visit https://review.coreboot.org/c/coreboot/+/29920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I893e00079b85c82dc9f43fefb00fc00b4d078928 Gerrit-Change-Number: 29920 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: arch/x86/Makefile.inc: Fix typo
by Hellsenberg (Code Review) 29 Nov '18

29 Nov '18

Hellsenberg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29878 ) Change subject: arch/x86/Makefile.inc: Fix typo ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/29878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0c06f494dcc035d182ab9034e910ceceb236198 Gerrit-Change-Number: 29878 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Hellsenberg <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Nov 2018 09:02:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/drivers/spi: Remove not used variable
by Hellsenberg (Code Review) 29 Nov '18

29 Nov '18

Hellsenberg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29917 ) Change subject: src/drivers/spi: Remove not used variable ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Hellsenberg <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Nov 2018 09:01:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/fizz/variants/karma: Disable native SD card controller
by David Wu (Code Review) 29 Nov '18

29 Nov '18

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29918 Change subject: mb/google/fizz/variants/karma: Disable native SD card controller ...................................................................... mb/google/fizz/variants/karma: Disable native SD card controller This change selects Kconfig option to disable native SD card controller in ACPI tables. BUG=b:119798840 BRANCH=master TEST=Compiles successfully and boot on DUT. Change-Id: I68dc9be511a370d882e4656c165efbe5dc6ee52e Signed-off-by: David Wu <David_Wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/fizz/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/29918/1 diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index e1fc38d..26f6f3a 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -11,6 +11,7 @@ select EC_GOOGLE_CHROMEEC_ACPI_USB_PORT_POWER select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_LPC + select EXCLUDE_NATIVE_SD_INTERFACE if BOARD_GOOGLE_KARMA select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_GMA_HAVE_VBT -- To view, visit https://review.coreboot.org/c/coreboot/+/29918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68dc9be511a370d882e4656c165efbe5dc6ee52e Gerrit-Change-Number: 29918 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [TESTME]soc/intel/fsp_broadwell_de: Implement postcar stage
by Arthur Heymans (Code Review) 29 Nov '18

29 Nov '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29908 ) Change subject: [TESTME]soc/intel/fsp_broadwell_de: Implement postcar stage ...................................................................... Patch Set 2: > Patch Set 2: > > Werner and I can test it Thx. It's a rather naive attempt and could amongst not booting at all result in a significant slowdown so checking the timestamps could be interesting. -- To view, visit https://review.coreboot.org/c/coreboot/+/29908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic31702514cf84e3480b622c28cd2857e613869d9 Gerrit-Change-Number: 29908 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Nov 2018 08:47:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/drivers/spi: Remove not used variable
by HAOUAS Elyes (Code Review) 29 Nov '18

29 Nov '18

Hello Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29917 to look at the new patch set (#2). Change subject: src/drivers/spi: Remove not used variable ...................................................................... src/drivers/spi: Remove not used variable Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/spi/sst.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/29917/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: src/drivers/spi: Remove not used variable
by HAOUAS Elyes (Code Review) 29 Nov '18

29 Nov '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29917 Change subject: src/drivers/spi: Remove not used variable ...................................................................... src/drivers/spi: Remove not used variable Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M Makefile.inc M src/drivers/spi/sst.c 2 files changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/29917/1 diff --git a/Makefile.inc b/Makefile.inc index aaae7bc..df3e227 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -395,7 +395,7 @@ CFLAGS_common += -Wno-packed-not-aligned CFLAGS_common += -fconserve-stack # cf. commit f69a99db (coreboot: x86: enable gc-sections) -CFLAGS_common += -Wno-unused-but-set-variable +CFLAGS_common += -Wall endif endif diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index 559969a..7a0428f 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -172,7 +172,7 @@ static int sst_write_256(const struct spi_flash *flash, u32 offset, size_t len, const void *buf) { - size_t actual, chunk_len, cmd_len; + size_t actual, chunk_len; unsigned long byte_addr; unsigned long page_size; int ret = 0; @@ -193,7 +193,6 @@ if (ret) goto done; - cmd_len = 4; cmd[0] = CMD_SST_AAI_WP; cmd[1] = offset >> 16; cmd[2] = offset >> 8; -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Fix coreboot table record alignment to 8-byte boundary
by Xiang Wang (Code Review) 29 Nov '18

29 Nov '18

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29916 Change subject: Fix coreboot table record alignment to 8-byte boundary ...................................................................... Fix coreboot table record alignment to 8-byte boundary I found that I triggered an unaligned memory access exception when debugging riscv's coreboot code. Because some records are aligned to a 4-byte boundary, such as lb_timestamp. It is defined as follows struct lb_timestamp { uint32_t tag; uint32_t size; uint32_t timestamp; }; This may causes data misaligned access exceptions at 64bit machine. Change-Id: I1846be0e26ab3c81858d8cf727517e1462035e64 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/lib/coreboot_table.c 1 file changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/29916/1 diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index c2ae094..20f9aae 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -84,8 +84,10 @@ { struct lb_record *rec; rec = lb_last_record(header); - if (header->table_entries) + if (header->table_entries) { + rec->size = ALIGN_UP(rec->size, 8); header->table_bytes += rec->size; + } rec = lb_last_record(header); header->table_entries++; rec->tag = LB_TAG_UNUSED; @@ -358,9 +360,9 @@ mainboard = (struct lb_mainboard *)rec; mainboard->tag = LB_TAG_MAINBOARD; - mainboard->size = ALIGN_UP(sizeof(*mainboard) + + mainboard->size = sizeof(*mainboard) + strlen(mainboard_vendor) + 1 + - strlen(mainboard_part_number) + 1, 8); + strlen(mainboard_part_number) + 1; mainboard->vendor_idx = 0; mainboard->part_number_idx = strlen(mainboard_vendor) + 1; @@ -411,7 +413,7 @@ rec = (struct lb_string *)lb_new_record(header); len = strlen(strings[i].string); rec->tag = strings[i].tag; - rec->size = ALIGN_UP(sizeof(*rec) + len + 1, 8); + rec->size = sizeof(*rec) + len + 1; memcpy(rec->string, strings[i].string, len+1); } -- To view, visit https://review.coreboot.org/c/coreboot/+/29916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1846be0e26ab3c81858d8cf727517e1462035e64 Gerrit-Change-Number: 29916 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/dragonegg: Don't use device_t
by HAOUAS Elyes (Code Review) 29 Nov '18

29 Nov '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29915 Change subject: mb/google/dragonegg: Don't use device_t ...................................................................... mb/google/dragonegg: Don't use device_t Use of device_t is deprecated. Change-Id: Ief858f6612d1c7b4b0c286cf5938f8c29055f1b5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/dragonegg/mainboard.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/29915/1 diff --git a/src/mainboard/google/dragonegg/mainboard.c b/src/mainboard/google/dragonegg/mainboard.c index 3e8fd9f..c4df94b 100644 --- a/src/mainboard/google/dragonegg/mainboard.c +++ b/src/mainboard/google/dragonegg/mainboard.c @@ -26,7 +26,7 @@ mainboard_ec_init(); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device *dev) { dev->ops->write_acpi_tables = NULL; dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; -- To view, visit https://review.coreboot.org/c/coreboot/+/29915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief858f6612d1c7b4b0c286cf5938f8c29055f1b5 Gerrit-Change-Number: 29915 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: tss: implement Cr50 vendor-specific VENDOR_CC_TPM_MODE
by build bot (Jenkins) (Code Review) 29 Nov '18

29 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29648 ) Change subject: tss: implement Cr50 vendor-specific VENDOR_CC_TPM_MODE ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/#/c/29648/6/src/security/tpm/tss/tcg-2.0/tss_ma… File src/security/tpm/tss/tcg-2.0/tss_marshaling.c: https://review.coreboot.org/#/c/29648/6/src/security/tpm/tss/tcg-2.0/tss_ma… PS6, Line 482: break; break is not useful after a goto or return -- To view, visit https://review.coreboot.org/c/coreboot/+/29648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd55708797d2b17336fcbe80c0724957f7052e90 Gerrit-Change-Number: 29648 Gerrit-PatchSet: 6 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Comment-Date: Thu, 29 Nov 2018 07:32:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2018