Change in ...coreboot[master]: Mistral: QCS405: Added RPM support

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[e-mail] has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29970

Change subject: Mistral: QCS405: Added RPM support
......................................................................

Mistral: QCS405: Added RPM support

This pacth adds support to read RPM image from
3rdparty/blobs and load it. It takes RPM out of reset.

Change-Id: I17f491f0a4bd0dce7522b7e80e1bac97ec18b945
Signed-off-by: Nitheesh Sekar 
Signed-off-by: Sricharan R 
---
M src/soc/qualcomm/qcs405/Makefile.inc
M src/soc/qualcomm/qcs405/clock.c
M src/soc/qualcomm/qcs405/include/soc/clock.h
M src/soc/qualcomm/qcs405/include/soc/memlayout.ld
A src/soc/qualcomm/qcs405/include/soc/rpm.h
M src/soc/qualcomm/qcs405/include/soc/symbols.h
M src/soc/qualcomm/qcs405/mmu.c
A src/soc/qualcomm/qcs405/rpm_load_reset.c
M src/soc/qualcomm/qcs405/soc.c
9 files changed, 105 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/29970/1

diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc
index ee68751..47ec7ca 100644
--- a/src/soc/qualcomm/qcs405/Makefile.inc
+++ b/src/soc/qualcomm/qcs405/Makefile.inc
@@ -38,6 +38,7 @@
 ramstage-y += gpio.c
 ramstage-y += clock.c
 ramstage-$(CONFIG_DRIVERS_UART) += uart.c
+ramstage-y += rpm_load_reset.c
 ramstage-y += usb.c
 ramstage-y += flash_controller.c

@@ -74,6 +75,17 @@
 endif

################################################################################
+RPM_FILE := $(QCS405_BLOB)/rpm.mbn
+rpm_file := $(shell ls $(RPM_FILE))
+ifneq (,$(findstring $(RPM_FILE),$(rpm_file)))
+	RPM_CBFS := $(CONFIG_CBFS_PREFIX)/rpm
+	$(RPM_CBFS)-file := $(RPM_FILE)
+	$(RPM_CBFS)-type := payload
+	$(RPM_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+	cbfs-files-y += $(RPM_CBFS)
+endif
+
+################################################################################
 QC_SEC_FILE := $(QCS405_BLOB)/qc_sec.mbn
 qc_sec_file := $(shell ls $(QC_SEC_FILE))
 ifneq (,$(findstring $(QC_SEC_FILE),$(qc_sec_file)))
diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c
index f26face..a129613 100644
--- a/src/soc/qualcomm/qcs405/clock.c
+++ b/src/soc/qualcomm/qcs405/clock.c
@@ -175,6 +175,13 @@
    return 0;
 }

+void clock_reset_rpm(void)
+{
+	/* Bring RPM out of RESET */
+
+	clrbits_le32(REG(GCC_APSS_MISC), BIT(RPM_RESET_REMOVAL));
+}
+
 int clock_reset_bcr(void *bcr_addr, bool reset)
 {
    struct qcs405_bcr *bcr = bcr_addr;
diff --git a/src/soc/qualcomm/qcs405/include/soc/clock.h b/src/soc/qualcomm/qcs405/include/soc/clock.h
index d02ecd7..2736133 100644
--- a/src/soc/qualcomm/qcs405/include/soc/clock.h
+++ b/src/soc/qualcomm/qcs405/include/soc/clock.h
@@ -16,6 +16,8 @@
 #define	__SOC_QUALCOMM_QCS405_CLOCK_H__

#define	GCC_APCS_CLOCK_BRANCH_ENA_VOTE			0x01845004
+#define GCC_APSS_MISC				0x1860000
+#define RPM_RESET_REMOVAL			0

#define	GCC_BLSP1_UART0_BASE			0x180600C
 #define	GCC_BLSP1_UART1_BASE			0x1802044
@@ -143,7 +145,7 @@
 };

void clock_init(void);
-void clock_reset_aop(void);
+void clock_reset_rpm(void);
 int clock_configure_qspi(uint32_t hz);
 int clock_reset_bcr(void *bcr_addr, bool reset);

diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld
index 8566f9f..9e7df11 100644
--- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld
@@ -24,8 +24,16 @@
 #define BSRAM_START(addr) SYMBOL(bsram, addr)
 #define BSRAM_END(addr) SYMBOL(ebsram, addr)

+/* RPM : 0x0B000000 - 0x0B100000 */
+#define RPMSRAM_START(addr) SYMBOL(rpmsram, addr)
+#define RPMSRAM_END(addr) SYMBOL(rpmsram, addr)
+
 SECTIONS
 {
+	RPMSRAM_START(0x00200000)
+	REGION(rpm, 0x00200000, 0xA4000, 0x0)
+	RPMSRAM_END(0x02A4000)
+
    SSRAM_START(0x8600000)
    SSRAM_END(0x8608000)

diff --git a/src/soc/qualcomm/qcs405/include/soc/rpm.h b/src/soc/qualcomm/qcs405/include/soc/rpm.h
new file mode 100644
index 0000000..e83253f
--- /dev/null
+++ b/src/soc/qualcomm/qcs405/include/soc/rpm.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_QUALCOMM_QCS405_RPM_H__
+#define _SOC_QUALCOMM_QCS405_RPM_H__
+
+void rpm_fw_load_reset(void);
+
+#endif  // _SOC_QUALCOMM_QCS405_RPM_H__
diff --git a/src/soc/qualcomm/qcs405/include/soc/symbols.h b/src/soc/qualcomm/qcs405/include/soc/symbols.h
index 447b7ae..74ba170 100644
--- a/src/soc/qualcomm/qcs405/include/soc/symbols.h
+++ b/src/soc/qualcomm/qcs405/include/soc/symbols.h
@@ -38,4 +38,8 @@
 extern u8 _epmic[];
 #define _pmic_size (_epmic - _pmic)

+extern u8 _rpm[];
+extern u8 _erpm[];
+#define _rpm_size (_erpm - _rpm)
+
 #endif // _SOC_QUALCOMM_QCS405_SYMBOLS_H_
diff --git a/src/soc/qualcomm/qcs405/mmu.c b/src/soc/qualcomm/qcs405/mmu.c
index ecae39f..1cf4a36 100644
--- a/src/soc/qualcomm/qcs405/mmu.c
+++ b/src/soc/qualcomm/qcs405/mmu.c
@@ -28,6 +28,7 @@
    mmu_config_range((void *)_ssram, _ssram_size, MA_MEM | MA_S | MA_RW);
    mmu_config_range((void *)_bsram, _bsram_size, MA_MEM | MA_S | MA_RW);
    mmu_config_range((void *)0x80000000, 0x40000000, MA_MEM | MA_S | MA_RW);
+	mmu_config_range((void *)_rpm, _rpm_size, MA_MEM | MA_NS | MA_RW);

mmu_enable();
 }
@@ -35,4 +36,5 @@
 void qcs405_mmu_dram_config_c(void)
 {
    mmu_config_range((void *)0x80000000, 0x40000000, MA_MEM | MA_NS | MA_RW);
+	mmu_config_range((void *)_rpm, _rpm_size, MA_MEM | MA_NS | MA_RW);
 }
diff --git a/src/soc/qualcomm/qcs405/rpm_load_reset.c b/src/soc/qualcomm/qcs405/rpm_load_reset.c
new file mode 100644
index 0000000..d0dac3f
--- /dev/null
+++ b/src/soc/qualcomm/qcs405/rpm_load_reset.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <arch/cache.h>
+#include <cbfs.h>
+#include <halt.h>
+#include <console/console.h>
+#include <timestamp.h>
+#include <soc/mmu.h>
+#include <soc/rpm.h>
+#include <soc/clock.h>
+
+void rpm_fw_load_reset(void)
+{
+	bool rpm_fw_entry;
+
+	struct prog rpm_fw_prog =
+		PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/rpm");
+	printk(BIOS_DEBUG, "\nNIT:PROG_INIT for /rpm has happened.\n");
+
+	if (prog_locate(&rpm_fw_prog))
+		die("SOC image: RPM_FW not found");
+	printk(BIOS_DEBUG, "\nNIT:PROG_LOCATE for /rpm has happened.\n");
+
+	rpm_fw_entry = selfload(&rpm_fw_prog);
+	if (!rpm_fw_entry)
+		die("SOC image: RPM load failed");
+	printk(BIOS_DEBUG, "\nNIT:SELF_LOAD of rpm has happened.\n");
+
+	clock_reset_rpm();
+
+	printk(BIOS_DEBUG, "\nSOC:RPM brought out of reset.\n");
+}
diff --git a/src/soc/qualcomm/qcs405/soc.c b/src/soc/qualcomm/qcs405/soc.c
index 3de3c02..9be1bdc 100644
--- a/src/soc/qualcomm/qcs405/soc.c
+++ b/src/soc/qualcomm/qcs405/soc.c
@@ -18,6 +18,7 @@
 #include <timestamp.h>
 #include <soc/mmu.h>
 #include <soc/symbols.h>
+#include <soc/rpm.h>

static void soc_read_resources(device_t dev)
 {
@@ -28,7 +29,7 @@

static void soc_init(device_t dev)
 {
-
+	rpm_fw_load_reset();
 }

static struct device_operations soc_ops = {