coreboot-gerrit August 2017

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Change in coreboot[master]: mainboard/google/soraka: Remove Atmel Touchscreen
by build bot (Jenkins) (Code Review) 29 Aug '17

29 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21248 ) Change subject: mainboard/google/soraka: Remove Atmel Touchscreen ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/14791/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59487/ : SUCCESS -- To view, visit https://review.coreboot.org/21248 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I67af787d231317a80998fb483eed5674de19aeb4 Gerrit-Change-Number: 21248 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Aug 2017 19:01:31 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/zoombini: Add new board
by build bot (Jenkins) (Code Review) 29 Aug '17

29 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21273 ) Change subject: google/zoombini: Add new board ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/59490/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/14794/ : SUCCESS -- To view, visit https://review.coreboot.org/21273 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I13ebaae403d08f1b2e6881eeba4dc1787c792b4e Gerrit-Change-Number: 21273 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Aug 2017 18:58:46 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Define Max PCIE Root Ports
by build bot (Jenkins) (Code Review) 29 Aug '17

29 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21272 ) Change subject: soc/intel/cannonlake: Define Max PCIE Root Ports ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/14789/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59485/ : SUCCESS -- To view, visit https://review.coreboot.org/21272 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id45ff6e96043ed71117018a4e73d08920ae9667e Gerrit-Change-Number: 21272 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Aug 2017 18:57:51 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/zoombini: Add new board
by Nick Vaccaro (Code Review) 29 Aug '17

29 Aug '17

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/21273 Change subject: google/zoombini: Add new board ...................................................................... google/zoombini: Add new board Add zoombini board files using cannonlake and FSP 2.0. BUG=b:64395641 BRANCH=None TEST=None Change-Id: I13ebaae403d08f1b2e6881eeba4dc1787c792b4e Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- A src/mainboard/google/zoombini/Kconfig A src/mainboard/google/zoombini/Kconfig.name A src/mainboard/google/zoombini/Makefile.inc A src/mainboard/google/zoombini/acpi/ec.asl A src/mainboard/google/zoombini/acpi/superio.asl A src/mainboard/google/zoombini/acpi_tables.c A src/mainboard/google/zoombini/board_info.txt A src/mainboard/google/zoombini/boardid.c A src/mainboard/google/zoombini/bootblock.c A src/mainboard/google/zoombini/chromeos.c A src/mainboard/google/zoombini/chromeos.fmd A src/mainboard/google/zoombini/ec.c A src/mainboard/google/zoombini/ramstage.c A src/mainboard/google/zoombini/romstage.c A src/mainboard/google/zoombini/smihandler.c A src/mainboard/google/zoombini/variants/baseboard/Makefile.inc A src/mainboard/google/zoombini/variants/baseboard/boardid.c A src/mainboard/google/zoombini/variants/baseboard/devicetree.cb A src/mainboard/google/zoombini/variants/baseboard/gpio.c A src/mainboard/google/zoombini/variants/baseboard/include/baseboard/ec.h A src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h A src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/zoombini/variants/zoombini/include/variant/ec.h M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/Makefile.inc 25 files changed, 982 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/21273/1 diff --git a/src/mainboard/google/zoombini/Kconfig b/src/mainboard/google/zoombini/Kconfig new file mode 100644 index 0000000..22502cd --- /dev/null +++ b/src/mainboard/google/zoombini/Kconfig @@ -0,0 +1,78 @@ +if BOARD_GOOGLE_ZOOMBINI + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ID_AUTO + select BOARD_ROMSIZE_KB_16384 + select DRIVERS_I2C_GENERIC + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_LPC + select MAINBOARD_HAS_CHROMEOS + select SOC_INTEL_CANNONLAKE + +config CHROMEOS + select EC_GOOGLE_CHROMEEC_SWITCHES + +config DEVICETREE + string + default "variants/baseboard/devicetree.cb" + +config DRIVER_TPM_I2C_BUS + depends on ZOOMBINI_USE_I2C_TPM + default 0x1 + +config DRIVER_TPM_I2C_ADDR + depends on ZOOMBINI_USE_I2C_TPM + default 0x50 + +config DRIVER_TPM_SPI_BUS + depends on ZOOMBINI_USE_SPI_TPM + default 0x1 + +config GBB_HWID + string + depends on CHROMEOS + default "ZOOMBINI TEST 5722" if BOARD_GOOGLE_ZOOMBINI + +config MAINBOARD_DIR + string + default "google/zoombini" + +config MAINBOARD_FAMILY + string + default "Google_Zoombini" if BOARD_GOOGLE_ZOOMBINI + +config MAINBOARD_PART_NUMBER + string + default "Zoombini" if BOARD_GOOGLE_ZOOMBINI + +config MAINBOARD_VENDOR + string + default "Google" + +config VARIANT_DIR + string + default "zoombini" if BOARD_GOOGLE_ZOOMBINI + +config VBOOT + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_LID_SWITCH + +# Select this option to enable use of cr50 I2C TPM on zoombini. +config ZOOMBINI_USE_I2C_TPM + bool + default n + select I2C_TPM + select MAINBOARD_HAS_I2C_TPM_CR50 + select TPM2 + +# Select this option to enable use of cr50 SPI TPM on zoombini. +config ZOOMBINI_USE_SPI_TPM + bool + default y + select MAINBOARD_HAS_SPI_TPM_CR50 + select SPI_TPM + select TPM2 + +endif # BOARD_GOOGLE_ZOOMBINI diff --git a/src/mainboard/google/zoombini/Kconfig.name b/src/mainboard/google/zoombini/Kconfig.name new file mode 100644 index 0000000..da038f6 --- /dev/null +++ b/src/mainboard/google/zoombini/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GOOGLE_ZOOMBINI + bool "Zoombini" diff --git a/src/mainboard/google/zoombini/Makefile.inc b/src/mainboard/google/zoombini/Makefile.inc new file mode 100644 index 0000000..97f0173 --- /dev/null +++ b/src/mainboard/google/zoombini/Makefile.inc @@ -0,0 +1,37 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += bootblock.c +bootblock-$(CONFIG_CHROMEOS) += chromeos.c + +verstage-$(CONFIG_CHROMEOS) += chromeos.c + +romstage-y += boardid.c +romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += romstage.c + +ramstage-y += boardid.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include + +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + + diff --git a/src/mainboard/google/zoombini/acpi/ec.asl b/src/mainboard/google/zoombini/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/zoombini/acpi/ec.asl diff --git a/src/mainboard/google/zoombini/acpi/superio.asl b/src/mainboard/google/zoombini/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/zoombini/acpi/superio.asl diff --git a/src/mainboard/google/zoombini/acpi_tables.c b/src/mainboard/google/zoombini/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/zoombini/acpi_tables.c diff --git a/src/mainboard/google/zoombini/board_info.txt b/src/mainboard/google/zoombini/board_info.txt new file mode 100644 index 0000000..3ed5a7e --- /dev/null +++ b/src/mainboard/google/zoombini/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Zoombini Cannonlake Reference Board +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/zoombini/boardid.c b/src/mainboard/google/zoombini/boardid.c new file mode 100644 index 0000000..bd9afde --- /dev/null +++ b/src/mainboard/google/zoombini/boardid.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <boardid.h> +#include <stddef.h> + +uint8_t board_id(void) +{ + MAYBE_STATIC int id = -1; + + if (id < 0) + id = variant_board_id(); + + return id; +} diff --git a/src/mainboard/google/zoombini/bootblock.c b/src/mainboard/google/zoombini/bootblock.c new file mode 100644 index 0000000..5f37206 --- /dev/null +++ b/src/mainboard/google/zoombini/bootblock.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <bootblock_common.h> +#include <soc/gpio.h> + +static void early_config_gpio(void) +{ + const struct pad_config *early_gpio_table; + size_t num_gpios = 0; + + early_gpio_table = variant_early_gpio_table(&num_gpios); + gpio_configure_pads(early_gpio_table, num_gpios); +} + +void bootblock_mainboard_init(void) +{ + early_config_gpio(); +} diff --git a/src/mainboard/google/zoombini/chromeos.c b/src/mainboard/google/zoombini/chromeos.c new file mode 100644 index 0000000..a04065e --- /dev/null +++ b/src/mainboard/google/zoombini/chromeos.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/gpio.h> +#include <gpio.h> +#include <rules.h> +#include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + + +#if ENV_RAMSTAGE +#include <boot/coreboot_tables.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), + "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} +#endif /* ENV_RAMSTAGE */ + +int get_write_protect_state(void) +{ + /* Read PCH_WP GPIO. */ + return gpio_get(GPIO_PCH_WP); +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/zoombini/chromeos.fmd b/src/mainboard/google/zoombini/chromeos.fmd new file mode 100644 index 0000000..bdadcf7 --- /dev/null +++ b/src/mainboard/google/zoombini/chromeos.fmd @@ -0,0 +1,43 @@ +FLASH@0xff000000 0x1000000 { + SI_ALL@0x0 0x200000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x1ff000 + } + SI_BIOS@0x200000 0xe00000 { + RW_SECTION_A@0x0 0x3e8000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x3d7fc0 + RW_FWID_A@0x3e7fc0 0x40 + } + RW_SECTION_B@0x3e8000 0x3e8000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x3d7fc0 + RW_FWID_B@0x3e7fc0 0x40 + } + RW_MISC@0x7d0000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_ELOG@0x20000 0x4000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD@0x28000 0x2000 + RW_NVRAM@0x2a000 0x6000 + } + RW_LEGACY(CBFS)@0x800000 0x200000 + WP_RO@0xa00000 0x400000 { + RO_VPD@0x0 0x4000 + RO_UNUSED@0x4000 0xc000 + RO_SECTION@0x10000 0x3f0000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x300000 + } + } + } +} diff --git a/src/mainboard/google/zoombini/ec.c b/src/mainboard/google/zoombini/ec.c new file mode 100644 index 0000000..850b13c --- /dev/null +++ b/src/mainboard/google/zoombini/ec.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <ec/google/chromeec/ec.h> + +#include <variant/ec.h> + +void mainboard_ec_init(void) +{ + if (acpi_is_wakeup_s3()) { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S3_WAKE_EVENTS); + + /* Disable SMI and wake events */ + google_chromeec_set_smi_mask(0); + + /* Clear pending events */ + while (google_chromeec_get_event() != 0) + ; + + /* Restore SCI event mask */ + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); + } else { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S5_WAKE_EVENTS); + } + + /* Clear wake event mask */ + google_chromeec_set_wake_mask(0); +} diff --git a/src/mainboard/google/zoombini/ramstage.c b/src/mainboard/google/zoombini/ramstage.c new file mode 100644 index 0000000..6dafe65 --- /dev/null +++ b/src/mainboard/google/zoombini/ramstage.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> + +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/google/zoombini/romstage.c b/src/mainboard/google/zoombini/romstage.c new file mode 100644 index 0000000..bbfb985 --- /dev/null +++ b/src/mainboard/google/zoombini/romstage.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/romstage.h> + +void mainboard_save_dimm_info(void); + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ +/* + meminit_lpddr4_by_sku(&memupd->FspmConfig, get_lpddr4_config(), + get_memory_sku()); +*/ +} + +void mainboard_save_dimm_info(void) +{ +/* + save_lpddr4_dimm_info(get_lpddr4_config(), get_memory_sku()); +*/ +} diff --git a/src/mainboard/google/zoombini/smihandler.c b/src/mainboard/google/zoombini/smihandler.c new file mode 100644 index 0000000..e4ca589 --- /dev/null +++ b/src/mainboard/google/zoombini/smihandler.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/smm.h> +#include <ec/google/chromeec/smm.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <soc/smm.h> + +#include "ec.h" + +void mainboard_smi_espi_handler(void) +{ + chromeec_smi_process_events(); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, + MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, + MAINBOARD_EC_SMI_EVENTS); + return 0; +} diff --git a/src/mainboard/google/zoombini/variants/baseboard/Makefile.inc b/src/mainboard/google/zoombini/variants/baseboard/Makefile.inc new file mode 100644 index 0000000..3385b4c --- /dev/null +++ b/src/mainboard/google/zoombini/variants/baseboard/Makefile.inc @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += gpio.c + +romstage-y += boardid.c + +ramstage-y += boardid.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/zoombini/variants/baseboard/boardid.c b/src/mainboard/google/zoombini/variants/baseboard/boardid.c new file mode 100644 index 0000000..1cb084a --- /dev/null +++ b/src/mainboard/google/zoombini/variants/baseboard/boardid.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <ec/google/chromeec/ec.h> + +uint8_t __attribute__((weak)) variant_board_id(void) +{ + return google_chromeec_get_board_version(); +} diff --git a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb new file mode 100644 index 0000000..e71f15b --- /dev/null +++ b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb @@ -0,0 +1,61 @@ +chip soc/intel/cannonlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA Thermal device + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.5 on end # SDCard + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on end # SATA + device pci 19.0 on end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 on end # UART #2 + device pci 1a.0 on end # eMMC + device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 + device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/google/zoombini/variants/baseboard/gpio.c b/src/mainboard/google/zoombini/variants/baseboard/gpio.c new file mode 100644 index 0000000..5eef040 --- /dev/null +++ b/src/mainboard/google/zoombini/variants/baseboard/gpio.c @@ -0,0 +1,274 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { +/* RCIN# */ PAD_CFG_GPI(GPP_A0, NONE, DEEP), /* PCH_CSI_GPIO1 */ +/* ESPI_IO0 */ +/* ESPI_IO1 */ +/* ESPI_IO2 */ +/* ESPI_IO3 */ +/* ESPI_CS# */ +/* SERIRQ */ PAD_CFG_GPI(GPP_A6, NONE, DEEP), /* PCH_CSI_GPIO2 */ +/* PIRQA# */ PAD_NC(GPP_A7, NONE), /* PCH_CSI_GPIO1 */ +/* CLKRUN# */ PAD_CFG_GPI(GPP_A8, NONE, DEEP), /* EC_IN_RW_OD */ +/* ESPI_CLK */ +/* CLKOUT_LPC1 */ PAD_CFG_GPO(GPP_A10, 0, DEEP), /* PEN_RESET_ODL */ +/* PME# */ PAD_NC(GPP_A11, NONE), +/* BM_BUSY# */ PAD_CFG_GPI(GPP_A12, UP_20K, DEEP), /* FPMCU_INT */ +/* SUSWARN# */ +/* ESPI_RESET# */ +/* SUSACK# */ +/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), +/* SD_PWR_EN# */ +/* ISH_GP0 */ PAD_CFG_GPO(GPP_A18, 0, DEEP), + /* GNSS_DISABLE_1V8_ODL */ +/* ISH_GP1 */ PAD_CFG_GPO(GPP_A19, 0, DEEP), + /* WWAN_RADIO_DISABLE_1V8_ODL */ +/* ISH_GP2 */ PAD_CFG_GPI(GPP_A20, NONE, DEEP), /* GP_INT_ODL */ +/* ISH_GP3 */ PAD_CFG_GPI(GPP_A21, NONE, DEEP), /* FPMCU_PCH_BOOT0 */ +/* ISH_GP4 */ PAD_CFG_GPI(GPP_A22, UP_20K, DEEP), /* FPMCU_INT */ +/* ISH_GP5 */ PAD_CFG_GPO(GPP_A23, 0, DEEP), /* FPMCU_RST_ODL */ +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), +/* VRALERT# */ PAD_NC(GPP_B2, NONE), +/* CPU_GP2 */ PAD_NC(GPP_B3, NONE), +/* CPU_GP3 */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0# */ PAD_NC(GPP_B5, NONE), +/* SRCCLKREQ1# */ +/* SRCCLKREQ2# */ +/* SRCCLKREQ3# */ +/* SRCCLKREQ4# */ PAD_NC(GPP_B9, NONE), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), +/* EXT_PWR_GATE# */ +/* SLP_S0# */ +/* PLTRST# */ +/* SPKR */ PAD_NC(GPP_B14, DN_20K), /* GPP_B14_STRAP */ +#if IS_ENABLED(CONFIG_ZOOMBINI_USE_SPI_TPM) +/* GSPI0_CS# */ /* H1_SLAVE_SPI_CS_L */ +/* GSPI0_CLK */ /* H1_SLAVE_SPI_CLK_R */ +/* GSPI0_MISO */ /* H1_SLAVE_SPI_MISO_R */ +/* GSPI0_MOSI */ /* H1_SLAVE_SPI_MOSI_R */ +#else +/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), +/* GSPI0_CLK */ PAD_NC(GPP_B16, NONE), +/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), +#endif +/* GSPI1_CS# */ +/* GSPI1_CLK */ +/* GSPI1_MISO */ +/* GSPI1_MOSI */ +/* SML1ALERT# */ PAD_NC(GPP_B23, DN_20K), /* GPP_B23_STRAP */ +/* SMBCLK */ PAD_CFG_GPO(GPP_C0, 0, DEEP), /* SOC_EDP_CABC_EN */ +/* SMBDATA */ PAD_CFG_GPI(GPP_C1, NONE, DEEP), + /* PCIE_8_WLAN_WAKE_ODL */ +/* SMBALERT# */ PAD_NC(GPP_C2, DN_20K), /* GPP_C2_STRAP - 20K_PD */ +/* SML0CLK */ PAD_CFG_GPO(GPP_C3, 0, DEEP), + /* EN_PP3300_TRACKPAD */ +/* SML0DATA */ PAD_NC(GPP_C4, NONE), +/* SML0ALERT# */ PAD_NC(GPP_C5, DN_20K), /* GPP_C5_STRAP - 20K_PD */ +/* SM1CLK */ PAD_CFG_GPI(GPP_C6, NONE, DEEP), /* PEN_PDCT_ODL */ +/* SM1DATA */ PAD_CFG_GPI(GPP_C7, NONE, DEEP), /* PEN_INT_ODL */ +/* UART0_RXD */ +/* UART0_TXD */ +/* UART0_RTS# */ PAD_NC(GPP_C10, NONE), +/* UART0_CTS# */ PAD_NC(GPP_C11, NONE), +/* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* H1_PCH_INT_ODL */ +/* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* TRACKPAD_INT_ODL */ +/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), + /* TOUCHSCREEN_INT_ODL */ +/* UART1_CTS# */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* TRACKPAD_INT_ODL */ +/* I2C0_SDA */ +/* I2C0_SCL */ +/* I2C1_SDA */ +/* I2C1_SCL */ +/* UART2_RXD */ PAD_NC(GPP_C20, NONE), +/* UART2_TXD */ PAD_NC(GPP_C21, NONE), +/* UART2_RTS# */ PAD_NC(GPP_C22, NONE), +/* UART2_CTS# */ PAD_NC(GPP_C23, NONE), +/* SPI1_CS# */ PAD_CFG_GPI(GPP_D0, NONE, DEEP), /* PCH_MEM_STRAP3 */ +/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), +/* SPI1_MISO */ PAD_NC(GPP_D2, NONE), +/* SPI1_MOSI */ PAD_CFG_GPI(GPP_D3, NONE, DEEP), /* PCH_MEM_STRAP0 */ +/* FASHTRIG */ +/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE), /* TP57 */ +/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE), /* TP58 */ +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), /* TP59 */ +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CS# */ PAD_NC(GPP_D9, NONE), +/* ISH_SPI_CLK */ PAD_NC(GPP_D10, NONE), +/* ISH_SPI_MISO */ PAD_NC(GPP_D11, NONE), +/* ISH_SPI_MOSI */ PAD_CFG_GPI(GPP_D12, NONE, DEEP), /* GPP_D12_STRAP */ +/* ISH_UART0_RXD */ PAD_CFG_GPI(GPP_D13, UP_20K, DEEP), /* VOL_UP_ODL */ +/* ISH_UART0_TXD */ PAD_CFG_GPI(GPP_D14, UP_20K, DEEP), /* VOL_DOWN_ODL */ +/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 0, DEEP), + /* TOUCHSCREEN_RST_ODL */ +/* ISH_UART0_CTS# */ PAD_CFG_GPO(GPP_D16, 0, DEEP), /* SPK_PA_EN */ +/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + /* BASE_CAM_DMIC_CLK */ +/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + /* BASE_CAM_DMIC_DATA */ +/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + /* LID_CAM_DMIC_CLK */ +/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + /* LID_CAM_DMIC_DATA */ +/* SPI1_IO2 */ PAD_CFG_GPI(GPP_D21, NONE, DEEP), /* PCH_MEM_STRAP1 */ +/* SPI1_IO3 */ PAD_CFG_GPI(GPP_D22, NONE, DEEP), /* PCH_MEM_STRAP2 */ +/* I2S_MCLK */ +/* SATAXPCI0 */ PAD_NC(GPP_E0, NONE), /* PCH_TP_1 */ +/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), /* PCH_TP_2 */ +/* SATAXPCIE2 */ PAD_NC(GPP_E2, NONE), /* PCH_TP_3 */ +/* CPU_GP0 */ PAD_NC(GPP_E3, NONE), +/* SATA_DEVSLP0 */ PAD_CFG_GPI(GPP_E4, NONE, DEEP), + /* PCIE_7_WWAN_WAKE_ODL */ +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* CPU_GP1 */ PAD_NC(GPP_E7, NONE), +/* SATALED# */ PAD_NC(GPP_E8, NONE), /* PCH_TP_4 */ +/* USB2_OCO# */ +/* USB2_OC1# */ +/* USB2_OC2# */ +/* USB2_OC3# */ +/* DDPB_HPD0 */ +/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* USB_C1_HPD */ +/* DDPD_HPD2 */ +/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), +/* EDP_HPD */ +/* DDPB_CTRLCLK */ PAD_NC(GPP_E18, NONE), +/* DDPB_CTRLDATA */ PAD_CFG_GPI(GPP_E19, DN_20K, DEEP), /* GPP_E19_STRAP */ +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), +/* DDPC_CTRLDATA */ PAD_CFG_GPI(GPP_E21, DN_20K, DEEP), /* GPP_E21_STRAP */ +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), +/* DDPD_CTRLDATA */ PAD_CFG_GPI(GPP_E23, DN_20K, DEEP), /* I2S2_SCLK */ +/* I2S2_SFRM */ PAD_CFG_GPO(GPP_F1, 0, DEEP), + /* WWAN_RESET_1V8_ODL */ +/* I2S2_TXD */ PAD_NC(GPP_F2, NONE), +/* I2S2_RXD */ PAD_CFG_GPO(GPP_F3, 0, DEEP), /* CNV_RF_RESET_L */ +/* I2C2_SDA */ +/* I2C2_SCL */ +/* I2C3_SDA */ +/* I2C3_SCL */ +/* I2C4_SDA */ +/* I2C4_SCL */ +/* I2C5_SDA */ +/* I2C5_SCL */ +/* EMMC_CMD */ +/* EMMC_DATA0 */ +/* EMMC_DATA1 */ +/* EMMC_DATA2 */ +/* EMMC_DATA3 */ +/* EMMC_DATA4 */ +/* EMMC_DATA5 */ +/* EMMC_DATA6 */ +/* EMMC_DATA7 */ +/* EMMC_RCLK */ +/* EMMC_CLK */ +/* RSVD */ PAD_NC(GPP_F23, NONE), +/* SD_CMD */ +/* SD_DATA0 */ +/* SD_DATA1 */ +/* SD_DATA2 */ +/* SD_DATA3 */ +/* SD_CD# */ +/* SD_CLK */ +/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), /* SD_CD_ODL */ +/* I2S2_SCLK */ PAD_NC(GPP_H0, NONE), /* I2S2_SCLK - TP75 */ +/* I2S2_SFRM */ PAD_NC(GPP_H1, NONE), /* I2S2_SFRM - TP74 */ +/* I2S2_TXD */ +/* I2S2_RXD */ PAD_NC(GPP_H3, NONE), /* I2S2_PCH_RX TP76 */ +/* I2C2_SDA */ +/* I2C2_SCL */ +/* I2C3_SDA */ +/* I2C3_SCL */ +/* I2C4_SDA */ +/* I2C4_SCL */ +/* I2C5_SDA */ +/* I2C5_SCL */ +/* M2_SKT2_CFG0 */ PAD_NC(GPP_H12, NONE), /* PCH_TP_5 - TP60 */ +/* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE), /* PCH_TP_6 - TP61 */ +/* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), /* PCH_TP_7 - TP62 */ +/* M2_SKT2_CFG3 */ PAD_NC(GPP_H15, NONE), /* PCH_TP_8 - TP63 */ +/* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE), +/* DPPF_CTRLDATA */ PAD_NC(GPP_H17, NONE), +/* CPU_C10_GATE# */ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* CPU_C10_GATE_PCH_L */ +/* TIMESYNC0 */ PAD_NC(GPP_H19, NONE), +/* IMGCLKOUT1 */ PAD_NC(GPP_H20, NONE), +/* GPP_H21 */ PAD_CFG_GPI(GPP_H21, DN_20K, DEEP), /* H21_STRAP */ +/* GPP_H22 */ +/* GPP_H23 */ PAD_NC(GPP_H23, DN_20K), /* H23_STRAP */ + +/* BATLOW# */ +/* ACPRESENT */ PAD_NC(GPD1, NONE), +/* LAN_WAKE# */ PAD_NC(GPD2, NONE), /* LAN_WAKE_L - TP71 */ +/* PWRBTN# */ +/* SLP_S3# */ +/* SLP_S4# */ +/* SLP_A# */ PAD_NC(GPD6, NONE), +/* RSVD */ +/* SUSCLK */ +/* SLP_WLAN# */ PAD_NC(GPD9, NONE), +/* SLP_S5# */ PAD_NC(GPD10, NONE), +/* LANPHYC */ PAD_NC(GPD11, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { +#if IS_ENABLED(CONFIG_ZOOMBINI_USE_SPI_TPM) +/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_CS_L */ +/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_CLK */ +/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_MISO */ +/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_MOSI */ +#endif +#if IS_ENABLED(CONFIG_ZOOMBINI_USE_I2C_TPM) +/* I2C5_SDA */ +/* I2C5_SCL */ +#endif +/* Ensure UART pins are in native mode for H1. */ +/* UART0_RXD */ /* UART_PCH_RX_DEBUG_TX */ +/* UART0_TXD */ /* UART_PCH_RX_DEBUG_RX */ +}; + +const struct pad_config *__attribute__((weak)) variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *__attribute__((weak)) + variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), +}; + +const struct cros_gpio *__attribute__((weak)) variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} + diff --git a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/ec.h new file mode 100644 index 0000000..9766c1d --- /dev/null +++ b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/ec.h @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __BASEBOARD_EC_H__ +#define __BASEBOARD_EC_H__ + +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> + +#include "gpio.h" + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* + * EC can wake from S3 with lid or power button or key press or + * mode change event. + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ + +#define EC_ENABLE_MKBP_DEVICE /* Enable cros_ec_keyb device */ + +#endif diff --git a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h new file mode 100644 index 0000000..8b0ad2b --- /dev/null +++ b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_GPIO_H__ +#define __MAINBOARD_GPIO_H__ + +#include <soc/gpio.h> + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_D3 +#define GPIO_MEM_CONFIG_1 GPP_D21 +#define GPIO_MEM_CONFIG_2 GPP_D22 +#define GPIO_MEM_CONFIG_3 GPP_D0 + +/* EC in RW */ +#define GPIO_EC_IN_RW GPP_A8 + +/* BIOS Flash Write Protect */ +#define GPIO_PCH_WP GPP_A1 + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPP_74 + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPP_76 + +const struct pad_config *get_gpio_table(size_t *num); +const struct pad_config *get_early_gpio_table(size_t *num); +#endif diff --git a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000..8181b8e --- /dev/null +++ b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include <soc/gpio.h> +#include <stdint.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* Return the board id for the current variant board. */ +uint8_t variant_board_id(void); + +/* + * The next set of functions return the gpio table and fill in the number of + * entries for each table. + */ +const struct pad_config *variant_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); + +const struct cros_gpio *variant_cros_gpios(size_t *num); + +#endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/zoombini/variants/zoombini/include/variant/ec.h b/src/mainboard/google/zoombini/variants/zoombini/include/variant/ec.h new file mode 100644 index 0000000..ef47d37 --- /dev/null +++ b/src/mainboard/google/zoombini/variants/zoombini/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_EC_H__ +#define __MAINBOARD_EC_H__ + +#include <baseboard/ec.h> + +#endif /* __MAINBOARD_EC_H__ */ diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 65b581e..85d94f6 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -16,6 +16,7 @@ select BOOT_DEVICE_SUPPORTS_WRITES select C_ENVIRONMENT_BOOTBLOCK select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select GENERIC_GPIO_LIB select HAVE_HARD_RESET select HAVE_INTEL_FIRMWARE select HAVE_MONOTONIC_TIMER diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 0c05057..9ce647d 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -19,6 +19,7 @@ bootblock-y += spi.c bootblock-$(CONFIG_UART_DEBUG) += uart.c +romstage-y += gpio.c romstage-y += gspi.c romstage-y += memmap.c romstage-y += pmutil.c @@ -28,6 +29,7 @@ ramstage-y += chip.c ramstage-y += cpu.c +ramstage-y += gpio.c ramstage-y += gspi.c ramstage-y += memmap.c ramstage-y += pmutil.c -- To view, visit https://review.coreboot.org/21273 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I13ebaae403d08f1b2e6881eeba4dc1787c792b4e Gerrit-Change-Number: 21273 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com>

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Change in coreboot[master]: mb/google/soraka: Camera PMIC runtime power control
by build bot (Jenkins) (Code Review) 29 Aug '17

29 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20741 ) Change subject: mb/google/soraka: Camera PMIC runtime power control ...................................................................... Patch Set 9: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/14788/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59484/ : SUCCESS -- To view, visit https://review.coreboot.org/20741 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I23b0c0a887c9eb5d29b89f14aebba273b01228e0 Gerrit-Change-Number: 20741 Gerrit-PatchSet: 9 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lakshmi G Prasad <lakshmi.g.prasad(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Ricky Liang <jcliang(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tomasz Figa <tfiga(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Comment-Date: Tue, 29 Aug 2017 18:51:29 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Define Max PCIE Root Ports
by Pratikkumar V Prajapati (Code Review) 29 Aug '17

29 Aug '17

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21272 Change subject: soc/intel/cannonlake: Define Max PCIE Root Ports ...................................................................... soc/intel/cannonlake: Define Max PCIE Root Ports This patch defines Max PCIE Root Ports and fixes bellow Coverity scan defect, *** CID 1380036: Control flow issues (NO_EFFECT) /src/soc/intel/cannonlake/romstage/romstage.c: 80 in soc_memory_init_params() 79 >>> CID 1380036: Control flow issues (NO_EFFECT) >>> "i" is converted to an unsigned type because it's compared to an unsigned constant. 80 for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { 81 if (config->PcieRpEnable[i]) 82 mask |= (1 << i); Change-Id: Id45ff6e96043ed71117018a4e73d08920ae9667e Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/romstage/romstage.c 2 files changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/21272/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 65b581e..cf0a534 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -89,6 +89,10 @@ hex default 0x400000 +config MAX_ROOT_PORTS + int + default 24 + config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 17c3191..74a2abc 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -68,7 +68,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) { - int i; + uint8_t i; uint32_t mask = 0; m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; -- To view, visit https://review.coreboot.org/21272 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id45ff6e96043ed71117018a4e73d08920ae9667e Gerrit-Change-Number: 21272 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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Change in coreboot[master]: [WIP]soc/skylake: Enable common LPC IP
by build bot (Jenkins) (Code Review) 29 Aug '17

29 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20120 ) Change subject: [WIP]soc/skylake: Enable common LPC IP ...................................................................... Patch Set 4: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/59483/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/14787/ : SUCCESS -- To view, visit https://review.coreboot.org/20120 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I042e459fb7c07f024a7f6a5fe7da13eb5f0dd688 Gerrit-Change-Number: 20120 Gerrit-PatchSet: 4 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Aug 2017 17:37:47 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: acpi_device: Provide a new function to add a list of properties
by build bot (Jenkins) (Code Review) 29 Aug '17

29 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21269 ) Change subject: acpi_device: Provide a new function to add a list of properties ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/14784/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59481/ : SUCCESS -- To view, visit https://review.coreboot.org/21269 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id272256639a8525406635e168a3db5ab1ba4df6b Gerrit-Change-Number: 21269 Gerrit-PatchSet: 3 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Aug 2017 17:36:10 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/eve: rt5514: Add 16ms delay on dmic init
by build bot (Jenkins) (Code Review) 29 Aug '17

29 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21271 ) Change subject: mb/google/eve: rt5514: Add 16ms delay on dmic init ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/14786/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59480/ : SUCCESS -- To view, visit https://review.coreboot.org/21271 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If9160ce6992153ba49719029de336595bbf4ae72 Gerrit-Change-Number: 21271 Gerrit-PatchSet: 3 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Aug 2017 17:34:31 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: drivers/i2c/generic: Support additional device properties
by build bot (Jenkins) (Code Review) 29 Aug '17

29 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21270 ) Change subject: drivers/i2c/generic: Support additional device properties ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/14785/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59482/ : SUCCESS -- To view, visit https://review.coreboot.org/21270 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2b8ceb208f4aba01053746547def6d07c8f8f3a2 Gerrit-Change-Number: 21270 Gerrit-PatchSet: 3 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Aug 2017 17:33:24 +0000 Gerrit-HasComments: No

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